- Timestamp:
- Feb 9, 2010, 5:08:49 PM (15 years ago)
- Location:
- anr
- Files:
-
- 6 edited
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anr/anr.tex
r120 r121 47 47 \def\Sformat#1{\begin{small}\textsc{#1}\end{small}} 48 48 \def\inria{INRIA\xspace} \def\Sinria{\Sformat{INRIA}\xspace} 49 \def\irisa{INRIA/CAIRN\xspace} \def\Sirisa{\Sformat{ CAIRN}\xspace}49 \def\irisa{INRIA/CAIRN\xspace} \def\Sirisa{\Sformat{IN/CN}\xspace} 50 50 %\def\citi{CITI\xspace} \def\Sciti{\Sformat{CITI}\xspace} 51 \def\lip{INRIA/COMPSYS\xspace} \def\Slip{\Sformat{ COMP}\xspace}51 \def\lip{INRIA/COMPSYS\xspace} \def\Slip{\Sformat{IN/CS}\xspace} 52 52 \def\tima{TIMA\xspace} \def\Stima{\Sformat{TIMA}\xspace} 53 53 \def\ubs{LAB-STICC\xspace} \def\Subs{\Sformat{UBS}\xspace} -
anr/gantt.l
r113 r121 42 42 struct partner_def { char *key, *name, *fnfull, *fnshort; } partner_table[] = { 43 43 { "UNKNOW" ,"relax" ,0 ,0 }, 44 { "irisa" ,"irisa" ,"table_i risa_full.tex" ,"table_irisa_short.tex" },45 { " lip" ,"lip" ,"table_lip_full.tex" ,"table_lip_short.tex" },44 { "irisa" ,"irisa" ,"table_inria_cairn_full.tex" ,"table_inria_cairn_short.tex" }, 45 { "inria_compsys" ,"inria_compsys" ,"table_inria_compsys_full.tex" ,"table_inria_compsys_short.tex" }, 46 46 { "tima" ,"tima" ,"table_tima_full.tex" ,"table_tima_short.tex" }, 47 47 { "ubs" ,"ubs" ,"table_ubs_full.tex" ,"table_ubs_short.tex" }, … … 781 781 prepare2(curr); 782 782 prepare3(curr); 783 do_partner_table_full(1); do_partner_table_short(1); 783 784 do_partner_table_full(3); do_partner_table_short(3); 784 785 do_partner_table_full(4); do_partner_table_short(4); -
anr/section-6.1.tex
r120 r121 1 1 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 2 \subsubsection{\inria }2 \subsubsection{\inria (CAIRN \& COMPSYS teams)} 3 3 4 4 Inria, the French national institute for research in computer science -
anr/section-7.tex
r120 r121 2 2 3 3 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 4 \subsection{Partner 1: \inria} 5 \ressourcehelp 6 7 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 8 \subsubsection*{\irisa} 9 10 11 \subsubsection*{\lip} 4 \subsection{Partner 1: \irisa} 5 6 \begin{figure}\leavevmode\center 7 \input{table_inria_cairn_full.tex} 8 \caption{\label{ress-detail-irisa}Man power in $mm$ for the delivrables of \irisa.} 9 \end{figure} 10 \begin{description} 11 \item [Equipment] 12 No specific equipment acquisition. 13 \item [Personnel costs] The faculty members involved in the project 14 are François Charot (INRIA researcher) Steven Derrien (associate 15 professor) and Charles Wagner (research engineer). The non-permanent 16 personal required is a PhD student that will mainly work on ASIP 17 generation. We are looking for profile with strong informatic skills 18 and good knowledge in computer architecture. 19 20 The table below summarizes the man power by task for both permanent and 21 non-permanent personnels. The detail by delivrables is given in 22 figure~\ref{ress-detail-irisa}. 23 The non-permanent personnels costs represent ??\% of the personnal 24 costs. The requested funding for non permanent personnels is 100\% of 25 the total ANR requested funding. 26 \begin{center}\input{table_inria_cairn_short.tex}\end{center} 27 28 \item [Subcontracting] 29 No subcontracting costs. 30 \item [Travel] 31 The travel costs are associated to project meeting as 32 well as participation to conferences. The travel costs are estimated 33 to ??\% of the total requested ANR funding. 34 \item [Expenses for inward billing] 35 The costs justified by internal invoicing procedures are evaluated to 4\% 36 of the total requested ANR funding.\\ 37 \end{description} 38 39 40 \subsection{Partner 2: \lip} 41 12 42 %\ressourcehelp 13 43 \begin{figure}\leavevmode\center … … 49 79 50 80 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 51 \subsection{Partner 2: \tima}81 \subsection{Partner 3: \tima} 52 82 \begin{figure}\leavevmode\center 53 83 \input{table_tima_full.tex} … … 90 120 91 121 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 92 \subsection{Partner 3: \ubs}122 \subsection{Partner 4: \ubs} 93 123 \begin{figure}\leavevmode\center 94 124 \input{table_ubs_full.tex} … … 125 155 126 156 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 127 \subsection{Partner 4: \upmc}157 \subsection{Partner 5: \upmc} 128 158 \begin{figure}\leavevmode\center 129 159 \input{table_upmc_full.tex} … … 159 189 160 190 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 161 \subsection{Partner 5: \xilinx}191 \subsection{Partner 6: \xilinx} 162 192 163 193 \begin{figure}\leavevmode\center … … 184 214 185 215 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 186 \subsection{Partner 6: \bull}216 \subsection{Partner 7: \bull} 187 217 188 218 \begin{description} … … 205 235 206 236 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 207 \subsection{Partner 7: \thales}237 \subsection{Partner 8: \thales} 208 238 \ressourcehelp 209 239 210 240 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 211 \subsection{Partner 8: \zied}241 \subsection{Partner 9: \zied} 212 242 \ressourcehelp 213 243 214 244 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 215 \subsection{Partner 9: \navtel}245 \subsection{Partner 10: \navtel} 216 246 \ressourcehelp 217 247 -
anr/task-2.tex
r114 r121 85 85 the SystemC modules of the components of the ALTERA architectural template 86 86 currently not available in the SocLib component library. 87 \itemL{18}{24}{h}{\Sirisa}{ALTERA architecture}{ 0:0:0}87 \itemL{18}{24}{h}{\Sirisa}{ALTERA architecture}{6:6:0} 88 88 The synthesizable VHDL description of the MWMR component corresponding to the 89 89 SystemC module of the former delivrable (\csgAlteraSystemC); -
anr/task-3.tex
r114 r121 27 27 \itemV{0}{18}{X}{\Sirisa}{ASIP compilation flow} 28 28 In this first version of the software, the computations patterns corresponding to 29 custom instruction are specified by the user, and then automatically extracted (when29 custom instructions are specified by the user, and then automatically extracted (when 30 30 beneficial) from the application intermediate representation. 31 31 %\mustbecompleted{FIXME .....} 32 \itemL{18}{24}{X}{\Sirisa}{ASIP compilation flow}{ 0:0:0}32 \itemL{18}{24}{X}{\Sirisa}{ASIP compilation flow}{6:9:0} 33 33 In this second version, the software will also be able to automatically identify 34 34 interesting pattern candidates in the application code, and use them as custom … … 37 37 38 38 \item In this sub-task, we provide micro-architectural template models for the two target 39 processor architectures (NIOS-II and MIPS) supported within inthe COACH-ASIP design flow.39 processor architectures (NIOS-II and MIPS) supported within the COACH-ASIP design flow. 40 40 For each processor, we provide a simulation model (System-C) and a synthesizable model (VHDL) 41 41 of the architecture, along with its architectural extensions 42 42 \begin{livrable} 43 43 \itemV{0}{12}{X}{\Sirisa}{SystemC for extensible MIPS } 44 { A SystemC simulation model for a nsimple extensible MIPS architectural template }45 \itemL{12}{20}{X}{\Sirisa}{SystemC for extensible MIPS}{ 0:0:0}46 {A SystemC simulation model for a extensible MIPS with a tight architectural integration of44 { A SystemC simulation model for a simple extensible MIPS architectural template } 45 \itemL{12}{20}{X}{\Sirisa}{SystemC for extensible MIPS}{2:3:0} 46 {A SystemC simulation model for an extensible MIPS with a tight architectural integration of 47 47 its instruction set extensions} 48 \itemL{0}{12}{X}{\Sirisa}{SystemC for NIOS processor}{ 0:0:0}48 \itemL{0}{12}{X}{\Sirisa}{SystemC for NIOS processor}{2:0:0} 49 49 { A SystemC simulation model for an extensible NIOS processor template, the VHDL model being 50 50 already available from Altera} 51 51 \itemV{12}{18}{H}{\Sirisa}{VHDL for an extensible MIPS} 52 {A synthesizable VHDL model for a nsimple extensible MIPS architectural template}53 \itemL{18}{24}{H}{\Sirisa}{VHDL for an extensible MIPS}{ 0:0:0}54 {A synthesizable VHDL model for a extensible MIPS with a tight architectural integration of52 {A synthesizable VHDL model for a simple extensible MIPS architectural template} 53 \itemL{18}{24}{H}{\Sirisa}{VHDL for an extensible MIPS}{9:12:0} 54 {A synthesizable VHDL model for an extensible MIPS with a tight architectural integration of 55 55 its instruction set extensions} 56 \itemL{24}{36}{D}{\Sirisa}{Evaluation report }{0:0: 0}57 {A evaluation report with quantitative analysis of the performance/area trade-off induced by56 \itemL{24}{36}{D}{\Sirisa}{Evaluation report }{0:0:2} 57 {An evaluation report with quantitative analysis of the performance/area trade-off induced by 58 58 the different approaches} 59 59 \end{livrable}
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