Changeset 85 for trunk/IPs/systemC
- Timestamp:
- May 14, 2008, 3:09:48 PM (17 years ago)
- Location:
- trunk/IPs/systemC
- Files:
-
- 38 edited
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Environment/Makefile.Environment (modified) (1 diff)
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Environment/Queue/include/Queue.h (modified) (1 diff)
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Environment/Queue/include/Sort_Queue.h (modified) (2 diffs)
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Environment/Queue/include/Sort_Queue_Dynamic.h (modified) (2 diffs)
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processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/include/Types.h (modified) (1 diff)
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processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_transition.cpp (modified) (3 diffs)
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processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/SelfTest/configuration.cfg (modified) (1 diff)
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processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/SelfTest/src/main.cpp (modified) (4 diffs)
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processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/SelfTest/src/test.cpp (modified) (3 diffs)
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processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/include/Ifetch_unit_Glue.h (modified) (1 diff)
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processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/include/Parameters.h (modified) (1 diff)
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processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/src/Ifetch_unit_Glue.cpp (modified) (2 diffs)
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processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/src/Ifetch_unit_Glue_allocation.cpp (modified) (1 diff)
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processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/src/Ifetch_unit_Glue_deallocation.cpp (modified) (1 diff)
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processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/src/Ifetch_unit_Glue_genMealy_icache_req.cpp (modified) (1 diff)
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processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/src/Parameters.cpp (modified) (1 diff)
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processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/src/Parameters_print.cpp (modified) (1 diff)
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processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/SelfTest/config.cfg (modified) (1 diff)
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processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/SelfTest/config_min.cfg (modified) (1 diff)
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processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/SelfTest/src/test.cpp (modified) (6 diffs)
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processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/src/Ifetch_unit_allocation.cpp (modified) (7 diffs)
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processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/src/Parameters.cpp (modified) (1 diff)
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processor/Morpheo/Behavioural/Makefile.Common (modified) (1 diff)
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processor/Morpheo/Behavioural/include/Debug_component.h (modified) (1 diff)
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processor/Morpheo/Behavioural/include/Version.h (modified) (2 diffs, 1 prop)
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processor/Morpheo/Behavioural/include/Version.h.sed (modified) (2 diffs, 1 prop)
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processor/Morpheo/Behavioural/src/Stat_create_expr.cpp (modified) (1 diff)
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processor/Morpheo/Behavioural/src/Vhdl_get_header.cpp (modified) (1 diff)
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processor/Morpheo/Behavioural/src/XML_header.cpp (modified) (3 diffs)
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processor/Morpheo/Script/SelfTest.sh (modified) (1 diff)
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processor/Morpheo/Script/execute.sh (modified) (1 diff)
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processor/Morpheo/Script/execute_n.sh (modified) (1 diff)
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processor/Morpheo/Script/first_run.sh (modified) (1 diff)
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processor/Morpheo/Script/lock.sh (modified) (1 diff)
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processor/Morpheo/Script/range.sh (modified) (1 diff)
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processor/Morpheo/Script/unlock.sh (modified) (1 diff)
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processor/Morpheo/Script/version.sh (modified) (1 diff)
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processor/Morpheo/Script/xilinx_extract_info.sh (modified) (1 diff)
Legend:
- Unmodified
- Added
- Removed
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trunk/IPs/systemC/Environment/Makefile.Environment
r82 r85 51 51 @\ 52 52 $(ECHO) "Compilation : $*";\ 53 $( DISTCXX) $(MORPHEO_CXX_FLAGS) -c -o $@ $<;53 $(CXX) $(MORPHEO_CXX_FLAGS) -c -o $@ $<; 54 54 55 55 $(DIR_OBJ)/%.o : $(DIR_SRC)/%.c $(HEADERS) 56 56 @\ 57 57 $(ECHO) "Compilation : $*";\ 58 $( DISTCC) $(MORPHEO_CC_FLAGS) -c -o $@ $<;58 $(CC) $(MORPHEO_CC_FLAGS) -c -o $@ $<; 59 59 60 60 $(DIR_OBJ)/%.o : $(DIR_TST)/%.cpp $(HEADERS) 61 61 @\ 62 62 $(ECHO) "Compilation : $*";\ 63 $( DISTCXX) $(MORPHEO_CXX_FLAGS) -c -o $@ $<;63 $(CXX) $(MORPHEO_CXX_FLAGS) -c -o $@ $<; 64 64 65 65 $(DIR_BIN)/%.x : $(OBJECTS_DEPS) $(OBJECTS) $(OBJECTS_BIN) -
trunk/IPs/systemC/Environment/Queue/include/Queue.h
r81 r85 61 61 // *****[ pop ]***** 62 62 // read the queue, and update the pointer 63 public : virtual T pop () = 0; 64 65 // *****[ pop ]***** 66 // read the queue, and update the pointer 67 public : virtual T pop (uint32_t num) = 0; 63 public : virtual T pop (uint32_t num=0) = 0; 68 64 69 65 // *****[ push ]***** 70 66 // Push a new value (they must have a slot free) 71 public : virtual bool push (T val) = 0;67 public : virtual bool push (T val) = 0; 72 68 73 69 }; // Queue -
trunk/IPs/systemC/Environment/Queue/include/Sort_Queue.h
r81 r85 59 59 // return the n-eme slot. 60 60 // (first = 0) 61 public : slot_t<T> read (uint32_t num )61 public : slot_t<T> read (uint32_t num=0) 62 62 { 63 63 if (num >= Queue <T>::_nb_slot) … … 72 72 // *****[ pop ]***** 73 73 // read the queue, and update the pointer 74 public : T pop () 75 { 76 return pop (0); 77 } 78 79 // *****[ pop ]***** 80 // read the queue, and update the pointer 81 public : T pop (uint32_t num) 74 public : T pop (uint32_t num=0) 82 75 { 83 76 if (num >= Queue <T>::_nb_slot) -
trunk/IPs/systemC/Environment/Queue/include/Sort_Queue_Dynamic.h
r81 r85 107 107 // return the n-eme slot. 108 108 // (first = 0) 109 public : slot_t<T> read (uint32_t num )109 public : slot_t<T> read (uint32_t num=0) 110 110 { 111 111 if (num >= Queue <T>::_nb_slot) … … 120 120 // *****[ pop ]***** 121 121 // read the queue, and update the pointer 122 public : T pop () 123 { 124 return pop (0); 125 } 126 127 // *****[ pop ]***** 128 // read the queue, and update the pointer 129 public : T pop (uint32_t num) 122 public : T pop (uint32_t num=0) 130 123 { 131 124 if (num >= Queue <T>::_nb_slot) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/include/Types.h
r81 r85 66 66 }; // end namespace core 67 67 }; // end namespace behavioural 68 69 template<> inline std::string toString<morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::ifetch_queue::ifetch_queue_state_t>(const morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::ifetch_queue::ifetch_queue_state_t& x) 70 { 71 switch (x) 72 { 73 case morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::ifetch_queue::IFETCH_QUEUE_STATE_EMPTY : return "empty" ; break; 74 // case morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::ifetch_queue::IFETCH_QUEUE_STATE_WAIT_REQ : return "wait_req" ; break; 75 case morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::ifetch_queue::IFETCH_QUEUE_STATE_WAIT_RSP : return "wait_rsp" ; break; 76 case morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::ifetch_queue::IFETCH_QUEUE_STATE_HAVE_RSP : return "have_rsp" ; break; 77 case morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::ifetch_queue::IFETCH_QUEUE_STATE_ERROR_WAIT_RSP : return "error_wait_rsp"; break; 78 default : return "" ; break; 79 } 80 }; 81 82 68 83 }; // end namespace morpheo 69 84 #endif -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_transition.cpp
r81 r85 34 34 else 35 35 { 36 log_printf(NONE,Ifetch_queue,FUNCTION," * KANE address : 0x%x",PORT_READ(in_ADDRESS_INSTRUCTION_ADDRESS)); 37 38 36 39 // ========================================================== 37 40 // =====[ ADDRESS ]========================================== … … 55 58 _queue[reg_PTR_WRITE]->_instruction_enable [i] = enable; 56 59 } 60 57 61 _queue[reg_PTR_WRITE]->_address = PORT_READ(in_ADDRESS_INSTRUCTION_ADDRESS ); 58 62 _queue[reg_PTR_WRITE]->_inst_ifetch_ptr = (_param->_have_port_instruction_ptr)?PORT_READ(in_ADDRESS_INST_IFETCH_PTR ):0; … … 133 137 } 134 138 135 // log_printf(TRACE,Ifetch_queue,FUNCTION,"reg_PTR_WRITE : %d",reg_PTR_WRITE); 136 // log_printf(TRACE,Ifetch_queue,FUNCTION,"reg_PTR_READ : %d",reg_PTR_READ ); 137 // for (uint32_t i=0; i<_param->_size_queue; i++) 138 // { 139 // log_printf(TRACE,Ifetch_queue,FUNCTION,"[%d] %d %.8x %d - %d %d %d", i, _queue [i]->_state, _queue [i]->_address,_queue [i]->_inst_ifetch_ptr,_queue [i]->_branch_state,_queue [i]->_branch_update_prediction_id,_queue [i]->_exception); 140 141 // for (uint32_t j=0; j<_param->_nb_instruction; j++) 142 // log_printf(TRACE,Ifetch_queue,FUNCTION," * %d %.8x", _queue [i]->_instruction_enable[i], _queue [i]->_instruction[i]); 143 // } 139 #if DEBUG >= DEBUG_TRACE 140 log_printf(TRACE,Ifetch_queue,FUNCTION,"Dump ifetch_queue"); 141 log_printf(TRACE,Ifetch_queue,FUNCTION," * reg_PTR_WRITE : %d",reg_PTR_WRITE); 142 log_printf(TRACE,Ifetch_queue,FUNCTION," * reg_PTR_READ : %d",reg_PTR_READ ); 143 for (uint32_t i=0; i<_param->_size_queue; i++) 144 { 145 log_printf(TRACE,Ifetch_queue,FUNCTION," * [%d] %s %.8x %d - %d %d %d", i, toString(_queue [i]->_state).c_str(), _queue [i]->_address,_queue [i]->_inst_ifetch_ptr,_queue [i]->_branch_state,_queue [i]->_branch_update_prediction_id,_queue [i]->_exception); 146 147 for (uint32_t j=0; j<_param->_nb_instruction; j++) 148 log_printf(TRACE,Ifetch_queue,FUNCTION," * %d %.8x", _queue [i]->_instruction_enable[j], _queue [i]->_instruction[j]); 149 } 150 #endif 144 151 145 152 #ifdef STATISTICS -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/SelfTest/configuration.cfg
r81 r85 1 1 Ifetch_unit_Glue 2 30 30 +32 # size_address -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/SelfTest/src/main.cpp
r81 r85 8 8 #include "Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/SelfTest/include/test.h" 9 9 10 #define NB_PARAMS 010 #define NB_PARAMS 1 11 11 12 12 void usage (int argc, char * argv[]) … … 14 14 err (_("<Usage> %s name_instance list_params.\n"),argv[0]); 15 15 err (_("list_params is :\n")); 16 err (_(" * ()\n"));16 err (_(" * size_address (uint32_t)\n")); 17 17 18 18 exit (1); … … 30 30 uint32_t x = 1; 31 31 32 string name = argv[x++]; 33 //const uint32_t size_data = atoi(argv[x++]); 34 //const uint32_t nb_port = atoi(argv[x++]); 32 string name = argv[x++]; 33 uint32_t _size_address = fromString<uint32_t>(argv[x++]); 35 34 36 35 int _return = EXIT_SUCCESS; … … 38 37 { 39 38 morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::ifetch_unit_glue::Parameters * param = new morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::ifetch_unit_glue::Parameters 40 (//size_data, 41 //nb_port 42 ); 39 (_size_address); 43 40 44 41 msg(_("%s"),param->print(1).c_str()); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/SelfTest/src/test.cpp
r82 r85 47 47 ALLOC_SC_SIGNAL( in_ICACHE_REQ_QUEUE_ACK ," in_ICACHE_REQ_QUEUE_ACK ",Tcontrol_t); 48 48 ALLOC_SC_SIGNAL(out_ICACHE_REQ_TYPE ,"out_ICACHE_REQ_TYPE ",Ticache_type_t); 49 ALLOC_SC_SIGNAL(out_ICACHE_REQ_ADDRESS ,"out_ICACHE_REQ_ADDRESS ",Taddress_t); 50 ALLOC_SC_SIGNAL( in_ICACHE_REQ_ADDRESS_ADDRESS," in_ICACHE_REQ_ADDRESS_ADDRESS",Taddress_t); 51 ALLOC_SC_SIGNAL(out_ICACHE_REQ_QUEUE_ADDRESS ,"out_ICACHE_REQ_QUEUE_ADDRESS ",Taddress_t); 49 52 ALLOC_SC_SIGNAL( in_EVENT_VAL ," in_EVENT_VAL ",Tcontrol_t); 50 53 ALLOC_SC_SIGNAL(out_EVENT_ADDRESS_VAL ,"out_EVENT_ADDRESS_VAL ",Tcontrol_t); … … 69 72 INSTANCE_SC_SIGNAL(_Ifetch_unit_Glue,out_ICACHE_REQ_ADDRESS_ACK); 70 73 INSTANCE_SC_SIGNAL(_Ifetch_unit_Glue, in_ICACHE_REQ_QUEUE_ACK ); 74 INSTANCE_SC_SIGNAL(_Ifetch_unit_Glue,out_ICACHE_REQ_ADDRESS ); 75 INSTANCE_SC_SIGNAL(_Ifetch_unit_Glue, in_ICACHE_REQ_ADDRESS_ADDRESS); 76 INSTANCE_SC_SIGNAL(_Ifetch_unit_Glue,out_ICACHE_REQ_QUEUE_ADDRESS ); 71 77 INSTANCE_SC_SIGNAL(_Ifetch_unit_Glue,out_ICACHE_REQ_TYPE ); 72 78 INSTANCE_SC_SIGNAL(_Ifetch_unit_Glue, in_EVENT_VAL ); … … 127 133 delete out_ICACHE_REQ_ADDRESS_ACK; 128 134 delete in_ICACHE_REQ_QUEUE_ACK ; 135 delete out_ICACHE_REQ_ADDRESS ; 136 delete in_ICACHE_REQ_ADDRESS_ADDRESS; 137 delete out_ICACHE_REQ_QUEUE_ADDRESS ; 129 138 delete out_ICACHE_REQ_TYPE ; 130 139 delete in_EVENT_VAL ; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/include/Ifetch_unit_Glue.h
r82 r85 72 72 73 73 public : SC_OUT(Ticache_type_t ) * out_ICACHE_REQ_TYPE ; 74 75 public : SC_OUT(Taddress_t ) * out_ICACHE_REQ_ADDRESS ; 76 public : SC_IN (Taddress_t ) * in_ICACHE_REQ_ADDRESS_ADDRESS; 77 public : SC_OUT(Taddress_t ) * out_ICACHE_REQ_QUEUE_ADDRESS ; 74 78 75 79 // ~~~~~[ Interface "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/include/Parameters.h
r81 r85 24 24 { 25 25 //-----[ fields ]------------------------------------------------------------ 26 public : uint32_t _size_address; 26 27 27 28 //-----[ methods ]----------------------------------------------------------- 28 public : Parameters ( );29 public : Parameters (uint32_t size_address); 29 30 // public : Parameters (Parameters & param) ; 30 31 public : ~Parameters () ; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/src/Ifetch_unit_Glue.cpp
r81 r85 88 88 sensitive << (*(in_ICACHE_REQ_ADDRESS_VAL)) 89 89 << (*(in_ICACHE_REQ_ACK )) 90 << (*(in_ICACHE_REQ_QUEUE_ACK )); 90 << (*(in_ICACHE_REQ_QUEUE_ACK )) 91 << (*(in_ICACHE_REQ_ADDRESS_ADDRESS)) 92 ; 91 93 92 94 # ifdef SYSTEMCASS_SPECIFIC … … 100 102 (*(out_ICACHE_REQ_ADDRESS_ACK)) (*( in_ICACHE_REQ_QUEUE_ACK )); 101 103 (*(out_ICACHE_REQ_ADDRESS_ACK)) (*( in_ICACHE_REQ_ACK )); 104 105 (*(out_ICACHE_REQ_ADDRESS )) (*( in_ICACHE_REQ_ADDRESS_ADDRESS)); 106 (*(out_ICACHE_REQ_QUEUE_ADDRESS)) (*( in_ICACHE_REQ_ADDRESS_ADDRESS)); 107 102 108 # endif 103 109 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/src/Ifetch_unit_Glue_allocation.cpp
r81 r85 60 60 ALLOC_INTERFACE("icache_req",OUT, WEST, "Instruction Cache request."); 61 61 62 ALLOC_SIGNAL_OUT(out_ICACHE_REQ_VAL ,"val" ,Tcontrol_t,1); 63 ALLOC_SIGNAL_IN ( in_ICACHE_REQ_ADDRESS_VAL,"address_val",Tcontrol_t,1); 64 ALLOC_SIGNAL_OUT(out_ICACHE_REQ_QUEUE_VAL ,"queue_val" ,Tcontrol_t,1); 65 ALLOC_SIGNAL_IN ( in_ICACHE_REQ_ACK ,"ack" ,Tcontrol_t,1); 66 ALLOC_SIGNAL_OUT(out_ICACHE_REQ_ADDRESS_ACK,"address_ack",Tcontrol_t,1); 67 ALLOC_SIGNAL_IN ( in_ICACHE_REQ_QUEUE_ACK ,"queue_ack" ,Tcontrol_t,1); 68 ALLOC_SIGNAL_OUT(out_ICACHE_REQ_TYPE ,"type" ,Ticache_type_t,_param->_size_icache_type); 62 ALLOC_SIGNAL_OUT(out_ICACHE_REQ_VAL ,"val" ,Tcontrol_t,1); 63 ALLOC_SIGNAL_IN ( in_ICACHE_REQ_ADDRESS_VAL ,"address_val" ,Tcontrol_t,1); 64 ALLOC_SIGNAL_OUT(out_ICACHE_REQ_QUEUE_VAL ,"queue_val" ,Tcontrol_t,1); 65 ALLOC_SIGNAL_IN ( in_ICACHE_REQ_ACK ,"ack" ,Tcontrol_t,1); 66 ALLOC_SIGNAL_OUT(out_ICACHE_REQ_ADDRESS_ACK ,"address_ack" ,Tcontrol_t,1); 67 ALLOC_SIGNAL_IN ( in_ICACHE_REQ_QUEUE_ACK ,"queue_ack" ,Tcontrol_t,1); 68 ALLOC_SIGNAL_OUT(out_ICACHE_REQ_TYPE ,"type" ,Ticache_type_t,_param->_size_icache_type); 69 ALLOC_SIGNAL_OUT(out_ICACHE_REQ_ADDRESS ,"address" ,Taddress_t,_param->_size_address); 70 ALLOC_SIGNAL_IN ( in_ICACHE_REQ_ADDRESS_ADDRESS,"address_address",Taddress_t,_param->_size_address); 71 ALLOC_SIGNAL_OUT(out_ICACHE_REQ_QUEUE_ADDRESS ,"queue_address" ,Taddress_t,_param->_size_address); 69 72 } 70 73 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/src/Ifetch_unit_Glue_deallocation.cpp
r81 r85 35 35 delete in_ICACHE_REQ_QUEUE_ACK ; 36 36 delete out_ICACHE_REQ_TYPE ; 37 delete out_ICACHE_REQ_ADDRESS ; 38 delete in_ICACHE_REQ_ADDRESS_ADDRESS ; 39 delete out_ICACHE_REQ_QUEUE_ADDRESS ; 37 40 38 41 delete in_EVENT_VAL ; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/src/Ifetch_unit_Glue_genMealy_icache_req.cpp
r81 r85 31 31 PORT_WRITE(out_ICACHE_REQ_ADDRESS_ACK, ack and queue_ack); // cache can accept a new transaction and queue have a slot empty 32 32 PORT_WRITE(out_ICACHE_REQ_QUEUE_VAL , address_val and ack); // cache can accept a new transaction and the address is valid 33 34 Taddress_t address = PORT_READ(in_ICACHE_REQ_ADDRESS_ADDRESS); 35 PORT_WRITE(out_ICACHE_REQ_ADDRESS ,address); 36 PORT_WRITE(out_ICACHE_REQ_QUEUE_ADDRESS,address); 33 37 34 38 log_printf(FUNC,Ifetch_unit_Glue,FUNCTION,"End"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/src/Parameters.cpp
r81 r85 19 19 #undef FUNCTION 20 20 #define FUNCTION "Ifetch_unit_Glue::Parameters" 21 Parameters::Parameters ( )21 Parameters::Parameters (uint32_t size_address) 22 22 { 23 23 log_printf(FUNC,Ifetch_unit_Glue,FUNCTION,"Begin"); 24 25 _size_address = size_address; 26 24 27 test(); 25 28 log_printf(FUNC,Ifetch_unit_Glue,FUNCTION,"End"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/src/Parameters_print.cpp
r81 r85 27 27 28 28 xml.balise_open("ifetch_unit_glue"); 29 // xml.singleton_begin(""); xml.attribut("value",toString(_)); xml.singleton_end();29 xml.singleton_begin("size_address"); xml.attribut("value",toString(_size_address)); xml.singleton_end(); 30 30 xml.balise_close(); 31 31 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/SelfTest/config.cfg
r82 r85 3 3 1 8 *2 # _nb_instruction 4 4 1 1 *2 # _size_branch_update_prediction 5 3 2 32*2 # _size_general_data5 30 30 *2 # _size_general_data -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/SelfTest/config_min.cfg
r82 r85 3 3 1 1 *2 # nb_instruction 4 4 1 1 *2 # size_branch_update_prediction 5 3 2 32*2 # size_general_data5 30 30 *2 # size_general_data -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/SelfTest/src/test.cpp
r82 r85 7 7 */ 8 8 9 #define NB_ITERATION 1 9 #define NB_ITERATION 128 10 10 #define CYCLE_MAX (128*NB_ITERATION) 11 11 12 12 #include "Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/SelfTest/include/test.h" 13 #include "../../../../../../../../Environment/Queue/include/Sort_Queue.h" 13 14 #include "Common/include/Test.h" 14 15 #include "Behavioural/include/Allocation.h" 16 17 //using namespace environment; 18 using namespace environment::queue; 19 20 class cache_req_t 21 { 22 public : Tpacket_t packet; 23 public : Taddress_t address; 24 25 public : cache_req_t (Tpacket_t packet, 26 Taddress_t address) 27 { 28 this->packet = packet ; 29 this->address = address; 30 } 31 }; 15 32 16 33 void test (string name, … … 20 37 21 38 #ifdef STATISTICS 22 morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5, 50);39 morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,1024); 23 40 #endif 24 41 … … 142 159 srand(seed); 143 160 161 const int32_t percent_transaction_icache_req = 75; 162 const int32_t percent_transaction_icache_rsp = 75; 163 const int32_t percent_transaction_predict = 75; 164 const int32_t percent_transaction_event = 5; 165 const int32_t percent_hit = 90; 166 const uint32_t delay_miss_min = 5; 167 const uint32_t delay_miss_max = 10; 168 144 169 SC_START(0); 145 170 LABEL("Initialisation"); 171 172 uint32_t jump = 7 ;// packet 173 uint32_t nb_packet_in = 1; 174 uint32_t nb_packet_out = 1; 175 176 Tcontrol_t c_val = false; 177 Tcontrol_t n_val = false; 178 Tcontrol_t nn_val = false; 179 180 Tgeneral_data_t c_addr = 0x100; 181 Tgeneral_data_t n_addr = 0x100; 182 Tgeneral_data_t nn_addr = 0x100; 183 184 Tcontrol_t c_enable [_param->_nb_instruction]; 185 Tcontrol_t n_enable [_param->_nb_instruction]; 186 187 Tcontrol_t c_is_ds_take = 0; 188 Tcontrol_t n_is_ds_take = 0; 189 Tcontrol_t nn_is_ds_take = 0; 190 191 bool slot_use [_param->_size_queue]; 192 193 environment::queue::Parameters * param_cache = new environment::queue::Parameters(_param->_size_queue); 194 Sort_Queue<cache_req_t*> * cache = new Sort_Queue<cache_req_t*> ("cache",param_cache); 195 196 cache->reset(); 197 198 for (uint32_t i=0; i<_param->_size_queue; i++) 199 slot_use [i] = false; 200 201 c_enable [0] = 1; 202 for (uint32_t i=1; i<_param->_nb_instruction; i++) 203 c_enable [i] = 0; 146 204 147 205 LABEL("Reset"); … … 150 208 in_NRESET->write(1); 151 209 210 LABEL("Test no out val/ack"); 211 212 TEST(Tcontrol_t,out_ICACHE_REQ_VAL->read(), 0); 213 TEST(Tcontrol_t,out_ICACHE_RSP_ACK->read(), 1); 214 TEST(Tcontrol_t,out_PREDICT_VAL ->read(), 1); 215 TEST(Tcontrol_t,out_EVENT_ACK ->read(), 1); 216 217 for (uint32_t i=0; i<_param->_nb_instruction; i++) 218 TEST(Tcontrol_t,out_DECOD_VAL [i]->read(), 0); 219 220 LABEL("Send Reset"); 221 do 222 { 223 in_EVENT_VAL ->write(1); 224 in_EVENT_ADDRESS->write(n_addr); 225 SC_START(1); 226 } while (out_EVENT_ACK->read() == false); 227 in_EVENT_VAL ->write(0); 228 229 n_val = 1; 230 152 231 LABEL("Loop of Test"); 153 232 … … 156 235 LABEL("Iteration %d",iteration); 157 236 158 SC_START(100); 237 // PREDICT 238 { 239 in_PREDICT_ACK ->write((rand()%100)<percent_transaction_predict); 240 241 SC_START(0); 242 243 Taddress_t addr = (out_PREDICT_PC_CURRENT_IS_DS_TAKE->read())?out_PREDICT_PC_PREVIOUS->read():out_PREDICT_PC_CURRENT->read(); 244 245 uint32_t begin = addr%_param->_nb_instruction; 246 uint32_t end = ((begin<<1)>_param->_nb_instruction)?(_param->_nb_instruction-1):(begin<<1); 247 Tcontrol_t take = (nb_packet_in%jump)==0; 248 249 if (take) 250 addr += 0x100; 251 else 252 addr += end-begin+1; 253 254 for (uint32_t i=0; i<_param->_nb_instruction; i++) 255 in_PREDICT_INSTRUCTION_ENABLE [i] ->write((i>=begin) and (i<=end)); 256 in_PREDICT_PC_NEXT ->write(addr); 257 in_PREDICT_PC_NEXT_IS_DS_TAKE ->write(take); 258 in_PREDICT_INST_IFETCH_PTR ->write(0); 259 in_PREDICT_BRANCH_STATE ->write(0); 260 in_PREDICT_BRANCH_UPDATE_PREDICTION_ID->write(0); 261 } 262 263 // DECOD 264 { 265 uint32_t nb_decod = (rand()%_param->_nb_instruction); 266 267 for (uint32_t i=0; i<_param->_nb_instruction; i++) 268 in_DECOD_ACK [i]->write(i<=nb_decod); 269 } 270 271 // EVENT 272 in_EVENT_VAL ->write((rand()%100)<percent_transaction_event ); 273 in_EVENT_ADDRESS->write(0x100); 274 275 // ICACHE_REQ 276 in_ICACHE_REQ_ACK->write((rand()%100)<percent_transaction_icache_req); 277 278 // ICACHE_RSP 279 { 280 Tcontrol_t val = false; 281 if (not cache->empty()) 282 { 283 slot_t<cache_req_t *> cache_rsp = cache->read(); 284 285 val = (cache_rsp._delay == 0); 286 287 Tpacket_t packet = cache_rsp._data->packet ; 288 Taddress_t address = cache_rsp._data->address; 289 290 in_ICACHE_RSP_PACKET_ID ->write(packet); 291 for (uint32_t i=0; i<_param->_nb_instruction; i++) 292 in_ICACHE_RSP_INSTRUCTION [i]->write(address+i); 293 in_ICACHE_RSP_ERROR ->write(0); 294 } 295 296 in_ICACHE_RSP_VAL->write(val); 297 } 298 299 //------------------------------------------------- 300 SC_START(0); 301 //------------------------------------------------- 302 303 if (out_ICACHE_REQ_VAL->read() and in_ICACHE_REQ_ACK->read()) 304 { 305 LABEL("ICACHE_REQ : Transaction accepted"); 306 307 Tpacket_t packet = (_param->_have_port_queue_ptr)?out_ICACHE_REQ_PACKET_ID->read():0; 308 Taddress_t address = out_ICACHE_REQ_ADDRESS->read(); 309 310 TEST(bool ,slot_use[packet], false); 311 TEST(Taddress_t,address ,c_addr); 312 313 slot_use[packet] = true; 314 315 uint32_t delay; 316 if ((rand()%100)<percent_hit) 317 delay = 1; 318 else 319 delay = delay_miss_min + (rand()%(delay_miss_max-delay_miss_min+1)); 320 321 cache_req_t * cache_req = new cache_req_t(packet,address); 322 cache->push(delay,cache_req); 323 324 c_val = 0; 325 nb_packet_in ++; 326 } 327 328 { 329 bool find=false; 330 331 Taddress_t addr=out_DECOD_ADDRESS->read(); 332 for (uint32_t i=0; i<_param->_nb_instruction; i++) 333 if (out_DECOD_VAL[i]->read() and in_DECOD_ACK [i]->read()) 334 { 335 Tinstruction_t inst = out_DECOD_INSTRUCTION[i]->read(); 336 LABEL("DECOD [%d] : Transaction accepted",i); 337 LABEL(" address : 0x%x",addr); 338 LABEL(" instruction : 0x%x",inst); 339 340 find = true; 341 TEST(Tinstruction_t,inst,addr+i); 342 } 343 344 if (find) 345 { 346 if (_param->_have_port_instruction_ptr) 347 TEST(Tinst_ifetch_ptr_t, out_DECOD_INST_IFETCH_PTR ->read(), 0); 348 TEST(Tbranch_state_t , out_DECOD_BRANCH_STATE ->read(), 0); 349 if (_param->_have_port_branch_update_prediction_id) 350 TEST(Tprediction_ptr_t , out_DECOD_BRANCH_UPDATE_PREDICTION_ID->read(), 0); 351 TEST(Texception_t , out_DECOD_EXCEPTION ->read(), 0); 352 } 353 } 354 355 if (in_ICACHE_RSP_VAL->read() and out_ICACHE_RSP_ACK->read()) 356 { 357 LABEL("ICACHE_RSP : Transaction accepted"); 358 359 slot_use[cache->read()._data->packet] = false; 360 361 cache->pop(); 362 } 363 364 if (out_PREDICT_VAL->read() and in_PREDICT_ACK->read()) 365 { 366 LABEL("PREDICT : Transaction accepted"); 367 368 if (c_val) 369 TEST(Tgeneral_address_t,out_PREDICT_PC_PREVIOUS ->read(),c_addr ); 370 TEST(Tgeneral_address_t,out_PREDICT_PC_CURRENT ->read(),n_addr ); 371 TEST(Tcontrol_t ,out_PREDICT_PC_CURRENT_IS_DS_TAKE->read(),n_is_ds_take); 372 373 nn_val = true; 374 nn_addr = in_PREDICT_PC_NEXT ->read(); 375 nn_is_ds_take = in_PREDICT_PC_NEXT_IS_DS_TAKE->read(); 376 377 for (uint32_t i=0; i<_param->_nb_instruction; i++) 378 n_enable [i] = in_PREDICT_INSTRUCTION_ENABLE [i]->read(); 379 } 380 381 if (not c_val) 382 { 383 if (n_val and nn_val) 384 { 385 c_val = 1; 386 c_addr = n_addr; 387 c_is_ds_take = n_is_ds_take; 388 389 for (uint32_t i=0; i<_param->_nb_instruction; i++) 390 c_enable [i] = n_enable [i]; 391 392 n_val = 1; 393 n_addr = nn_addr; 394 n_is_ds_take = nn_is_ds_take; 395 396 nn_val = 0; 397 } 398 } 399 400 if (in_EVENT_VAL->read() and out_EVENT_ACK->read()) 401 { 402 LABEL("EVENT : Transaction accepted"); 403 404 c_val = false; 405 n_val = true; 406 nn_val = false; 407 408 n_addr = in_EVENT_ADDRESS->read(); 409 n_is_ds_take = 0; 410 411 n_enable [0] = 1; 412 for (uint32_t i=1; i<_param->_nb_instruction; i++) 413 n_enable [i] = 0; 414 } 415 416 417 { 418 string str_c_enable = ""; 419 string str_n_enable = ""; 420 421 for (uint32_t i=0; i<_param->_nb_instruction; i++) 422 { 423 str_c_enable += " " + toString(c_enable [i]); 424 str_n_enable += " " + toString(n_enable [i]); 425 } 426 427 LABEL("-----------------------------------"); 428 LABEL(" * nb_packet_in : %d",nb_packet_in); 429 LABEL(" * nb_packet_out : %d",nb_packet_out); 430 LABEL(" * pc : %d %d %.8x %s",c_val ,c_is_ds_take , c_addr ,str_c_enable.c_str()); 431 if (nn_val) 432 { 433 LABEL(" * pc+4 : %d %d %.8x %s",n_val ,n_is_ds_take , n_addr ,str_n_enable.c_str()); 434 } 435 else 436 { 437 LABEL(" * pc+4 : %d %d %.8x" ,n_val ,n_is_ds_take , n_addr ); 438 } 439 LABEL(" * pc+8 : %d %d %.8x" ,nn_val ,nn_is_ds_take, nn_addr); 440 LABEL("-----------------------------------"); 441 } 442 443 SC_START(1); 444 cache->transition(); 159 445 } 160 446 … … 210 496 delete out_EVENT_ACK ; 211 497 delete in_EVENT_ADDRESS ; 498 499 delete param_cache; 500 delete cache; 212 501 #endif 213 502 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/src/Ifetch_unit_allocation.cpp
r82 r85 213 213 214 214 { 215 dest = _name; 216 217 #ifdef POSITION 218 _component->interface_map (src ,"address", 219 dest,"icache_req"); 220 _component->interface_map (src ,"address", 221 dest+"_ifetch_unit_glue","address"); 222 #endif 215 dest = _name+"_ifetch_queue"; 223 216 224 217 for (uint32_t i=0; i<_param->_nb_instruction; i++) 225 218 { 226 219 #ifdef POSITION 227 _component->interface_map (src 228 dest +"_ifetch_queue","address_"+toString(i));229 #endif 230 PORT_MAP(_component,src,"out_ADDRESS_"+toString(i)+"_INSTRUCTION_ENABLE",231 dest+"_ifetch_queue", "in_ADDRESS_"+toString(i)+"_INSTRUCTION_ENABLE");220 _component->interface_map (src ,"address_"+toString(i), 221 dest,"address_"+toString(i)); 222 #endif 223 COMPONENT_MAP(_component,src ,"out_ADDRESS_"+toString(i)+"_INSTRUCTION_ENABLE", 224 dest, "in_ADDRESS_"+toString(i)+"_INSTRUCTION_ENABLE"); 232 225 } 233 226 234 PORT_MAP(_component,src ,"out_ADDRESS_VAL" ,235 dest+"_ifetch_unit_glue", "in_ICACHE_REQ_ADDRESS_VAL" );236 PORT_MAP(_component,src , "in_ADDRESS_ACK" ,237 dest+"_ifetch_unit_glue","out_ICACHE_REQ_ADDRESS_ACK" );238 PORT_MAP(_component,src ,"out_ADDRESS_INSTRUCTION_ADDRESS" ,239 dest,"out_ICACHE_REQ_ADDRESS");240 PORT_MAP(_component,src ,"out_ADDRESS_INSTRUCTION_ADDRESS" ,241 dest+"_ifetch_queue", "in_ADDRESS_INSTRUCTION_ADDRESS" );242 227 if (_param->_have_port_instruction_ptr) 243 PORT_MAP(_component,src ,"out_ADDRESS_INST_IFETCH_PTR" ,244 dest+"_ifetch_queue", "in_ADDRESS_INST_IFETCH_PTR" );245 PORT_MAP(_component,src ,"out_ADDRESS_BRANCH_STATE" ,246 dest+"_ifetch_queue", "in_ADDRESS_BRANCH_STATE" );228 COMPONENT_MAP(_component,src ,"out_ADDRESS_INST_IFETCH_PTR" , 229 dest, "in_ADDRESS_INST_IFETCH_PTR" ); 230 COMPONENT_MAP(_component,src ,"out_ADDRESS_BRANCH_STATE" , 231 dest, "in_ADDRESS_BRANCH_STATE" ); 247 232 if (_param->_have_port_branch_update_prediction_id) 248 PORT_MAP(_component,src ,"out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID", 249 dest+"_ifetch_queue", "in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID"); 233 COMPONENT_MAP(_component,src ,"out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID", 234 dest, "in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID"); 235 236 dest = _name+"_ifetch_unit_glue"; 237 238 #ifdef POSITION 239 _component->interface_map (src ,"address", 240 dest,"address"); 241 #endif 242 243 COMPONENT_MAP(_component,src ,"out_ADDRESS_VAL" , 244 dest, "in_ICACHE_REQ_ADDRESS_VAL"); 245 COMPONENT_MAP(_component,src , "in_ADDRESS_ACK" , 246 dest,"out_ICACHE_REQ_ADDRESS_ACK"); 247 COMPONENT_MAP(_component,src ,"out_ADDRESS_INSTRUCTION_ADDRESS", 248 dest, "in_ICACHE_REQ_ADDRESS_ADDRESS"); 250 249 } 251 250 … … 302 301 #endif 303 302 304 PORT_MAP(_component,src , "in_EVENT_VAL" ,dest ,"out_EVENT_ADDRESS_VAL"); 305 PORT_MAP(_component,src ,"out_EVENT_ACK" ,dest , "in_EVENT_ADDRESS_ACK"); 306 PORT_MAP(_component,src , "in_EVENT_ADDRESS",_name, "in_EVENT_ADDRESS"); 303 COMPONENT_MAP(_component,src , "in_EVENT_VAL" ,dest ,"out_EVENT_ADDRESS_VAL"); 304 COMPONENT_MAP(_component,src ,"out_EVENT_ACK" ,dest , "in_EVENT_ADDRESS_ACK"); 305 306 307 dest = _name; 308 PORT_MAP(_component,src , "in_EVENT_ADDRESS",dest, "in_EVENT_ADDRESS"); 307 309 } 308 310 } … … 333 335 #endif 334 336 337 if (_param->_have_port_queue_ptr) 338 PORT_MAP(_component,src ,"out_ADDRESS_IFETCH_QUEUE_ID" , 339 dest,"out_ICACHE_REQ_PACKET_ID" ); 340 335 341 for (uint32_t i=0; i<_param->_nb_instruction; i++) 336 342 { … … 339 345 dest+"_address_management","address_"+toString(i)); 340 346 #endif 341 342 PORT_MAP(_component,src , "in_ADDRESS_"+toString(i)+"_INSTRUCTION_ENABLE" , 343 dest+"_address_management","out_ADDRESS_"+toString(i)+"_INSTRUCTION_ENABLE" ); 347 348 //out_ADDRESS_INSTRUCTION_ENABLE - address_management 344 349 } 345 350 346 PORT_MAP(_component,src , "in_ADDRESS_VAL" , 347 dest+"_ifetch_unit_glue" ,"out_ICACHE_REQ_QUEUE_VAL" ); 348 PORT_MAP(_component,src ,"out_ADDRESS_ACK" , 349 dest+"_ifetch_unit_glue" , "in_ICACHE_REQ_QUEUE_ACK" ); 350 if (_param->_have_port_queue_ptr) 351 PORT_MAP(_component,src ,"out_ADDRESS_IFETCH_QUEUE_ID" , 352 dest ,"out_ICACHE_REQ_PACKET_ID" ); 353 PORT_MAP(_component,src , "in_ADDRESS_INSTRUCTION_ADDRESS" , 354 dest+"_address_management","out_ADDRESS_INSTRUCTION_ADDRESS" ); 355 if (_param->_have_port_instruction_ptr) 356 PORT_MAP(_component,src , "in_ADDRESS_INST_IFETCH_PTR" , 357 dest+"_address_management","out_ADDRESS_INST_IFETCH_PTR" ); 358 PORT_MAP(_component,src , "in_ADDRESS_BRANCH_STATE" , 359 dest+"_address_management","out_ADDRESS_BRANCH_STATE" ); 360 if (_param->_have_port_branch_update_prediction_id) 361 PORT_MAP(_component,src , "in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID", 362 dest+"_address_management","out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID"); 351 dest = _name+"_ifetch_unit_glue"; 352 353 COMPONENT_MAP(_component,src , "in_ADDRESS_VAL" , 354 dest,"out_ICACHE_REQ_QUEUE_VAL"); 355 COMPONENT_MAP(_component,src ,"out_ADDRESS_ACK" , 356 dest, "in_ICACHE_REQ_QUEUE_ACK"); 357 COMPONENT_MAP(_component,src , "in_ADDRESS_INSTRUCTION_ADDRESS", 358 dest,"out_ICACHE_REQ_QUEUE_ADDRESS"); 359 // in_ADDRESS_INST_IFETCH_PTR - address_management 360 // in_ADDRESS_BRANCH_STATE - address_management 361 // in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID - address_management 363 362 } 364 363 … … 428 427 #endif 429 428 430 PORT_MAP(_component,src , "in_EVENT_RESET_VAL",dest,"out_EVENT_QUEUE_VAL");431 PORT_MAP(_component,src ,"out_EVENT_RESET_ACK",dest, "in_EVENT_QUEUE_ACK");429 COMPONENT_MAP(_component,src , "in_EVENT_RESET_VAL",dest,"out_EVENT_QUEUE_VAL"); 430 COMPONENT_MAP(_component,src ,"out_EVENT_RESET_ACK",dest, "in_EVENT_QUEUE_ACK"); 432 431 } 433 432 } … … 458 457 #endif 459 458 460 PORT_MAP(_component,src ,"out_ICACHE_REQ_VAL" ,dest ,"out_ICACHE_REQ_VAL"); 461 PORT_MAP(_component,src , "in_ICACHE_REQ_ADDRESS_VAL",dest+"_address_management","out_ADDRESS_VAL"); 462 PORT_MAP(_component,src ,"out_ICACHE_REQ_QUEUE_VAL" ,dest+"_ifetch_queue" , "in_ADDRESS_VAL" ); 463 PORT_MAP(_component,src , "in_ICACHE_REQ_ACK" ,dest , "in_ICACHE_REQ_ACK"); 464 PORT_MAP(_component,src ,"out_ICACHE_REQ_ADDRESS_ACK",dest+"_address_management", "in_ADDRESS_ACK"); 465 PORT_MAP(_component,src , "in_ICACHE_REQ_QUEUE_ACK" ,dest+"_ifetch_queue" ,"out_ADDRESS_ACK"); 466 PORT_MAP(_component,src ,"out_ICACHE_REQ_TYPE" ,dest ,"out_ICACHE_REQ_TYPE"); 459 PORT_MAP(_component,src ,"out_ICACHE_REQ_VAL" ,dest,"out_ICACHE_REQ_VAL"); 460 PORT_MAP(_component,src , "in_ICACHE_REQ_ACK" ,dest, "in_ICACHE_REQ_ACK"); 461 PORT_MAP(_component,src ,"out_ICACHE_REQ_TYPE" ,dest,"out_ICACHE_REQ_TYPE"); 462 PORT_MAP(_component,src ,"out_ICACHE_REQ_ADDRESS",dest,"out_ICACHE_REQ_ADDRESS"); 463 464 // in_ICACHE_REQ_ADDRESS_VAL - address_management 465 //out_ICACHE_REQ_QUEUE_VAL - ifetch_queue 466 //out_ICACHE_REQ_ADDRESS_ACK - address_management 467 // in_ICACHE_REQ_QUEUE_ACK - ifetch_queue 468 // in_ICACHE_REQ_ADDRESS_ADDRESS - address_management 469 //out_ICACHE_REQ_QUEUE_ADDRESS - ifetch_queue 470 467 471 } 468 472 … … 476 480 477 481 PORT_MAP(_component,src , "in_EVENT_VAL" ,dest , "in_EVENT_VAL" ); 478 PORT_MAP(_component,src ,"out_EVENT_ADDRESS_VAL",dest+"_address_management", "in_EVENT_VAL" );479 PORT_MAP(_component,src ,"out_EVENT_QUEUE_VAL" ,dest+"_ifetch_queue" , "in_EVENT_RESET_VAL" );480 482 PORT_MAP(_component,src ,"out_EVENT_ACK" ,dest ,"out_EVENT_ACK" ); 481 PORT_MAP(_component,src , "in_EVENT_ADDRESS_ACK",dest+"_address_management","out_EVENT_ACK" ); 482 PORT_MAP(_component,src , "in_EVENT_QUEUE_ACK" ,dest+"_ifetch_queue" ,"out_EVENT_RESET_ACK" ); 483 484 //out_EVENT_ADDRESS_VAL - address_management 485 //out_EVENT_QUEUE_VAL - ifetch_queue 486 // in_EVENT_ADDRESS_ACK - address_management 487 // in_EVENT_QUEUE_ACK - ifetch_queue 483 488 } 484 489 } 485 490 486 491 // ~~~~~[ Others ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 487 _component->test_map(); 492 if (DEBUG_Ifetch_unit == true) 493 _component->test_map(); 488 494 489 495 #ifdef POSITION -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/src/Parameters.cpp
r81 r85 49 49 size_address ); 50 50 _param_ifetch_unit_glue = new morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::ifetch_unit_glue:: Parameters 51 ( );51 (size_address); 52 52 53 53 log_printf(FUNC,Ifetch_unit,FUNCTION,"End"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.Common
r83 r85 17 17 #-----[ Compilation ]-------------------------------------- 18 18 INCDIR = $(SYSTEMC_INCDIR_$(SIMULATOR)) \ 19 -I. \ 19 20 -I$(DIR_MORPHEO) 20 21 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Debug_component.h
r84 r85 45 45 # define DEBUG_Decod false 46 46 # define DEBUG_Decod_queue false 47 # define DEBUG_Ifetch_unit false47 # define DEBUG_Ifetch_unit true 48 48 # define DEBUG_Address_management true 49 # define DEBUG_Ifetch_queue false50 # define DEBUG_Ifetch_unit_Glue false49 # define DEBUG_Ifetch_queue true 50 # define DEBUG_Ifetch_unit_Glue true 51 51 # define DEBUG_Prediction_unit false 52 52 # define DEBUG_Branch_Target_Buffer false -
trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Version.h
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r84 r85 1 1 #ifndef morpheo_behavioural_Version_h 2 2 #define morpheo_behavioural_Version_h 3 4 /* 5 * $Id$ 6 */ 3 7 4 8 #include "Common/include/ToString.h" … … 6 10 #define MORPHEO_MAJOR_VERSION 0 7 11 #define MORPHEO_MINOR_VERSION 2 8 #define MORPHEO_REVISION 84 9 10 // Identification : MORPHEO_MAJOR_VERSION.MORPHEO_MINOR_VERSION.MORPHEO_REVISION 12 #define MORPHEO_REVISION 85 11 13 12 14 #define MORPHEO_VERSION morpheo::toString(MORPHEO_MAJOR_VERSION)+"."+morpheo::toString(MORPHEO_MINOR_VERSION)+"."+morpheo::toString(MORPHEO_REVISION) 13 15 16 /* 17 18 [ Change Log ] 19 | 20 +-[ Major Version 0 ] 21 | 22 | SystemC Only 23 | 24 +-[ Minor Version 1 ] 25 | | 26 | | Second Architecture, change the load_store_unit and implement exception 27 | 28 +-[ Minor Version 0 ] 29 | | 30 | | First Architecture, not in this svn 31 */ 32 14 33 #endif -
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trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Version.h.sed
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r82 r85 1 1 #ifndef morpheo_behavioural_Version_h 2 2 #define morpheo_behavioural_Version_h 3 4 /* 5 * $Id$ 6 */ 3 7 4 8 #include "Common/include/ToString.h" … … 8 12 #define MORPHEO_REVISION @REVISION 9 13 10 // Identification : MORPHEO_MAJOR_VERSION.MORPHEO_MINOR_VERSION.MORPHEO_REVISION11 12 14 #define MORPHEO_VERSION morpheo::toString(MORPHEO_MAJOR_VERSION)+"."+morpheo::toString(MORPHEO_MINOR_VERSION)+"."+morpheo::toString(MORPHEO_REVISION) 13 15 16 /* 17 18 [ Change Log ] 19 | 20 +-[ Major Version 0 ] 21 | 22 | SystemC Only 23 | 24 +-[ Minor Version 1 ] 25 | | 26 | | Second Architecture, change the load_store_unit and implement exception 27 | 28 +-[ Minor Version 0 ] 29 | | 30 | | First Architecture, not in this svn 31 */ 32 14 33 #endif -
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trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Stat_create_expr.cpp
r84 r85 28 28 bool each_cycle) 29 29 { 30 if (type = TYPE_COUNTER)30 if (type == TYPE_COUNTER) 31 31 create_counter (varname,unit,description); 32 32 else -
trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_get_header.cpp
r81 r85 19 19 #define FUNCTION "Vhdl::get_header" 20 20 std::string Vhdl::get_header(uint32_t depth, 21 std::string filename)21 std::string filename) 22 22 { 23 23 log_printf(FUNC,Behavioural,FUNCTION,"Begin"); 24 24 25 std::string 26 std:: ostringstreamtext;25 std::string tab = std::string(depth,'\t'); 26 std::string text; 27 27 28 28 time_t current_time; 29 29 time (¤t_time); 30 30 31 text << tab << "-------------------------------------------------------------------------------" << std::endl32 << tab << "-- file : " << filename << std::endl 33 << tab << "-- date : " << ctime (¤t_time ) 34 << tab << "-- morpheo version : " << MORPHEO_VERSION << std::endl 35 << tab << "-- comment : it's a autogenerated file : don't modify" << std::endl 36 << tab << "-------------------------------------------------------------------------------" << std::endl;31 text += "-------------------------------------------------------------------------------\n"; 32 text += "-- "+toString(_("File : ")) + filename +"\n"; 33 text += "-- "+toString(_("Date : ")) + ctime (¤t_time ); 34 text += "-- "+toString(_("Morpheo version : ")) + MORPHEO_VERSION +"\n"; 35 text += "-- "+toString(_("Comment : ")) + _("it's a autogenerated file, don't modify") +"\n"; 36 text += "-------------------------------------------------------------------------------\n"; 37 37 38 38 log_printf(FUNC,Behavioural,FUNCTION,"End"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/src/XML_header.cpp
r81 r85 7 7 8 8 #include "Behavioural/include/XML.h" 9 #include "Behavioural/include/Version.h" 9 10 10 11 namespace morpheo { … … 20 21 time (¤t_time); 21 22 22 std::string str_time = ctime (¤t_time );23 24 23 std::string str; 25 24 … … 27 26 str += "\n"; 28 27 str += "<!--\n"; 29 str += "\tFile : " + _name+"."+_filename_extension + "\n"; 30 str += "\tDate : " + str_time; 31 str += "\tComment : it's a autogenerated file : don't modify\n"; 28 str += "\t"+toString(_("File : ")) + _name+"."+_filename_extension + "\n"; 29 str += "\t"+toString(_("Date : ")) + ctime (¤t_time ); 30 str += "\t"+toString(_("Morpheo version : ")) + MORPHEO_VERSION +"\n"; 31 str += "\t"+toString(_("Comment : ")) + toString(_("it's a autogenerated file, don't modify")) +"\n"; 32 32 str += "-->\n"; 33 33 str += "\n"; -
trunk/IPs/systemC/processor/Morpheo/Script/SelfTest.sh
r83 r85 1 #!/bin/sh 1 #!/bin/bash 2 2 3 #----------------------------------------------------------- 3 4 # $Id$ -
trunk/IPs/systemC/processor/Morpheo/Script/execute.sh
r82 r85 1 #!/bin/sh 1 #!/bin/bash 2 2 3 #----------------------------------------------------------- 3 4 # $Id$ -
trunk/IPs/systemC/processor/Morpheo/Script/execute_n.sh
r82 r85 1 #!/bin/sh 1 #!/bin/bash 2 2 3 #----------------------------------------------------------- 3 4 # $Id$ -
trunk/IPs/systemC/processor/Morpheo/Script/first_run.sh
r82 r85 1 #!/bin/sh 1 #!/bin/bash 2 2 3 #----------------------------------------------------------- 3 4 # $Id$ -
trunk/IPs/systemC/processor/Morpheo/Script/lock.sh
r82 r85 1 #!/bin/sh 1 #!/bin/bash 2 2 3 #----------------------------------------------------------- 3 4 # $Id$ -
trunk/IPs/systemC/processor/Morpheo/Script/range.sh
r82 r85 1 #!/bin/sh 1 #!/bin/bash 2 2 3 #----------------------------------------------------------- 3 4 # $Id$ -
trunk/IPs/systemC/processor/Morpheo/Script/unlock.sh
r82 r85 1 #!/bin/sh 1 #!/bin/bash 2 2 3 #----------------------------------------------------------- 3 4 # $Id$ -
trunk/IPs/systemC/processor/Morpheo/Script/version.sh
r83 r85 1 #!/bin/sh 1 #!/bin/bash 2 2 3 #----------------------------------------------------------- 3 4 # $Id$ -
trunk/IPs/systemC/processor/Morpheo/Script/xilinx_extract_info.sh
r82 r85 1 #!/bin/sh 1 #!/bin/bash 2 2 3 #----------------------------------------------------------- 3 4 # $Id$
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