Ignore:
Timestamp:
Dec 10, 2008, 7:31:39 PM (16 years ago)
Author:
rosiere
Message:

Almost complete design
with Test and test platform

Location:
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit
Files:
47 edited

Legend:

Unmodified
Added
Removed

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/SelfTest/Makefile

    r81 r88  
    2424library_clean                   : Address_management_library_clean
    2525
     26local_clean                     :
     27
    2628include                         $(DIR_COMPONENT)/Makefile.deps
    2729include                         $(DIR_MORPHEO)/Behavioural/Makefile.flags

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/SelfTest/src/main.cpp

    r81 r88  
    4444        (_nb_instruction               ,
    4545         _size_address                 ,
    46          _size_branch_update_prediction);
     46         _size_branch_update_prediction,
     47         true // is_toplevel
     48         );
    4749     
    4850      msg(_("%s"),param->print(1).c_str());

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/SelfTest/src/test.cpp

    r84 r88  
    2424#endif
    2525
     26  Tusage_t _usage = USE_ALL;
     27
     28//   _usage = usage_unset(_usage,USE_SYSTEMC              );
     29//   _usage = usage_unset(_usage,USE_VHDL                 );
     30//   _usage = usage_unset(_usage,USE_VHDL_TESTBENCH       );
     31//   _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT);
     32//   _usage = usage_unset(_usage,USE_POSITION             );
     33//   _usage = usage_unset(_usage,USE_STATISTICS           );
     34//   _usage = usage_unset(_usage,USE_INFORMATION          );
     35
    2636  Address_management * _Address_management = new Address_management
    2737    (name.c_str(),
    … …  
    3040#endif
    3141     _param,
    32      USE_ALL);
     42     _usage);
    3343 
    3444#ifdef SYSTEMC
    … …  
    6272  ALLOC_SC_SIGNAL (out_EVENT_ACK                          ,"out_EVENT_ACK                          ",Tcontrol_t        );
    6373  ALLOC_SC_SIGNAL ( in_EVENT_ADDRESS                      ," in_EVENT_ADDRESS                      ",Tgeneral_address_t);
     74  ALLOC_SC_SIGNAL ( in_EVENT_ADDRESS_NEXT                 ," in_EVENT_ADDRESS_NEXT                 ",Tgeneral_address_t);
     75  ALLOC_SC_SIGNAL ( in_EVENT_ADDRESS_NEXT_VAL             ," in_EVENT_ADDRESS_NEXT_VAL             ",Tcontrol_t        );
     76  ALLOC_SC_SIGNAL ( in_EVENT_IS_DS_TAKE                   ," in_EVENT_IS_DS_TAKE                   ",Tcontrol_t        );
    6477 
    6578  /********************************************************
    … …  
    7689  INSTANCE_SC_SIGNAL (_Address_management,out_ADDRESS_INSTRUCTION_ADDRESS        );
    7790  INSTANCE1_SC_SIGNAL(_Address_management,out_ADDRESS_INSTRUCTION_ENABLE         ,_param->_nb_instruction);
    78   if (_param->_have_port_instruction_ptr)
     91  if (_param->_have_port_inst_ifetch_ptr)
    7992  INSTANCE_SC_SIGNAL (_Address_management,out_ADDRESS_INST_IFETCH_PTR            );
    8093  INSTANCE_SC_SIGNAL (_Address_management,out_ADDRESS_BRANCH_STATE               );
    81   if (_param->_have_port_branch_update_prediction_id)
     94  if (_param->_have_port_depth)
    8295  INSTANCE_SC_SIGNAL (_Address_management,out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID);
    8396  INSTANCE_SC_SIGNAL (_Address_management,out_PREDICT_VAL                        );
    … …  
    89102  INSTANCE_SC_SIGNAL (_Address_management, in_PREDICT_PC_NEXT_IS_DS_TAKE         );
    90103  INSTANCE1_SC_SIGNAL(_Address_management, in_PREDICT_INSTRUCTION_ENABLE         ,_param->_nb_instruction);
    91   if (_param->_have_port_instruction_ptr)
     104  if (_param->_have_port_inst_ifetch_ptr)
    92105  INSTANCE_SC_SIGNAL (_Address_management, in_PREDICT_INST_IFETCH_PTR            );
    93106  INSTANCE_SC_SIGNAL (_Address_management, in_PREDICT_BRANCH_STATE               );
    94   if (_param->_have_port_branch_update_prediction_id)
     107  if (_param->_have_port_depth)
    95108  INSTANCE_SC_SIGNAL (_Address_management, in_PREDICT_BRANCH_UPDATE_PREDICTION_ID);
    96109  INSTANCE_SC_SIGNAL (_Address_management, in_EVENT_VAL                          );
    97110  INSTANCE_SC_SIGNAL (_Address_management,out_EVENT_ACK                          );
    98111  INSTANCE_SC_SIGNAL (_Address_management, in_EVENT_ADDRESS                      );
     112  INSTANCE_SC_SIGNAL (_Address_management, in_EVENT_ADDRESS_NEXT                 );
     113  INSTANCE_SC_SIGNAL (_Address_management, in_EVENT_ADDRESS_NEXT_VAL             );
     114  INSTANCE_SC_SIGNAL (_Address_management, in_EVENT_IS_DS_TAKE                   );
    99115
    100116  msg(_("<%s> : Start Simulation ............\n"),name.c_str());
    … …  
    143159  Tcontrol_t      nn_val  = false;
    144160
    145   Tgeneral_data_t c_addr  = 0x100;
    146   Tgeneral_data_t n_addr  = 0x100;
    147   Tgeneral_data_t nn_addr = 0x100;
     161  Tgeneral_data_t c_addr  = 0x100>>2;
     162  Tgeneral_data_t n_addr  = 0x100>>2;
     163  Tgeneral_data_t nn_addr = 0x100>>2;
    148164
    149165  Tcontrol_t      c_enable [_param->_nb_instruction];
    … …  
    159175
    160176  LABEL("Send Reset");
    161   do
    162     {
    163       in_EVENT_VAL    ->write(1);
    164       in_EVENT_ADDRESS->write(n_addr);
    165       SC_START(1); 
    166     } while (out_EVENT_ACK->read() == false);
    167   in_EVENT_VAL    ->write(0);
     177//   do
     178//     {
     179//       in_EVENT_VAL             ->write(1);
     180//       in_EVENT_ADDRESS         ->write(n_addr);
     181//       in_EVENT_ADDRESS_NEXT    ->write(nn_addr);
     182//       in_EVENT_ADDRESS_NEXT_VAL->write(0);
     183//       in_EVENT_IS_DS_TAKE      ->write(0);
     184//       SC_START(1); 
     185//     } while (out_EVENT_ACK->read() == false);
     186//   in_EVENT_VAL    ->write(0);
    168187
    169188  n_val = 1;
    … …  
    206225      }
    207226
    208       in_EVENT_VAL    ->write((rand()%100)<percent_transaction_event  );
    209       in_EVENT_ADDRESS->write(0x100);
     227      in_EVENT_VAL             ->write((rand()%100)<percent_transaction_event  );
     228      in_EVENT_ADDRESS         ->write(0x77);
     229      in_EVENT_ADDRESS_NEXT    ->write(0x171);
     230      Tcontrol_t next_val = rand()%2;
     231      in_EVENT_ADDRESS_NEXT_VAL->write(next_val);
     232      in_EVENT_IS_DS_TAKE      ->write(next_val);
    210233
    211234      //-------------------------------------------------
    … …  
    238261          for (uint32_t i=0; i<_param->_nb_instruction; i++)
    239262          TEST(Tcontrol_t        ,out_ADDRESS_INSTRUCTION_ENABLE     [i] ->read(),c_enable[i]);
    240           if (_param->_have_port_instruction_ptr)
     263          if (_param->_have_port_inst_ifetch_ptr)
    241264          TEST(Tinst_ifetch_ptr_t,out_ADDRESS_INST_IFETCH_PTR            ->read(),0);
    242265          TEST(Tbranch_state_t   ,out_ADDRESS_BRANCH_STATE               ->read(),0);
    243           if (_param->_have_port_branch_update_prediction_id)
     266          if (_param->_have_port_depth)
    244267          TEST(Tprediction_ptr_t ,out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID->read(),0);
    245268
    … …  
    272295          LABEL("EVENT      : Transaction accepted");
    273296
    274           c_val           = false;
    275           n_val           = true;
    276           nn_val          = false;
    277 
    278           n_addr         = in_EVENT_ADDRESS->read();
    279           n_is_ds_take   = 0;
     297          c_val        = false;
     298          n_val        = true;
     299          n_addr       = in_EVENT_ADDRESS         ->read();
     300          n_is_ds_take = in_EVENT_IS_DS_TAKE      ->read();
     301          nn_val       = in_EVENT_ADDRESS_NEXT_VAL->read();
     302          nn_addr      = in_EVENT_ADDRESS_NEXT    ->read();
     303          nn_is_ds_take= false;
     304//           nn_val = false;
     305//           n_is_ds_take = 0;
    280306
    281307          n_enable [0] = 1;
    282           for (uint32_t i=1; i<_param->_nb_instruction; i++)
    283             n_enable [i] = 0;
     308          for (uint32_t i=1; i<_param->_nb_instruction; i++)
     309            n_enable [i] = 0;
    284310        }
    285311
    … …  
    347373  delete    out_EVENT_ACK                          ;
    348374  delete     in_EVENT_ADDRESS                      ;
     375  delete     in_EVENT_ADDRESS_NEXT                 ;
     376  delete     in_EVENT_ADDRESS_NEXT_VAL             ;
     377  delete     in_EVENT_IS_DS_TAKE                   ;
    349378#endif
    350379

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/include/Address_management.h

    r84 r88  
    9191  public    : SC_OUT(Tcontrol_t        )    * out_EVENT_ACK                           ;
    9292  public    : SC_IN (Tgeneral_address_t)    *  in_EVENT_ADDRESS                       ;
     93  public    : SC_IN (Tgeneral_address_t)    *  in_EVENT_ADDRESS_NEXT                  ;
     94  public    : SC_IN (Tcontrol_t        )    *  in_EVENT_ADDRESS_NEXT_VAL              ;
     95  public    : SC_IN (Tcontrol_t        )    *  in_EVENT_IS_DS_TAKE                    ;
    9396
    9497    // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~   

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/include/Parameters.h

    r81 r88  
    2424    //-----[ fields ]------------------------------------------------------------
    2525  public : uint32_t _nb_instruction               ;
    26   public : uint32_t _size_address                 ;
    27   public : uint32_t _size_branch_update_prediction;
     26//public : uint32_t _size_address                 ;
     27//public : uint32_t _size_branch_update_prediction;
    2828
    29   public : uint32_t _size_instruction_ptr                 ;
    30 
    31   public : bool     _have_port_instruction_ptr            ;
    32   public : bool     _have_port_branch_update_prediction_id;
     29//public : uint32_t _size_instruction_ptr                 ;
     30//
     31//public : bool     _have_port_instruction_ptr            ;
     32//public : bool     _have_port_branch_update_prediction_id;
    3333
    3434    //-----[ methods ]-----------------------------------------------------------
    3535  public : Parameters  (uint32_t nb_instruction,
    3636                        uint32_t size_address  ,
    37                         uint32_t size_branch_update_prediction);
     37                        uint32_t size_branch_update_prediction,
     38                        bool     is_toplevel=false);
    3839
    3940//   public : Parameters  (Parameters & param) ;
    4041  public : ~Parameters () ;
     42
     43  public :        void            copy       (void);
    4144
    4245  public :        Parameters_test msg_error  (void);

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management.cpp

    r81 r88  
    3838    log_printf(FUNC,Address_management,FUNCTION,"Begin");
    3939
     40#if DEBUG_Address_management == true
     41    log_printf(INFO,Address_management,FUNCTION,_("<%s> Parameters"),_name.c_str());
     42
     43    std::cout << *param << std::endl;
     44#endif   
     45
    4046    log_printf(INFO,Address_management,FUNCTION,"Allocation");
    4147
    … …  
    4753
    4854#ifdef STATISTICS
    49     if (_usage & USE_STATISTICS)
     55    if (usage_is_set(_usage,USE_STATISTICS))
    5056      {
    5157        log_printf(INFO,Address_management,FUNCTION,"Allocation of statistics");
    … …  
    5662
    5763#ifdef VHDL
    58     if (_usage & USE_VHDL)
     64    if (usage_is_set(_usage,USE_VHDL))
    5965      {
    6066        // generate the vhdl
    … …  
    6672
    6773#ifdef SYSTEMC
    68     if (_usage & USE_SYSTEMC)
     74    if (usage_is_set(_usage,USE_SYSTEMC))
    6975      {
    7076        // Affect output constant
    … …  
    94100#endif
    95101      }
     102
    96103    log_printf(FUNC,Address_management,FUNCTION,"End");
    97104  };
    … …  
    104111
    105112#ifdef STATISTICS
    106     if (_usage & USE_STATISTICS)
     113    if (usage_is_set(_usage,USE_STATISTICS))
    107114      {
    108115        statistics_deallocation();

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_allocation.cpp

    r81 r88  
    6262      ALLOC_VALACK_OUT (out_ADDRESS_VAL                        ,VAL);
    6363      ALLOC_VALACK_IN  ( in_ADDRESS_ACK                        ,ACK);
    64       ALLOC_SIGNAL_OUT (out_ADDRESS_INSTRUCTION_ADDRESS        ,"instruction_address"        ,Tgeneral_address_t,_param->_size_address                 );
    65       ALLOC_SIGNAL_OUT (out_ADDRESS_INST_IFETCH_PTR            ,"inst_ifetch_ptr"            ,Tinst_ifetch_ptr_t,_param->_size_instruction_ptr         );
     64      ALLOC_SIGNAL_OUT (out_ADDRESS_INSTRUCTION_ADDRESS        ,"instruction_address"        ,Tgeneral_address_t,_param->_size_instruction_address     );
     65      ALLOC_SIGNAL_OUT (out_ADDRESS_INST_IFETCH_PTR            ,"inst_ifetch_ptr"            ,Tinst_ifetch_ptr_t,_param->_size_inst_ifetch_ptr         );
    6666      ALLOC_SIGNAL_OUT (out_ADDRESS_BRANCH_STATE               ,"branch_state"               ,Tbranch_state_t   ,_param->_size_branch_state            );
    67       ALLOC_SIGNAL_OUT (out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_branch_update_prediction);
     67      ALLOC_SIGNAL_OUT (out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth);
    6868    }
    6969
    … …  
    8080      ALLOC_VALACK_OUT (out_PREDICT_VAL                        ,VAL);
    8181      ALLOC_VALACK_IN  ( in_PREDICT_ACK                        ,ACK);
    82       ALLOC_SIGNAL_OUT (out_PREDICT_PC_PREVIOUS                ,"pc_previous"                ,Tgeneral_address_t,_param->_size_address);
    83       ALLOC_SIGNAL_OUT (out_PREDICT_PC_CURRENT                 ,"pc_current"                 ,Tgeneral_address_t,_param->_size_address);
     82      ALLOC_SIGNAL_OUT (out_PREDICT_PC_PREVIOUS                ,"pc_previous"                ,Tgeneral_address_t,_param->_size_instruction_address);
     83      ALLOC_SIGNAL_OUT (out_PREDICT_PC_CURRENT                 ,"pc_current"                 ,Tgeneral_address_t,_param->_size_instruction_address);
    8484      ALLOC_SIGNAL_OUT (out_PREDICT_PC_CURRENT_IS_DS_TAKE      ,"pc_current_is_ds_take"      ,Tcontrol_t        ,1);
    85       ALLOC_SIGNAL_IN  ( in_PREDICT_PC_NEXT                    ,"pc_next"                    ,Tgeneral_address_t,_param->_size_address);
     85      ALLOC_SIGNAL_IN  ( in_PREDICT_PC_NEXT                    ,"pc_next"                    ,Tgeneral_address_t,_param->_size_instruction_address);
    8686      ALLOC_SIGNAL_IN  ( in_PREDICT_PC_NEXT_IS_DS_TAKE         ,"pc_next_is_ds_take"         ,Tcontrol_t        ,1);
    87       ALLOC_SIGNAL_IN  ( in_PREDICT_INST_IFETCH_PTR            ,"inst_ifetch_ptr"            ,Tinst_ifetch_ptr_t,_param->_size_instruction_ptr);
     87      ALLOC_SIGNAL_IN  ( in_PREDICT_INST_IFETCH_PTR            ,"inst_ifetch_ptr"            ,Tinst_ifetch_ptr_t,_param->_size_inst_ifetch_ptr);
    8888      ALLOC_SIGNAL_IN  ( in_PREDICT_BRANCH_STATE               ,"branch_state"               ,Tbranch_state_t   ,_param->_size_branch_state);
    89       ALLOC_SIGNAL_IN  ( in_PREDICT_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_branch_update_prediction);
     89      ALLOC_SIGNAL_IN  ( in_PREDICT_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth);
    9090    }
    9191    {
    … …  
    9999      ALLOC_INTERFACE("event", IN, SOUTH, "Event (miss, exception ...)");
    100100
    101       ALLOC_VALACK_IN ( in_EVENT_VAL    ,VAL);
    102       ALLOC_VALACK_OUT(out_EVENT_ACK    ,ACK);
    103       ALLOC_SIGNAL_IN ( in_EVENT_ADDRESS,"address",Tgeneral_address_t,_param->_size_address);
     101      ALLOC_VALACK_IN ( in_EVENT_VAL          ,VAL);
     102      ALLOC_VALACK_OUT(out_EVENT_ACK          ,ACK);
     103      ALLOC_SIGNAL_IN ( in_EVENT_ADDRESS         ,"address"         ,Tgeneral_address_t,_param->_size_instruction_address);
     104      ALLOC_SIGNAL_IN ( in_EVENT_ADDRESS_NEXT    ,"address_next"    ,Tgeneral_address_t,_param->_size_instruction_address);
     105      ALLOC_SIGNAL_IN ( in_EVENT_ADDRESS_NEXT_VAL,"address_next_val",Tcontrol_t,1);
     106      ALLOC_SIGNAL_IN ( in_EVENT_IS_DS_TAKE      ,"is_ds_take"      ,Tcontrol_t,1);
    104107    }
    105108
     109    // ~~~~~[ Internal  ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~   
     110    if (usage_is_set(_usage,USE_SYSTEMC))
     111      {
     112        reg_PC_CURRENT_INSTRUCTION_ENABLE = new Tcontrol_t [_param->_nb_instruction];
     113        reg_PC_NEXT_INSTRUCTION_ENABLE    = new Tcontrol_t [_param->_nb_instruction];
     114      }
     115
    106116    // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~   
    107     reg_PC_CURRENT_INSTRUCTION_ENABLE = new Tcontrol_t [_param->_nb_instruction];
    108     reg_PC_NEXT_INSTRUCTION_ENABLE    = new Tcontrol_t [_param->_nb_instruction];
    109 
    110117#ifdef POSITION
    111     _component->generate_file();
     118     if (usage_is_set(_usage,USE_POSITION))
     119       _component->generate_file();
    112120#endif
    113121

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_deallocation.cpp

    r81 r88  
    2323    log_printf(FUNC,Address_management,FUNCTION,"Begin");
    2424
    25     if (_usage & USE_SYSTEMC)
     25    if (usage_is_set(_usage,USE_SYSTEMC))
    2626      {
    2727        delete    in_CLOCK ;
    … …  
    3232        delete    out_ADDRESS_INSTRUCTION_ADDRESS        ;
    3333        delete [] out_ADDRESS_INSTRUCTION_ENABLE         ;
    34         if (_param->_have_port_instruction_ptr)
     34        if (_param->_have_port_inst_ifetch_ptr)
    3535        delete    out_ADDRESS_INST_IFETCH_PTR            ;
    3636        delete    out_ADDRESS_BRANCH_STATE               ;
    37         if (_param->_have_port_branch_update_prediction_id)
     37        if (_param->_have_port_depth)
    3838        delete    out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID;
    3939        delete    out_PREDICT_VAL                        ;
    … …  
    4545        delete     in_PREDICT_PC_NEXT_IS_DS_TAKE         ;
    4646        delete []  in_PREDICT_INSTRUCTION_ENABLE         ;
    47         if (_param->_have_port_instruction_ptr)
     47        if (_param->_have_port_inst_ifetch_ptr)
    4848        delete     in_PREDICT_INST_IFETCH_PTR            ;
    4949        delete     in_PREDICT_BRANCH_STATE               ;
    50         if (_param->_have_port_branch_update_prediction_id)
     50        if (_param->_have_port_depth)
    5151        delete     in_PREDICT_BRANCH_UPDATE_PREDICTION_ID;
    5252        delete     in_EVENT_VAL                          ;
    5353        delete    out_EVENT_ACK                          ;
    5454        delete     in_EVENT_ADDRESS                      ;
     55        delete     in_EVENT_ADDRESS_NEXT                 ;
     56        delete     in_EVENT_ADDRESS_NEXT_VAL             ;
     57        delete     in_EVENT_IS_DS_TAKE                   ;
     58     
     59        // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~   
     60        if (usage_is_set(_usage,USE_SYSTEMC))
     61          {
     62            delete reg_PC_CURRENT_INSTRUCTION_ENABLE;
     63            delete reg_PC_NEXT_INSTRUCTION_ENABLE   ;
     64          }
    5565      }
    5666
    57     // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~   
    58     delete reg_PC_CURRENT_INSTRUCTION_ENABLE;
    59     delete reg_PC_NEXT_INSTRUCTION_ENABLE   ;
    6067
    6168    // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~   

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_end_cycle.cpp

    r81 r88  
    2525
    2626#ifdef STATISTICS
    27     _stat->end_cycle();
     27    if (usage_is_set(_usage,USE_STATISTICS))
     28      _stat->end_cycle();
    2829#endif   
    2930
    … …  
    3132    // Evaluation before read the ouput signal
    3233//  sc_start(0);
    33     _interfaces->testbench();
     34    if (usage_is_set(_usage,USE_VHDL_TESTBENCH))
     35      _interfaces->testbench();
    3436#endif
    3537

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_genMoore.cpp

    r84 r88  
    3232    PORT_WRITE(out_ADDRESS_VAL                        ,internal_ADDRESS_VAL                      );
    3333    PORT_WRITE(out_ADDRESS_INSTRUCTION_ADDRESS        ,reg_PC_CURRENT                            );
    34     if (_param->_have_port_instruction_ptr)
     34    if (_param->_have_port_inst_ifetch_ptr)
    3535    PORT_WRITE(out_ADDRESS_INST_IFETCH_PTR            ,reg_PC_CURRENT_INST_IFETCH_PTR            );
    3636    PORT_WRITE(out_ADDRESS_BRANCH_STATE               ,reg_PC_CURRENT_BRANCH_STATE               );
    37     if (_param->_have_port_branch_update_prediction_id)
     37    if (_param->_have_port_depth)
    3838    PORT_WRITE(out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID,reg_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID);
    3939

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_transition.cpp

    r84 r88  
    2222  void Address_management::transition (void)
    2323  {
    24     log_printf(FUNC,Address_management,FUNCTION,"Begin");
     24    log_begin(Address_management,FUNCTION);
     25    log_function(Address_management,FUNCTION,_name.c_str());
    2526
    2627    if (PORT_READ(in_NRESET) == 0)
    … …  
    2829        // nothing is valid
    2930        reg_PC_CURRENT_VAL   = 0;
    30         reg_PC_NEXT_VAL      = 0;
     31
     32        reg_PC_NEXT_VAL      = 1;
     33        reg_PC_NEXT          = 0x100>>2;
     34
    3135        reg_PC_NEXT_NEXT_VAL = 0;
    3236      }
    … …  
    4044            for (uint32_t i=0; i<_param->_nb_instruction; i++)
    4145            reg_PC_NEXT_INSTRUCTION_ENABLE [i] = PORT_READ(in_PREDICT_INSTRUCTION_ENABLE [i]);
    42             if (_param->_have_port_instruction_ptr)
     46            if (_param->_have_port_inst_ifetch_ptr)
    4347            reg_PC_NEXT_INST_IFETCH_PTR             = PORT_READ(in_PREDICT_INST_IFETCH_PTR            );
    4448            reg_PC_NEXT_BRANCH_STATE                = PORT_READ(in_PREDICT_BRANCH_STATE               );
    45             if (_param->_have_port_branch_update_prediction_id)
     49            if (_param->_have_port_depth)
    4650            reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID = PORT_READ(in_PREDICT_BRANCH_UPDATE_PREDICTION_ID);
    4751           
    … …  
    5155
    5256#ifdef STATISTICS
    53             (*_stat_nb_transaction_predict) ++;
     57            if (usage_is_set(_usage,USE_STATISTICS))
     58              (*_stat_nb_transaction_predict) ++;
    5459#endif
    5560          }
    … …  
    6267          {
    6368#ifdef STATISTICS
    64             if (reg_PC_CURRENT_VAL)
    65               {
    66                 (*_stat_nb_transaction_address) ++;
    67 
    68                 for (uint32_t i=0; i<_param->_nb_instruction; i++)
    69                   if (reg_PC_CURRENT_INSTRUCTION_ENABLE [i] == true)
    70                     (*_stat_sum_packet_size) ++;
    71               }
     69            if (usage_is_set(_usage,USE_STATISTICS))
     70              if (reg_PC_CURRENT_VAL)
     71                {
     72                  (*_stat_nb_transaction_address) ++;
     73                 
     74                  for (uint32_t i=0; i<_param->_nb_instruction; i++)
     75                    if (reg_PC_CURRENT_INSTRUCTION_ENABLE [i] == true)
     76                      (*_stat_sum_packet_size) ++;
     77                }
    7278#endif
    7379
    … …  
    110116        if (PORT_READ(in_EVENT_VAL) and internal_EVENT_ACK)
    111117          {
    112             log_printf(TRACE,Address_management,FUNCTION,"EVENT : Transaction");
     118            log_printf(TRACE,Address_management,FUNCTION,"  * EVENT : Transaction");
     119            log_printf(TRACE,Address_management,FUNCTION,"    * IS_DS_TAKE       : %d"  ,PORT_READ(in_EVENT_IS_DS_TAKE      ));
     120            log_printf(TRACE,Address_management,FUNCTION,"    * ADDRESS          : %.8x (%.8x)",PORT_READ(in_EVENT_ADDRESS         ),PORT_READ(in_EVENT_ADDRESS         )<<2);
     121            log_printf(TRACE,Address_management,FUNCTION,"    * ADDRESS_NEXT     : %.8x (%.8x)",PORT_READ(in_EVENT_ADDRESS_NEXT    ),PORT_READ(in_EVENT_ADDRESS_NEXT    )<<2);
     122            log_printf(TRACE,Address_management,FUNCTION,"    * ADDRESS_NEXT_VAL : %d"  ,PORT_READ(in_EVENT_ADDRESS_NEXT_VAL));
    113123            reg_PC_CURRENT_VAL                      = 0;
    114124            reg_PC_NEXT_VAL                         = 1;
    … …  
    118128            //  * load   miss speculation : the load is execute, the event_address is the next address (also the destination of branch)
    119129            //  * exception               : goto the first instruction of exception handler (also is not in delay slot).
    120             reg_PC_NEXT_IS_DS_TAKE                  = 0;
     130
     131            reg_PC_NEXT_IS_DS_TAKE                  = PORT_READ(in_EVENT_IS_DS_TAKE);
    121132//          reg_PC_NEXT_INST_IFETCH_PTR             = 0;
    122133//          reg_PC_NEXT_BRANCH_STATE                = BRANCH_STATE_NONE;
    123134//          reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID = 0;
    124135           
    125 //          reg_PC_NEXT_INSTRUCTION_ENABLE [0]      = 1; // only the instruction at the event address is valid, because we have no information on the branch presence in the instruction bundle.
    126 //          for (uint32_t i=1; i<_param->_nb_instruction; i++)
    127 //            reg_PC_NEXT_INSTRUCTION_ENABLE [i] = 0;
     136            reg_PC_NEXT_INSTRUCTION_ENABLE [0]      = 1; // only the instruction at the event address is valid, because we have no information on the branch presence in the instruction bundle.
     137            for (uint32_t i=1; i<_param->_nb_instruction; i++)
     138              reg_PC_NEXT_INSTRUCTION_ENABLE [i] = 0;
    128139
    129             reg_PC_NEXT_NEXT_VAL                    = 0; // cancel all prediction (event is send at the predict unit)
     140            reg_PC_NEXT_NEXT_VAL                    = PORT_READ(in_EVENT_ADDRESS_NEXT_VAL);
     141            reg_PC_NEXT_NEXT                        = PORT_READ(in_EVENT_ADDRESS_NEXT);
     142            reg_PC_NEXT_NEXT_IS_DS_TAKE             = 0;//??
     143
     144            // Note : is_ds_take = address_next_val
     145            // Because, is not ds take, can continue in sequence
     146
     147#ifdef DEBUG_TEST
     148            if (PORT_READ(in_EVENT_ADDRESS_NEXT_VAL) and not PORT_READ(in_EVENT_IS_DS_TAKE))
     149              throw ERRORMORPHEO(FUNCTION,_("Event : address_next_next_val but next is not a ds take"));
     150#endif
    130151
    131152#ifdef STATISTICS
    132             (*_stat_nb_transaction_event) ++;
     153            if (usage_is_set(_usage,USE_STATISTICS))
     154              (*_stat_nb_transaction_event) ++;
    133155#endif
    134156          }
    135157      }
    136158
    137 #if DEBUG >= DEBUG_TRACE
    138     log_printf(TRACE,Address_management,FUNCTION,"Address_Management : ");
    139     log_printf(TRACE,Address_management,FUNCTION,"Current   : %d %d 0x%x",reg_PC_CURRENT_VAL, reg_PC_CURRENT_IS_DS_TAKE, reg_PC_CURRENT);
    140     log_printf(TRACE,Address_management,FUNCTION,"Next      : %d %d 0x%x",reg_PC_NEXT_VAL, reg_PC_NEXT_IS_DS_TAKE, reg_PC_NEXT);   
    141     log_printf(TRACE,Address_management,FUNCTION,"Next_Next : %d %d 0x%x",reg_PC_NEXT_NEXT_VAL, reg_PC_NEXT_NEXT_IS_DS_TAKE, reg_PC_NEXT_NEXT);   
     159#if defined(DEBUG) and (DEBUG >= DEBUG_TRACE)
     160    log_printf(TRACE,Address_management,FUNCTION,"  * Dump PC");
     161    log_printf(TRACE,Address_management,FUNCTION,"    * Current   : %d %d 0x%.8x (%.8x)",reg_PC_CURRENT_VAL  , reg_PC_CURRENT_IS_DS_TAKE  , reg_PC_CURRENT  , reg_PC_CURRENT  <<2);
     162    log_printf(TRACE,Address_management,FUNCTION,"    * Next      : %d %d 0x%.8x (%.8x)",reg_PC_NEXT_VAL     , reg_PC_NEXT_IS_DS_TAKE     , reg_PC_NEXT     , reg_PC_NEXT     <<2);   
     163    log_printf(TRACE,Address_management,FUNCTION,"    * Next_Next : %d %d 0x%.8x (%.8x)",reg_PC_NEXT_NEXT_VAL, reg_PC_NEXT_NEXT_IS_DS_TAKE, reg_PC_NEXT_NEXT, reg_PC_NEXT_NEXT<<2);   
    142164#endif
    143165
    … …  
    145167    end_cycle ();
    146168#endif
    147 
    148     log_printf(FUNC,Address_management,FUNCTION,"End");
     169   
     170    log_end(Address_management,FUNCTION);
    149171  };
    150172

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Parameters.cpp

    r81 r88  
    2121  Parameters::Parameters (uint32_t nb_instruction,
    2222                          uint32_t size_address  ,
    23                           uint32_t size_branch_update_prediction)
     23                          uint32_t size_branch_update_prediction,
     24                          bool     is_toplevel)
    2425  {
    2526    log_printf(FUNC,Address_management,FUNCTION,"Begin");
    2627
    27     _nb_instruction                        = nb_instruction               ;
    28     _size_address                          = size_address                 ;
    29     _size_branch_update_prediction         = size_branch_update_prediction;
    30 
    31     _size_instruction_ptr                  = log2(nb_instruction);
    32 
    33     _have_port_instruction_ptr             = _size_instruction_ptr > 0;
    34     _have_port_branch_update_prediction_id = size_branch_update_prediction > 0;
     28    _nb_instruction = nb_instruction               ;
    3529
    3630    test();
     31
     32    if (is_toplevel)
     33      {
     34        _size_instruction_address  = size_address                 ;
     35        _size_depth                = size_branch_update_prediction;
     36        _size_inst_ifetch_ptr      = log2(nb_instruction);
     37       
     38        _have_port_inst_ifetch_ptr = _size_inst_ifetch_ptr > 0;
     39        _have_port_depth           = _size_depth > 0;
     40
     41        copy();
     42      }
     43
    3744    log_printf(FUNC,Address_management,FUNCTION,"End");
    3845  };
    … …  
    5562  };
    5663
     64#undef  FUNCTION
     65#define FUNCTION "Address_management::copy"
     66  void Parameters::copy (void)
     67  {
     68    log_printf(FUNC,Address_management,FUNCTION,"Begin");
     69    log_printf(FUNC,Address_management,FUNCTION,"End");
     70  };
     71
    5772}; // end namespace address_management
    5873}; // end namespace ifetch_unit

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Parameters_print.cpp

    r81 r88  
    2424    log_printf(FUNC,Address_management,FUNCTION,"Begin");
    2525
    26     XML xml ("address_management");
     26//     XML xml ("address_management");
    2727
    28     xml.balise_open("address_management");
    29     xml.singleton_begin("nb_instruction               "); xml.attribut("value",toString(_nb_instruction               )); xml.singleton_end();
    30     xml.singleton_begin("size_address                 "); xml.attribut("value",toString(_size_address                 )); xml.singleton_end();
    31     xml.singleton_begin("size_branch_update_prediction"); xml.attribut("value",toString(_size_branch_update_prediction)); xml.singleton_end();
    32     xml.balise_close();
     28//     xml.balise_open("address_management");
     29//     xml.singleton_begin("nb_instruction               "); xml.attribut("value",toString(_nb_instruction               )); xml.singleton_end();
     30// //  xml.singleton_begin("size_address                 "); xml.attribut("value",toString(_size_address                 )); xml.singleton_end();
     31// //  xml.singleton_begin("size_branch_update_prediction"); xml.attribut("value",toString(_size_branch_update_prediction)); xml.singleton_end();
     32//     xml.balise_close();
     33
     34//     return xml.get_body(depth);
     35
     36    std::string str = "";
    3337
    3438    log_printf(FUNC,Address_management,FUNCTION,"End");
    35    
    36     return xml.get_body(depth);
     39
     40    return str;
    3741  };
    3842

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/SelfTest/Makefile

    r81 r88  
    2424library_clean                   : Ifetch_queue_library_clean
    2525
     26local_clean                     :
     27
    2628include                         $(DIR_COMPONENT)/Makefile.deps
    2729include                         $(DIR_MORPHEO)/Behavioural/Makefile.flags

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/SelfTest/src/main.cpp

    r81 r88  
    4747         _nb_instruction                ,
    4848         _size_branch_update_prediction ,
    49          _size_general_data             );
     49         _size_general_data             ,
     50         true // is_toplevel
     51         );
    5052     
    5153      msg(_("%s"),param->print(1).c_str());

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/SelfTest/src/test.cpp

    r82 r88  
    4141#endif
    4242
     43  Tusage_t _usage = USE_ALL;
     44
     45//   _usage = usage_unset(_usage,USE_SYSTEMC              );
     46//   _usage = usage_unset(_usage,USE_VHDL                 );
     47//   _usage = usage_unset(_usage,USE_VHDL_TESTBENCH       );
     48//   _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT);
     49//   _usage = usage_unset(_usage,USE_POSITION             );
     50//   _usage = usage_unset(_usage,USE_STATISTICS           );
     51//   _usage = usage_unset(_usage,USE_INFORMATION          );
     52
    4353  Ifetch_queue * _Ifetch_queue = new Ifetch_queue
    4454    (name.c_str(),
    … …  
    4757#endif
    4858     _param,
    49      USE_ALL);
     59     _usage);
    5060 
    5161#ifdef SYSTEMC
    … …  
    93103  INSTANCE_SC_SIGNAL (_Ifetch_queue, in_ADDRESS_VAL                        );
    94104  INSTANCE_SC_SIGNAL (_Ifetch_queue,out_ADDRESS_ACK                        );
    95   if (_param->_have_port_queue_ptr)
     105  if (_param->_have_port_ifetch_queue_ptr)
    96106  INSTANCE_SC_SIGNAL (_Ifetch_queue,out_ADDRESS_IFETCH_QUEUE_ID            );
    97107  INSTANCE1_SC_SIGNAL(_Ifetch_queue, in_ADDRESS_INSTRUCTION_ENABLE         ,_param->_nb_instruction);
    98108  INSTANCE_SC_SIGNAL (_Ifetch_queue, in_ADDRESS_INSTRUCTION_ADDRESS        );
    99   if (_param->_have_port_instruction_ptr)
     109  if (_param->_have_port_inst_ifetch_ptr)
    100110  INSTANCE_SC_SIGNAL (_Ifetch_queue, in_ADDRESS_INST_IFETCH_PTR            );
    101111  INSTANCE_SC_SIGNAL (_Ifetch_queue, in_ADDRESS_BRANCH_STATE               );
    102   if (_param->_have_port_branch_update_prediction_id)
     112  if (_param->_have_port_depth)
    103113  INSTANCE_SC_SIGNAL (_Ifetch_queue, in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID);
    104114  INSTANCE1_SC_SIGNAL(_Ifetch_queue,out_DECOD_VAL                          ,_param->_nb_instruction);
    … …  
    106116  INSTANCE1_SC_SIGNAL(_Ifetch_queue,out_DECOD_INSTRUCTION                  ,_param->_nb_instruction);
    107117  INSTANCE_SC_SIGNAL (_Ifetch_queue,out_DECOD_ADDRESS                      );
    108   if (_param->_have_port_instruction_ptr)
     118  if (_param->_have_port_inst_ifetch_ptr)
    109119  INSTANCE_SC_SIGNAL (_Ifetch_queue,out_DECOD_INST_IFETCH_PTR              );
    110120  INSTANCE_SC_SIGNAL (_Ifetch_queue,out_DECOD_BRANCH_STATE                 );
    111   if (_param->_have_port_branch_update_prediction_id)
     121  if (_param->_have_port_depth)
    112122  INSTANCE_SC_SIGNAL (_Ifetch_queue,out_DECOD_BRANCH_UPDATE_PREDICTION_ID  );
    113123  INSTANCE_SC_SIGNAL (_Ifetch_queue,out_DECOD_EXCEPTION                    );
    114124  INSTANCE_SC_SIGNAL (_Ifetch_queue, in_ICACHE_RSP_VAL                     );
    115125  INSTANCE_SC_SIGNAL (_Ifetch_queue,out_ICACHE_RSP_ACK                     );
    116   if (_param->_have_port_queue_ptr)
     126  if (_param->_have_port_ifetch_queue_ptr)
    117127  INSTANCE_SC_SIGNAL (_Ifetch_queue, in_ICACHE_RSP_PACKET_ID               );
    118128  INSTANCE1_SC_SIGNAL(_Ifetch_queue, in_ICACHE_RSP_INSTRUCTION             ,_param->_nb_instruction);
    … …  
    180190          for (uint32_t i=0; i<_param->_nb_instruction; i++)
    181191          in_ADDRESS_INSTRUCTION_ENABLE [i]      ->write(i<=nb_inst_enable);
    182           if (_param->_have_port_instruction_ptr)
     192          if (_param->_have_port_inst_ifetch_ptr)
    183193          in_ADDRESS_INST_IFETCH_PTR             ->write(address%_param->_nb_instruction);
    184194          in_ADDRESS_BRANCH_STATE                ->write(address%SIZE_BRANCH_STATE);
    185           if (_param->_have_port_branch_update_prediction_id)
    186           in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID ->write(address%_param->_size_branch_update_prediction);
     195          if (_param->_have_port_depth)
     196          in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID ->write(address%_param->_size_depth);
    187197
    188198          // =====
    … …  
    241251             
    242252              list_wait_decod.push_back(address);
    243 //            list_req_icache.insert(, entry_t((_param->_have_port_queue_ptr)?out_ADDRESS_IFETCH_QUEUE_ID->read():0,address));
     253//            list_req_icache.insert(, entry_t((_param->_have_port_ifetch_queue_ptr)?out_ADDRESS_IFETCH_QUEUE_ID->read():0,address));
    244254
    245255              uint32_t cycle = ((rand()%100)<percent_icache_hit)?1:icache_miss_penality;
    … …  
    252262
    253263              LABEL("  * list_req_icache : %d",list_req_icache.size());
    254               list_req_icache.insert(it,entry_t(cycle,(_param->_have_port_queue_ptr)?out_ADDRESS_IFETCH_QUEUE_ID->read():0,address));
     264              list_req_icache.insert(it,entry_t(cycle,(_param->_have_port_ifetch_queue_ptr)?out_ADDRESS_IFETCH_QUEUE_ID->read():0,address));
    255265              LABEL("  * list_req_icache : %d",list_req_icache.size());       
    256266              address += 4*_param->_nb_instruction;
    … …  
    292302              TEST(Tgeneral_data_t   ,out_DECOD_ADDRESS                    ->read(), addr);
    293303              TEST(Tbranch_state_t   ,out_DECOD_BRANCH_STATE               ->read(),addr%SIZE_BRANCH_STATE);
    294               if (_param->_have_port_instruction_ptr)
     304              if (_param->_have_port_inst_ifetch_ptr)
    295305              TEST(Tinst_ifetch_ptr_t,out_DECOD_INST_IFETCH_PTR            ->read(),addr%_param->_nb_instruction);
    296               if (_param->_have_port_branch_update_prediction_id)
    297               TEST(Tprediction_ptr_t ,out_DECOD_BRANCH_UPDATE_PREDICTION_ID->read(),addr%_param->_size_branch_update_prediction);
     306              if (_param->_have_port_depth)
     307              TEST(Tprediction_ptr_t ,out_DECOD_BRANCH_UPDATE_PREDICTION_ID->read(),addr%_param->_size_depth);
    298308              if ((addr % modulo_iberr) == 0)
    299309              TEST(Texception_t      ,out_DECOD_EXCEPTION                  ->read(),EXCEPTION_IFETCH_BUS_ERROR);

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/include/Parameters.h

    r81 r88  
    2626  public : uint32_t _size_queue                           ;
    2727  public : uint32_t _nb_instruction                       ;
    28   public : uint32_t _size_branch_update_prediction        ;
    29   public : uint32_t _size_general_data                    ;
     28//public : uint32_t _size_branch_update_prediction        ;
     29//public : uint32_t _size_general_data                    ;
    3030
    31   public : uint32_t _size_queue_ptr                       ;
    32   public : uint32_t _size_instruction_ptr                 ;
     31//public : uint32_t _size_queue_ptr                       ;
     32//public : uint32_t _size_instruction_ptr                 ;
    3333
    34   public : bool     _have_port_queue_ptr                  ;
    35   public : bool     _have_port_instruction_ptr            ;
    36   public : bool     _have_port_branch_update_prediction_id;
     34//public : bool     _have_port_queue_ptr                  ;
     35//public : bool     _have_port_instruction_ptr            ;
     36//public : bool     _have_port_branch_update_prediction_id;
    3737
    3838    //-----[ methods ]-----------------------------------------------------------
    39   public : Parameters  (uint32_t _size_queue                   ,
    40                         uint32_t _nb_instruction               ,
    41                         uint32_t _size_branch_update_prediction,
    42                         uint32_t _size_general_data            );
     39  public : Parameters  (uint32_t size_queue                   ,
     40                        uint32_t nb_instruction               ,
     41                        uint32_t size_branch_update_prediction,
     42                        uint32_t size_general_data            ,
     43                        bool     is_toplevel=false);
    4344//   public : Parameters  (Parameters & param) ;
    4445  public : ~Parameters () ;
     46
     47  public :        void            copy       (void);
    4548
    4649  public :        Parameters_test msg_error  (void);

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue.cpp

    r81 r88  
    3838    log_printf(FUNC,Ifetch_queue,FUNCTION,"Begin");
    3939
    40     log_printf(INFO,Ifetch_queue,FUNCTION,"Allocation");
     40#if DEBUG_Ifetch_queue == true
     41    log_printf(INFO,Ifetch_queue,FUNCTION,_("<%s> Parameters"),_name.c_str());
     42
     43    std::cout << *param << std::endl;
     44#endif   
     45
     46    log_printf(INFO,Ifetch_queue,FUNCTION,_("<%s> Allocation"),_name.c_str());
    4147
    4248    allocation (
    … …  
    4753
    4854#ifdef STATISTICS
    49     if (_usage & USE_STATISTICS)
     55    if (usage_is_set(_usage,USE_STATISTICS))
    5056      {
    51         log_printf(INFO,Ifetch_queue,FUNCTION,"Allocation of statistics");
     57        log_printf(INFO,Ifetch_queue,FUNCTION,_("<%s> Allocation of statistics"),_name.c_str());
    5258
    5359        statistics_allocation(param_statistics);
    … …  
    5662
    5763#ifdef VHDL
    58     if (_usage & USE_VHDL)
     64    if (usage_is_set(_usage,USE_VHDL))
    5965      {
    6066        // generate the vhdl
    61         log_printf(INFO,Ifetch_queue,FUNCTION,"Generate the vhdl");
     67        log_printf(INFO,Ifetch_queue,FUNCTION,_("<%s> Generate the vhdl"),_name.c_str());
    6268       
    6369        vhdl();
    … …  
    6672
    6773#ifdef SYSTEMC
    68     if (_usage & USE_SYSTEMC)
     74    if (usage_is_set(_usage,USE_SYSTEMC))
    6975      {
    7076        // constant output
    … …  
    7581        PORT_WRITE(out_EVENT_RESET_ACK, internal_EVENT_RESET_ACK);
    7682
    77         log_printf(INFO,Ifetch_queue,FUNCTION,"Method - transition");
     83        log_printf(INFO,Ifetch_queue,FUNCTION,_("<%s> Method - transition"),_name.c_str());
    7884
    7985        SC_METHOD (transition);
    … …  
    8591# endif   
    8692
    87         log_printf(INFO,Ifetch_queue,FUNCTION,"Method - genMoore");
     93        log_printf(INFO,Ifetch_queue,FUNCTION,_("<%s> Method - genMoore"),_name.c_str());
    8894
    8995        SC_METHOD (genMoore);
    … …  
    107113
    108114#ifdef STATISTICS
    109     if (_usage & USE_STATISTICS)
     115    if (usage_is_set(_usage,USE_STATISTICS))
    110116      {
    111117        statistics_deallocation();
    … …  
    113119#endif
    114120
    115     log_printf(INFO,Ifetch_queue,FUNCTION,"Deallocation");
     121    log_printf(INFO,Ifetch_queue,FUNCTION,_("<%s> Deallocation"),_name.c_str());
    116122    deallocation ();
    117123

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_allocation.cpp

    r81 r88  
    6262      ALLOC_VALACK_IN ( in_ADDRESS_VAL                        ,VAL);
    6363      ALLOC_VALACK_OUT(out_ADDRESS_ACK                        ,ACK);
    64       ALLOC_SIGNAL_IN ( in_ADDRESS_INSTRUCTION_ADDRESS        ,"instruction_address"        ,Tgeneral_address_t ,_param->_size_general_data            );
    65       ALLOC_SIGNAL_IN ( in_ADDRESS_INST_IFETCH_PTR            ,"inst_ifetch_ptr"            ,Tinst_ifetch_ptr_t ,_param->_size_instruction_ptr         );
    66       ALLOC_SIGNAL_IN ( in_ADDRESS_BRANCH_STATE               ,"branch_state"               ,Tbranch_state_t    ,_param->_size_branch_state            );
    67       ALLOC_SIGNAL_IN ( in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t  ,_param->_size_branch_update_prediction);
    68       ALLOC_SIGNAL_OUT(out_ADDRESS_IFETCH_QUEUE_ID            ,"ifetch_queue_id"            ,Tifetch_queue_ptr_t,_param->_size_queue_ptr               );
     64      ALLOC_SIGNAL_IN ( in_ADDRESS_INSTRUCTION_ADDRESS        ,"instruction_address"        ,Tgeneral_address_t ,_param->_size_instruction_address        );
     65      ALLOC_SIGNAL_IN ( in_ADDRESS_INST_IFETCH_PTR            ,"inst_ifetch_ptr"            ,Tinst_ifetch_ptr_t ,_param->_size_inst_ifetch_ptr);
     66      ALLOC_SIGNAL_IN ( in_ADDRESS_BRANCH_STATE               ,"branch_state"               ,Tbranch_state_t    ,_param->_size_branch_state   );
     67      ALLOC_SIGNAL_IN ( in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t  ,_param->_size_depth          );
     68      ALLOC_SIGNAL_OUT(out_ADDRESS_IFETCH_QUEUE_ID            ,"ifetch_queue_id"            ,Tifetch_queue_ptr_t,_param->_size_ifetch_queue_ptr);
    6969
    7070    }
    … …  
    8686      ALLOC_INTERFACE("decod",OUT, EAST, "Send instruction bundle to the decod's stage.");
    8787     
    88       ALLOC_SIGNAL_OUT(out_DECOD_ADDRESS                    ,"address"                    ,Tgeneral_address_t,_param->_size_general_data            );
    89       ALLOC_SIGNAL_OUT(out_DECOD_INST_IFETCH_PTR            ,"inst_ifetch_ptr"            ,Tinst_ifetch_ptr_t,_param->_size_instruction_ptr        );
    90       ALLOC_SIGNAL_OUT(out_DECOD_BRANCH_STATE               ,"branch_state"               ,Tbranch_state_t   ,_param->_size_branch_state            );
    91       ALLOC_SIGNAL_OUT(out_DECOD_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_branch_update_prediction);
    92       ALLOC_SIGNAL_OUT(out_DECOD_EXCEPTION                  ,"exception"                  ,Texception_t      ,_param->_size_exception_ifetch        );
     88      ALLOC_SIGNAL_OUT(out_DECOD_ADDRESS                    ,"address"                    ,Tgeneral_address_t,_param->_size_instruction_address         );
     89      ALLOC_SIGNAL_OUT(out_DECOD_INST_IFETCH_PTR            ,"inst_ifetch_ptr"            ,Tinst_ifetch_ptr_t,_param->_size_inst_ifetch_ptr );
     90      ALLOC_SIGNAL_OUT(out_DECOD_BRANCH_STATE               ,"branch_state"               ,Tbranch_state_t   ,_param->_size_branch_state    );
     91      ALLOC_SIGNAL_OUT(out_DECOD_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth           );
     92      ALLOC_SIGNAL_OUT(out_DECOD_EXCEPTION                  ,"exception"                  ,Texception_t      ,_param->_size_exception_ifetch);
    9393    }
    9494
    … …  
    9999      ALLOC_VALACK_IN ( in_ICACHE_RSP_VAL      ,VAL);
    100100      ALLOC_VALACK_OUT(out_ICACHE_RSP_ACK      ,ACK);
    101       ALLOC_SIGNAL_IN ( in_ICACHE_RSP_PACKET_ID,"packet_id",Tpacket_t      ,_param->_size_queue_ptr   );
     101      ALLOC_SIGNAL_IN ( in_ICACHE_RSP_PACKET_ID,"packet_id",Tpacket_t      ,_param->_size_ifetch_queue_ptr);
    102102      ALLOC_SIGNAL_IN ( in_ICACHE_RSP_ERROR    ,"error"    ,Ticache_error_t,_param->_size_icache_error);
    103103    }
    … …  
    117117
    118118    // ~~~~~[ Internal ] ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    119     internal_DECOD_VAL = new Tcontrol_t [_param->_nb_instruction];
    120 
    121     _queue = new ifetch_queue_entry_t * [_param->_size_queue];
    122     for (uint32_t i=0;i<_param->_size_queue; i++)
    123       _queue [i] = new ifetch_queue_entry_t (_param->_nb_instruction);
     119    if (usage_is_set(_usage,USE_SYSTEMC))
     120      {
     121        internal_DECOD_VAL = new Tcontrol_t [_param->_nb_instruction];
     122       
     123        _queue = new ifetch_queue_entry_t * [_param->_size_queue];
     124        for (uint32_t i=0;i<_param->_size_queue; i++)
     125          _queue [i] = new ifetch_queue_entry_t (_param->_nb_instruction);
     126      }
    124127
    125128    // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~   
    126129
    127130#ifdef POSITION
    128     _component->generate_file();
     131     if (usage_is_set(_usage,USE_POSITION))
     132       _component->generate_file();
    129133#endif
    130134

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_deallocation.cpp

    r81 r88  
    2323    log_printf(FUNC,Ifetch_queue,FUNCTION,"Begin");
    2424
    25     if (_usage & USE_SYSTEMC)
     25    if (usage_is_set(_usage,USE_SYSTEMC))
    2626      {
    2727        delete    in_CLOCK ;
    … …  
    3030        delete     in_ADDRESS_VAL                        ;
    3131        delete    out_ADDRESS_ACK                        ;
    32         if (_param->_have_port_queue_ptr)
     32        if (_param->_have_port_ifetch_queue_ptr)
    3333        delete    out_ADDRESS_IFETCH_QUEUE_ID            ;
    3434        delete []  in_ADDRESS_INSTRUCTION_ENABLE         ;
    3535        delete     in_ADDRESS_INSTRUCTION_ADDRESS        ;
    36         if (_param->_have_port_instruction_ptr)
     36        if (_param->_have_port_inst_ifetch_ptr)
    3737        delete     in_ADDRESS_INST_IFETCH_PTR            ;
    3838        delete     in_ADDRESS_BRANCH_STATE               ;
    39         if (_param->_have_port_branch_update_prediction_id)
     39        if (_param->_have_port_depth)
    4040        delete     in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID;
    4141        delete [] out_DECOD_VAL                          ;
    … …  
    4343        delete [] out_DECOD_INSTRUCTION                  ;
    4444        delete    out_DECOD_ADDRESS                      ;
    45         if (_param->_have_port_instruction_ptr)
     45        if (_param->_have_port_inst_ifetch_ptr)
    4646        delete    out_DECOD_INST_IFETCH_PTR              ;
    4747        delete    out_DECOD_BRANCH_STATE                 ;
    48         if (_param->_have_port_branch_update_prediction_id)
     48        if (_param->_have_port_depth)
    4949        delete    out_DECOD_BRANCH_UPDATE_PREDICTION_ID  ;
    5050        delete    out_DECOD_EXCEPTION                    ;
    5151        delete     in_ICACHE_RSP_VAL                     ;
    5252        delete    out_ICACHE_RSP_ACK                     ;
    53         if (_param->_have_port_queue_ptr)
     53        if (_param->_have_port_ifetch_queue_ptr)
    5454        delete     in_ICACHE_RSP_PACKET_ID               ;
    5555        delete []  in_ICACHE_RSP_INSTRUCTION             ;
    … …  
    5858        delete    out_EVENT_RESET_ACK                    ;
    5959      }
     60
     61    // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~   
     62    if (usage_is_set(_usage,USE_SYSTEMC))
     63      {
     64        delete    internal_DECOD_VAL;
     65        delete [] _queue;
     66      }
     67
    6068    // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~   
    61 
    62     delete    internal_DECOD_VAL;
    63     delete [] _queue;
    6469    delete    _component;
    6570

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_end_cycle.cpp

    r81 r88  
    2525
    2626#ifdef STATISTICS
    27     _stat->end_cycle();
     27    if (usage_is_set(_usage,USE_STATISTICS))
     28      _stat->end_cycle();
    2829#endif   
    2930
    … …  
    3132    // Evaluation before read the ouput signal
    3233//  sc_start(0);
    33     _interfaces->testbench();
     34    if (usage_is_set(_usage,USE_VHDL_TESTBENCH))
     35      _interfaces->testbench();
    3436#endif
    3537

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_genMoore.cpp

    r81 r88  
    2929
    3030    PORT_WRITE(out_ADDRESS_ACK            , internal_ADDRESS_ACK);
    31     if (_param->_have_port_queue_ptr)
     31    if (_param->_have_port_ifetch_queue_ptr)
    3232    PORT_WRITE(out_ADDRESS_IFETCH_QUEUE_ID, reg_PTR_WRITE);
    3333
    … …  
    4545
    4646    PORT_WRITE(out_DECOD_ADDRESS                    , _queue[reg_PTR_READ]->_address                    );
    47     if (_param->_have_port_instruction_ptr)
     47    if (_param->_have_port_inst_ifetch_ptr)
    4848    PORT_WRITE(out_DECOD_INST_IFETCH_PTR            , _queue[reg_PTR_READ]->_inst_ifetch_ptr            );
    4949    PORT_WRITE(out_DECOD_BRANCH_STATE               , _queue[reg_PTR_READ]->_branch_state               );
    50     if (_param->_have_port_branch_update_prediction_id)
     50    if (_param->_have_port_depth)
    5151    PORT_WRITE(out_DECOD_BRANCH_UPDATE_PREDICTION_ID, _queue[reg_PTR_READ]->_branch_update_prediction_id);
    5252    PORT_WRITE(out_DECOD_EXCEPTION                  , _queue[reg_PTR_READ]->_exception                  );

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_transition.cpp

    r85 r88  
    2222  void Ifetch_queue::transition (void)
    2323  {
    24     log_printf(FUNC,Ifetch_queue,FUNCTION,"Begin");
     24    log_begin(Ifetch_queue,FUNCTION);
    2525
    2626    if (PORT_READ(in_NRESET) == 0)
    … …  
    3434    else
    3535      {
    36         log_printf(NONE,Ifetch_queue,FUNCTION," * KANE address : 0x%x",PORT_READ(in_ADDRESS_INSTRUCTION_ADDRESS));
    37    
    38 
    3936        // ==========================================================
    4037        // =====[ ADDRESS ]==========================================
    … …  
    4744             
    4845#ifdef STATISTICS
    49             (*_sum_transaction_address) ++;
     46            if (usage_is_set(_usage,USE_STATISTICS))
     47              (*_sum_transaction_address) ++;
    5048#endif
    5149
    … …  
    5452                Tcontrol_t enable = PORT_READ(in_ADDRESS_INSTRUCTION_ENABLE [i]);
    5553#ifdef STATISTICS
    56                 (*_sum_inst_enable) += enable;
     54                if (usage_is_set(_usage,USE_STATISTICS))
     55                  (*_sum_inst_enable) += enable;
    5756#endif
    5857                _queue[reg_PTR_WRITE]->_instruction_enable [i]      = enable;
    … …  
    6059
    6160            _queue[reg_PTR_WRITE]->_address                     = PORT_READ(in_ADDRESS_INSTRUCTION_ADDRESS        );
    62             _queue[reg_PTR_WRITE]->_inst_ifetch_ptr             = (_param->_have_port_instruction_ptr)?PORT_READ(in_ADDRESS_INST_IFETCH_PTR            ):0;
     61            _queue[reg_PTR_WRITE]->_inst_ifetch_ptr             = (_param->_have_port_inst_ifetch_ptr)?PORT_READ(in_ADDRESS_INST_IFETCH_PTR            ):0;
    6362            _queue[reg_PTR_WRITE]->_branch_state                = PORT_READ(in_ADDRESS_BRANCH_STATE               );
    64             _queue[reg_PTR_WRITE]->_branch_update_prediction_id = (_param->_have_port_branch_update_prediction_id)?PORT_READ(in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID):0;
     63            _queue[reg_PTR_WRITE]->_branch_update_prediction_id = (_param->_have_port_depth)?PORT_READ(in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID):0;
    6564           
    6665            reg_PTR_WRITE = (reg_PTR_WRITE+1)%_param->_size_queue;
    … …  
    9594        if (PORT_READ(in_ICACHE_RSP_VAL) and internal_ICACHE_RSP_ACK)
    9695          {
    97             Tpacket_t ptr = (_param->_have_port_queue_ptr)?PORT_READ(in_ICACHE_RSP_PACKET_ID):0;
     96            Tpacket_t ptr = (_param->_have_port_ifetch_queue_ptr)?PORT_READ(in_ICACHE_RSP_PACKET_ID):0;
    9897           
    9998            for (uint32_t i=0; i<_param->_nb_instruction; i++)
    … …  
    137136          }
    138137
    139 #if DEBUG >= DEBUG_TRACE
    140         log_printf(TRACE,Ifetch_queue,FUNCTION,"Dump ifetch_queue");
    141         log_printf(TRACE,Ifetch_queue,FUNCTION," * reg_PTR_WRITE : %d",reg_PTR_WRITE);
    142         log_printf(TRACE,Ifetch_queue,FUNCTION," * reg_PTR_READ  : %d",reg_PTR_READ );
     138#if defined(DEBUG) and (DEBUG >= DEBUG_TRACE)
     139        log_printf(TRACE,Ifetch_queue,FUNCTION,"  * Dump ifetch_queue");
     140        log_printf(TRACE,Ifetch_queue,FUNCTION,"    * reg_PTR_WRITE : %d",reg_PTR_WRITE);
     141        log_printf(TRACE,Ifetch_queue,FUNCTION,"    * reg_PTR_READ  : %d",reg_PTR_READ );
    143142        for (uint32_t i=0; i<_param->_size_queue; i++)
    144143          {
    145             log_printf(TRACE,Ifetch_queue,FUNCTION," * [%d] %s %.8x %d - %d %d %d", i, toString(_queue [i]->_state).c_str(), _queue [i]->_address,_queue [i]->_inst_ifetch_ptr,_queue [i]->_branch_state,_queue [i]->_branch_update_prediction_id,_queue [i]->_exception);
     144            log_printf(TRACE,Ifetch_queue,FUNCTION,"    * [%d] %s %.8x %d - %d %d %d", i, toString(_queue [i]->_state).c_str(), _queue [i]->_address,_queue [i]->_inst_ifetch_ptr,_queue [i]->_branch_state,_queue [i]->_branch_update_prediction_id,_queue [i]->_exception);
    146145           
    147146            for (uint32_t j=0; j<_param->_nb_instruction; j++)
    148               log_printf(TRACE,Ifetch_queue,FUNCTION,"    * %d %.8x", _queue [i]->_instruction_enable[j], _queue [i]->_instruction[j]);
     147              log_printf(TRACE,Ifetch_queue,FUNCTION,"      * %d %.8x", _queue [i]->_instruction_enable[j], _queue [i]->_instruction[j]);
    149148          }
    150149#endif
    151150
    152151#ifdef STATISTICS
    153         for (uint32_t i=0; i<_param->_size_queue; i++)
    154           switch (_queue[i]->_state)
    155             {
    156             case IFETCH_QUEUE_STATE_EMPTY          : break;
    157             case IFETCH_QUEUE_STATE_WAIT_RSP       : (*_sum_use_queue_wait_rsp      ) ++; break;
    158             case IFETCH_QUEUE_STATE_HAVE_RSP       : (*_sum_use_queue_have_rsp      ) ++; break;
    159             case IFETCH_QUEUE_STATE_ERROR_WAIT_RSP : (*_sum_use_queue_error_wait_rsp) ++; break;
    160             default : break;
    161             }
     152        if (usage_is_set(_usage,USE_STATISTICS))
     153          for (uint32_t i=0; i<_param->_size_queue; i++)
     154            switch (_queue[i]->_state)
     155              {
     156              case IFETCH_QUEUE_STATE_EMPTY          : break;
     157              case IFETCH_QUEUE_STATE_WAIT_RSP       : (*_sum_use_queue_wait_rsp      ) ++; break;
     158              case IFETCH_QUEUE_STATE_HAVE_RSP       : (*_sum_use_queue_have_rsp      ) ++; break;
     159              case IFETCH_QUEUE_STATE_ERROR_WAIT_RSP : (*_sum_use_queue_error_wait_rsp) ++; break;
     160              default : break;
     161              }
    162162#endif
    163163      }
    164 
     164   
    165165#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
    166166    end_cycle ();
    167167#endif
    168168
    169     log_printf(FUNC,Ifetch_queue,FUNCTION,"End");
     169    log_end(Ifetch_queue,FUNCTION);
    170170  };
    171171

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Parameters.cpp

    r81 r88  
    2222                          uint32_t nb_instruction               ,
    2323                          uint32_t size_branch_update_prediction,
    24                           uint32_t size_general_data            )
     24                          uint32_t size_general_data            ,
     25                          bool     is_toplevel)
    2526  {
    2627    log_printf(FUNC,Ifetch_queue,FUNCTION,"Begin");
    … …  
    2829    _size_queue                            = size_queue                   ;
    2930    _nb_instruction                        = nb_instruction               ;
    30     _size_branch_update_prediction         = size_branch_update_prediction;
    31     _size_general_data                     = size_general_data            ;
     31//  _size_branch_update_prediction         = size_branch_update_prediction;
     32//  _size_general_data                     = size_general_data            ;
    3233
    33     _size_queue_ptr                        = log2(size_queue);
    34     _size_instruction_ptr                  = log2(nb_instruction);
     34    test();
    3535
    36     _have_port_queue_ptr                   = _size_queue_ptr > 0;
    37     _have_port_instruction_ptr             = _size_instruction_ptr > 0;
    38     _have_port_branch_update_prediction_id = size_branch_update_prediction > 0;
    39    
    40     test();
     36    if (is_toplevel)
     37      {
     38        _size_instruction_address   = size_general_data;
     39        _size_ifetch_queue_ptr      = log2(size_queue);
     40        _size_inst_ifetch_ptr       = log2(nb_instruction);
     41        _size_depth                 = size_branch_update_prediction;
     42
     43        _have_port_ifetch_queue_ptr = _size_ifetch_queue_ptr > 0;
     44        _have_port_inst_ifetch_ptr  = _size_inst_ifetch_ptr > 0;
     45        _have_port_depth            = _size_depth > 0;
     46
     47        copy ();
     48      }
     49
    4150    log_printf(FUNC,Ifetch_queue,FUNCTION,"End");
    4251  };
    … …  
    5968  };
    6069
     70#undef  FUNCTION
     71#define FUNCTION "Ifetch_queue::copy"
     72  void Parameters::copy (void)
     73  {
     74    log_printf(FUNC,Ifetch_queue,FUNCTION,"Begin");
     75    log_printf(FUNC,Ifetch_queue,FUNCTION,"End");
     76  };
     77
    6178}; // end namespace ifetch_queue
    6279}; // end namespace ifetch_unit

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Parameters_msg_error.cpp

    r81 r88  
    2828
    2929    if (_size_queue == 1)
    30       test.warning("To best perfomance, size_queue must be > 1.");
     30      test.warning("To best perfomance, size_queue must be > 1.\n");
    3131   
    32 //     if (not _have_port_queue_ptr)
    33 //       test.information("They have not port '..._QUEUE_PTR'.");
    34 
    35 //     if (not _have_port_instruction_ptr)
    36 //       test.information("They have not port '..._INST_IFETCH_PTR'.");
    37 
    38 //     if (not _have_port_branch_update_prediction_id)
    39 //       test.information("They have not port '..._BRANCH_UPDATE_PREDICTION_ID'.");
    40 
    4132    log_printf(FUNC,Ifetch_queue,FUNCTION,"End");
    4233

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Parameters_print.cpp

    r81 r88  
    2929    xml.singleton_begin("size_queue                   "); xml.attribut("value",toString(_size_queue                   )); xml.singleton_end();
    3030    xml.singleton_begin("nb_instruction               "); xml.attribut("value",toString(_nb_instruction               )); xml.singleton_end();
    31     xml.singleton_begin("size_branch_update_prediction"); xml.attribut("value",toString(_size_branch_update_prediction)); xml.singleton_end();
    32     xml.singleton_begin("size_general_data            "); xml.attribut("value",toString(_size_general_data            )); xml.singleton_end();
     31//  xml.singleton_begin("size_branch_update_prediction"); xml.attribut("value",toString(_size_branch_update_prediction)); xml.singleton_end();
     32//  xml.singleton_begin("size_general_data            "); xml.attribut("value",toString(_size_general_data            )); xml.singleton_end();
    3333    xml.balise_close();
    3434

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/SelfTest/Makefile

    r81 r88  
    2424library_clean                   : Ifetch_unit_Glue_library_clean
    2525
     26local_clean                     :
     27
    2628include                         $(DIR_COMPONENT)/Makefile.deps
    2729include                         $(DIR_MORPHEO)/Behavioural/Makefile.flags

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/SelfTest/src/main.cpp

    r85 r88  
    3737    {
    3838      morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::ifetch_unit_glue::Parameters * param = new morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::ifetch_unit_glue::Parameters
    39         (_size_address);
     39        (_size_address,
     40         true //is_toplevel
     41         );
    4042     
    4143      msg(_("%s"),param->print(1).c_str());

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/SelfTest/src/test.cpp

    r85 r88  
    2323#endif
    2424
     25  Tusage_t _usage = USE_ALL;
     26
     27//   _usage = usage_unset(_usage,USE_SYSTEMC              );
     28//   _usage = usage_unset(_usage,USE_VHDL                 );
     29//   _usage = usage_unset(_usage,USE_VHDL_TESTBENCH       );
     30//   _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT);
     31//   _usage = usage_unset(_usage,USE_POSITION             );
     32//   _usage = usage_unset(_usage,USE_STATISTICS           );
     33//   _usage = usage_unset(_usage,USE_INFORMATION          );
     34
    2535  Ifetch_unit_Glue * _Ifetch_unit_Glue = new Ifetch_unit_Glue
    2636    (name.c_str(),
    … …  
    2939#endif
    3040     _param,
    31      USE_ALL);
     41     _usage);
    3242 
    3343#ifdef SYSTEMC

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/include/Parameters.h

    r85 r88  
    2424  {
    2525    //-----[ fields ]------------------------------------------------------------
    26   public : uint32_t _size_address;
     26//public : uint32_t _size_address;
    2727
    2828    //-----[ methods ]-----------------------------------------------------------
    29   public : Parameters  (uint32_t size_address);
     29  public : Parameters  (uint32_t size_address,
     30                        bool     is_toplevel=false);
    3031//   public : Parameters  (Parameters & param) ;
    3132  public : ~Parameters () ;
     33
     34  public :        void            copy       (void);
    3235
    3336  public :        Parameters_test msg_error  (void);

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/src/Ifetch_unit_Glue.cpp

    r85 r88  
    3838    log_printf(FUNC,Ifetch_unit_Glue,FUNCTION,"Begin");
    3939
     40#if DEBUG_Ifetch_unit_Glue == true
     41    log_printf(INFO,Ifetch_unit_Glue,FUNCTION,_("<%s> Parameters"),_name.c_str());
     42
     43    std::cout << *param << std::endl;
     44#endif   
     45
    4046    log_printf(INFO,Ifetch_unit_Glue,FUNCTION,"Allocation");
    4147
    … …  
    4753
    4854#ifdef STATISTICS
    49     if (_usage & USE_STATISTICS)
     55    if (usage_is_set(_usage,USE_STATISTICS))
    5056      {
    5157        log_printf(INFO,Ifetch_unit_Glue,FUNCTION,"Allocation of statistics");
    … …  
    5662
    5763#ifdef VHDL
    58     if (_usage & USE_VHDL)
     64    if (usage_is_set(_usage,USE_VHDL))
    5965      {
    6066        // generate the vhdl
    … …  
    6672
    6773#ifdef SYSTEMC
    68     PORT_WRITE(out_ICACHE_REQ_TYPE,ICACHE_TYPE_LOAD);
     74    if (usage_is_set(_usage,USE_SYSTEMC))
     75      {
     76        // Write constant
     77        PORT_WRITE(out_ICACHE_REQ_TYPE,ICACHE_TYPE_LOAD);
    6978
    70     if (_usage & USE_SYSTEMC)
    71       {
    7279# if defined(STATISTICS) or defined(VHDL_TESTBENCH)
    7380        log_printf(INFO,Ifetch_unit_Glue,FUNCTION,"Method - transition");
    … …  
    140147
    141148#ifdef STATISTICS
    142     if (_usage & USE_STATISTICS)
     149    if (usage_is_set(_usage,USE_STATISTICS)) 
    143150      {
    144151        statistics_deallocation();

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/src/Ifetch_unit_Glue_allocation.cpp

    r85 r88  
    6767      ALLOC_SIGNAL_IN ( in_ICACHE_REQ_QUEUE_ACK      ,"queue_ack"      ,Tcontrol_t,1);
    6868      ALLOC_SIGNAL_OUT(out_ICACHE_REQ_TYPE           ,"type"           ,Ticache_type_t,_param->_size_icache_type);
    69       ALLOC_SIGNAL_OUT(out_ICACHE_REQ_ADDRESS        ,"address"        ,Taddress_t,_param->_size_address);
    70       ALLOC_SIGNAL_IN ( in_ICACHE_REQ_ADDRESS_ADDRESS,"address_address",Taddress_t,_param->_size_address);
    71       ALLOC_SIGNAL_OUT(out_ICACHE_REQ_QUEUE_ADDRESS  ,"queue_address"  ,Taddress_t,_param->_size_address);
     69      ALLOC_SIGNAL_OUT(out_ICACHE_REQ_ADDRESS        ,"address"        ,Taddress_t,_param->_size_instruction_address);
     70      ALLOC_SIGNAL_IN ( in_ICACHE_REQ_ADDRESS_ADDRESS,"address_address",Taddress_t,_param->_size_instruction_address);
     71      ALLOC_SIGNAL_OUT(out_ICACHE_REQ_QUEUE_ADDRESS  ,"queue_address"  ,Taddress_t,_param->_size_instruction_address);
    7272    }
    7373
    … …  
    8787
    8888#ifdef POSITION
    89     _component->generate_file();
     89     if (usage_is_set(_usage,USE_POSITION))
     90       _component->generate_file();
    9091#endif
    9192

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/src/Ifetch_unit_Glue_deallocation.cpp

    r85 r88  
    2323    log_printf(FUNC,Ifetch_unit_Glue,FUNCTION,"Begin");
    2424
    25     if (_usage & USE_SYSTEMC)
     25    if (usage_is_set(_usage,USE_SYSTEMC))
    2626      {
    2727        delete     in_CLOCK ;

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/src/Ifetch_unit_Glue_end_cycle.cpp

    r81 r88  
    2525
    2626#ifdef STATISTICS
    27     _stat->end_cycle();
     27    if (usage_is_set(_usage,USE_STATISTICS))
     28      _stat->end_cycle();
    2829#endif   
    2930
    … …  
    3132    // Evaluation before read the ouput signal
    3233//  sc_start(0);
    33     _interfaces->testbench();
     34    if (usage_is_set(_usage,USE_VHDL_TESTBENCH))
     35      _interfaces->testbench();
    3436#endif
    3537

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/src/Parameters.cpp

    r85 r88  
    1919#undef  FUNCTION
    2020#define FUNCTION "Ifetch_unit_Glue::Parameters"
    21   Parameters::Parameters (uint32_t size_address)
     21  Parameters::Parameters (uint32_t size_address,
     22                          bool     is_toplevel)
    2223  {
    2324    log_printf(FUNC,Ifetch_unit_Glue,FUNCTION,"Begin");
    2425
    25     _size_address = size_address;
     26    test();
    2627
    27     test();
     28    if (is_toplevel)
     29      {
     30        _size_instruction_address = size_address;
     31
     32        copy ();
     33      }
     34
    2835    log_printf(FUNC,Ifetch_unit_Glue,FUNCTION,"End");
    2936  };
    … …  
    4653  };
    4754
     55#undef  FUNCTION
     56#define FUNCTION "Ifetch_unit_Glue::copy"
     57  void Parameters::copy (void)
     58  {
     59    log_printf(FUNC,Ifetch_unit_Glue,FUNCTION,"Begin");
     60    log_printf(FUNC,Ifetch_unit_Glue,FUNCTION,"End");
     61  };
     62
    4863}; // end namespace ifetch_unit_glue
    4964}; // end namespace ifetch_unit

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/src/Parameters_print.cpp

    r85 r88  
    2727
    2828    xml.balise_open("ifetch_unit_glue");
    29     xml.singleton_begin("size_address"); xml.attribut("value",toString(_size_address)); xml.singleton_end();
     29//  xml.singleton_begin("size_address"); xml.attribut("value",toString(_size_address)); xml.singleton_end();
    3030    xml.balise_close();
    3131

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/SelfTest/Makefile

    r81 r88  
    2424library_clean                   : Ifetch_unit_library_clean
    2525
     26local_clean                     :
     27
    2628include                         $(DIR_COMPONENT)/Makefile.deps
    2729include                         $(DIR_MORPHEO)/Behavioural/Makefile.flags

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/SelfTest/src/main.cpp

    r81 r88  
    4747         _nb_instruction                ,
    4848         _size_branch_update_prediction ,
    49          _size_general_data             );
     49         _size_general_data             ,
     50         true // is_toplevel
     51         );
    5052     
    5153      msg(_("%s"),param->print(1).c_str());

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/SelfTest/src/test.cpp

    r85 r88  
    77 */
    88
    9 #define NB_ITERATION  128
     9#define NB_ITERATION  1024
    1010#define CYCLE_MAX     (128*NB_ITERATION)
    1111
    … …  
    4040#endif
    4141
     42  Tusage_t _usage = USE_ALL;
     43//   _usage = usage_unset(_usage,USE_SYSTEMC              );
     44//   _usage = usage_unset(_usage,USE_VHDL                 );
     45//   _usage = usage_unset(_usage,USE_VHDL_TESTBENCH       );
     46//   _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT);
     47//   _usage = usage_unset(_usage,USE_POSITION             );
     48  _usage = usage_unset(_usage,USE_STATISTICS           );
     49//   _usage = usage_unset(_usage,USE_INFORMATION          );
     50
    4251  Ifetch_unit * _Ifetch_unit = new Ifetch_unit
    4352    (name.c_str(),
    … …  
    4655#endif
    4756     _param,
    48      USE_ALL);
     57     _usage);
    4958 
    5059#ifdef SYSTEMC
    … …  
    92101  ALLOC_SC_SIGNAL (out_EVENT_ACK                          ,"out_EVENT_ACK                          ",Tcontrol_t           );
    93102  ALLOC_SC_SIGNAL ( in_EVENT_ADDRESS                      ," in_EVENT_ADDRESS                      ",Tgeneral_address_t   );
     103  ALLOC_SC_SIGNAL ( in_EVENT_ADDRESS_NEXT                 ," in_EVENT_ADDRESS_NEXT                 ",Tgeneral_address_t   );
     104  ALLOC_SC_SIGNAL ( in_EVENT_ADDRESS_NEXT_VAL             ," in_EVENT_ADDRESS_NEXT_VAL             ",Tcontrol_t           );
     105  ALLOC_SC_SIGNAL ( in_EVENT_IS_DS_TAKE                   ," in_EVENT_IS_DS_TAKE                   ",Tcontrol_t           );
    94106 
    95107  /********************************************************
    … …  
    105117  INSTANCE_SC_SIGNAL (_Ifetch_unit, in_ICACHE_REQ_ACK                     );
    106118//INSTANCE_SC_SIGNAL (_Ifetch_unit,out_ICACHE_REQ_THREAD_ID               );
    107   if (_param->_have_port_queue_ptr)
     119  if (_param->_have_port_ifetch_queue_ptr)
    108120  INSTANCE_SC_SIGNAL (_Ifetch_unit,out_ICACHE_REQ_PACKET_ID               );
    109121  INSTANCE_SC_SIGNAL (_Ifetch_unit,out_ICACHE_REQ_ADDRESS                 );
    … …  
    112124  INSTANCE_SC_SIGNAL (_Ifetch_unit,out_ICACHE_RSP_ACK                     );
    113125//INSTANCE_SC_SIGNAL (_Ifetch_unit, in_ICACHE_RSP_THREAD_ID               );
    114   if (_param->_have_port_queue_ptr)
     126  if (_param->_have_port_ifetch_queue_ptr)
    115127  INSTANCE_SC_SIGNAL (_Ifetch_unit, in_ICACHE_RSP_PACKET_ID               );
    116128  INSTANCE1_SC_SIGNAL(_Ifetch_unit, in_ICACHE_RSP_INSTRUCTION             ,_param->_nb_instruction);
    … …  
    124136  INSTANCE_SC_SIGNAL (_Ifetch_unit, in_PREDICT_PC_NEXT_IS_DS_TAKE         );
    125137  INSTANCE1_SC_SIGNAL(_Ifetch_unit, in_PREDICT_INSTRUCTION_ENABLE         ,_param->_nb_instruction);
    126   if (_param->_have_port_instruction_ptr)
     138  if (_param->_have_port_inst_ifetch_ptr)
    127139  INSTANCE_SC_SIGNAL (_Ifetch_unit, in_PREDICT_INST_IFETCH_PTR            );
    128140  INSTANCE_SC_SIGNAL (_Ifetch_unit, in_PREDICT_BRANCH_STATE               );
    129   if (_param->_have_port_branch_update_prediction_id)
     141  if (_param->_have_port_depth)
    130142  INSTANCE_SC_SIGNAL (_Ifetch_unit, in_PREDICT_BRANCH_UPDATE_PREDICTION_ID);
    131143  INSTANCE1_SC_SIGNAL(_Ifetch_unit,out_DECOD_VAL                          ,_param->_nb_instruction);
    … …  
    134146//INSTANCE_SC_SIGNAL (_Ifetch_unit,out_DECOD_CONTEXT_ID                   );
    135147  INSTANCE_SC_SIGNAL (_Ifetch_unit,out_DECOD_ADDRESS                      );
    136   if (_param->_have_port_instruction_ptr)
     148  if (_param->_have_port_inst_ifetch_ptr)
    137149  INSTANCE_SC_SIGNAL (_Ifetch_unit,out_DECOD_INST_IFETCH_PTR              );
    138150  INSTANCE_SC_SIGNAL (_Ifetch_unit,out_DECOD_BRANCH_STATE                 );
    139   if (_param->_have_port_branch_update_prediction_id)
     151  if (_param->_have_port_depth)
    140152  INSTANCE_SC_SIGNAL (_Ifetch_unit,out_DECOD_BRANCH_UPDATE_PREDICTION_ID  );
    141153  INSTANCE_SC_SIGNAL (_Ifetch_unit,out_DECOD_EXCEPTION                    );
    … …  
    143155  INSTANCE_SC_SIGNAL (_Ifetch_unit,out_EVENT_ACK                          );
    144156  INSTANCE_SC_SIGNAL (_Ifetch_unit, in_EVENT_ADDRESS                      );
     157  INSTANCE_SC_SIGNAL (_Ifetch_unit, in_EVENT_ADDRESS_NEXT                 );
     158  INSTANCE_SC_SIGNAL (_Ifetch_unit, in_EVENT_ADDRESS_NEXT_VAL             );
     159  INSTANCE_SC_SIGNAL (_Ifetch_unit, in_EVENT_IS_DS_TAKE                   );
    145160
    146161  msg(_("<%s> : Start Simulation ............\n"),name.c_str());
    … …  
    178193  Tcontrol_t      nn_val  = false;
    179194
    180   Tgeneral_data_t c_addr  = 0x100;
    181   Tgeneral_data_t n_addr  = 0x100;
    182   Tgeneral_data_t nn_addr = 0x100;
     195  Tgeneral_data_t c_addr  = 0x100>>2;
     196  Tgeneral_data_t n_addr  = 0x100>>2;
     197  Tgeneral_data_t nn_addr = 0x100>>2;
    183198
    184199  Tcontrol_t      c_enable [_param->_nb_instruction];
    … …  
    218233    TEST(Tcontrol_t,out_DECOD_VAL [i]->read(), 0);
    219234
    220   LABEL("Send Reset");
    221   do
    222     {
    223       in_EVENT_VAL    ->write(1);
    224       in_EVENT_ADDRESS->write(n_addr);
    225       SC_START(1); 
    226     } while (out_EVENT_ACK->read() == false);
    227   in_EVENT_VAL    ->write(0);
     235//   LABEL("Send Reset");
     236//   do
     237//     {
     238//       in_EVENT_VAL    ->write(1);
     239//       in_EVENT_ADDRESS->write(n_addr);
     240//       SC_START(1); 
     241//     } while (out_EVENT_ACK->read() == false);
     242//   in_EVENT_VAL    ->write(0);
    228243
    229244  n_val = 1;
    … …  
    270285
    271286      // EVENT
    272       in_EVENT_VAL    ->write((rand()%100)<percent_transaction_event  );
    273       in_EVENT_ADDRESS->write(0x100);
     287      in_EVENT_VAL             ->write((rand()%100)<percent_transaction_event  );
     288      in_EVENT_ADDRESS         ->write(0x77);
     289      in_EVENT_ADDRESS_NEXT    ->write(0x171);
     290      Tcontrol_t is_ds_take = rand();
     291      in_EVENT_ADDRESS_NEXT_VAL->write(is_ds_take);
     292      in_EVENT_IS_DS_TAKE      ->write(is_ds_take);
    274293
    275294      // ICACHE_REQ
    … …  
    305324          LABEL("ICACHE_REQ : Transaction accepted");
    306325
    307           Tpacket_t  packet  = (_param->_have_port_queue_ptr)?out_ICACHE_REQ_PACKET_ID->read():0;
     326          Tpacket_t  packet  = (_param->_have_port_ifetch_queue_ptr)?out_ICACHE_REQ_PACKET_ID->read():0;
    308327          Taddress_t address = out_ICACHE_REQ_ADDRESS->read();
    309328
    … …  
    344363        if (find)
    345364          {
    346             if (_param->_have_port_instruction_ptr)
     365            if (_param->_have_port_inst_ifetch_ptr)
    347366            TEST(Tinst_ifetch_ptr_t, out_DECOD_INST_IFETCH_PTR            ->read(), 0);
    348367            TEST(Tbranch_state_t   , out_DECOD_BRANCH_STATE               ->read(), 0);
    349             if (_param->_have_port_branch_update_prediction_id)
     368            if (_param->_have_port_depth)
    350369            TEST(Tprediction_ptr_t , out_DECOD_BRANCH_UPDATE_PREDICTION_ID->read(), 0);
    351370            TEST(Texception_t      , out_DECOD_EXCEPTION                  ->read(), 0);
    … …  
    404423          c_val           = false;
    405424          n_val           = true;
    406           nn_val          = false;
    407 
    408           n_addr         = in_EVENT_ADDRESS->read();
    409           n_is_ds_take   = 0;
     425
     426          n_addr          = in_EVENT_ADDRESS->read();
     427          n_is_ds_take    = in_EVENT_IS_DS_TAKE->read();
     428          nn_val          = in_EVENT_ADDRESS_NEXT_VAL->read();
     429          nn_addr         = in_EVENT_ADDRESS_NEXT    ->read();
     430          nn_is_ds_take   = 0;
    410431
    411432          n_enable [0] = 1;
    … …  
    496517  delete    out_EVENT_ACK                           ;
    497518  delete     in_EVENT_ADDRESS                       ;
     519  delete     in_EVENT_ADDRESS_NEXT                  ;
     520  delete     in_EVENT_ADDRESS_NEXT_VAL              ;
     521  delete     in_EVENT_IS_DS_TAKE                    ;
    498522
    499523  delete    param_cache;

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/include/Ifetch_unit.h

    r82 r88  
    109109  public    : SC_OUT(Tcontrol_t        )    * out_EVENT_ACK                           ;
    110110  public    : SC_IN (Tgeneral_address_t)    *  in_EVENT_ADDRESS                       ;
     111  public    : SC_IN (Tgeneral_address_t)    *  in_EVENT_ADDRESS_NEXT                  ;
     112  public    : SC_IN (Tcontrol_t        )    *  in_EVENT_ADDRESS_NEXT_VAL              ;
     113  public    : SC_IN (Tcontrol_t        )    *  in_EVENT_IS_DS_TAKE                    ;
    111114   
    112115    // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~   

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/include/Parameters.h

    r81 r88  
    2828  public : uint32_t _size_queue                   ;
    2929  public : uint32_t _nb_instruction               ;
    30   public : uint32_t _size_address                 ;
    31   public : uint32_t _size_branch_update_prediction;
    32 
    33   public : uint32_t _size_queue_ptr                       ;
    34   public : uint32_t _size_instruction_ptr                 ;
    35 
    36   public : bool     _have_port_queue_ptr                  ;
    37   public : bool     _have_port_instruction_ptr            ;
    38   public : bool     _have_port_branch_update_prediction_id;
     30//public : uint32_t _size_address                 ;
     31//public : uint32_t _size_branch_update_prediction;
     32//
     33//public : uint32_t _size_queue_ptr                       ;
     34//public : uint32_t _size_instruction_ptr                 ;
     35//
     36//public : bool     _have_port_queue_ptr                  ;
     37//public : bool     _have_port_instruction_ptr            ;
     38//public : bool     _have_port_branch_update_prediction_id;
    3939
    4040  public :morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::address_management::Parameters * _param_address_management;
    … …  
    4646                        uint32_t nb_instruction               ,
    4747                        uint32_t size_branch_update_prediction,
    48                         uint32_t size_address                 );
     48                        uint32_t size_address                 ,
     49                        bool     is_toplevel=false
     50                        );
    4951//   public : Parameters  (Parameters & param) ;
    5052  public : ~Parameters () ;
     53
     54  public :        void            copy       (void);
    5155
    5256  public :        Parameters_test msg_error  (void);

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/src/Ifetch_unit.cpp

    r81 r88  
    3737    log_printf(FUNC,Ifetch_unit,FUNCTION,"Begin");
    3838
     39#if DEBUG_Ifetch_unit == true
     40    log_printf(INFO,Ifetch_unit,FUNCTION,_("<%s> Parameters"),_name.c_str());
     41
     42    std::cout << *param << std::endl;
     43#endif   
     44
    3945    log_printf(INFO,Ifetch_unit,FUNCTION,"Allocation");
    4046
    … …  
    4652
    4753#ifdef STATISTICS
    48     if (_usage & USE_STATISTICS)
     54    if (usage_is_set(_usage,USE_STATISTICS))
    4955      {
    5056        log_printf(INFO,Ifetch_unit,FUNCTION,"Allocation of statistics");
    … …  
    5561
    5662#ifdef VHDL
    57     if (_usage & USE_VHDL)
     63    if (usage_is_set(_usage,USE_VHDL))
    5864      {
    5965        // generate the vhdl
    … …  
    6571
    6672#ifdef SYSTEMC
    67     if (_usage & USE_SYSTEMC)
     73    if (usage_is_set(_usage,USE_SYSTEMC))
    6874      {
    6975        log_printf(INFO,Ifetch_unit,FUNCTION,"Method - transition");
    … …  
    8995
    9096#ifdef STATISTICS
    91     if (_usage & USE_STATISTICS)
     97    if (usage_is_set(_usage,USE_STATISTICS))
    9298      {
    9399        statistics_deallocation();

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/src/Ifetch_unit_allocation.cpp

    r85 r88  
    5757    // ~~~~~[ Interface "icache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    5858    {
    59       ALLOC_INTERFACE("icache_req",OUT, WEST, "Instruction cache request.");
     59      ALLOC_INTERFACE("icache_req",OUT, WEST, _("Instruction cache request."));
    6060
    6161      ALLOC_VALACK_OUT(out_ICACHE_REQ_VAL      ,VAL);
    6262      ALLOC_VALACK_IN ( in_ICACHE_REQ_ACK      ,ACK);
    6363    //ALLOC_SIGNAL_OUT(out_ICACHE_REQ_THREAD_ID,"thread_id",Tcontext_t           ,_param->_size_context_id );
    64       ALLOC_SIGNAL_OUT(out_ICACHE_REQ_PACKET_ID,"packet_id",Tpacket_t            ,_param->_size_queue_ptr  );
    65       ALLOC_SIGNAL_OUT(out_ICACHE_REQ_ADDRESS  ,"address"  ,Ticache_instruction_t,_param->_size_address    );
     64      ALLOC_SIGNAL_OUT(out_ICACHE_REQ_PACKET_ID,"packet_id",Tpacket_t            ,_param->_size_ifetch_queue_ptr  );
     65      ALLOC_SIGNAL_OUT(out_ICACHE_REQ_ADDRESS  ,"address"  ,Ticache_instruction_t,_param->_size_instruction_address    );
    6666      ALLOC_SIGNAL_OUT(out_ICACHE_REQ_TYPE     ,"type"     ,Ticache_type_t       ,_param->_size_icache_type);
    6767    }
    … …  
    6969    // ~~~~~[ Interface "icache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    7070    {
    71       ALLOC_INTERFACE("icache_rsp",IN , WEST, "Instruction cache respons.");
     71      ALLOC_INTERFACE("icache_rsp",IN , WEST, _("Instruction cache respons."));
    7272
    7373      ALLOC_VALACK_IN  ( in_ICACHE_RSP_VAL        ,VAL);
    7474      ALLOC_VALACK_OUT (out_ICACHE_RSP_ACK        ,ACK);
    7575    //ALLOC_SIGNAL_IN  ( in_ICACHE_RSP_THREAD_ID  ,"thread_id"  ,Tcontext_t           ,_param->_size_context_id  );
    76       ALLOC_SIGNAL_IN  ( in_ICACHE_RSP_PACKET_ID  ,"packet_id"  ,Tpacket_t            ,_param->_size_queue_ptr   );
     76      ALLOC_SIGNAL_IN  ( in_ICACHE_RSP_PACKET_ID  ,"packet_id"  ,Tpacket_t            ,_param->_size_ifetch_queue_ptr   );
    7777      ALLOC_SIGNAL_IN  ( in_ICACHE_RSP_ERROR      ,"error"      ,Ticache_error_t      ,_param->_size_icache_error);
    7878    }
    7979    {
    80       ALLOC1_INTERFACE("icache_rsp",IN , WEST, "Instruction cache respons.",_param->_nb_instruction);
     80      ALLOC1_INTERFACE("icache_rsp",IN , WEST, _("Instruction cache respons."),_param->_nb_instruction);
    8181
    8282      ALLOC1_SIGNAL_IN ( in_ICACHE_RSP_INSTRUCTION,"instruction",Ticache_instruction_t,_param->_size_instruction );
    … …  
    8585    // ~~~~~[ Interface : "predict" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    8686    {
    87       ALLOC_INTERFACE("predict",OUT, NORTH, "Acces Instruction cache respons.");
     87      ALLOC_INTERFACE("predict",OUT, NORTH, _("Predict the next pc."));
    8888
    8989      ALLOC_VALACK_OUT (out_PREDICT_VAL                        ,VAL);
    9090      ALLOC_VALACK_IN  ( in_PREDICT_ACK                        ,ACK);
    91       ALLOC_SIGNAL_OUT (out_PREDICT_PC_PREVIOUS                ,"pc_previous"                ,Tgeneral_address_t,_param->_size_address);
    92       ALLOC_SIGNAL_OUT (out_PREDICT_PC_CURRENT                 ,"pc_current"                 ,Tgeneral_address_t,_param->_size_address);
     91      ALLOC_SIGNAL_OUT (out_PREDICT_PC_PREVIOUS                ,"pc_previous"                ,Tgeneral_address_t,_param->_size_instruction_address);
     92      ALLOC_SIGNAL_OUT (out_PREDICT_PC_CURRENT                 ,"pc_current"                 ,Tgeneral_address_t,_param->_size_instruction_address);
    9393      ALLOC_SIGNAL_OUT (out_PREDICT_PC_CURRENT_IS_DS_TAKE      ,"pc_current_is_ds_take"      ,Tcontrol_t        ,1);
    94       ALLOC_SIGNAL_IN  ( in_PREDICT_PC_NEXT                    ,"pc_next"                    ,Tgeneral_address_t,_param->_size_address);
     94      ALLOC_SIGNAL_IN  ( in_PREDICT_PC_NEXT                    ,"pc_next"                    ,Tgeneral_address_t,_param->_size_instruction_address);
    9595      ALLOC_SIGNAL_IN  ( in_PREDICT_PC_NEXT_IS_DS_TAKE         ,"pc_next_is_ds_take"         ,Tcontrol_t        ,1);
    96       ALLOC_SIGNAL_IN  ( in_PREDICT_INST_IFETCH_PTR            ,"inst_ifetch_ptr"            ,Tinst_ifetch_ptr_t,_param->_size_instruction_ptr);
     96      ALLOC_SIGNAL_IN  ( in_PREDICT_INST_IFETCH_PTR            ,"inst_ifetch_ptr"            ,Tinst_ifetch_ptr_t,_param->_size_inst_ifetch_ptr);
    9797      ALLOC_SIGNAL_IN  ( in_PREDICT_BRANCH_STATE               ,"branch_state"               ,Tbranch_state_t   ,_param->_size_branch_state);
    98       ALLOC_SIGNAL_IN  ( in_PREDICT_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_branch_update_prediction);
    99     }
    100     {
    101       ALLOC1_INTERFACE("predict",IN , NORTH, "Acces Instruction cache respons.",_param->_nb_instruction);
     98      ALLOC_SIGNAL_IN  ( in_PREDICT_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth);
     99    }
     100    {
     101      ALLOC1_INTERFACE("predict",IN , NORTH, _("Predict the next pc."),_param->_nb_instruction);
    102102
    103103      ALLOC1_SIGNAL_IN ( in_PREDICT_INSTRUCTION_ENABLE         ,"instruction_enable"         ,Tcontrol_t        ,1);
    … …  
    106106    // ~~~~~[ Interface : "decod" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    107107    {
    108       ALLOC_INTERFACE("decod",OUT , EAST, "Send bundle to the decod unit.");
     108      ALLOC_INTERFACE("decod",OUT , EAST, _("Send bundle to the decod unit."));
    109109
    110110    //ALLOC_SIGNAL_OUT (out_DECOD_CONTEXT_ID                 ,"context_id"                 ,Tcontext_t        ,_param->_size_context_id);
    111       ALLOC_SIGNAL_OUT (out_DECOD_ADDRESS                    ,"address"                    ,Tgeneral_address_t,_param->_size_address);
    112       ALLOC_SIGNAL_OUT (out_DECOD_INST_IFETCH_PTR            ,"inst_ifetch_ptr"            ,Tinst_ifetch_ptr_t,_param->_size_instruction_ptr);
     111      ALLOC_SIGNAL_OUT (out_DECOD_ADDRESS                    ,"address"                    ,Tgeneral_address_t,_param->_size_instruction_address);
     112      ALLOC_SIGNAL_OUT (out_DECOD_INST_IFETCH_PTR            ,"inst_ifetch_ptr"            ,Tinst_ifetch_ptr_t,_param->_size_inst_ifetch_ptr);
    113113      ALLOC_SIGNAL_OUT (out_DECOD_BRANCH_STATE               ,"branch_state"               ,Tbranch_state_t   ,_param->_size_branch_state);
    114       ALLOC_SIGNAL_OUT (out_DECOD_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_branch_update_prediction);
     114      ALLOC_SIGNAL_OUT (out_DECOD_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth);
    115115      ALLOC_SIGNAL_OUT (out_DECOD_EXCEPTION                  ,"exception"                  ,Texception_t      ,_param->_size_exception_ifetch);
    116116    }
    117117    {
    118       ALLOC1_INTERFACE("decod",OUT , EAST, "Send bundle to the decod unit.",_param->_nb_instruction);
     118      ALLOC1_INTERFACE("decod",OUT , EAST, _("Send bundle to the decod unit."),_param->_nb_instruction);
    119119
    120120      ALLOC1_VALACK_OUT(out_DECOD_VAL                        ,VAL);
    … …  
    125125    // ~~~~~[ Interface "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    126126    {
    127       ALLOC_INTERFACE("event",IN , NORTH, "Event interface.");
    128 
    129       ALLOC_VALACK_IN ( in_EVENT_VAL    ,VAL);
    130       ALLOC_VALACK_OUT(out_EVENT_ACK    ,ACK);
    131       ALLOC_SIGNAL_IN ( in_EVENT_ADDRESS,"address",Tgeneral_address_t,_param->_size_address);
     127      ALLOC_INTERFACE("event",IN , NORTH, _("Event interface."));
     128
     129      ALLOC_VALACK_IN ( in_EVENT_VAL              ,VAL);
     130      ALLOC_VALACK_OUT(out_EVENT_ACK              ,ACK);
     131      ALLOC_SIGNAL_IN ( in_EVENT_ADDRESS          ,"address"         ,Tgeneral_address_t,_param->_size_instruction_address);
     132      ALLOC_SIGNAL_IN ( in_EVENT_ADDRESS_NEXT     ,"address_next"    ,Tgeneral_address_t,_param->_size_instruction_address);
     133      ALLOC_SIGNAL_IN ( in_EVENT_ADDRESS_NEXT_VAL ,"address_next_val",Tcontrol_t,1);
     134      ALLOC_SIGNAL_IN ( in_EVENT_IS_DS_TAKE       ,"is_ds_take"      ,Tcontrol_t,1);
    132135    }
    133136   
    … …  
    137140    {
    138141      name = _name+"_address_management";
    139       std::cout << "Create   : " << name << std::endl;
     142      log_printf(Ifetch_unit,Core,FUNCTION,_("Create   : %s"),name.c_str());
    140143     
    141144      _component_address_management = new morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::address_management::Address_management
    … …  
    156159    {
    157160      name = _name+"_ifetch_queue";
    158       std::cout << "Create   : " << name << std::endl;
     161      log_printf(Ifetch_unit,Core,FUNCTION,_("Create   : %s"),name.c_str());
    159162     
    160163      _component_ifetch_queue = new morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::ifetch_queue::Ifetch_queue
    … …  
    175178    {
    176179      name = _name+"_ifetch_unit_glue";
    177       std::cout << "Create   : " << name << std::endl;
     180      log_printf(Ifetch_unit,Core,FUNCTION,_("Create   : %s"),name.c_str());
    178181     
    179182      _component_ifetch_unit_glue = new morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::ifetch_unit_glue::Ifetch_unit_Glue
    … …  
    200203    {
    201204      src = _name+"_address_management";
    202       std::cout << "Instance : " << src << std::endl;
     205      log_printf(INFO,Core,FUNCTION,_("Instance : %s"),src.c_str());
    203206           
    204207      {
    … …  
    225228          }
    226229
    227         if (_param->_have_port_instruction_ptr)
     230        if (_param->_have_port_inst_ifetch_ptr)
    228231        COMPONENT_MAP(_component,src ,"out_ADDRESS_INST_IFETCH_PTR"            ,
    229232                                 dest, "in_ADDRESS_INST_IFETCH_PTR"            );
    230233        COMPONENT_MAP(_component,src ,"out_ADDRESS_BRANCH_STATE"               ,
    231234                                 dest, "in_ADDRESS_BRANCH_STATE"               );
    232         if (_param->_have_port_branch_update_prediction_id)
     235        if (_param->_have_port_depth)
    233236        COMPONENT_MAP(_component,src ,"out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID",
    234237                                 dest, "in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID");
    … …  
    281284        PORT_MAP(_component,src , "in_PREDICT_PC_NEXT_IS_DS_TAKE"         
    282285                           ,dest, "in_PREDICT_PC_NEXT_IS_DS_TAKE"         );
    283         if (_param->_have_port_instruction_ptr)
     286        if (_param->_have_port_inst_ifetch_ptr)
    284287        PORT_MAP(_component,src , "in_PREDICT_INST_IFETCH_PTR"           
    285288                           ,dest, "in_PREDICT_INST_IFETCH_PTR"            );
    286289        PORT_MAP(_component,src , "in_PREDICT_BRANCH_STATE"               
    287290                           ,dest, "in_PREDICT_BRANCH_STATE"               );
    288         if (_param->_have_port_branch_update_prediction_id)
     291        if (_param->_have_port_depth)
    289292        PORT_MAP(_component,src , "in_PREDICT_BRANCH_UPDATE_PREDICTION_ID"
    290293                           ,dest, "in_PREDICT_BRANCH_UPDATE_PREDICTION_ID");
    … …  
    306309
    307310        dest = _name;
    308         PORT_MAP(_component,src , "in_EVENT_ADDRESS",dest, "in_EVENT_ADDRESS");
     311        PORT_MAP(_component,src , "in_EVENT_ADDRESS"         ,dest , "in_EVENT_ADDRESS"          );
     312        PORT_MAP(_component,src , "in_EVENT_ADDRESS_NEXT"    ,dest , "in_EVENT_ADDRESS_NEXT"     );
     313        PORT_MAP(_component,src , "in_EVENT_ADDRESS_NEXT_VAL",dest , "in_EVENT_ADDRESS_NEXT_VAL" );
     314        PORT_MAP(_component,src , "in_EVENT_IS_DS_TAKE"      ,dest , "in_EVENT_IS_DS_TAKE"       );
    309315      }
    310316    }
    … …  
    315321    {
    316322      src = _name+"_ifetch_queue";
    317       std::cout << "Instance : " << src << std::endl;
     323      log_printf(INFO,Core,FUNCTION,_("Instance : %s"),src.c_str());
    318324           
    319325      {
    … …  
    335341#endif
    336342
    337         if (_param->_have_port_queue_ptr)
     343        if (_param->_have_port_ifetch_queue_ptr)
    338344        PORT_MAP(_component,src ,"out_ADDRESS_IFETCH_QUEUE_ID"            ,
    339345                            dest,"out_ICACHE_REQ_PACKET_ID"               );
    … …  
    386392
    387393        PORT_MAP(_component,src ,"out_DECOD_ADDRESS"                    ,dest,"out_DECOD_ADDRESS"                    );
    388         if (_param->_have_port_instruction_ptr)
     394        if (_param->_have_port_inst_ifetch_ptr)
    389395        PORT_MAP(_component,src ,"out_DECOD_INST_IFETCH_PTR"            ,dest,"out_DECOD_INST_IFETCH_PTR"            );
    390396        PORT_MAP(_component,src ,"out_DECOD_BRANCH_STATE"               ,dest,"out_DECOD_BRANCH_STATE"               );
    391         if (_param->_have_port_branch_update_prediction_id)
     397        if (_param->_have_port_depth)
    392398        PORT_MAP(_component,src ,"out_DECOD_BRANCH_UPDATE_PREDICTION_ID",dest,"out_DECOD_BRANCH_UPDATE_PREDICTION_ID");
    393399        PORT_MAP(_component,src ,"out_DECOD_EXCEPTION"                  ,dest,"out_DECOD_EXCEPTION"                  );
    … …  
    404410        PORT_MAP(_component,src , "in_ICACHE_RSP_VAL"      ,dest, "in_ICACHE_RSP_VAL"      );
    405411        PORT_MAP(_component,src ,"out_ICACHE_RSP_ACK"      ,dest,"out_ICACHE_RSP_ACK"      );
    406         if (_param->_have_port_queue_ptr)
     412        if (_param->_have_port_ifetch_queue_ptr)
    407413        PORT_MAP(_component,src , "in_ICACHE_RSP_PACKET_ID",dest, "in_ICACHE_RSP_PACKET_ID");
    408414        PORT_MAP(_component,src , "in_ICACHE_RSP_ERROR"    ,dest, "in_ICACHE_RSP_ERROR"    );
    … …  
    437443    {
    438444      src = _name+"_ifetch_unit_glue";
    439       std::cout << "Instance : " << src << std::endl;
     445      log_printf(INFO,Core,FUNCTION,_("Instance : %s"),src.c_str());
    440446           
    441447      {
    … …  
    490496
    491497    // ~~~~~[ Others ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    492     if (DEBUG_Ifetch_unit == true)
    493       _component->test_map();
    494 
    495 #ifdef POSITION
    496     _component->generate_file();
     498#if DEBUG_Ifetch_unit == true
     499    _component->test_map();
     500#endif
     501   
     502#ifdef POSITION
     503    if (usage_is_set(_usage,USE_POSITION))
     504      _component->generate_file();
    497505#endif
    498506

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/src/Ifetch_unit_deallocation.cpp

    r81 r88  
    2222    log_printf(FUNC,Ifetch_unit,FUNCTION,"Begin");
    2323
    24     if (_usage & USE_SYSTEMC)
     24    if (usage_is_set(_usage,USE_SYSTEMC))
    2525      {
    2626        delete     in_CLOCK ;
    … …  
    3030        delete     in_ICACHE_REQ_ACK                      ;
    3131      //delete    out_ICACHE_REQ_THREAD_ID                ;
    32         if (_param->_have_port_queue_ptr)
     32        if (_param->_have_port_ifetch_queue_ptr)
    3333        delete    out_ICACHE_REQ_PACKET_ID                ;
    3434        delete    out_ICACHE_REQ_ADDRESS                  ;
    … …  
    3838        delete    out_ICACHE_RSP_ACK                      ;
    3939      //delete     in_ICACHE_RSP_THREAD_ID                ;
    40         if (_param->_have_port_queue_ptr)
     40        if (_param->_have_port_ifetch_queue_ptr)
    4141        delete     in_ICACHE_RSP_PACKET_ID                ;
    4242        delete []  in_ICACHE_RSP_INSTRUCTION              ;
    … …  
    5151        delete     in_PREDICT_PC_NEXT_IS_DS_TAKE          ;
    5252        delete []  in_PREDICT_INSTRUCTION_ENABLE          ;
    53         if (_param->_have_port_instruction_ptr)
     53        if (_param->_have_port_inst_ifetch_ptr)
    5454        delete     in_PREDICT_INST_IFETCH_PTR             ;
    5555        delete     in_PREDICT_BRANCH_STATE                ;
    56         if (_param->_have_port_branch_update_prediction_id)
     56        if (_param->_have_port_depth)
    5757        delete     in_PREDICT_BRANCH_UPDATE_PREDICTION_ID ;
    5858
    … …  
    6262      //delete    out_DECOD_CONTEXT_ID                    ;
    6363        delete    out_DECOD_ADDRESS                       ;
    64         if (_param->_have_port_instruction_ptr)
     64        if (_param->_have_port_inst_ifetch_ptr)
    6565        delete    out_DECOD_INST_IFETCH_PTR               ;
    6666        delete    out_DECOD_BRANCH_STATE                  ;
    67         if (_param->_have_port_branch_update_prediction_id)
     67        if (_param->_have_port_depth)
    6868        delete    out_DECOD_BRANCH_UPDATE_PREDICTION_ID   ;
    6969        delete    out_DECOD_EXCEPTION                     ;
    … …  
    7272        delete    out_EVENT_ACK                           ;
    7373        delete     in_EVENT_ADDRESS                       ;
     74        delete     in_EVENT_ADDRESS_NEXT                  ;
     75        delete     in_EVENT_ADDRESS_NEXT_VAL              ;
     76        delete     in_EVENT_IS_DS_TAKE                    ;
    7477      }
    7578    // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~   

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/src/Ifetch_unit_end_cycle.cpp

    r81 r88  
    2424
    2525#ifdef STATISTICS
    26     _stat->end_cycle();
     26    if (usage_is_set(_usage,USE_STATISTICS))
     27      _stat->end_cycle();
    2728#endif   
    2829
    … …  
    3031    // Evaluation before read the ouput signal
    3132//  sc_start(0);
    32     _interfaces->testbench();
     33    if (usage_is_set(_usage,USE_VHDL_TESTBENCH))
     34      _interfaces->testbench();
    3335#endif
    3436

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/src/Parameters.cpp

    r85 r88  
    2121                          uint32_t nb_instruction               ,
    2222                          uint32_t size_branch_update_prediction,
    23                           uint32_t size_address                 )
     23                          uint32_t size_address                 ,
     24                          bool     is_toplevel
     25                          )
    2426  {
    2527    log_printf(FUNC,Ifetch_unit,FUNCTION,"Begin");
    … …  
    2729    _size_queue                            = size_queue                   ;
    2830    _nb_instruction                        = nb_instruction               ;
    29     _size_branch_update_prediction         = size_branch_update_prediction;
    30     _size_address                          = size_address                 ;
    31 
    32     _size_queue_ptr                        = log2(size_queue);
    33     _size_instruction_ptr                  = log2(nb_instruction);
    34 
    35     _have_port_queue_ptr                   = _size_queue_ptr > 0;
    36     _have_port_instruction_ptr             = _size_instruction_ptr > 0;
    37     _have_port_branch_update_prediction_id = size_branch_update_prediction > 0;
     31//  _size_branch_update_prediction         = size_branch_update_prediction;
     32//  _size_address                          = size_address                 ;
    3833
    3934    test();
    … …  
    5045    _param_ifetch_unit_glue   = new morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::ifetch_unit_glue::  Parameters
    5146      (size_address);
    52    
     47
     48    if (is_toplevel)
     49      {
     50        _size_instruction_address   = size_address;
     51        _size_ifetch_queue_ptr      = log2(size_queue);
     52        _size_inst_ifetch_ptr       = log2(nb_instruction);
     53        _size_depth                 = size_branch_update_prediction;
     54
     55        _have_port_ifetch_queue_ptr = _size_ifetch_queue_ptr > 0;
     56        _have_port_inst_ifetch_ptr  = _size_inst_ifetch_ptr > 0;
     57        _have_port_depth            = _size_depth > 0;
     58
     59        copy ();
     60      }
     61
    5362    log_printf(FUNC,Ifetch_unit,FUNCTION,"End");
    5463  };
    … …  
    7483  };
    7584
     85#undef  FUNCTION
     86#define FUNCTION "Ifetch_unit::copy"
     87  void Parameters::copy (void)
     88  {
     89    log_printf(FUNC,Ifetch_unit,FUNCTION,"Begin");
     90   
     91    COPY(_param_address_management);
     92    COPY(_param_ifetch_queue      );
     93    COPY(_param_ifetch_unit_glue  );
     94
     95    log_printf(FUNC,Ifetch_unit,FUNCTION,"End");
     96  };
     97
    7698}; // end namespace ifetch_unit
    7799}; // end namespace front_end

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/src/Parameters_print.cpp

    r81 r88  
    2323    log_printf(FUNC,Ifetch_unit,FUNCTION,"Begin");
    2424
    25     XML xml ("ifetch_unit");
     25//     XML xml ("ifetch_unit");
    2626
    27     xml.balise_open("ifetch_unit");
    28     xml.singleton_begin("size_queue                   "); xml.attribut("value",toString(_size_queue                   )); xml.singleton_end();
    29     xml.singleton_begin("nb_instruction               "); xml.attribut("value",toString(_nb_instruction               )); xml.singleton_end();
    30     xml.singleton_begin("size_branch_update_prediction"); xml.attribut("value",toString(_size_branch_update_prediction)); xml.singleton_end();
    31     xml.singleton_begin("size_address                 "); xml.attribut("value",toString(_size_address                 )); xml.singleton_end();
    32     xml.balise_close();
     27//     xml.balise_open("ifetch_unit");
     28//     xml.singleton_begin("size_queue                   "); xml.attribut("value",toString(_size_queue                   )); xml.singleton_end();
     29//     xml.singleton_begin("nb_instruction               "); xml.attribut("value",toString(_nb_instruction               )); xml.singleton_end();
     30// //  xml.singleton_begin("size_branch_update_prediction"); xml.attribut("value",toString(_size_branch_update_prediction)); xml.singleton_end();
     31// //  xml.singleton_begin("size_address                 "); xml.attribut("value",toString(_size_address                 )); xml.singleton_end();
     32//     xml.balise_close();
     33
     34//     return xml.get_body(depth);
     35
     36    std::string str = "";
    3337
    3438    log_printf(FUNC,Ifetch_unit,FUNCTION,"End");
     39
     40    return str;
    3541   
    36     return xml.get_body(depth);
    3742  };
    3843
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