Changeset 95 for trunk/IPs/systemC/processor/Morpheo/Behavioural
- Timestamp:
- Dec 16, 2008, 5:24:26 PM (16 years ago)
- Location:
- trunk/IPs/systemC/processor/Morpheo/Behavioural
- Files:
-
- 59 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/src/test.cpp
r88 r95 54 54 //ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_MISS_PREDICTION ," in_BRANCH_EVENT_MISS_PREDICTION ",Tcontrol_t ,_param->_nb_context); 55 55 ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_ADDRESS_SRC ," in_BRANCH_EVENT_ADDRESS_SRC ",Taddress_t ,_param->_nb_context); 56 ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_ADDRESS_DEST_VAL ," in_BRANCH_EVENT_ADDRESS_DEST_VAL ",Tcontrol_t ,_param->_nb_context); 56 57 ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_ADDRESS_DEST ," in_BRANCH_EVENT_ADDRESS_DEST ",Taddress_t ,_param->_nb_context); 57 58 … … 129 130 //INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_EVENT_MISS_PREDICTION ,_param->_nb_context); 130 131 INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_EVENT_ADDRESS_SRC ,_param->_nb_context); 132 INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_EVENT_ADDRESS_DEST_VAL ,_param->_nb_context); 131 133 INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_EVENT_ADDRESS_DEST ,_param->_nb_context); 132 134 INSTANCE1_SC_SIGNAL(_Context_State, in_DECOD_EVENT_VAL ,_param->_nb_decod_unit); … … 1234 1236 //DELETE1_SC_SIGNAL( in_BRANCH_EVENT_MISS_PREDICTION ,_param->_nb_context); 1235 1237 DELETE1_SC_SIGNAL( in_BRANCH_EVENT_ADDRESS_SRC ,_param->_nb_context); 1238 DELETE1_SC_SIGNAL( in_BRANCH_EVENT_ADDRESS_DEST_VAL ,_param->_nb_context); 1236 1239 DELETE1_SC_SIGNAL( in_BRANCH_EVENT_ADDRESS_DEST ,_param->_nb_context); 1237 1240 DELETE1_SC_SIGNAL( in_DECOD_EVENT_VAL ,_param->_nb_decod_unit); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Context_State.h
r88 r95 70 70 //public : SC_IN (Tcontrol_t ) ** in_BRANCH_EVENT_MISS_PREDICTION ;//[nb_context] 71 71 public : SC_IN (Taddress_t ) ** in_BRANCH_EVENT_ADDRESS_SRC ;//[nb_context] 72 public : SC_IN (Tcontrol_t ) ** in_BRANCH_EVENT_ADDRESS_DEST_VAL ;//[nb_context] 72 73 public : SC_IN (Taddress_t ) ** in_BRANCH_EVENT_ADDRESS_DEST ;//[nb_context] 73 74 … … 116 117 public : SC_OUT(Tcontrol_t ) ** out_EVENT_ADDRESS_NEXT_VAL ;//[nb_context] 117 118 public : SC_OUT(Tcontrol_t ) ** out_EVENT_IS_DS_TAKE ;//[nb_context] 119 public : SC_OUT(Tevent_type_t ) ** out_EVENT_TYPE ;//[nb_context] 120 public : SC_OUT(Tdepth_t ) ** out_EVENT_DEPTH ;//[nb_context] 118 121 119 122 // ~~~~~[ Interface "spr_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_allocation.cpp
r88 r95 66 66 // ALLOC1_SIGNAL_IN ( in_BRANCH_EVENT_MISS_PREDICTION ,"miss_prediction" ,Tcontrol_t ,1); 67 67 ALLOC1_SIGNAL_IN ( in_BRANCH_EVENT_ADDRESS_SRC ,"address_src" ,Taddress_t ,_param->_size_instruction_address); 68 ALLOC1_SIGNAL_IN ( in_BRANCH_EVENT_ADDRESS_DEST_VAL ,"address_dest_val" ,Tcontrol_t ,1); 68 69 ALLOC1_SIGNAL_IN ( in_BRANCH_EVENT_ADDRESS_DEST ,"address_dest" ,Taddress_t ,_param->_size_instruction_address); 69 70 } -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_deallocation.cpp
r88 r95 34 34 // DELETE1_SIGNAL( in_BRANCH_EVENT_MISS_PREDICTION ,_param->_nb_context,1); 35 35 DELETE1_SIGNAL( in_BRANCH_EVENT_ADDRESS_SRC ,_param->_nb_context,_param->_size_instruction_address); 36 DELETE1_SIGNAL( in_BRANCH_EVENT_ADDRESS_DEST_VAL ,_param->_nb_context,1); 36 37 DELETE1_SIGNAL( in_BRANCH_EVENT_ADDRESS_DEST ,_param->_nb_context,_param->_size_instruction_address); 37 38 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_transition.cpp
r88 r95 69 69 if (is_valid) 70 70 { 71 Tcontrol_t dest_val = PORT_READ(in_BRANCH_EVENT_ADDRESS_DEST_VAL[i]); 71 72 reg_STATE [i] = CONTEXT_STATE_KO_MISS; 72 reg_EVENT_ADDRESS [i] = PORT_READ(in_BRANCH_EVENT_ADDRESS_SRC [i])+1; // address delay slot73 reg_EVENT_ADDRESS_EPCR [i] = PORT_READ(in_BRANCH_EVENT_ADDRESS_DEST [i]); // address_next74 reg_EVENT_ADDRESS_EPCR_VAL [i] = 1; // address_dest is valid73 reg_EVENT_ADDRESS [i] = PORT_READ(in_BRANCH_EVENT_ADDRESS_SRC [i])+1; // address delay slot 74 reg_EVENT_ADDRESS_EPCR [i] = PORT_READ(in_BRANCH_EVENT_ADDRESS_DEST [i]); // address_next 75 reg_EVENT_ADDRESS_EPCR_VAL [i] = dest_val; 75 76 //reg_EVENT_ADDRESS_EEAR [i] = 0; 76 77 reg_EVENT_ADDRESS_EEAR_VAL [i] = 0; 77 reg_EVENT_IS_DELAY_SLOT [i] = 1;78 reg_EVENT_IS_DS_TAKE [i] = 0;// ??78 reg_EVENT_IS_DELAY_SLOT [i] = dest_val; 79 reg_EVENT_IS_DS_TAKE [i] = dest_val; 79 80 reg_EVENT_DEPTH [i] = depth; 80 81 } -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/include/Decod_request.h
r88 r95 234 234 235 235 // ===== l.bf 11 236 w = y+(11 <<2);236 w = y+(11); 237 237 request.push_back (entry_t( 238 238 0x1000000b,x,y,z, … … 262 262 263 263 // ===== l.bf -9 264 w = y+(-9 <<2);264 w = y+(-9); 265 265 request.push_back (entry_t( 266 266 0x13fffff7,x,y,z, … … 290 290 291 291 // ===== l.bnf 11 292 w = y+(11 <<2);292 w = y+(11); 293 293 request.push_back (entry_t( 294 294 0x0c00000b,x,y,z, … … 318 318 319 319 // ===== l.bnf -9 320 w = y+(-9 <<2);320 w = y+(-9); 321 321 request.push_back (entry_t( 322 322 0x0ffffff7,x,y,z, … … 382 382 383 383 // ===== l.j 1018 384 w = y+(1018 <<2);384 w = y+(1018); 385 385 request.push_back (entry_t( 386 386 0x000003fa,x,y,z, … … 410 410 411 411 // ===== l.j -1018 412 w = y+(-1018 <<2);412 w = y+(-1018); 413 413 request.push_back (entry_t( 414 414 0x03fffc06,x,y,z, … … 438 438 439 439 // ===== l.jal 1018 440 w = y+(1018 <<2);440 w = y+(1018); 441 441 request.push_back (entry_t( 442 442 0x040003fa,x,y,z, … … 466 466 467 467 // ===== l.jal -1018 468 w = y+(-1018 <<2);468 w = y+(-1018); 469 469 request.push_back (entry_t( 470 470 0x07fffc06,x,y,z, -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_allocation.cpp
r88 r95 89 89 ALLOC1_SIGNAL_OUT(out_DECOD_NO_EXECUTE ,"no_execute" ,Tcontrol_t ,1 ); 90 90 ALLOC1_SIGNAL_OUT(out_DECOD_IS_DELAY_SLOT,"is_delay_slot",Tcontrol_t ,1 ); 91 ALLOC1_SIGNAL_OUT(out_DECOD_ADDRESS ,"address" ,Tgeneral_data_t ,_param->_size_instruction_address 91 ALLOC1_SIGNAL_OUT(out_DECOD_ADDRESS ,"address" ,Tgeneral_data_t ,_param->_size_instruction_address ); 92 92 ALLOC1_SIGNAL_OUT(out_DECOD_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t ,1 ); 93 93 ALLOC1_SIGNAL_OUT(out_DECOD_IMMEDIAT ,"immediat" ,Tgeneral_data_t ,_param->_size_general_data ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_allocation.cpp
r88 r95 67 67 ALLOC1_SIGNAL_IN ( in_DECOD_IN_NO_EXECUTE ,"no_execute" ,Tcontrol_t ,1 ); 68 68 ALLOC1_SIGNAL_IN ( in_DECOD_IN_IS_DELAY_SLOT ,"is_delay_slot",Tcontrol_t ,1 ); 69 ALLOC1_SIGNAL_IN ( in_DECOD_IN_ADDRESS ,"address" ,Tgeneral_data_t ,_param->_size_ general_data);69 ALLOC1_SIGNAL_IN ( in_DECOD_IN_ADDRESS ,"address" ,Tgeneral_data_t ,_param->_size_instruction_address ); 70 70 ALLOC1_SIGNAL_IN ( in_DECOD_IN_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t ,1 ); 71 71 ALLOC1_SIGNAL_IN ( in_DECOD_IN_IMMEDIAT ,"immediat" ,Tgeneral_data_t ,_param->_size_general_data ); … … 96 96 ALLOC1_SIGNAL_OUT(out_DECOD_OUT_NO_EXECUTE ,"no_execute" ,Tcontrol_t ,1 ); 97 97 ALLOC1_SIGNAL_OUT(out_DECOD_OUT_IS_DELAY_SLOT ,"is_delay_slot",Tcontrol_t ,1 ); 98 ALLOC1_SIGNAL_OUT(out_DECOD_OUT_ADDRESS ,"address" ,Tgeneral_data_t ,_param->_size_ general_data);98 ALLOC1_SIGNAL_OUT(out_DECOD_OUT_ADDRESS ,"address" ,Tgeneral_data_t ,_param->_size_instruction_address ); 99 99 ALLOC1_SIGNAL_OUT(out_DECOD_OUT_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t ,1 ); 100 100 ALLOC1_SIGNAL_OUT(out_DECOD_OUT_IMMEDIAT ,"immediat" ,Tgeneral_data_t ,_param->_size_general_data ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Parameters.cpp
r88 r95 42 42 if (is_toplevel) 43 43 { 44 _size_context_id = log2(nb_context); 45 _size_nb_inst_decod = log2(_size_queue)+1; 46 _size_depth = log2(max<uint32_t>(_nb_branch_speculated,_nb_context)); 47 _size_general_data = size_general_data; 44 _size_context_id = log2(nb_context); 45 _size_nb_inst_decod = log2(_size_queue)+1; 46 _size_depth = log2(max<uint32_t>(_nb_branch_speculated,_nb_context)); 47 _size_general_data = size_general_data; 48 _size_instruction_address = size_general_data-2; 48 49 49 _have_port_context_id = _size_context_id > 0;50 _have_port_depth = _size_depth > 0;50 _have_port_context_id = _size_context_id > 0; 51 _have_port_depth = _size_depth > 0; 51 52 52 53 copy (); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/SelfTest/src/test.cpp
r88 r95 71 71 ALLOC1_SC_SIGNAL( in_UPDATE_CONTEXT_ID ," in_UPDATE_CONTEXT_ID ",Tcontext_t,_param->_nb_inst_update ); 72 72 ALLOC1_SC_SIGNAL( in_UPDATE_PUSH ," in_UPDATE_PUSH ",Tcontrol_t,_param->_nb_inst_update ); 73 ALLOC1_SC_SIGNAL( in_UPDATE_FLUSH ," in_UPDATE_FLUSH ",Tcontrol_t,_param->_nb_inst_update ); 73 74 ALLOC1_SC_SIGNAL( in_UPDATE_INDEX ," in_UPDATE_INDEX ",Tptr_t ,_param->_nb_inst_update ); 74 75 ALLOC1_SC_SIGNAL( in_UPDATE_ADDRESS ," in_UPDATE_ADDRESS ",Taddress_t,_param->_nb_inst_update ); … … 109 110 INSTANCE1_SC_SIGNAL(_Return_Address_Stack, in_UPDATE_CONTEXT_ID ,_param->_nb_inst_update ); 110 111 INSTANCE1_SC_SIGNAL(_Return_Address_Stack, in_UPDATE_PUSH ,_param->_nb_inst_update ); 112 INSTANCE1_SC_SIGNAL(_Return_Address_Stack, in_UPDATE_FLUSH ,_param->_nb_inst_update ); 111 113 INSTANCE1_SC_SIGNAL(_Return_Address_Stack, in_UPDATE_INDEX ,_param->_nb_inst_update ); 112 114 INSTANCE1_SC_SIGNAL(_Return_Address_Stack, in_UPDATE_ADDRESS ,_param->_nb_inst_update ); … … 451 453 DELETE1_SC_SIGNAL( in_UPDATE_CONTEXT_ID ,_param->_nb_inst_update); 452 454 DELETE1_SC_SIGNAL( in_UPDATE_PUSH ,_param->_nb_inst_update); 455 DELETE1_SC_SIGNAL( in_UPDATE_FLUSH ,_param->_nb_inst_update); 453 456 DELETE1_SC_SIGNAL( in_UPDATE_ADDRESS ,_param->_nb_inst_update); 454 457 DELETE1_SC_SIGNAL( in_UPDATE_INDEX ,_param->_nb_inst_update); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/include/Return_Address_Stack.h
r82 r95 88 88 public : SC_IN (Tcontext_t) ** in_UPDATE_CONTEXT_ID ; //[nb_inst_update] 89 89 public : SC_IN (Tcontrol_t) ** in_UPDATE_PUSH ; //[nb_inst_update] 1 = push, else pop 90 public : SC_IN (Tcontrol_t) ** in_UPDATE_FLUSH ; //[nb_inst_update] 1 = push, else pop 90 91 public : SC_IN (Taddress_t) ** in_UPDATE_ADDRESS ; //[nb_inst_update] 91 92 public : SC_IN (Tptr_t ) ** in_UPDATE_INDEX ; //[nb_inst_update] -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Parameters.cpp
r88 r95 37 37 _nb_inst_update = nb_inst_update ; 38 38 39 _size_index = max<uint32_t>(size_queue,nb_context);39 _size_index = log2(max<uint32_t>(size_queue,nb_context)); 40 40 41 41 test(); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Return_Address_Stack_allocation.cpp
r88 r95 91 91 ALLOC1_SIGNAL_IN ( in_UPDATE_CONTEXT_ID ,"context_id" ,Tcontext_t,_param->_size_context_id); 92 92 ALLOC1_SIGNAL_IN ( in_UPDATE_PUSH ,"push" ,Tcontrol_t,1); 93 ALLOC1_SIGNAL_IN ( in_UPDATE_FLUSH ,"flush" ,Tcontrol_t,1); 93 94 ALLOC1_SIGNAL_IN ( in_UPDATE_ADDRESS ,"address" ,Taddress_t,_param->_size_instruction_address); 94 95 ALLOC1_SIGNAL_IN ( in_UPDATE_INDEX ,"index" ,Tptr_t ,_param->_size_index); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Return_Address_Stack_deallocation.cpp
r88 r95 52 52 DELETE1_SIGNAL( in_UPDATE_CONTEXT_ID ,_param->_nb_inst_update,_param->_size_context_id); 53 53 DELETE1_SIGNAL( in_UPDATE_PUSH ,_param->_nb_inst_update,1); 54 DELETE1_SIGNAL( in_UPDATE_FLUSH ,_param->_nb_inst_update,1); 54 55 DELETE1_SIGNAL( in_UPDATE_ADDRESS ,_param->_nb_inst_update,_param->_size_instruction_address); 55 56 DELETE1_SIGNAL( in_UPDATE_INDEX ,_param->_nb_inst_update,_param->_size_index); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Return_Address_Stack_transition.cpp
r88 r95 207 207 if (PORT_READ(in_UPDATE_VAL [i]) and internal_UPDATE_ACK [i]) 208 208 { 209 ERRORMORPHEO(FUNCTION,"Fonction à implémenter !!!!!!!!!!!!");209 throw ERRORMORPHEO(FUNCTION,"Fonction à implémenter !!!!!!!!!!!!"); 210 210 211 211 … … 217 217 // Tcontrol_t ifetch = PORT_READ(in_UPDATE_PREDICTION_IFETCH [i]); 218 218 // Tcontrol_t push = PORT_READ(in_UPDATE_PUSH [i]); 219 // Tcontrol_t flush = PORT_READ(in_UPDATE_FLUSH [i]); 219 220 // Tptr_t index = PORT_READ(in_UPDATE_INDEX [i]); 220 221 // Taddress_t address = PORT_READ(in_UPDATE_ADDRESS [i]); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/SelfTest/config_min.cfg
r88 r95 36 36 1 1 +1 # dir_pht_size_address_share [2] [3] 37 37 2 2 +1 # ras_size_queue [0] [nb_context] 38 2 2 +1 # upt_size_queue [0] [nb_context] 38 1 1 +1 # upt_size_queue [0] [nb_context] 39 1 1 +1 # ufpt_size_queue [0] [nb_context] -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/SelfTest/config_mono_context.cfg
r88 r95 6 6 1 4 *4 # nb_inst_decod [0] [nb_decod_unit] 7 7 1 1 +1 # nb_inst_branch_predict 8 12 +1 # nb_inst_branch_decod9 12 +1 # nb_inst_branch_update10 12 +1 # nb_inst_branch_complete11 2 8 * 4# btb_size_queue8 2 2 +1 # nb_inst_branch_decod 9 2 2 +1 # nb_inst_branch_update 10 2 2 +1 # nb_inst_branch_complete 11 2 8 *8 # btb_size_queue 12 12 2 2 +1 # btb_associativity 13 13 2 2 +1 # btb_size_counter … … 35 35 1 1 +1 # dir_pht_size_address_share [1] [3] 36 36 1 1 +1 # dir_pht_size_address_share [2] [3] 37 2 4 *2 # ras_size_queue [0] [nb_context] 38 2 4 *2 # upt_size_queue [0] [nb_context] 37 4 4 *2 # ras_size_queue [0] [nb_context] 38 4 4 *2 # upt_size_queue [0] [nb_context] 39 2 2 +1 # ufpt_size_queue [0] [nb_context] -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/SelfTest/config_mono_context_multi_decod.cfg
r82 r95 40 40 4 4 *2 # ras_size_queue [0] [nb_context] 41 41 4 4 *4 # upt_size_queue [0] [nb_context] 42 2 2 *4 # ufpt_size_queue [0] [nb_context] -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/SelfTest/config_multi_context.cfg
r88 r95 46 46 4 4 *4 # upt_size_queue [2] [nb_context] 47 47 8 8 *4 # upt_size_queue [3] [nb_context] 48 1 1 *4 # ufpt_size_queue [0] [nb_context] 49 4 4 *4 # ufpt_size_queue [1] [nb_context] 50 2 2 *4 # ufpt_size_queue [2] [nb_context] 51 4 4 *4 # ufpt_size_queue [3] [nb_context] -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/SelfTest/src/main.cpp
r88 r95 37 37 err (_(" * ras_size_queue [nb_context] (uint32_t )\n")); 38 38 err (_(" * upt_size_queue [nb_context] (uint32_t )\n")); 39 err (_(" * ufpt_size_queue [nb_context] (uint32_t )\n")); 39 40 40 41 exit (1); … … 57 58 uint32_t _size_address = fromString<uint32_t>(argv[x++]); 58 59 59 if (argc != static_cast<int>(2+NB_PARAMS+ 3*_nb_context+_nb_decod_unit))60 if (argc != static_cast<int>(2+NB_PARAMS+4*_nb_context+_nb_decod_unit)) 60 61 usage (argc, argv); 61 62 … … 102 103 for (uint32_t i=0; i<_nb_context; i++) 103 104 _upt_size_queue [i] = fromString<uint32_t >(argv[x++]); 105 uint32_t * _ufpt_size_queue = new uint32_t [_nb_context]; 106 for (uint32_t i=0; i<_nb_context; i++) 107 _ufpt_size_queue [i] = fromString<uint32_t >(argv[x++]); 104 108 105 109 int _return = EXIT_SUCCESS; … … 130 134 _ras_size_queue , 131 135 _upt_size_queue , 136 _ufpt_size_queue , 132 137 true // is_toplevel 133 138 ); … … 152 157 delete [] _ras_size_queue ; 153 158 delete [] _upt_size_queue ; 159 delete [] _ufpt_size_queue ; 154 160 155 161 return (_return); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/SelfTest/src/test.cpp
r88 r95 91 91 //ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_MISS_PREDICTION ,"out_BRANCH_EVENT_MISS_PREDICTION ",Tcontrol_t ,_param->_nb_context); 92 92 ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_ADDRESS_SRC ,"out_BRANCH_EVENT_ADDRESS_SRC ",Taddress_t ,_param->_nb_context); 93 ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_ADDRESS_DEST_VAL ,"out_BRANCH_EVENT_ADDRESS_DEST_VAL ",Tcontrol_t ,_param->_nb_context); 93 94 ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_ADDRESS_DEST ,"out_BRANCH_EVENT_ADDRESS_DEST ",Taddress_t ,_param->_nb_context); 94 95 96 ALLOC1_SC_SIGNAL( in_EVENT_STATE ," in_EVENT_STATE ",Tevent_state_t ,_param->_nb_context); 97 ALLOC1_SC_SIGNAL( in_EVENT_TYPE ," in_EVENT_TYPE ",Tevent_type_t ,_param->_nb_context); 98 ALLOC1_SC_SIGNAL( in_EVENT_DEPTH ," in_EVENT_DEPTH ",Tdepth_t ,_param->_nb_context); 99 95 100 ALLOC1_SC_SIGNAL(out_DEPTH_CURRENT ,"out_DEPTH_CURRENT ",Tdepth_t ,_param->_nb_context); 96 101 ALLOC1_SC_SIGNAL(out_DEPTH_MIN ,"out_DEPTH_MIN ",Tdepth_t ,_param->_nb_context); … … 152 157 //INSTANCE1_SC_SIGNAL(_Prediction_unit,out_BRANCH_EVENT_MISS_PREDICTION ,_param->_nb_context); 153 158 INSTANCE1_SC_SIGNAL(_Prediction_unit,out_BRANCH_EVENT_ADDRESS_SRC ,_param->_nb_context); 159 INSTANCE1_SC_SIGNAL(_Prediction_unit,out_BRANCH_EVENT_ADDRESS_DEST_VAL ,_param->_nb_context); 154 160 INSTANCE1_SC_SIGNAL(_Prediction_unit,out_BRANCH_EVENT_ADDRESS_DEST ,_param->_nb_context); 155 161 162 INSTANCE1_SC_SIGNAL(_Prediction_unit, in_EVENT_STATE ,_param->_nb_context); 163 INSTANCE1_SC_SIGNAL(_Prediction_unit, in_EVENT_TYPE ,_param->_nb_context); 156 164 if (_param->_have_port_depth) 157 165 { 166 INSTANCE1_SC_SIGNAL(_Prediction_unit, in_EVENT_DEPTH ,_param->_nb_context); 158 167 INSTANCE1_SC_SIGNAL(_Prediction_unit,out_DEPTH_CURRENT ,_param->_nb_context); 159 168 INSTANCE1_SC_SIGNAL(_Prediction_unit,out_DEPTH_MIN ,_param->_nb_context); … … 211 220 for (uint32_t i=0; i<_param->_nb_context; ++i) 212 221 { 213 TEST(Tcontrol_t,out_PREDICT_ACK [i]->read(),1); // Accept new request222 // TEST(Tcontrol_t,out_PREDICT_ACK [i]->read(),1); // Accept new request 214 223 TEST(Tcontrol_t,out_BRANCH_EVENT_VAL [i]->read(),0); 215 224 TEST(Tdepth_t ,out_DEPTH_CURRENT [i]->read(),0); … … 346 355 DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_ADDRESS_DEST ,_param->_nb_inst_branch_complete); 347 356 348 DELETE1_SC_SIGNAL(out_BRANCH_EVENT_VAL ,_param->_nb_context); 349 DELETE1_SC_SIGNAL( in_BRANCH_EVENT_ACK ,_param->_nb_context); 350 //DELETE1_SC_SIGNAL(out_BRANCH_EVENT_CONTEXT_ID ,_param->_nb_context); 351 //DELETE1_SC_SIGNAL(out_BRANCH_EVENT_DEPTH ,_param->_nb_context); 352 //DELETE1_SC_SIGNAL(out_BRANCH_EVENT_MISS_PREDICTION,_param->_nb_context); 353 DELETE1_SC_SIGNAL(out_BRANCH_EVENT_ADDRESS_SRC ,_param->_nb_context); 354 DELETE1_SC_SIGNAL(out_BRANCH_EVENT_ADDRESS_DEST ,_param->_nb_context); 357 DELETE1_SC_SIGNAL(out_BRANCH_EVENT_VAL ,_param->_nb_context); 358 DELETE1_SC_SIGNAL( in_BRANCH_EVENT_ACK ,_param->_nb_context); 359 //DELETE1_SC_SIGNAL(out_BRANCH_EVENT_CONTEXT_ID ,_param->_nb_context); 360 //DELETE1_SC_SIGNAL(out_BRANCH_EVENT_DEPTH ,_param->_nb_context); 361 //DELETE1_SC_SIGNAL(out_BRANCH_EVENT_MISS_PREDICTION ,_param->_nb_context); 362 DELETE1_SC_SIGNAL(out_BRANCH_EVENT_ADDRESS_SRC ,_param->_nb_context); 363 DELETE1_SC_SIGNAL(out_BRANCH_EVENT_ADDRESS_DEST_VAL ,_param->_nb_context); 364 DELETE1_SC_SIGNAL(out_BRANCH_EVENT_ADDRESS_DEST ,_param->_nb_context); 365 366 DELETE1_SC_SIGNAL( in_EVENT_STATE ,_param->_nb_context); 367 DELETE1_SC_SIGNAL( in_EVENT_TYPE ,_param->_nb_context); 368 DELETE1_SC_SIGNAL( in_EVENT_DEPTH ,_param->_nb_context); 355 369 356 370 DELETE1_SC_SIGNAL(out_DEPTH_CURRENT ,_param->_nb_context); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/config_mono_context.cfg
r94 r95 1 1 Update_Prediction_Table 2 2 1 1 +1 # nb_context 3 4 8 *2# size_upt_queue [0] [nb_context]3 4 8 +1 # size_upt_queue [0] [nb_context] 4 4 1 4 +1 # size_ufpt_queue [0] [nb_context] 5 5 32 32 *2 # size_address -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/src/test.cpp
r94 r95 7 7 */ 8 8 9 #define NB_ITERATION 810 #define CYCLE_MAX (1 28*NB_ITERATION)9 #define NB_ITERATION 16 10 #define CYCLE_MAX (1024*NB_ITERATION) 11 11 12 12 #include "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/include/test.h" … … 136 136 ALLOC1_SC_SIGNAL(out_UPDATE_RAS_INDEX ,"out_UPDATE_RAS_INDEX ",Tptr_t ,_param->_nb_inst_update); 137 137 ALLOC1_SC_SIGNAL(out_UPDATE_RAS_PREDICTION_IFETCH ,"out_UPDATE_RAS_PREDICTION_IFETCH ",Tcontrol_t ,_param->_nb_inst_update); 138 139 ALLOC1_SC_SIGNAL( in_EVENT_STATE ," in_EVENT_STATE ",Tevent_state_t ,_param->_nb_context); 140 ALLOC1_SC_SIGNAL( in_EVENT_TYPE ," in_EVENT_TYPE ",Tevent_type_t ,_param->_nb_context); 141 ALLOC1_SC_SIGNAL( in_EVENT_DEPTH ," in_EVENT_DEPTH ",Tdepth_t ,_param->_nb_context); 142 138 143 ALLOC1_SC_SIGNAL(out_DEPTH_CURRENT ,"out_DEPTH_CURRENT ",Tdepth_t ,_param->_nb_context); 139 144 ALLOC1_SC_SIGNAL(out_DEPTH_MIN ,"out_DEPTH_MIN ",Tdepth_t ,_param->_nb_context); … … 225 230 INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_INDEX ,_param->_nb_inst_update); 226 231 INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_PREDICTION_IFETCH ,_param->_nb_inst_update); 232 INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_EVENT_STATE ,_param->_nb_context); 233 INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_EVENT_TYPE ,_param->_nb_context); 227 234 if (_param->_have_port_depth) 228 235 { 236 INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_EVENT_DEPTH ,_param->_nb_context); 229 237 INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_DEPTH_CURRENT ,_param->_nb_context); 230 238 INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_DEPTH_MIN ,_param->_nb_context); … … 253 261 const int32_t percent_transaction_branch_event = 75; 254 262 255 const bool test1 = false;256 const bool test2 = false;257 const bool test3 = false;263 const bool test1 = true; 264 const bool test2 = true; 265 const bool test3 = true; 258 266 const bool test4 = true; 259 267 … … 270 278 in_NRESET->write(1); 271 279 272 Tdepth_t ufpt_bottom [_param->_nb_context]; 273 Tdepth_t ufpt_top [_param->_nb_context]; 274 275 Tdepth_t upt_bottom [_param->_nb_context]; 276 Tdepth_t upt_top [_param->_nb_context]; 280 Tdepth_t ufpt_bottom [_param->_nb_context]; 281 Tdepth_t ufpt_top [_param->_nb_context]; 282 283 Tdepth_t upt_bottom [_param->_nb_context]; 284 Tdepth_t upt_top [_param->_nb_context]; 285 Tdepth_t upt_top_event[_param->_nb_context]; 277 286 278 287 for (uint32_t i=0; i<_param->_nb_context; ++i) 279 288 { 280 ufpt_bottom [i] = 0; 281 ufpt_top [i] = 0; 282 upt_bottom [i] = 0; 283 upt_top [i] = 0; 289 ufpt_bottom [i] = 0; 290 ufpt_top [i] = 0; 291 upt_bottom [i] = 0; 292 upt_top [i] = 0; 293 upt_top_event[i] = 0; 284 294 } 285 295 … … 305 315 for (uint32_t i=0; i<_param->_nb_inst_update; ++i) 306 316 in_UPDATE_ACK [i]->write(0); 307 317 for (uint32_t i=0; i<_param->_nb_context; ++i) 318 { 319 in_EVENT_STATE [i]->write(EVENT_STATE_NO_EVENT); 320 in_EVENT_TYPE [i]->write(EVENT_TYPE_NONE ); 321 } 308 322 //--------------------------------------------------------------------- 309 323 //--------------------------------------------------------------------- … … 913 927 } 914 928 } 915 929 930 { 931 LABEL("EVENT_STATE"); 932 933 SC_START(1); 934 in_EVENT_STATE [context]->write(EVENT_STATE_END ); 935 in_EVENT_TYPE [context]->write(EVENT_TYPE_MISS_SPECULATION); 936 937 SC_START(1); 938 in_EVENT_STATE [context]->write(EVENT_STATE_NO_EVENT ); 939 in_EVENT_TYPE [context]->write(EVENT_TYPE_NONE ); 940 } 916 941 917 942 // Wait Garbage Collector … … 1337 1362 } 1338 1363 1364 { 1365 LABEL("EVENT_STATE"); 1366 1367 SC_START(1); 1368 in_EVENT_STATE [context]->write(EVENT_STATE_END ); 1369 in_EVENT_TYPE [context]->write(EVENT_TYPE_MISS_SPECULATION); 1370 1371 SC_START(1); 1372 in_EVENT_STATE [context]->write(EVENT_STATE_NO_EVENT ); 1373 in_EVENT_TYPE [context]->write(EVENT_TYPE_NONE ); 1374 } 1375 1339 1376 // Wait Garbage Collector 1340 1377 { … … 1378 1415 request.take_good = 1; 1379 1416 request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good); 1380 request.is_accurate = false;1417 request.is_accurate = true ; 1381 1418 request.miss_ifetch = false; 1382 1419 request.miss_decod = false; … … 1472 1509 LABEL("DECOD [%d] %d - %d", 1473 1510 port, 1474 in_ PREDICT_VAL [port]->read(),1475 out_ PREDICT_ACK [port]->read());1511 in_DECOD_VAL [port]->read(), 1512 out_DECOD_ACK [port]->read()); 1476 1513 1477 1514 if (in_DECOD_VAL [port]->read() and out_DECOD_ACK [port]->read()) … … 1520 1557 request.take_good = 1; 1521 1558 request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good); 1522 request.is_accurate = false;1559 request.is_accurate = true ; 1523 1560 request.miss_ifetch = false; 1524 1561 request.miss_decod = false; … … 1583 1620 std::list<request_t>::iterator it_event; 1584 1621 { 1585 LABEL("BRANCH_COMPLETE - hitifetch");1622 LABEL("BRANCH_COMPLETE - Miss ifetch"); 1586 1623 1587 1624 uint32_t port = rand() % _param->_nb_inst_branch_complete; … … 1600 1637 1601 1638 if (update_ras(it_event->condition)) 1602 it_event->address_good = ~(it_event->address_dest); 1639 { 1640 it_event->address_good = ~(it_event->address_dest); 1641 } 1603 1642 else 1604 1643 { … … 1649 1688 TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_DEST [port]->read(),it_event->address_good); 1650 1689 1651 upt_top [it_event->context] = it_event->upt_ptr; 1690 upt_top_event [it_event->context] = upt_top [it_event->context]; 1691 upt_top [it_event->context] = it_event->upt_ptr; 1692 } 1693 1694 SC_START(1); 1695 } while (not have_transaction); 1696 1697 in_BRANCH_COMPLETE_VAL [port]->write(0); 1698 1699 if (_param->_have_port_depth) 1700 TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]); 1701 TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]); 1702 } 1703 } 1704 1705 { 1706 LABEL("BRANCH_COMPLETE - Hit ifetch"); 1707 1708 uint32_t port = rand() % _param->_nb_inst_branch_complete; 1709 1710 LABEL(" * port : %d",port); 1711 1712 std::list<request_t>::iterator it_upt = upt.begin(); 1713 1714 while (it_upt != it_event) 1715 { 1716 bool have_transaction = false; 1717 1718 do 1719 { 1720 in_BRANCH_COMPLETE_VAL [port]->write((rand()%100)<percent_transaction_branch_complete); 1721 in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(it_upt->context ); 1722 in_BRANCH_COMPLETE_DEPTH [port]->write(it_upt->upt_ptr ); 1723 in_BRANCH_COMPLETE_ADDRESS [port]->write(it_upt->address_dest); 1724 in_BRANCH_COMPLETE_FLAG [port]->write(it_upt->flag ); 1725 1726 if (_param->_have_port_depth) 1727 TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]); 1728 TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]); 1729 1730 SC_START(0); 1731 1732 LABEL("BRANCH_COMPLETE [%d] %d - %d.",port,in_BRANCH_COMPLETE_VAL [port]->read(),out_BRANCH_COMPLETE_ACK [port]->read()); 1733 1734 if (in_BRANCH_COMPLETE_VAL [port]->read() and out_BRANCH_COMPLETE_ACK [port]->read()) 1735 { 1736 LABEL("BRANCH_COMPLETE [%d] - Transaction accepted",port); 1737 LABEL(" * CONTEXT_ID %d" ,it_upt->context ); 1738 LABEL(" * DEPTH %d" ,it_upt->upt_ptr ); 1739 LABEL(" * CONDITION %d" ,it_upt->condition ); 1740 LABEL(" * ADDRESS %.8x",it_upt->address_dest); 1741 LABEL(" * FLAG %d" ,it_upt->flag ); 1742 1743 have_transaction = true; 1744 1745 TEST(Tcontrol_t,out_BRANCH_COMPLETE_MISS_PREDICTION[port]->read(),it_upt->miss_commit ); 1746 TEST(Tcontrol_t,out_BRANCH_COMPLETE_TAKE [port]->read(),it_upt->take ); 1747 it_upt->take_good = it_upt->take; 1748 TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_SRC [port]->read(),it_upt->address_src ); 1749 TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_DEST [port]->read(),it_upt->address_dest); 1750 1751 it_upt++; 1652 1752 } 1653 1753 … … 1740 1840 1741 1841 { 1742 LABEL("UPDATE - upt ");1842 LABEL("UPDATE - upt (after event)"); 1743 1843 1744 1844 uint32_t port = 0; … … 1746 1846 LABEL(" * port : %d",port); 1747 1847 std::list<request_t>::iterator it_upt = upt.end(); 1748 --it_upt;1749 1848 1750 1849 // for (uint32_t i=0; i<upt.size(); i++) 1751 while (it_upt != it_event)1850 do 1752 1851 { 1852 --it_upt; 1853 1753 1854 bool have_transaction = false; 1754 1855 1856 if (need_update(it_upt->condition)) 1755 1857 do 1756 1858 { … … 1768 1870 { 1769 1871 LABEL("UPDATE [%d] - Transaction accepted",port); 1872 LABEL(" * address_src : %.8x",it_upt->address_src); 1873 LABEL(" * out_UPDATE_BTB_ADDRESS_SRC : %.8x",out_UPDATE_BTB_ADDRESS_SRC[port]->read()); 1874 1770 1875 have_transaction = true; 1771 1876 1877 bool btb_val = ((it_upt == it_event) and 1878 (update_btb(it_upt->condition))); 1879 bool dir_val = ((it_upt == it_event) and 1880 update_dir(it_upt->condition) and 1881 not (it_upt->miss_ifetch or it_upt->miss_decod)); 1882 bool ras_val = update_ras(it_upt->condition); 1883 1772 1884 if (_param->_have_port_context_id) 1773 1885 TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_upt->context); 1774 1886 TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),it_upt->miss_commit); 1775 TEST(Tcontrol_t ,out_UPDATE_ DIRECTION_GOOD [port]->read(),it_upt->take_good);1776 TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),update_btb(it_upt->condition)); 1777 if ( update_btb(it_upt->condition))1887 TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),btb_val); 1888 1889 if (btb_val) 1778 1890 { 1779 1891 TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_upt->address_src); … … 1781 1893 TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_upt->condition); 1782 1894 } 1783 TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(), update_dir(it_upt->condition) and not (it_upt->miss_ifetch or it_upt->miss_decod));1895 TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),dir_val); 1784 1896 1785 if (update_dir(it_upt->condition)) 1897 if (dir_val) 1898 { 1899 TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_upt->take_good); 1786 1900 if (_param->_have_port_history) 1787 1901 TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_upt->history); 1788 TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),update_ras(it_upt->condition)); 1789 if (update_ras(it_upt->condition)) 1902 } 1903 TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),ras_val); 1904 1905 if (ras_val) 1790 1906 { 1791 1907 // TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0); … … 1796 1912 } 1797 1913 1798 -- it_upt;1914 // -- it_upt; 1799 1915 } 1800 1916 … … 1808 1924 // TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]); 1809 1925 } 1926 while (it_upt != it_event); 1927 1810 1928 } 1811 // upt.clear(); // Not yet 1812 1929 1813 1930 { 1814 1931 LABEL("BRANCH_EVENT - have miss decod"); … … 1852 1969 } 1853 1970 } 1854 1971 1855 1972 { 1856 LABEL("UPDATE - upt"); 1973 LABEL("EVENT_STATE"); 1974 1975 SC_START(1); 1976 in_EVENT_STATE [context]->write(EVENT_STATE_END ); 1977 in_EVENT_TYPE [context]->write(EVENT_TYPE_MISS_SPECULATION); 1978 1979 SC_START(1); 1980 in_EVENT_STATE [context]->write(EVENT_STATE_NO_EVENT ); 1981 in_EVENT_TYPE [context]->write(EVENT_TYPE_NONE ); 1982 } 1983 1984 { 1985 LABEL("UPDATE - upt (before event)"); 1857 1986 1858 1987 uint32_t port = 0; 1859 1988 1860 1989 LABEL(" * port : %d",port); 1990 LABEL(" * size : %d",upt.size()); 1861 1991 std::list<request_t>::iterator it_upt = upt.begin(); 1862 1992 … … 1908 2038 } 1909 2039 1910 --it_upt;2040 ++ it_upt; 1911 2041 } 1912 2042 … … 1920 2050 } 1921 2051 } 1922 upt.clear(); // Not yet2052 upt.clear(); 1923 2053 1924 2054 // Wait Garbage Collector 1925 2055 { 1926 upt_bottom [context] = (upt_bottom [context]+1)%_param->_size_upt_queue[context]; 1927 // upt_top [context] = (upt_top [context]); 2056 LABEL("GARBAGE COLLECTOR"); 2057 LABEL(" * upt bottom : %d",upt_bottom [context]); 2058 LABEL(" * upt top : %d",upt_top [context]); 2059 2060 upt_top [context] = (upt_top_event [context]); 2061 upt_bottom [context] = (upt_top [context]); 1928 2062 1929 2063 while ((upt_bottom [context] != out_DEPTH_MIN [context]->read()) or 1930 2064 (upt_top [context] != out_DEPTH_MAX [context]->read())) 1931 SC_START(1); 2065 { 2066 SC_START(1); 2067 } 1932 2068 1933 2069 } … … 1993 2129 delete [] out_BRANCH_EVENT_VAL ; 1994 2130 delete [] in_BRANCH_EVENT_ACK ; 1995 // 1996 // 1997 // 2131 //delete [] in_BRANCH_EVENT_CONTEXT_ID ; 2132 //delete [] in_BRANCH_EVENT_DEPTH ; 2133 //delete [] out_BRANCH_EVENT_MISS_PREDICTION; 1998 2134 delete [] out_BRANCH_EVENT_ADDRESS_SRC ; 1999 2135 delete [] out_BRANCH_EVENT_ADDRESS_DEST_VAL; … … 2019 2155 delete [] out_UPDATE_RAS_PREDICTION_IFETCH; 2020 2156 2157 DELETE1_SC_SIGNAL( in_EVENT_STATE ,_param->_nb_context); 2158 DELETE1_SC_SIGNAL( in_EVENT_TYPE ,_param->_nb_context); 2159 DELETE1_SC_SIGNAL( in_EVENT_DEPTH ,_param->_nb_context); 2160 2021 2161 // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2022 2162 delete [] out_DEPTH_CURRENT; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Types.h
r88 r95 21 21 typedef enum 22 22 { 23 EVENT_STATE_OK , // Can predict24 EVENT_STATE_FLUSH_UFPT , // in decod stage, detect a miss, continue to execute but flush ufpt25 EVENT_STATE_FLUSH_UFPT_AND_UPT , // in commit stage, detect a miss, stop context and flush ufpt and upt26 EVENT_STATE_FLUSH_UPT _RAS, // in commit stage, detect a miss, context is stop and ufpt is flush, update RAS27 EVENT_STATE_ FLUSH_UPT , // in commit stage, detect a miss, context is stop and ufpt is flush28 EVENT_STATE_ UPDATE_CONTEXT // prediction unit is update, send signal to context manager23 EVENT_STATE_OK , // Can predict 24 EVENT_STATE_FLUSH_UFPT , // in decod stage, detect a miss, continue to execute but flush ufpt 25 EVENT_STATE_FLUSH_UFPT_AND_UPT , // in commit stage, detect a miss, stop context and flush ufpt and upt 26 EVENT_STATE_FLUSH_UPT , // in commit stage, detect a miss, context is stop and ufpt is flush, update RAS 27 EVENT_STATE_UPDATE_CONTEXT , // prediction unit is update, send signal to context manager 28 EVENT_STATE_WAIT_END_EVENT // prediction unit is ok, wait the end of envent (send by Context State) 29 29 } event_state_t; 30 30 … … 44 44 UPDATE_PREDICTION_STATE_KO , // this branch is a miss prediction 45 45 UPDATE_PREDICTION_STATE_EVENT , // previous branch is a miss prediction 46 UPDATE_PREDICTION_STATE_END // branch is updated 46 UPDATE_PREDICTION_STATE_END_OK , // branch is updated, update pointer 47 UPDATE_PREDICTION_STATE_END_KO // branch is updated, don't update pointer 47 48 } upt_state_t; 48 49 … … 114 115 switch (x) 115 116 { 116 case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::EVENT_STATE_OK : return "ok"; break;117 case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::EVENT_STATE_FLUSH_UFPT : return "flush_ufpt"; break;118 case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::EVENT_STATE_FLUSH_UFPT_AND_UPT : return "flush_ufpt_and_upt"; break;119 case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::EVENT_STATE_FLUSH_UPT _RAS : return "flush_upt_ras"; break;120 case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::EVENT_STATE_ FLUSH_UPT : return "flush_upt"; break;121 case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::EVENT_STATE_ UPDATE_CONTEXT : return "update_context"; break;117 case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::EVENT_STATE_OK : return "ok" ; break; 118 case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::EVENT_STATE_FLUSH_UFPT : return "flush_ufpt" ; break; 119 case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::EVENT_STATE_FLUSH_UFPT_AND_UPT : return "flush_ufpt_and_upt" ; break; 120 case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::EVENT_STATE_FLUSH_UPT : return "flush_upt" ; break; 121 case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::EVENT_STATE_UPDATE_CONTEXT : return "update_context" ; break; 122 case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::EVENT_STATE_WAIT_END_EVENT : return "wait_and_event" ; break; 122 123 default : return "" ; break; 123 124 } … … 145 146 case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::UPDATE_PREDICTION_STATE_KO : return "ko" ; break; 146 147 case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::UPDATE_PREDICTION_STATE_EVENT : return "event" ; break; 147 case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::UPDATE_PREDICTION_STATE_END : return "end" ; break; 148 case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::UPDATE_PREDICTION_STATE_END_OK : return "end_ok" ; break; 149 case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::UPDATE_PREDICTION_STATE_END_KO : return "end_ko" ; break; 148 150 default : return "" ; break; 149 151 } -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Update_Prediction_Table.h
r94 r95 170 170 private : uint32_t * reg_UPT_BOTTOM ; //[nb_context] 171 171 private : uint32_t * reg_UPT_TOP ; //[nb_context] 172 private : uint32_t * reg_UPT_TOP_EVENT ; //[nb_context] 172 173 private : uint32_t * reg_UPT_UPDATE ; //[nb_context] 173 174 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_allocation.cpp
r94 r95 197 197 ALLOC1(reg_UPT_BOTTOM ,uint32_t ,_param->_nb_context); 198 198 ALLOC1(reg_UPT_TOP ,uint32_t ,_param->_nb_context); 199 ALLOC1(reg_UPT_TOP_EVENT ,uint32_t ,_param->_nb_context); 199 200 ALLOC1(reg_UPT_UPDATE ,uint32_t ,_param->_nb_context); 200 201 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_deallocation.cpp
r94 r95 80 80 81 81 // ~~~~~[ Interface : "branch_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 82 delete [] out_BRANCH_EVENT_VAL ; 83 delete [] in_BRANCH_EVENT_ACK ; 84 // if (_param->_have_port_context_id) 85 // delete [] in_BRANCH_EVENT_CONTEXT_ID ; 86 // if (_param->_have_port_depth) 87 // delete [] in_BRANCH_EVENT_DEPTH ; 88 // delete [] out_BRANCH_EVENT_MISS_PREDICTION; 89 delete [] out_BRANCH_EVENT_ADDRESS_SRC ; 90 delete [] out_BRANCH_EVENT_ADDRESS_DEST_VAL; 91 delete [] out_BRANCH_EVENT_ADDRESS_DEST ; 92 82 DELETE1_SIGNAL(out_BRANCH_EVENT_VAL ,_param->_nb_context,1); 83 DELETE1_SIGNAL( in_BRANCH_EVENT_ACK ,_param->_nb_context,1); 84 // DELETE1_SIGNAL(out_BRANCH_EVENT_CONTEXT_ID ,_param->_nb_context,_param->_size_context_id); 85 // DELETE1_SIGNAL(out_BRANCH_EVENT_DEPTH ,_param->_nb_context,_param->_size_depth); 86 // DELETE1_SIGNAL(out_BRANCH_EVENT_MISS_PREDICTION ,_param->_nb_context,1); 87 DELETE1_SIGNAL(out_BRANCH_EVENT_ADDRESS_SRC ,_param->_nb_context,_param->_size_instruction_address); 88 DELETE1_SIGNAL(out_BRANCH_EVENT_ADDRESS_DEST_VAL ,_param->_nb_context,1); 89 DELETE1_SIGNAL(out_BRANCH_EVENT_ADDRESS_DEST ,_param->_nb_context,_param->_size_instruction_address); 90 93 91 // ~~~~~[ Interface : "update" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 94 92 delete [] out_UPDATE_VAL ; … … 118 116 119 117 // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 120 if (_param->_have_port_depth) 121 { 122 delete [] out_DEPTH_CURRENT; 123 delete [] out_DEPTH_MIN; 124 } 125 delete [] out_DEPTH_MAX; 126 118 DELETE1_SIGNAL(out_DEPTH_CURRENT ,_param->_nb_context,_param->_size_depth); 119 DELETE1_SIGNAL(out_DEPTH_MIN ,_param->_nb_context,_param->_size_depth); 120 DELETE1_SIGNAL(out_DEPTH_MAX ,_param->_nb_context,_param->_size_depth+1); 121 127 122 // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 128 123 DELETE1(internal_PREDICT_ACK ,_param->_nb_inst_predict); … … 155 150 DELETE1(reg_UPT_BOTTOM ,_param->_nb_context); 156 151 DELETE1(reg_UPT_TOP ,_param->_nb_context); 152 DELETE1(reg_UPT_TOP_EVENT ,_param->_nb_context); 157 153 DELETE1(reg_UPT_UPDATE ,_param->_nb_context); 158 154 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_genMealy_decod.cpp
r88 r95 26 26 27 27 // WARNING : One branch per context per cycle 28 if (PORT_READ(in_NRESET) != 0) 29 { 28 30 for (uint32_t i=0; i<_param->_nb_inst_decod; i++) 29 31 { … … 58 60 PORT_WRITE(out_DECOD_ACK [i], internal_DECOD_ACK [i]); 59 61 } 60 62 } 61 63 log_end(Update_Prediction_Table,FUNCTION); 62 64 }; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_genMoore.cpp
r94 r95 57 57 event_state_t event_state = reg_EVENT_STATE [i]; 58 58 59 retire_ras_from_ufpt [i] = ((event_state == EVENT_STATE_FLUSH_UFPT ) or59 retire_ras_from_ufpt [i] = ((event_state == EVENT_STATE_FLUSH_UFPT ) or 60 60 (event_state == EVENT_STATE_FLUSH_UFPT_AND_UPT)); 61 retire_ras_from_upt [i] = (event_state == EVENT_STATE_FLUSH_UPT _RAS);61 retire_ras_from_upt [i] = (event_state == EVENT_STATE_FLUSH_UPT); 62 62 63 63 ufpt_update [i] = true; … … 154 154 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * condition : %s",toString(condition).c_str()); 155 155 156 Tcontrol_t state_is_ok_ko = ((state == UPDATE_PREDICTION_STATE_OK) or 157 (state == UPDATE_PREDICTION_STATE_KO)); 158 Tcontrol_t state_is_event = (state == UPDATE_PREDICTION_STATE_EVENT); 156 Tcontrol_t state_is_ok_ko = ((state == UPDATE_PREDICTION_STATE_OK ) or 157 (state == UPDATE_PREDICTION_STATE_KO )); 158 Tcontrol_t state_is_event = ((state == UPDATE_PREDICTION_STATE_KO ) or 159 (state == UPDATE_PREDICTION_STATE_EVENT)); 159 160 Tcontrol_t state_is_event_update = state_is_event and need_update(condition); 160 161 Tcontrol_t state_is_event_no_update = state_is_event and not need_update(condition); … … 167 168 else 168 169 { 169 val = state_is_ok_ko;170 val = (state == UPDATE_PREDICTION_STATE_OK); 170 171 val_without_ack = false; 171 172 } … … 173 174 miss_prediction = (state != UPDATE_PREDICTION_STATE_OK); 174 175 direction_good = reg_UPDATE_PREDICTION_TABLE [context][depth]._good_take ; 175 btb_val = update_btb(condition);176 btb_val = state_is_ok_ko and update_btb(condition); 176 177 btb_address_src = reg_UPDATE_PREDICTION_TABLE [context][depth]._address_src ; 177 178 btb_address_dest = reg_UPDATE_PREDICTION_TABLE [context][depth]._address_dest; 178 179 btb_condition = condition; 179 dir_val = update_dir(condition) and ifetch; // if not ifetch, then static prediction180 dir_val = state_is_ok_ko and update_dir(condition) and ifetch; // if not ifetch, then static prediction 180 181 dir_history = reg_UPDATE_PREDICTION_TABLE [context][depth]._history ; 181 182 ras_val = update_ras(condition); // repop/ repush data -> don't corrupt ras … … 208 209 } 209 210 } 210 211 211 212 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * val : %d",val ); 212 213 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * val_without_ack : %d",val_without_ack); 214 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss_prediction : %d",miss_prediction); 215 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * direction_good : %d",direction_good ); 213 216 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * btb_val : %d",btb_val); 214 217 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * dir_val : %d",dir_val); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_transition.cpp
r94 r95 44 44 reg_UPT_BOTTOM [i] = 0; 45 45 reg_UPT_TOP [i] = 0; 46 reg_UPT_TOP_EVENT [i] = 0; 46 47 reg_UPT_UPDATE [i] = 0; 47 48 … … 87 88 { 88 89 uint32_t bottom = reg_UPT_BOTTOM [i]; 89 90 bool end_ok = (reg_UPDATE_PREDICTION_TABLE [i][bottom]._state == UPDATE_PREDICTION_STATE_END_OK); 91 bool end_ko = (reg_UPDATE_PREDICTION_TABLE [i][bottom]._state == UPDATE_PREDICTION_STATE_END_KO); 92 90 93 // Test if state is end 91 if ( reg_UPDATE_PREDICTION_TABLE [i][bottom]._state == UPDATE_PREDICTION_STATE_END)94 if (end_ok or end_ko) 92 95 { 93 96 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d]",i,bottom); … … 96 99 // Free slot 97 100 reg_UPDATE_PREDICTION_TABLE [i][bottom]._state = UPDATE_PREDICTION_STATE_EMPTY; 101 98 102 // Update pointer 99 103 reg_UPT_BOTTOM [i] = (bottom+1)%_param->_size_upt_queue[i]; 104 // if (bottom = reg_UPT_UPDATE [i]) 105 // reg_UPT_UPDATE [i] = reg_UPT_BOTTOM [i]; 106 if (end_ko) // free 107 { 108 reg_UPT_TOP [i] = reg_UPT_TOP_EVENT [i]; 109 reg_UPT_UPDATE [i] = reg_UPT_TOP_EVENT [i]; 110 } 100 111 } 101 112 } … … 299 310 300 311 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * BRANCH_COMPLETE[%d] - Accepted",i); 301 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context);302 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth : %d",depth);303 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss : %d",miss);312 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context); 313 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth : %d",depth); 314 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss : %d",miss); 304 315 305 316 if (miss) … … 312 323 uint32_t top = reg_UPT_TOP [context]; 313 324 uint32_t new_update = ((top==0)?_param->_size_upt_queue[context]:top)-1; 325 326 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * top : %d",top); 327 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * new_update : %d",new_update); 328 314 329 for (uint32_t j=(depth+1)%_param->_size_upt_queue[context]; 315 330 j!=top; … … 317 332 reg_UPDATE_PREDICTION_TABLE [context][j]._state = UPDATE_PREDICTION_STATE_EVENT; 318 333 319 // TOP is next write slot : last slot is TOP-1 320 reg_UPT_UPDATE [context] = new_update; 321 322 // reg_UPT_BOTTOM [context]; 323 reg_UPT_TOP [context] = depth; 334 335 // reg_UPT_BOTTOM [context]; 336 reg_UPT_TOP [context] = depth; 337 reg_UPT_TOP_EVENT [context] = top; 324 338 325 339 #ifdef DEBUG_TEST … … 331 345 reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_KO; 332 346 333 334 Taddress_t address_src = reg_UPDATE_PREDICTION_TABLE [context][depth]._address_src; 347 Taddress_t address_src = reg_UPDATE_PREDICTION_TABLE [context][depth]._address_src; 348 event_state_t event_state = reg_EVENT_STATE [context]; 349 bool previous_update_ras = (event_state == EVENT_STATE_FLUSH_UPT); 350 bool update_ras = (new_update != depth); 351 352 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * update_ras : %d",update_ras); 335 353 336 354 if (reg_UFPT_NB_NEED_UPDATE [context] > 0) … … 341 359 else 342 360 { 343 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_FLUSH_UFPT_RAS (branch_complete - miss)",context); 344 // have ras prediction ? 345 reg_EVENT_STATE [context] = (new_update!=depth)?EVENT_STATE_FLUSH_UPT_RAS:EVENT_STATE_UPDATE_CONTEXT; 346 } 361 if (not previous_update_ras) 362 { 363 // have ras prediction ? 364 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_FLUSH_UPT (branch_complete - miss)",context); 365 366 reg_EVENT_STATE [context] = EVENT_STATE_FLUSH_UPT; 367 368 } 369 } 370 371 if (not previous_update_ras) 372 { 373 reg_UPT_UPDATE [context] = new_update; 374 } 375 // else no update 347 376 348 377 reg_EVENT_ADDRESS_SRC [context] = address_src; // delay_slot is compute in Context_State … … 370 399 // =====[ UPDATE ]==================================================== 371 400 // =================================================================== 372 for (uint32_t i=0; i<_param->_nb_inst_update; i++) 373 if ((internal_UPDATE_VAL[i] and PORT_READ(in_UPDATE_ACK [i])) or 374 (internal_UPDATE_VAL_WITHOUT_ACK [i]))375 { 376 Tcontext_t context = internal_UPDATE_CONTEXT_ID [i]; 377 Tdepth_t depth = internal_UPDATE_DEPTH [i]; 378 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPDATE[%d] - Accepted",i); 379 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context);380 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth : %d",depth); 381 382 if (internal_UPDATE_FROM_UFPT [i])401 { 402 bool can_continue [_param->_nb_context]; 403 for (uint32_t i=0; i<_param->_nb_context; ++i) 404 can_continue [i] = true; 405 406 for (uint32_t i=0; i<_param->_nb_inst_update; i++) 407 { 408 Tcontext_t context = internal_UPDATE_CONTEXT_ID [i]; 409 410 if ((internal_UPDATE_VAL[i] and PORT_READ(in_UPDATE_ACK [i])) or 411 (internal_UPDATE_VAL_WITHOUT_ACK [i] and can_continue [context])) 383 412 { 384 // if free a slot, also all queue is updated 385 // Last slot ? 386 if (reg_UFPT_UPDATE [context] == reg_UFPT_BOTTOM [context]) 387 switch (reg_EVENT_STATE [context]) 388 { 389 case EVENT_STATE_FLUSH_UFPT : reg_EVENT_STATE [context] = EVENT_STATE_UPDATE_CONTEXT; break; 390 case EVENT_STATE_FLUSH_UFPT_AND_UPT : reg_EVENT_STATE [context] = (reg_UPT_UPDATE[context]!=reg_UPT_TOP[context])?EVENT_STATE_FLUSH_UPT_RAS:EVENT_STATE_UPDATE_CONTEXT; break; 391 default : break; 392 } 393 394 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Update Fetch Prediction Table"); 395 396 // Change state 397 #ifdef DEBUG_TEST 398 if (reg_UPDATE_FETCH_PREDICTION_TABLE [context][depth]._state != UPDATE_FETCH_PREDICTION_STATE_EVENT) 399 throw ERRORMORPHEO(FUNCTION,_("Update : invalid ufpt state.")); 400 #endif 401 402 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UFPT [%d][%d].state <- UPDATE_FETCH_PREDICTION_STATE_END (update)",context,depth); 403 404 reg_UPDATE_FETCH_PREDICTION_TABLE [context][depth]._state = UPDATE_FETCH_PREDICTION_STATE_END; 405 406 407 // Update pointer 408 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_UPDATE (before) : %d",reg_UFPT_UPDATE [context]); 409 reg_UFPT_UPDATE [context] = ((depth==0)?_param->_size_ufpt_queue[context]:depth)-1; 410 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_UPDATE (after ) : %d",reg_UFPT_UPDATE [context]); 411 // Free a register that need update ? 412 if (need_update(reg_UPDATE_FETCH_PREDICTION_TABLE [context][depth]._condition)) 413 reg_UFPT_NB_NEED_UPDATE [context] --; 413 Tdepth_t depth = internal_UPDATE_DEPTH [i]; 414 415 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPDATE[%d] - Accepted",i); 416 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context); 417 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth : %d",depth); 418 419 if (internal_UPDATE_FROM_UFPT [i]) 420 { 421 // if free a slot, also all queue is updated 422 // Last slot ? 423 if (reg_UFPT_UPDATE [context] == reg_UFPT_BOTTOM [context]) 424 switch (reg_EVENT_STATE [context]) 425 { 426 case EVENT_STATE_FLUSH_UFPT : reg_EVENT_STATE [context] = EVENT_STATE_UPDATE_CONTEXT; break; 427 // impossible to have an update on ufpt and reg_upt_update>reg_upt_top 428 case EVENT_STATE_FLUSH_UFPT_AND_UPT : reg_EVENT_STATE [context] = EVENT_STATE_FLUSH_UPT ; break; 429 default : break; 430 } 431 432 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Update Fetch Prediction Table"); 433 434 // Change state 435 #ifdef DEBUG_TEST 436 if (reg_UPDATE_FETCH_PREDICTION_TABLE [context][depth]._state != UPDATE_FETCH_PREDICTION_STATE_EVENT) 437 throw ERRORMORPHEO(FUNCTION,_("Update : invalid ufpt state.")); 438 #endif 439 440 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UFPT [%d][%d].state <- UPDATE_FETCH_PREDICTION_STATE_END (update)",context,depth); 441 442 reg_UPDATE_FETCH_PREDICTION_TABLE [context][depth]._state = UPDATE_FETCH_PREDICTION_STATE_END; 443 444 445 // Update pointer 446 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_UPDATE (before) : %d",reg_UFPT_UPDATE [context]); 447 reg_UFPT_UPDATE [context] = ((depth==0)?_param->_size_ufpt_queue[context]:depth)-1; 448 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_UPDATE (after ) : %d",reg_UFPT_UPDATE [context]); 449 // Free a register that need update ? 450 if (need_update(reg_UPDATE_FETCH_PREDICTION_TABLE [context][depth]._condition)) 451 reg_UFPT_NB_NEED_UPDATE [context] --; 452 } 453 else 454 { 455 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Update Prediction Table"); 456 457 // Change state 458 #ifdef DEBUG_TEST 459 if (internal_UPDATE_RAS [i]) 460 { 461 if ((reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_EVENT) and 462 (reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_KO )) 463 throw ERRORMORPHEO(FUNCTION,_("Update : invalid upt state.")); 464 } 465 else 466 { 467 if (reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_OK ) 468 throw ERRORMORPHEO(FUNCTION,_("Update : invalid upt state.")); 469 } 470 #endif 471 472 // bool have_event = ((reg_UPDATE_PREDICTION_TABLE [context][depth]._state == UPDATE_PREDICTION_STATE_KO) or 473 // (reg_UPDATE_PREDICTION_TABLE [context][depth]._state == UPDATE_PREDICTION_STATE_EVENT)); 474 bool ko = (reg_UPDATE_PREDICTION_TABLE [context][depth]._state == UPDATE_PREDICTION_STATE_KO); 475 476 // Have an update, test the state to transiste to the good state 477 if (ko) 478 { 479 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_END_KO (update)",context,depth); 480 481 reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_END_KO; 482 } 483 else 484 { 485 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_END_OK (update)",context,depth); 486 487 reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_END_OK; 488 } 489 490 // Update pointer 491 // * if update RAS : update pointer is decreaste until it equal at top pointer 492 if (internal_UPDATE_RAS [i]) 493 { 494 // if end_event, restart too bottom, else decrease pointer 495 bool end_event = (reg_UPT_UPDATE [context] == reg_UPT_TOP [context]); 496 497 reg_UPT_UPDATE [context] = (end_event)?reg_UPT_BOTTOM[context]:(((depth==0)?_param->_size_upt_queue[context]:depth)-1); 498 if (end_event) 499 { 500 reg_UPT_UPDATE [context] = reg_UPT_BOTTOM[context]; 501 reg_EVENT_STATE [context] = EVENT_STATE_UPDATE_CONTEXT; 502 } 503 else 504 { 505 reg_UPT_UPDATE [context] = (((depth==0)?_param->_size_upt_queue[context]:depth)-1); 506 } 507 } 508 else 509 { 510 // increase pointer 511 reg_UPT_UPDATE [context] = (depth+1)%_param->_size_upt_queue[context]; 512 } 513 514 // Free the branch with no accurate ? 515 if (reg_UPDATE_PREDICTION_TABLE [context][depth]._is_accurate == false) 516 reg_IS_ACCURATE [context] = true; 517 } 414 518 } 415 519 else 416 { 417 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Update Prediction Table"); 418 419 // Change state 420 #ifdef DEBUG_TEST 421 if (internal_UPDATE_RAS [i]) 422 { 423 if (reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_EVENT) 424 throw ERRORMORPHEO(FUNCTION,_("Update : invalid upt state.")); 425 } 426 else 427 { 428 if ((reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_OK ) and 429 (reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_KO )) 430 throw ERRORMORPHEO(FUNCTION,_("Update : invalid upt state.")); 431 } 432 #endif 433 434 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_END (update)",context,depth); 435 436 reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_END; 437 438 // Update pointer 439 bool end_event = (reg_UPT_UPDATE [context] == reg_UPT_TOP [context]); 440 441 if (internal_UPDATE_RAS [i]) 442 { 443 reg_UPT_UPDATE [context] = (end_event)?reg_UPT_BOTTOM[context]:(((depth==0)?_param->_size_upt_queue[context]:depth)-1); 444 } 445 else 446 { 447 reg_UPT_UPDATE [context] = (depth+1)%_param->_size_upt_queue[context]; 448 } 449 450 // End and event ? 451 if (end_event and 452 (reg_EVENT_STATE [context] != EVENT_STATE_OK)) 453 { 454 reg_EVENT_STATE [context] = EVENT_STATE_UPDATE_CONTEXT; 455 } 456 457 // Free the branch with no accurate ? 458 if (reg_UPDATE_PREDICTION_TABLE [context][depth]._is_accurate == false) 459 reg_IS_ACCURATE [context] = true; 460 } 461 } 520 can_continue [context] = false; 521 } 462 522 463 // Round robin 464 reg_UPDATE_PRIORITY = (reg_UPDATE_PRIORITY+1)%_param->_nb_context; 523 // Round robin 524 reg_UPDATE_PRIORITY = (reg_UPDATE_PRIORITY+1)%_param->_nb_context; 525 } 465 526 466 527 // =================================================================== … … 470 531 if (internal_BRANCH_EVENT_VAL [i] and PORT_READ(in_BRANCH_EVENT_ACK [i])) 471 532 { 472 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPDATE[%d] - Accepted",i);533 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * BRANCH_EVENT [%d] - Accepted",i); 473 534 474 535 #ifdef DEBUG_TEST … … 478 539 479 540 // Change state 480 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_ OK(branch_event)",i);541 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_WAIT_END_EVENT (branch_event)",i); 481 542 482 reg_EVENT_STATE [i] = EVENT_STATE_ OK;543 reg_EVENT_STATE [i] = EVENT_STATE_WAIT_END_EVENT; 483 544 } 545 546 // =================================================================== 547 // =====[ EVENT ]===================================================== 548 // =================================================================== 549 for (uint32_t i=0; i<_param->_nb_context; ++i) 550 { 551 //---------------------------------------------------------------- 552 // Cases 553 //---------------------------------------------------------------- 554 // * EVENT_TYPE_NONE - nothing 555 // * EVENT_TYPE_MISS_SPECULATION 556 // * EVENT_STATE_END - Change state, reset pointer 557 // * EVENT_TYPE_EXCEPTION - 558 // * EVENT_STATE_EVENT - Flush upft and upt 559 // * EVENT_STATE_END - Change state, reset pointer 560 // * EVENT_TYPE_BRANCH_NO_ACCURATE - nothing : manage in decod and update 561 // * EVENT_TYPE_SPR_ACCESS - nothing 562 // * EVENT_TYPE_MSYNC - nothing 563 // * EVENT_TYPE_PSYNC - nothing 564 // * EVENT_TYPE_CSYNC - nothing 565 566 Tevent_state_t event_state = PORT_READ(in_EVENT_STATE [i]); 567 Tevent_type_t event_type = PORT_READ(in_EVENT_TYPE [i]); 568 // Tdepth_t depth = PORT_READ(in_EVENT_DEPTH [i]); 569 570 // Test if end of miss 571 if ((event_state == EVENT_STATE_END) and 572 (event_type == EVENT_TYPE_MISS_SPECULATION)) 573 { 574 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT"); 575 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * state : EVENT_STATE_END"); 576 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * type : EVENT_TYPE_MISS_SPECULATION"); 577 578 #ifdef DEBUG_TEST 579 if (reg_EVENT_STATE [i] != EVENT_STATE_WAIT_END_EVENT) 580 throw ERRORMORPHEO(FUNCTION,_("Event : invalid event state.")); 581 #endif 582 583 // Change state 584 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_OK (event)",i); 585 586 reg_EVENT_STATE [i] = EVENT_STATE_OK; 587 588 // uint32_t bottom = reg_UPT_BOTTOM [i]; 589 590 // reg_UPT_TOP [i] = bottom; 591 // reg_UPT_UPDATE [i] = bottom; 592 } 593 } 484 594 485 595 // =================================================================== … … 561 671 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_BOTTOM : %d",reg_UPT_BOTTOM [i]); 562 672 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_TOP : %d",reg_UPT_TOP [i]); 673 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_TOP_EVENT : %d",reg_UPT_TOP_EVENT [i]); 563 674 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_UPDATE : %d",reg_UPT_UPDATE [i]); 564 675 for (uint32_t j=0; j<_param->_size_upt_queue[i]; j++) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/include/Parameters.h
r88 r95 51 51 public : uint32_t * _ras_size_queue ;//[nb_context] 52 52 public : uint32_t * _upt_size_queue ;//[nb_context] 53 public : uint32_t * _ufpt_size_queue ;//[nb_context] 53 54 54 55 //public : uint32_t _size_context_id ; … … 96 97 uint32_t * ras_size_queue ,//[nb_context] 97 98 uint32_t * upt_size_queue ,//[nb_context] 99 uint32_t * ufpt_size_queue ,//[nb_context] 98 100 bool is_toplevel=false 99 101 ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/include/Prediction_unit.h
r88 r95 111 111 //public : SC_OUT(Tcontrol_t ) ** out_BRANCH_EVENT_MISS_PREDICTION ; //[nb_context] 112 112 public : SC_OUT(Taddress_t ) ** out_BRANCH_EVENT_ADDRESS_SRC ; //[nb_context] 113 public : SC_OUT(Tcontrol_t ) ** out_BRANCH_EVENT_ADDRESS_DEST_VAL ; //[nb_context] 113 114 public : SC_OUT(Taddress_t ) ** out_BRANCH_EVENT_ADDRESS_DEST ; //[nb_context] 115 116 // ~~~~~[ Interface : "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 117 public : SC_IN (Tevent_state_t ) ** in_EVENT_STATE ; //[nb_context] 118 public : SC_IN (Tevent_type_t ) ** in_EVENT_TYPE ; //[nb_context] 119 public : SC_IN (Tdepth_t ) ** in_EVENT_DEPTH ; //[nb_context] 114 120 115 121 // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/src/Parameters.cpp
r88 r95 42 42 uint32_t * ras_size_queue ,//[nb_context] 43 43 uint32_t * upt_size_queue ,//[nb_context] 44 uint32_t * ufpt_size_queue ,//[nb_context] 44 45 bool is_toplevel 45 46 ) … … 73 74 _ras_size_queue = ras_size_queue ; 74 75 _upt_size_queue = upt_size_queue ; 76 _ufpt_size_queue = ufpt_size_queue ; 75 77 76 78 _array_size_depth = new uint32_t [_nb_context]; … … 133 135 (_nb_context , 134 136 _upt_size_queue , 137 _ufpt_size_queue , 135 138 _size_address , 136 139 _nb_inst_branch_predict , -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/src/Parameters_print.cpp
r82 r95 68 68 xml. singleton_begin("ras_size_queue "); xml.attribut("value",toString(_ras_size_queue [i])); xml.singleton_end(); 69 69 xml. singleton_begin("upt_size_queue "); xml.attribut("value",toString(_upt_size_queue [i])); xml.singleton_end(); 70 xml. singleton_begin("ufpt_size_queue "); xml.attribut("value",toString(_ufpt_size_queue [i])); xml.singleton_end(); 70 71 xml. balise_close(); 71 72 } -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/src/Prediction_unit_allocation.cpp
r88 r95 113 113 ALLOC1_INTERFACE("branch_event", IN,SOUTH, "branch_event", _param->_nb_context); 114 114 115 ALLOC1_VALACK_OUT(out_BRANCH_EVENT_VAL ,VAL); 116 ALLOC1_VALACK_IN ( in_BRANCH_EVENT_ACK ,ACK); 117 // ALLOC1_SIGNAL_OUT(out_BRANCH_EVENT_CONTEXT_ID ,"context_id" ,Tcontext_t,_param->_size_context_id); 118 // ALLOC1_SIGNAL_OUT(out_BRANCH_EVENT_DEPTH ,"depth" ,Tdepth_t ,_param->_size_depth); 119 // ALLOC1_SIGNAL_OUT(out_BRANCH_EVENT_MISS_PREDICTION,"miss_prediction",Tcontrol_t,1); 120 ALLOC1_SIGNAL_OUT(out_BRANCH_EVENT_ADDRESS_SRC ,"address_src" ,Taddress_t,_param->_size_address); 121 ALLOC1_SIGNAL_OUT(out_BRANCH_EVENT_ADDRESS_DEST ,"address_dest" ,Taddress_t,_param->_size_address); 115 ALLOC1_VALACK_OUT(out_BRANCH_EVENT_VAL ,VAL); 116 ALLOC1_VALACK_IN ( in_BRANCH_EVENT_ACK ,ACK); 117 // ALLOC1_SIGNAL_OUT(out_BRANCH_EVENT_CONTEXT_ID ,"context_id" ,Tcontext_t,_param->_size_context_id); 118 // ALLOC1_SIGNAL_OUT(out_BRANCH_EVENT_DEPTH ,"depth" ,Tdepth_t ,_param->_size_depth); 119 // ALLOC1_SIGNAL_OUT(out_BRANCH_EVENT_MISS_PREDICTION ,"miss_prediction" ,Tcontrol_t,1); 120 ALLOC1_SIGNAL_OUT(out_BRANCH_EVENT_ADDRESS_SRC ,"address_src" ,Taddress_t,_param->_size_address); 121 ALLOC1_SIGNAL_OUT(out_BRANCH_EVENT_ADDRESS_DEST_VAL ,"address_dest_val",Tcontrol_t,1); 122 ALLOC1_SIGNAL_OUT(out_BRANCH_EVENT_ADDRESS_DEST ,"address_dest" ,Taddress_t,_param->_size_address); 122 123 } 123 124 … … 129 130 ALLOC1_SIGNAL_OUT(out_DEPTH_MIN ,"min" ,Tdepth_t,_param->_size_depth); 130 131 ALLOC1_SIGNAL_OUT(out_DEPTH_MAX ,"max" ,Tdepth_t,_param->_size_depth+1); 132 } 133 134 // ~~~~~[ Interface : "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 135 { 136 ALLOC1_INTERFACE("event", IN,SOUTH,"event", _param->_nb_context); 137 138 ALLOC1_SIGNAL_IN ( in_EVENT_STATE ,"state",Tevent_state_t,_param->_size_event_state); 139 ALLOC1_SIGNAL_IN ( in_EVENT_TYPE ,"type" ,Tevent_type_t ,_param->_size_event_type ); 140 ALLOC1_SIGNAL_IN ( in_EVENT_DEPTH ,"depth",Tdepth_t ,_param->_size_depth ); 131 141 } 132 142 … … 509 519 COMPONENT_MAP(_component,src , "in_UPDATE_"+toString(i)+ "_PUSH" , 510 520 dest,"out_UPDATE_"+toString(i)+"_RAS_PUSH" ); 521 COMPONENT_MAP(_component,src , "in_UPDATE_"+toString(i)+ "_FLUSH" , 522 dest,"out_UPDATE_"+toString(i)+"_RAS_FLUSH" ); 511 523 COMPONENT_MAP(_component,src , "in_UPDATE_"+toString(i)+ "_ADDRESS" , 512 524 dest,"out_UPDATE_"+toString(i)+"_RAS_ADDRESS" ); … … 636 648 //in_UPDATE_UPT_RAS_ADDRESS - component_map return_address_stack 637 649 //in_UPDATE_UPT_RAS_PUSH - component_map return_address_stack 650 //in_UPDATE_UPT_RAS_FLUSH - component_map return_address_stack 638 651 //in_UPDATE_UPT_RAS_INDEX - component_map return_address_stack 639 652 //in_UPDATE_UPT_RAS_PREDICTION_IFETCH - component_map return_address_stack … … 682 695 #endif 683 696 684 PORT_MAP(_component,src ,"out_BRANCH_EVENT_"+toString(i)+"_VAL" ,dest,"out_BRANCH_EVENT_"+toString(i)+"_VAL" ); 685 PORT_MAP(_component,src , "in_BRANCH_EVENT_"+toString(i)+"_ACK" ,dest, "in_BRANCH_EVENT_"+toString(i)+"_ACK" ); 686 PORT_MAP(_component,src ,"out_BRANCH_EVENT_"+toString(i)+"_ADDRESS_SRC" ,dest,"out_BRANCH_EVENT_"+toString(i)+"_ADDRESS_SRC" ); 687 PORT_MAP(_component,src ,"out_BRANCH_EVENT_"+toString(i)+"_ADDRESS_DEST",dest,"out_BRANCH_EVENT_"+toString(i)+"_ADDRESS_DEST"); 688 } 697 PORT_MAP(_component,src ,"out_BRANCH_EVENT_"+toString(i)+"_VAL" ,dest,"out_BRANCH_EVENT_"+toString(i)+"_VAL" ); 698 PORT_MAP(_component,src , "in_BRANCH_EVENT_"+toString(i)+"_ACK" ,dest, "in_BRANCH_EVENT_"+toString(i)+"_ACK" ); 699 PORT_MAP(_component,src ,"out_BRANCH_EVENT_"+toString(i)+"_ADDRESS_SRC" ,dest,"out_BRANCH_EVENT_"+toString(i)+"_ADDRESS_SRC" ); 700 PORT_MAP(_component,src ,"out_BRANCH_EVENT_"+toString(i)+"_ADDRESS_DEST_VAL",dest,"out_BRANCH_EVENT_"+toString(i)+"_ADDRESS_DEST_VAL"); 701 PORT_MAP(_component,src ,"out_BRANCH_EVENT_"+toString(i)+"_ADDRESS_DEST" ,dest,"out_BRANCH_EVENT_"+toString(i)+"_ADDRESS_DEST" ); 702 } 703 704 for (uint32_t i=0; i<_param->_nb_context; i++) 705 { 706 dest = _name; 707 708 #ifdef POSITION 709 _component->interface_map (src ,"event_"+toString(i), 710 dest,"event_"+toString(i)); 711 #endif 712 713 PORT_MAP(_component,src , "in_EVENT_"+toString(i)+"_STATE",dest, "in_EVENT_"+toString(i)+"_STATE"); 714 PORT_MAP(_component,src , "in_EVENT_"+toString(i)+"_TYPE" ,dest, "in_EVENT_"+toString(i)+"_TYPE" ); 715 if (_param->_have_port_depth) 716 PORT_MAP(_component,src , "in_EVENT_"+toString(i)+"_DEPTH",dest, "in_EVENT_"+toString(i)+"_DEPTH"); 717 } 689 718 690 719 for (uint32_t i=0; i<_param->_nb_context; i++) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/src/Prediction_unit_deallocation.cpp
r88 r95 62 62 DELETE1_SIGNAL(out_BRANCH_COMPLETE_ADDRESS_DEST ,_param->_nb_inst_branch_complete,_param->_size_instruction_address); 63 63 64 DELETE1_SIGNAL(out_BRANCH_EVENT_VAL ,_param->_nb_context,1); 65 DELETE1_SIGNAL( in_BRANCH_EVENT_ACK ,_param->_nb_context,1); 66 // DELETE1_SIGNAL(out_BRANCH_EVENT_CONTEXT_ID ,_param->_nb_context,_param->_size_context_id); 67 // DELETE1_SIGNAL(out_BRANCH_EVENT_DEPTH ,_param->_nb_context,_param->_size_depth); 68 // DELETE1_SIGNAL(out_BRANCH_EVENT_MISS_PREDICTION,_param->_nb_context,1); 69 DELETE1_SIGNAL(out_BRANCH_EVENT_ADDRESS_SRC ,_param->_nb_context,_param->_size_instruction_address); 70 DELETE1_SIGNAL(out_BRANCH_EVENT_ADDRESS_DEST ,_param->_nb_context,_param->_size_instruction_address); 64 DELETE1_SIGNAL(out_BRANCH_EVENT_VAL ,_param->_nb_context,1); 65 DELETE1_SIGNAL( in_BRANCH_EVENT_ACK ,_param->_nb_context,1); 66 // DELETE1_SIGNAL(out_BRANCH_EVENT_CONTEXT_ID ,_param->_nb_context,_param->_size_context_id); 67 // DELETE1_SIGNAL(out_BRANCH_EVENT_DEPTH ,_param->_nb_context,_param->_size_depth); 68 // DELETE1_SIGNAL(out_BRANCH_EVENT_MISS_PREDICTION ,_param->_nb_context,1); 69 DELETE1_SIGNAL(out_BRANCH_EVENT_ADDRESS_SRC ,_param->_nb_context,_param->_size_instruction_address); 70 DELETE1_SIGNAL(out_BRANCH_EVENT_ADDRESS_DEST_VAL ,_param->_nb_context,1); 71 DELETE1_SIGNAL(out_BRANCH_EVENT_ADDRESS_DEST ,_param->_nb_context,_param->_size_instruction_address); 72 73 DELETE1_SIGNAL( in_EVENT_STATE ,_param->_nb_context,_param->_size_event_state); 74 DELETE1_SIGNAL( in_EVENT_TYPE ,_param->_nb_context,_param->_size_event_type ); 75 DELETE1_SIGNAL( in_EVENT_DEPTH ,_param->_nb_context,_param->_size_depth ); 71 76 72 77 DELETE1_SIGNAL(out_DEPTH_CURRENT ,_param->_nb_context,_param->_size_depth); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/config-context_1-decod_unit_1-a.cfg
r88 r95 43 43 8 8 +1 # ras_size_queue [0] [nb_context] 44 44 1 1 +1 # upt_size_queue [0] [nb_context] 45 1 1 +1 # ufpt_size_queue [0] [nb_context] 45 46 1 1 +1 # size_inst_commit -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/config-context_4-decod_unit_1-a.cfg
r88 r95 58 58 2 2 +1 # upt_size_queue [2] [nb_context] 59 59 8 8 +1 # upt_size_queue [3] [nb_context] 60 6 6 +1 # ufpt_size_queue [0] [nb_context] 61 1 1 +1 # ufpt_size_queue [1] [nb_context] 62 1 1 +1 # ufpt_size_queue [2] [nb_context] 63 4 4 +1 # ufpt_size_queue [3] [nb_context] 60 64 1 1 +1 # size_inst_commit -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/config-context_4-decod_unit_2-a.cfg
r88 r95 63 63 2 2 +1 # upt_size_queue [2] [nb_context] 64 64 8 8 +1 # upt_size_queue [3] [nb_context] 65 6 6 +1 # ufpt_size_queue [0] [nb_context] 66 1 1 +1 # ufpt_size_queue [1] [nb_context] 67 1 1 +1 # ufpt_size_queue [2] [nb_context] 68 4 4 +1 # ufpt_size_queue [3] [nb_context] 65 69 1 1 +1 # size_inst_commit -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/config-context_4-decod_unit_2-b.cfg
r88 r95 63 63 2 2 +1 # upt_size_queue [2] [nb_context] 64 64 8 8 +1 # upt_size_queue [3] [nb_context] 65 6 6 +1 # ufpt_size_queue [0] [nb_context] 66 1 1 +1 # ufpt_size_queue [1] [nb_context] 67 1 1 +1 # ufpt_size_queue [2] [nb_context] 68 4 4 +1 # ufpt_size_queue [3] [nb_context] 65 69 1 1 +1 # size_inst_commit -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/config-min.cfg
r88 r95 43 43 2 2 +1 # ras_size_queue [0] [nb_context] 44 44 1 1 +1 # upt_size_queue [0] [nb_context] 45 1 1 +1 # ufpt_size_queue [0] [nb_context] 45 46 1 1 +1 # size_inst_commit -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/src/main.cpp
r88 r95 44 44 err (_(" * ras_size_queue [nb_context] (uint32_t )\n")); 45 45 err (_(" * upt_size_queue [nb_context] (uint32_t )\n")); 46 err (_(" * ufpt_size_queue [nb_context] (uint32_t )\n")); 46 47 err (_(" * size_inst_commit (uint32_t )\n")); 47 48 … … 69 70 uint32_t _nb_decod_unit = fromString<uint32_t >(argv[x++]); 70 71 71 if (argc != static_cast<int>(2+NB_PARAMS+ 5*_nb_context+5*_nb_decod_unit))72 if (argc != static_cast<int>(2+NB_PARAMS+6*_nb_context+5*_nb_decod_unit)) 72 73 { 73 74 msg("argc : %d\n",argc); … … 158 159 for (uint32_t i=0; i<_nb_context; ++i) 159 160 _upt_size_queue [i] = fromString<uint32_t>(argv[x++]); 161 162 uint32_t * _ufpt_size_queue = new uint32_t [_nb_context]; 163 for (uint32_t i=0; i<_nb_context; ++i) 164 _ufpt_size_queue [i] = fromString<uint32_t>(argv[x++]); 160 165 161 166 uint32_t _size_inst_commit = fromString<uint32_t>(argv[x++]); … … 197 202 _ras_size_queue , 198 203 _upt_size_queue , 204 _ufpt_size_queue , 199 205 _size_inst_commit , 200 206 true // is_toplevel … … 231 237 delete [] _dir_pht_nb_counter ; 232 238 delete [] _dir_pht_size_address_share ; 239 delete [] _ufpt_size_queue ; 233 240 delete [] _upt_size_queue ; 234 241 delete [] _ras_size_queue ; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/include/Parameters.h
r88 r95 65 65 public : uint32_t * _ras_size_queue ;//[nb_context] 66 66 public : uint32_t * _upt_size_queue ;//[nb_context] 67 public : uint32_t * _ufpt_size_queue ;//[nb_context] 68 67 69 // context_state 68 70 //public : uint32_t _size_nb_inst_commit ; … … 132 134 uint32_t * ras_size_queue , 133 135 uint32_t * upt_size_queue , 136 uint32_t * ufpt_size_queue , 134 137 // context_state 135 138 uint32_t size_nb_inst_commit , -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Front_end_allocation.cpp
r88 r95 564 564 #endif 565 565 566 COMPONENT_MAP(_component,src ,"out_BRANCH_EVENT_"+toString(i)+"_VAL" , 567 dest, "in_BRANCH_EVENT_"+toString(i)+"_VAL" ); 568 COMPONENT_MAP(_component,src , "in_BRANCH_EVENT_"+toString(i)+"_ACK" , 569 dest,"out_BRANCH_EVENT_"+toString(i)+"_ACK" ); 570 // COMPONENT_MAP(_component,src ,"out_BRANCH_EVENT_"+toString(i)+"_CONTEXT_ID" , 571 // dest, "in_BRANCH_EVENT_"+toString(i)+"_CONTEXT_ID" ); 572 // COMPONENT_MAP(_component,src ,"out_BRANCH_EVENT_"+toString(i)+"_DEPTH" , 573 // dest, "in_BRANCH_EVENT_"+toString(i)+"_DEPTH" ); 574 // COMPONENT_MAP(_component,src ,"out_BRANCH_EVENT_"+toString(i)+"_MISS_PREDICTION", 575 // dest, "in_BRANCH_EVENT_"+toString(i)+"_MISS_PREDICTION"); 576 COMPONENT_MAP(_component,src ,"out_BRANCH_EVENT_"+toString(i)+"_ADDRESS_SRC" , 577 dest, "in_BRANCH_EVENT_"+toString(i)+"_ADDRESS_SRC" ); 578 COMPONENT_MAP(_component,src ,"out_BRANCH_EVENT_"+toString(i)+"_ADDRESS_DEST" , 579 dest, "in_BRANCH_EVENT_"+toString(i)+"_ADDRESS_DEST" ); 566 COMPONENT_MAP(_component,src ,"out_BRANCH_EVENT_"+toString(i)+"_VAL" , 567 dest, "in_BRANCH_EVENT_"+toString(i)+"_VAL" ); 568 COMPONENT_MAP(_component,src , "in_BRANCH_EVENT_"+toString(i)+"_ACK" , 569 dest,"out_BRANCH_EVENT_"+toString(i)+"_ACK" ); 570 // COMPONENT_MAP(_component,src ,"out_BRANCH_EVENT_"+toString(i)+"_CONTEXT_ID" , 571 // dest, "in_BRANCH_EVENT_"+toString(i)+"_CONTEXT_ID" ); 572 // COMPONENT_MAP(_component,src ,"out_BRANCH_EVENT_"+toString(i)+"_DEPTH" , 573 // dest, "in_BRANCH_EVENT_"+toString(i)+"_DEPTH" ); 574 // COMPONENT_MAP(_component,src ,"out_BRANCH_EVENT_"+toString(i)+"_MISS_PREDICTION" , 575 // dest, "in_BRANCH_EVENT_"+toString(i)+"_MISS_PREDICTION" ); 576 COMPONENT_MAP(_component,src ,"out_BRANCH_EVENT_"+toString(i)+"_ADDRESS_SRC" , 577 dest, "in_BRANCH_EVENT_"+toString(i)+"_ADDRESS_SRC" ); 578 COMPONENT_MAP(_component,src ,"out_BRANCH_EVENT_"+toString(i)+"_ADDRESS_DEST_VAL", 579 dest, "in_BRANCH_EVENT_"+toString(i)+"_ADDRESS_DEST_VAL"); 580 COMPONENT_MAP(_component,src ,"out_BRANCH_EVENT_"+toString(i)+"_ADDRESS_DEST" , 581 dest, "in_BRANCH_EVENT_"+toString(i)+"_ADDRESS_DEST" ); 580 582 } 581 583 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Parameters.cpp
r88 r95 52 52 uint32_t * ras_size_queue , 53 53 uint32_t * upt_size_queue , 54 uint32_t * ufpt_size_queue , 54 55 // context_state 55 56 uint32_t size_nb_inst_commit , … … 93 94 _ras_size_queue = ras_size_queue ; 94 95 _upt_size_queue = upt_size_queue ; 96 _ufpt_size_queue = ufpt_size_queue ; 95 97 96 98 test(); … … 114 116 _nb_inst_fetch [i] , 115 117 log2(_upt_size_queue[i]) , 116 size_instruction_address 118 size_instruction_address ); 117 119 } 118 120 … … 140 142 _dir_pht_size_address_share , 141 143 _ras_size_queue , 142 _upt_size_queue ); 144 _upt_size_queue , 145 _ufpt_size_queue ); 143 146 144 147 _translate_context_id_from_decod_unit= new std::vector<uint32_t> [_nb_decod_unit]; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/SelfTest/include/test.h
r81 r95 14 14 15 15 #include "Behavioural/Generic/Victim/Victim_Pseudo_LRU/include/Victim_Pseudo_LRU.h" 16 #include "Common/include/Time.h" 16 17 17 18 using namespace std; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/SelfTest/src/test.cpp
r88 r95 89 89 (*(_Victim_Pseudo_LRU->out_ACCESS_VICTIM [i])) (ACCESS_VICTIM [i]); 90 90 } 91 92 Time * _time = new Time(); 91 93 92 94 /******************************************************** … … 210 212 211 213 cout << "<" << name << "> ............ Stop Simulation" << endl; 214 delete _time; 212 215 213 216 #endif -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/src/Victim_Pseudo_LRU_allocation.cpp
r88 r95 36 36 ); 37 37 38 in_CLOCK = interface->set_signal_clk ("clock" ,1 );39 in_NRESET = interface->set_signal_in <Tcontrol_t> ("nreset",1 );38 in_CLOCK = interface->set_signal_clk ("clock" ,1, CLOCK_VHDL_YES); 39 in_NRESET = interface->set_signal_in <Tcontrol_t> ("nreset",1, RESET_VHDL_YES); 40 40 } 41 41 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/src/Victim_Pseudo_LRU_vhdl_body.cpp
r81 r95 116 116 } 117 117 118 vhdl->set_body ("");119 vhdl->set_body ("-- port update");120 for (uint32_t i=0; i<_param->_nb_update; i++)121 for (int32_t j=static_cast<uint32_t>(log2(_param->_nb_entity)-1); j>=0; j--)122 {123 uint32_t cpt=0;118 // vhdl->set_body (""); 119 // vhdl->set_body ("-- port update"); 120 // for (uint32_t i=0; i<_param->_nb_update; i++) 121 // for (int32_t j=static_cast<uint32_t>(log2(_param->_nb_entity)-1); j>=0; j--) 122 // { 123 // uint32_t cpt=0; 124 124 125 for (int32_t k=(1<<j)-1; k<static_cast<int32_t>(_param->_nb_entity-1); k+=(1<<(j+1)))126 {127 bool have_cond = false;128 std::string cond = "";129 130 // condition to change the bit131 for (uint32_t l=j+1; l<static_cast<uint32_t>(log2(_param->_nb_entity));l++)132 {133 have_cond = true;134 135 if (l==static_cast<uint32_t>(j+1))136 cond += "when";137 else138 cond += " and";139 cond += " in_UPDATE_"+toString(i)+"_ENTITY("+toString(l)+")='"+toString((cpt>>(l-(j+1)))&1)+"'";140 }141 142 vhdl->set_body ("update_next_entry_"+toString(i)+"("+toString(k)+") <=");143 vhdl->set_body ("\tnot in_UPDATE_"+toString(i)+"_ENTITY("+toString(j)+") "+cond);144 if (have_cond == true)145 {146 std::string update_address;147 148 if (_param->_size_table>1)149 update_address = "conv_integer(in_UPDATE_"+toString(i)+"_ADDRESS)";150 else151 update_address = "0";125 // for (int32_t k=(1<<j)-1; k<static_cast<int32_t>(_param->_nb_entity-1); k+=(1<<(j+1))) 126 // { 127 // bool have_cond = false; 128 // std::string cond = ""; 129 130 // // condition to change the bit 131 // for (uint32_t l=j+1; l<static_cast<uint32_t>(log2(_param->_nb_entity));l++) 132 // { 133 // have_cond = true; 134 135 // if (l==static_cast<uint32_t>(j+1)) 136 // cond += "when"; 137 // else 138 // cond += " and"; 139 // cond += " in_UPDATE_"+toString(i)+"_ENTITY("+toString(l)+")='"+toString((cpt>>(l-(j+1)))&1)+"'"; 140 // } 141 142 // vhdl->set_body ("update_next_entry_"+toString(i)+"("+toString(k)+") <="); 143 // vhdl->set_body ("\tnot in_UPDATE_"+toString(i)+"_ENTITY("+toString(j)+") "+cond); 144 // if (have_cond == true) 145 // { 146 // std::string update_address; 147 148 // if (_param->_size_table>1) 149 // update_address = "conv_integer(in_UPDATE_"+toString(i)+"_ADDRESS)"; 150 // else 151 // update_address = "0"; 152 152 153 vhdl->set_body ("\telse reg_TABLE ("+update_address+")("+toString(k)+")");154 }155 vhdl->set_body ("\t;");156 cpt ++;157 }158 }153 // vhdl->set_body ("\telse reg_TABLE ("+update_address+")("+toString(k)+")"); 154 // } 155 // vhdl->set_body ("\t;"); 156 // cpt ++; 157 // } 158 // } 159 159 160 160 vhdl->set_body (""); … … 182 182 } 183 183 184 vhdl->set_body ("\t\t-- Update port");185 for (uint32_t i=0; i<_param->_nb_update; i++)186 {187 std::string update_address;188 189 if (_param->_size_table>1)190 update_address = "conv_integer(in_UPDATE_"+toString(i)+"_ADDRESS)";191 else192 update_address = "0";184 // vhdl->set_body ("\t\t-- Update port"); 185 // for (uint32_t i=0; i<_param->_nb_update; i++) 186 // { 187 // std::string update_address; 188 189 // if (_param->_size_table>1) 190 // update_address = "conv_integer(in_UPDATE_"+toString(i)+"_ADDRESS)"; 191 // else 192 // update_address = "0"; 193 193 194 vhdl->set_body ("\t\tif (in_UPDATE_"+toString(i)+"_VAL = '1') then");195 vhdl->set_body ("\t\t\treg_TABLE ("+update_address+") <= update_next_entry_"+toString(i)+";");196 vhdl->set_body ("\t\tend if;");197 }194 // vhdl->set_body ("\t\tif (in_UPDATE_"+toString(i)+"_VAL = '1') then"); 195 // vhdl->set_body ("\t\t\treg_TABLE ("+update_address+") <= update_next_entry_"+toString(i)+";"); 196 // vhdl->set_body ("\t\tend if;"); 197 // } 198 198 199 199 vhdl->set_body ("\tend if;"); … … 210 210 { 211 211 vhdl->set_body ("out_ACCESS_"+toString(i)+"_ACK <= '1';"); 212 vhdl->set_body ("out_ACCESS_"+toString(i)+"_ ENTITY<= access_entity_"+toString(i)+" when in_ACCESS_"+toString(i)+"_VAL = '1' else (others => '0');");212 vhdl->set_body ("out_ACCESS_"+toString(i)+"_VICTIM <= access_entity_"+toString(i)+" when in_ACCESS_"+toString(i)+"_VAL = '1' else (others => '0');"); 213 213 } 214 214 vhdl->set_body (""); 215 for (uint32_t i=0; i<_param->_nb_update; i++)216 {217 vhdl->set_body ("out_UPDATE_"+toString(i)+"_ACK <= '1';");218 }215 // for (uint32_t i=0; i<_param->_nb_update; i++) 216 // { 217 // vhdl->set_body ("out_UPDATE_"+toString(i)+"_ACK <= '1';"); 218 // } 219 219 }; 220 220 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/src/Victim_Pseudo_LRU_vhdl_declaration.cpp
r81 r95 29 29 } 30 30 31 for (uint32_t i=0; i<_param->_nb_update; i++)32 {33 vhdl->set_signal ("update_next_entry_"+toString(i)+"",std_logic(_param->_nb_entity-1));34 }31 // for (uint32_t i=0; i<_param->_nb_update; i++) 32 // { 33 // vhdl->set_signal ("update_next_entry_"+toString(i)+"",std_logic(_param->_nb_entity-1)); 34 // } 35 35 }; 36 36 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Version.h
r94 r95 10 10 #define MORPHEO_MAJOR_VERSION 0 11 11 #define MORPHEO_MINOR_VERSION 2 12 #define MORPHEO_REVISION "9 4"12 #define MORPHEO_REVISION "95" 13 13 #define MORPHEO_CODENAME "Castor" 14 14 15 #define MORPHEO_DATE_DAY "1 5"15 #define MORPHEO_DATE_DAY "16" 16 16 #define MORPHEO_DATE_MONTH "12" 17 17 #define MORPHEO_DATE_YEAR "2008" -
trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Vhdl.h
r94 r95 26 26 std::string std_logic_conv (uint32_t size, std::string value); 27 27 std::string std_logic_conv (uint32_t size, uint32_t value); 28 std::string std_logic_cst (uint32_t size, uint32_t value); 28 29 std::string std_logic_range (uint32_t size, uint32_t max , uint32_t min , bool force=false); 29 30 std::string std_logic_range ( uint32_t max , uint32_t min , bool force=false); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Component_vhdl_instance.cpp
r81 r95 27 27 std::list<Interface_fifo *> * list_interface = (_entity)->get_interfaces_list()->get_interface_list(); 28 28 std::list<Interface_fifo *>::iterator j = list_interface->begin(); 29 bool print_comment = false; 29 30 if (not list_interface->empty()) 30 31 { 31 vhdl->set_body ("------------------------------------------------------");32 vhdl->set_body ("-- Output's Buffer");33 vhdl->set_body ("------------------------------------------------------");34 35 32 while (j != list_interface->end()) 36 33 { … … 48 45 (signal->get_connect_from_signal () != NULL) ) 49 46 { 47 if (not print_comment) 48 { 49 vhdl->set_body ("------------------------------------------------------"); 50 vhdl->set_body ("-- Output's Buffer"); 51 vhdl->set_body ("------------------------------------------------------"); 52 53 print_comment = true; 54 } 55 50 56 // Create name 51 57 std::string signal_name = "signal_"+toString(cpt++); … … 67 73 ++j; 68 74 } 69 vhdl->set_body (""); 70 vhdl->set_body ("------------------------------------------------------"); 71 vhdl->set_body (""); 75 76 if (print_comment) 77 { 78 vhdl->set_body (""); 79 vhdl->set_body ("------------------------------------------------------"); 80 vhdl->set_body (""); 81 } 72 82 } 73 83 } -
trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Interface_testbench_test.cpp
r81 r95 24 24 25 25 std::string test_name = testbench_test_name(vhdl); 26 std::string test_name_ok = testbench_test_ok 26 std::string test_name_ok = testbench_test_ok (vhdl); 27 27 28 28 vhdl->set_body(test_name + " <= '1' when ("+reset_name+" = '0') else "+test_name_ok+";"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Interface_testbench_test_ok.cpp
r81 r95 24 24 if (_list_signal->empty()== false) 25 25 { 26 std::list<Signal*>::iterator i 26 std::list<Signal*>::iterator i = _list_signal->begin(); 27 27 28 28 while (i != _list_signal->end()) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Signal_testbench_test_ok.cpp
r81 r95 19 19 if (_direction == OUT) 20 20 vhdl->set_body ("\tand "+_name+" = "+_name+"_test"); 21 21 22 22 log_printf(FUNC,Behavioural,"testbench_test_ok","End"); 23 23 }; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_set_constant.cpp
r81 r95 27 27 28 28 void Vhdl::set_constant (std::string name , 29 uint32_t size ,29 uint32_t size , 30 30 std::string init) 31 31 { … … 35 35 }; 36 36 37 void Vhdl::set_constant (std::string 37 void Vhdl::set_constant (std::string name , 38 38 uint32_t size , 39 39 uint32_t init) 40 40 { 41 41 log_printf(FUNC,Behavioural,FUNCTION,"Begin"); 42 set_constant(name,std_logic(size),std_logic_c onv(size,init));42 set_constant(name,std_logic(size),std_logic_cst(size,init)); 43 43 log_printf(FUNC,Behavioural,FUNCTION,"End"); 44 44 }; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_set_signal.cpp
r93 r95 9 9 10 10 #include "Behavioural/include/Vhdl.h" 11 11 #include "Common/include/ToBase2.h" 12 12 #include <sstream> 13 13 … … 56 56 { 57 57 log_printf(FUNC,Behavioural,FUNCTION,"Begin"); 58 set_signal(name,std_logic(size),std_logic_c onv(size,init));58 set_signal(name,std_logic(size),std_logic_cst(size,init)); 59 59 log_printf(FUNC,Behavioural,FUNCTION,"End"); 60 60 }; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_std_logic.cpp
r94 r95 10 10 #include <math.h> 11 11 #include "Behavioural/include/Vhdl.h" 12 #include "Common/include/ToBase2.h" 12 13 13 14 namespace morpheo { … … 57 58 58 59 return _return; 60 }; 61 62 #undef FUNCTION 63 #define FUNCTION "Vhdl::std_logic_cst" 64 std::string std_logic_cst (uint32_t size, uint32_t value) 65 { 66 log_printf(FUNC,Behavioural,FUNCTION,"Begin"); 67 68 std::string conv; 69 70 if (size == 1) 71 conv = "'"+toString(value&1)+"'"; 72 else 73 conv = "\""+toBase2<uint32_t>(value,size)+"\""; 74 75 log_printf(FUNC,Behavioural,FUNCTION,"End"); 76 77 return conv; 59 78 }; 60 79
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