|
|
@149
|
14 years |
alain |
bug fixing
|
|
|
@148
|
14 years |
alain |
Introducing two new components : vci_vdspin_initiator_wrapper & …
|
|
|
@147
|
14 years |
alain |
Return to version 134 :
The multi-processor version of the L1 cache …
|
|
|
@146
|
14 years |
choichil |
Modifications to make the code easier to read
|
|
|
@145
|
14 years |
choichil |
Adding function to get Latencies and a period for broadcast calculated …
|
|
|
@144
|
14 years |
kane |
in vci_cc_xcache_wrapper_v4 : (1) Fix bug in MISS_VICTIM state, (2) …
|
|
|
@143
|
14 years |
kane |
fix bug in ccxcachev4, save cpu_info in memcachev4
|
|
|
@142
|
14 years |
guthmull |
Eviction can now be random. Unselected by default.
|
|
|
@141
|
14 years |
guthmull |
Improve activity counters. Table sizes are now instance parameters.
|
|
|
@140
|
14 years |
kane |
yAjout du multi_cache : plusieurs processeur peuvent ce partager le …
|
|
|
@139
|
14 years |
gao |
Cleanup FSM changed
|
|
|
@138
|
14 years |
guthmull |
Handle bad accesses cleanly : transmit all accesses to the xram and …
|
|
|
@137
|
14 years |
simerabe |
replacing old ring versions with new one
|
|
|
@136
|
14 years |
simerabe |
deleting old ring components
|
|
|
@135
|
14 years |
choichil |
Initiator with bug correction in latency computing
|
|
|
@134
|
14 years |
kane |
add multi write buffer in cc_xcache_v4
|
|
|
@133
|
14 years |
choichil |
Platform with more parameters
|
|
|
@132
|
14 years |
choichil |
Synthetic Initiator with the latests bugs fixed
|
|
|
@131
|
14 years |
choichil |
Initiator with only one FSM for responses
|
|
|
@130
|
14 years |
gao |
Cleanup fsm seperated from vci fsm to evite deadlock
|
|
|
@129
|
14 years |
alain |
|
|
|
@128
|
14 years |
alain |
decreasing the number of registers
|
|
|
@127
|
14 years |
choichil |
Removing useless prints
|
|
|
@126
|
14 years |
choichil |
Synthetic Initiator only with sc_signal
|
|
|
@125
|
14 years |
choichil |
Synthetic Initiator with good data to print
|
|
|
@124
|
14 years |
choichil |
Synthetic Initiator…
|
|
|
@123
|
14 years |
choichil |
Synthetic Initiator with parallel transactions
|
|
|
@122
|
14 years |
choichil |
Synthetic Initiator before being change for multiple requests
|
|
|
@121
|
14 years |
choichil |
Generic platform for VDSPIN tests and measurements
|
|
|
@120
|
14 years |
gao |
Separated cleanup from the vci_fsm to avoid deadlock
|
|
|
@119
|
14 years |
gao |
Modification for synthetisable reason
|
|
|
@118
|
14 years |
alain |
update print_trace() prototype
|
|
|
@117
|
14 years |
alain |
Introducing two generic hardware platforms:
- tsarv4_vgmn_generic_32
- …
|
|
|
@116
|
14 years |
alain |
Introducing a print_trace() method
|
|
|
@115
|
14 years |
choichil |
Adding deterministic for debug
|
|
|
@114
|
14 years |
alain |
Improving the print_trace() display.
|
|
|
@113
|
14 years |
alain |
Improving the print_trace() function
|
|
|
@112
|
14 years |
choichil |
Platform that works…
|
|
|
@111
|
14 years |
choichil |
Puisque c'est comme ça, je commite mon truc…
|
|
|
@110
|
14 years |
guthmull |
Fix an issue with systemcass 64 bits conversions.
|
|
|
@109
|
14 years |
guthmull |
Don't check rsp length in case of error.
Check that the processor …
|
|
|
@108
|
14 years |
gao |
Bug correction
|
|
|
@107
|
14 years |
guthmull |
Add a simple TsarV4 platform
|
|
|
@106
|
14 years |
choichil |
Vci_Synthetic_Initiator correction of some bugs... some may still exist
|
|
|
@105
|
14 years |
choichil |
PF ended
|
|
|
@104
|
14 years |
gao |
Verify broadcast address using mask
|
|
|
@103
|
14 years |
choichil |
Platform using vci_simple_ram which is not the svn working copy (allow …
|
|
|
@102
|
14 years |
choichil |
Synthetic initiator that compiles
|
|
|
@101
|
14 years |
gao |
Delete the evaluation codes for speedup simulation
|
|
|
@100
|
14 years |
choichil |
Deleting modelsim files
|
|
|
@99
|
14 years |
choichil |
Platform without targets
|
|
|
@98
|
14 years |
choichil |
Correcting file names of vci_synthetic_initiator
|
|
|
@97
|
14 years |
choichil |
Draft of new platform with VciSyntheticInitiator? and VDSPIN
|
|
|
@96
|
14 years |
gao |
Redo ins TLB access bit update when it miss in dcache
|
|
|
@95
|
14 years |
choichil |
Platform with DMA and FB
|
|
|
@94
|
14 years |
choichil |
Deleting work directory
|
|
|
@93
|
14 years |
choichil |
Platform with DMA
|
|
|
@92
|
14 years |
choichil |
Platform with DMA VHDL
|
|
|
@91
|
14 years |
alain |
polishing
|
|
|
@90
|
14 years |
alain |
Introducing a print_trace() method for debug.
|
|
|
@89
|
14 years |
simerabe |
fixing bug vci_ring_initiator : fifo_wok
|
|
|
@88
|
14 years |
gao |
Correction of itlb access bit set and dtlb dirty bit set
|
|
|
@87
|
14 years |
simerabe |
platform for new vdspin_router/vci_local_ring_fast
|
|
|
@86
|
14 years |
simerabe |
simple_ring_fast platform
|
|
|
@85
|
14 years |
simerabe |
removing duplicate ring_signals_2
|
|
|
@84
|
14 years |
bouyer |
ICACHE_SW_FLUSH/ICACHE_CACHE_FLUSH: when walking the tlb/cache looking …
|
|
|
@83
|
14 years |
guthmull |
Fix the masking of RERROR field
|
|
|
@82
|
14 years |
guthmull |
Add broadcast limitation compatibility, indicate the type of response …
|
|
|
@81
|
14 years |
choichil |
vci_synthetic_initiator draft
|
|
|
@80
|
14 years |
gao |
Modified the coherence check for TLB entry updating
|
|
|
@79
|
14 years |
gao |
Correction of dirty bit and access bit in data cache
|
|
|
@78
|
14 years |
choichil |
Modification of the vci_synthetic_initiator draft
|
|
|
@77
|
14 years |
choichil |
Rename of vci_traffic_generator to vci_synthetic_initiator
|
|
|
@76
|
14 years |
choichil |
Metadata file…
|
|
|
@75
|
14 years |
choichil |
Rearranging hierarchy
|
|
|
@74
|
14 years |
choichil |
Adding files hierarchy of vci_traffic_generator
|
|
|
@73
|
14 years |
bouyer |
Fix several issues regarding management of the …
|
|
|
@72
|
14 years |
bouyer |
2 fixes:
- do not test r_dcache_in_[id]tlb[] just after setting the …
|
|
|
@71
|
14 years |
bouyer |
When updating PTE bits, don't write back to the dcache locally, the …
|
|
|
@70
|
14 years |
bouyer |
Check/update the dirty bit on SC too
|
|
|
@69
|
14 years |
bouyer |
Fix cut'n'paste error
|
|
|
@68
|
14 years |
bouyer |
A SC cause the dcache entry to be updated by the memcache, and the
tlb …
|
|
|
@67
|
14 years |
nipo |
Namespaces
|
|
|
@66
|
14 years |
nipo |
Namespaces
|
|
|
@65
|
14 years |
nipo |
Use proper namespaces
|
|
|
@64
|
14 years |
nipo |
Use proper namespaces
|
|
|
@63
|
14 years |
nipo |
Use proper namespaces
|
|
|
@62
|
14 years |
gao |
Debug infos deleted
|
|
|
@61
|
14 years |
gao |
Active caches
|
|
|
@60
|
14 years |
gao |
bug correction
|
|
|
@59
|
15 years |
alain |
modifying the chek in the constructor to accept up to 4096 sets.
|
|
|
@58
|
15 years |
guthmull |
Fix partial instruction updates
|
|
|
@57
|
15 years |
guthmull |
Fix a bug with uncached reads, add more debug capabilities
|
|
|
@56
|
15 years |
guthmull |
SC don't generate invalidations and cleanup any more, add treatment of …
|
|
|
@55
|
15 years |
guthmull |
Fix a bug in SC, add start cycle debug
|
|
|
@54
|
15 years |
bouyer |
Remove debug output
|
|
|
@53
|
15 years |
gao |
debug
|
|
|
@52
|
15 years |
bouyer |
Make it build with systemcass.
|
|
|
@51
|
15 years |
gao |
Activity counter update
|
|
|
@50
|
15 years |
gao |
Activity counter update
|
|
|