[56] | 1 | % vim:set spell: |
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| 2 | % vim:spell spelllang=en: |
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| 3 | |
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[23] | 4 | \begin{taskinfo} |
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| 5 | \let\UPMC\leader |
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| 6 | \let\TIMA\enable |
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| 7 | \let\ALTERA\enable |
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| 8 | \end{taskinfo} |
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| 9 | % |
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| 10 | \begin{objectif} |
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| 11 | This task pools the features dedicated to HPC system design. It is described on |
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| 12 | figures~\ref{coach-flow} and \ref{archi-hpc}. It consists in |
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| 13 | \begin{itemize} |
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[111] | 14 | \item Providing a software tool that helps the HPC designer to find a good partition of the initial application |
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[56] | 15 | (figure~\ref{archi-hpc}). |
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| 16 | \item Providing communication schemes between the software part running on the PC and the |
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[111] | 17 | FPGA-SoC. %FIXME = {Quelle difference avec l'item qui suit ???} |
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[38] | 18 | \item Implementing the communication scheme at all levels: partition help, software |
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[23] | 19 | implementation both on the PC and in the operating system of the FPGA-SoC, hardware. |
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[63] | 20 | \item Providing support for dynamic partial reconfiguration of \xilinx FPGA in order |
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| 21 | to optimize FPGA ressource usage. |
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[23] | 22 | \end{itemize} |
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[56] | 23 | |
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[23] | 24 | The low level hardware transmission support will be the PCI/X bus which allows high bit-rate |
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| 25 | transfers. The reasons of this choices are that both ALTERA and Xilinx provide PCI/X IP for |
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| 26 | their FPGA and that GPU HPC softwares use also it. |
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[111] | 27 | %FIXME == {ai supprime (mis en commentaire) la phrse qui suivait} |
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| 28 | %This will allow us at least to be inspired by GPU communication schemes and may be to reuse |
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| 29 | %parts of the GPU softwares. |
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[56] | 30 | |
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[23] | 31 | \end{objectif} |
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| 32 | % |
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[111] | 33 | %FIXME == {Ne doit onpas fusionner les taches ST6-1, ST6-2, ST6-3 et pourquoi pas ST6-4 ???} |
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[52] | 34 | \begin{workpackage} |
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[38] | 35 | \item This \ST is the definition of the communication schemes as a software API |
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[23] | 36 | (Application Programing Interface) between the application part running on the PC and |
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| 37 | the application part running on the FPGA-SoC. |
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| 38 | \begin{livrable} |
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[52] | 39 | \itemL{0}{6}{d}{\Supmc}{HPC communication API}{1.0:0:0} |
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| 40 | \setMacroInAuxFile{hpcCommApi} |
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[111] | 41 | Specification describing the API. |
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[23] | 42 | \end{livrable} |
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[56] | 43 | \item This \ST consists in helping to partition applications. |
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[36] | 44 | It is a library implementing the communication API with features to profile |
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[40] | 45 | the partitioned application. |
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[56] | 46 | %FIXME (Olivier) pour moi, on veut un outil de profiling pour partitionner l'application. |
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| 47 | % It is a profiling (or simulation) library implementing the communication API |
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| 48 | |
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[23] | 49 | \begin{livrable} |
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[52] | 50 | \itemL{6}{12}{x}{\Supmc}{HPC partionning helper}{1:0:0} |
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| 51 | A library implementing the communication API defined in the {\hpcCommApi} delivrable. |
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[23] | 52 | \end{livrable} |
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[40] | 53 | \item This \ST deals with the implementation of the communication API on the both sides (PC |
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[23] | 54 | part and FPGA-SoC). |
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| 55 | \begin{livrable} |
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[52] | 56 | \itemL{12}{21}{x}{\Supmc}{HPC API for Linux PC}{0:3:0} |
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| 57 | The PC part of the HPC communication API that comminicates with the FPGA-SOC, a |
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| 58 | library and probably a LINUX module. |
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| 59 | \itemL{12}{21}{x}{\Supmc}{HPC API for MUTEK OS}{0:3:0} |
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| 60 | \setMacroInAuxFile{hpcMutekDriver} |
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| 61 | The FPGA-SoC part of the communication API, a driver. |
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[57] | 62 | \itemL{21}{24}{x}{\Stima}{HPC API for DNA OS}{0:3:0} |
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[52] | 63 | Port of the {\hpcMutekDriver} driver on the DNA OS. |
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| 64 | \itemL{24}{33}{x}{\Supmc}{HPC API}{0:0:1} |
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[56] | 65 | Maintenance work of HPC API for both Linux PC and MUTEK OS. |
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[23] | 66 | \end{livrable} |
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[59] | 67 | \item This \ST deals with the implementation of hardware and SystemC modules |
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| 68 | required by the COACH architectural template for using the PCI/X IP of \altera and \xilinx. |
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[23] | 69 | \begin{livrable} |
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[57] | 70 | \itemL{9}{18}{h}{\Stima}{HPC hardware \xilinx}{3:9:0} |
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[36] | 71 | \setMacroInAuxFile{hpcPlbBridge} |
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| 72 | The synthesizable VHDL description of a PLB/VCI bridge and its corresponding SystemC model. |
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[52] | 73 | \itemL{9}{18}{h}{\Saltera}{HPC hardware \altera}{0:0:0} |
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[36] | 74 | \setMacroInAuxFile{hpcAvalonBridge} |
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[40] | 75 | The synthesizable VHDL description of an AVALON/VCI bridge and its corresponding SystemC model. |
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[59] | 76 | \itemL{9}{24}{h}{\Supmc}{PCI/X traffic generator}{1:1:0} |
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| 77 | The SystemC description of a component that generates PCI/X traffic. It is |
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| 78 | required to prototype FPGA-SoC dedicated to HPC. |
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[23] | 79 | \end{livrable} |
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[59] | 80 | |
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[56] | 81 | \item This \ST consists in integrating dynamic partial reconfiguration of \xilinx FPGA in the CSG design flow. |
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| 82 | It also includes appropriate SoC-FPGA OS drivers and a modification of the profiling library. |
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[23] | 83 | \begin{livrable} |
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[63] | 84 | \itemL{18}{36}{x}{\Supmc}{CSG support for \ganttlf reconfiguration}{0:0:2} |
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| 85 | Modification of CSG software to support statically reconfigurable task. |
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| 86 | \itemL{18}{36}{x}{\Stima}{CSG module for \ganttlf dynamic reconfiguration}{0:6:12} |
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| 87 | This livrable is a CSG module allowing to partition the task graph on |
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| 88 | the dynamic partial reconfiguration regions. The resulting task-region assignement |
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| 89 | is directly used for generation of bitstreams. The module also produces reconfiguration |
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| 90 | management software to be run on the SoC-FPGA. |
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| 91 | \itemL{18}{30}{x}{\Stima}{dynamic reconfiguration \ganttlf DNA drivers}{0:3:3} |
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[52] | 92 | \setMacroInAuxFile{hpcDynconfDriver} |
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[59] | 93 | The drivers required by the DNA OS in order to manage dynamic partial |
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| 94 | reconfiguration inside the SoC-FPGA. |
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[52] | 95 | \itemL{30}{36}{x}{\Supmc}{dynamic reconfiguration \ganttlf MUTEK drivers}{0:0:1} |
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[56] | 96 | Port of the {\hpcDynconfDriver} drivers on the MUTEK OS. |
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[63] | 97 | \itemL{24}{36}{x}{\Stima}{Profiler for \ganttlf dynamic reconfiguration}{0:0:6} |
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[59] | 98 | Extension of the HPC partionning helper in order to integrate dynamic partial |
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| 99 | reconfiguration dedicated features (reconfiguration time of regions, variable |
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| 100 | number of coprocessors). |
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| 101 | \end{livrable} |
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[27] | 102 | \item This \ST is the delivery of 2 PCI/X \mustbecompleted{FIXME: Stratix4} FPGA board |
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| 103 | with its PCI/X IP. These boards are dedicated to the COACH HPC development. |
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| 104 | They are based on \mustbecompleted{FIXME:stratix4} FPGA device of 400,000 LUT. |
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| 105 | \begin{livrable} |
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[52] | 106 | \itemL{0}{6}{m}{\Saltera}{HPC development boards}{0:0:0} Two PCI/X FPGA boards. |
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[27] | 107 | \end{livrable} |
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[23] | 108 | \end{workpackage} |
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