Changeset 52 for anr


Ignore:
Timestamp:
Jan 31, 2010, 10:17:25 PM (15 years ago)
Author:
coach
Message:

IA: modification des macros livrable & sortie des tableaux de ressources.

Location:
anr
Files:
13 edited

Legend:

Unmodified
Added
Removed

  • anr/Makefile

    r51 r52  
    1010                        dependence-task-h.pdf \
    1111                        section-4.2.tex section-5.tex \
    12                         section-6.1.tex section-6.2.tex
     12                        section-6.1.tex section-6.2.tex section-7.tex
     13
     14TABLES= table_upmc.tex
    1315
    1416# PROGRAMS
    … …  
    1921        @$(FIG2DEV) -L pdf -p aaa $< $@
    2022
    21 anr.pdf: $(SOURCES) gantt1.tex gantt2.tex gantt
     23anr.pdf: $(SOURCES) gantt1.tex gantt2.tex gantt $(TABLES)
    2224        @echo "Generating pdf file"
    2325        @pdflatex anr.tex
    … …  
    3032        bibtex anr || true
    3133
    32 anr.aux gantt1.tex gantt2.tex:
     34anr.aux gantt1.tex gantt2.tex $(TABLES):
    3335        touch $@
    3436
    … …  
    3638        @flex gantt.l && gcc -g lex.yy.c -o gantt
    3739        @rm lex.yy.c
     40
     41clean:
     42        rm -f $(TABLES) anr.aux gantt1.tex gantt2.tex anr.pdf anr.gantt

  • anr/anr.sty

    r49 r52  
    8484\newcount\subtaskcnt
    8585\newcount\livrablecnt
    86 \newenvironment{workpackage}[1]%
     86\newenvironment{workpackage}%
    8787{\global\advance\taskcnt1
    8888 \global\subtaskcnt0
    … …  
    9797
    9898%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
     99\def\writeganttinfo#1#2#3#4#5{{%
     100    \let\xcoach\relax
     101    \let\xcoachplus\relax
     102    \let\irisa\relax    \let\Sirisa\relax
     103    \let\lip\relax      \let\Slip\relax
     104    \let\tima\relax     \let\Stima\relax
     105    \let\ubs\relax      \let\Subs\relax
     106    \let\upmc\relax     \let\Supmc\relax
     107    \let\altera\relax   \let\Saltera\relax
     108    \let\xilinx\relax   \let\Sxilinx\relax
     109    \let\bull\relax     \let\Sbull\relax
     110    \let\thales\relax   \let\Sthales\relax
     111    \let\zied\relax     \let\Szied\relax
     112    \let\navtel\relax   \let\Snavtel\relax
     113    \immediate\write\ganttdata{%
     114      T=\the\taskcnt\space S=\the\subtaskcnt\space%
     115      D=\the\livrablecnt\space V=\vers\space%
     116      BM=#1 EM=#2 R=#3 PART={#4} TITLE=#5%
     117    }
     118}}
    99119\newenvironment{livrable}%
    100120{%
     121 \newcount\verscnt\verscnt=-1
     122 \newif\ifIsLivrableStarted\IsLivrableStartedfalse
    101123 \newif\ifLivrableTopLine\LivrableTopLinetrue
    102  \newif\ifLivrableStart\LivrableStarttrue
    103124 \def\livrableTableDef{\begin{tabular}{|c|c|c|c|p{.625\linewidth}|}\hline}
    104125 \def\livrableTableLine##1##2##3##4{%
    … …  
    113134 \livrablecnt-1
    114135 \ifvmode\else\vspace{.75ex}\\\fi
    115  \def\item##1##2##3##4##5##6{%
    116         \def\tmpa{##1}\def\vers{}
    117         \def\tmp{}  \ifx\tmp\tmpa\global\advance\livrablecnt1\def\vers{VF}\global\LivrableStarttrue\fi%
    118     \def\tmp{1} \ifx\tmp\tmpa\global\advance\livrablecnt1\def\vers{V1}\global\LivrableStarttrue\fi%
    119     \def\tmp{V1}\ifx\tmp\tmpa\global\advance\livrablecnt1\def\vers{V1}\global\LivrableStarttrue\fi%
    120     \def\tmp{2} \ifx\tmp\tmpa\def\vers{V2}\fi%
    121     \def\tmp{V2}\ifx\tmp\tmpa\def\vers{V2}\fi%
    122     \def\tmp{3} \ifx\tmp\tmpa\def\vers{V3}\fi%
    123     \def\tmp{V3}\ifx\tmp\tmpa\def\vers{V3}\fi%
    124     \def\tmp{F} \ifx\tmp\tmpa\def\vers{VF}\fi%
    125     \def\tmp{VF}\ifx\tmp\tmpa\def\vers{VF}\fi%
    126     %\gdef\name{D-\the\taskcnt\the\subtaskcnt\the\livrablecnt-##1}%
     136   
     137 \def\itemV##1##2##3##4##5{%
     138    \ifIsLivrableStarted
     139        \global\advance\verscnt1
     140    \else
     141        \global\advance\livrablecnt1
     142        \global\verscnt1
     143    \fi
     144    \def\vers{V\the\verscnt}
    127145    \global\edef\name{D\the\taskcnt\the\subtaskcnt\the\livrablecnt-\vers}%
    128     {
    129       \let\xcoach\relax
    130       \let\xcoachplus\relax
    131       \let\irisa\relax    \let\Sirisa\relax
    132       \let\lip\relax      \let\Slip\relax
    133       \let\tima\relax     \let\Stima\relax
    134       \let\ubs\relax      \let\Subs\relax
    135       \let\upmc\relax     \let\Supmc\relax
    136       \let\altera\relax   \let\Saltera\relax
    137       \let\xilinx\relax   \let\Sxilinx\relax
    138       \let\bull\relax     \let\Sbull\relax
    139       \let\thales\relax   \let\Sthales\relax
    140       \let\zied\relaxe    \let\Szied\relax
    141       \let\navtel\relax   \let\Snavtel\relax
    142       \immediate\write\ganttdata{%
    143         T=\the\taskcnt\space S=\the\subtaskcnt\space%
    144         D=\the\livrablecnt\space V=##1 BM=##2 EM=##3 TITLE=##6%
    145       }
    146     }
     146    \writeganttinfo{##1}{##2}{none}{##4}{##5}
    147147    \\\hline
    148148    \ifLivrableTopLine
    149       \ifLivrableStart\hline\hline\fi
     149      \ifIsLivrableStarted\else\hline\hline\fi
    150150    \else
    151       \ifLivrableStart\end{tabular}\\\livrableTableDef\fi
     151      \ifIsLivrableStarted\else\end{tabular}\\\livrableTableDef\fi
    152152    \fi
    153153    \global\LivrableTopLinefalse
    154     \global\LivrableStartfalse
     154    \global\IsLivrableStartedtrue
     155    %\global\LivrableStartfalse
    155156    \livrableTableLine%
    156157        {\textsc{\name}}%
    157         {\textsc{T0+##3}}%
     158        {\textsc{T0+##2}}%
     159        {\textsc{##3}}%
    158160        {\textsc{##4}}%
    159         {\textsc{##5}}%
     161 }
     162 \def\itemL##1##2##3##4##5##6{%
     163    \ifIsLivrableStarted
     164        %\global\advance\verscnt1
     165    \else
     166        \global\advance\livrablecnt1
     167        %\global\verscnt1
     168    \fi
     169    \def\vers{VF}
     170    \global\edef\name{D\the\taskcnt\the\subtaskcnt\the\livrablecnt-\vers}%
     171    \writeganttinfo{##1}{##2}{##6}{##4}{##5}
     172    \\\hline
     173    \ifLivrableTopLine
     174      \ifIsLivrableStarted\else\hline\hline\fi
     175    \else
     176      \ifIsLivrableStarted\else\end{tabular}\\\livrableTableDef\fi
     177    \fi
     178    \global\LivrableTopLinefalse
     179    \global\IsLivrableStartedfalse
     180    %\global\LivrableStartfalse
     181    \livrableTableLine%
     182        {\textsc{\name}}%
     183        {\textsc{T0+##2}}%
     184        {\textsc{##3}}%
     185        {\textsc{##4}}%
    160186 }
    161187% \begin{small}

  • anr/anr.tex

    r51 r52  
    292292Chaque partenaire justifiera les moyens qu'il demande en distinguant les
    293293différents postes de dépenses.}
    294 
    295 \subsection{Partner 1: XXX}
    296 \anrdoc{\begin{itemize}
     294\def\ressourcehelp{\anrdoc{\begin{itemize}
    297295\item Equipment: 1) Préciser la nature des équipements* et justifier le
    298296    choix des équipements. 2) Si nécessaire, préciser la part de financement
    … …  
    319317\item Other working costs. Toute dépense significative relevant de ce poste
    320318devra être justifiée.
    321 \end{itemize}}
    322 
    323 \subsection{Partner 2: XXX}
     319\end{itemize}}}
     320\input{section-7}
    324321
    325322%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

  • anr/gantt.l

    r51 r52  
    3939    0
    4040};
     41struct partner_def { char *key, *name, *file; } partner_table[] = {
     42    { "UNKNOW", "relax",   0,                 },
     43    { "irisa",  "irisa",   "table_irisa.tex"  },
     44    { "lip",    "lip",     "table_lip.tex"    },
     45    { "tima",   "tima",    "table_tima.tex"   },
     46    { "ubs",    "ubs",     "table_ubs.tex"    },
     47    { "upmc",   "upmc",    "table_upmc.tex"   },
     48    { "altera", "altera",  "table_altera.tex" },
     49    { "xilinx", "xilinx",  "table_xilinx.tex" },
     50    { "bull",   "bull",    "table_bull.tex"   },
     51    { "thales", "thales",  "table_thales.tex" },
     52    { "zied",   "zied",    "table_zied.tex"   },
     53    { "navtel", "navtel",  "table_navtel.tex" },
     54    { 0,        0,         0                  },
     55};
    4156
    4257typedef struct _Tlivrable {
    … …  
    4459    char v;            // 0, 1, 2, ..., F
    4560    char* title;
    46     int   bm,em;   // mois de bebut et de fin
     61    int   bm,em;       // mois de bebut et de fin
     62    double hman[3];    // nombre de mh par an
     63    int    partner;    // index dans partner_table
    4764    // these fields are filled by the program for data[tn][0][0][0]
    4865    double task_y;           // top of task
    4966    double task_dy;          // bot of task is task_y+task_dy
    5067    double task_y_del;       // delivrables start at task_y+task_y_del
     68    double nbma[3];          // durée en mois par annee
    5169    // these fields are filled by the program for data[tn][stn][dn][0]
    5270    struct _Tlivrable
    … …  
    106124        *l = *data_org.ls[tn][stn][dn][v];
    107125        data->ls[tn][stn][dn][v] = l;
    108 fprintf(stderr,"selected: [tn][stn][dn][v]=%d,%d,%d,%d\n",tn,stn,dn,v);
     126//fprintf(stderr,"selected: [tn][stn][dn][v]=%d,%d,%d,%d\n",tn,stn,dn,v);
    109127    }
    110128    return data;
    … …  
    196214%%
    197215 int tn,stn,dn,v,bm,em; char* title;
     216 double an[3];
     217 char*  an_comment;
     218 int    partner;
    198219#.*\n   ;
    199 T=[0-9]+ { tn=atoi(yytext+2); }
    200 T=D[0-9]+ { tn=atoi(yytext+3); }
    201 S=[0-9]+ { stn=atoi(yytext+2); }
    202 D=[0-9]+ { dn=atoi(yytext+2); }
    203 V=V.     { v=yytext[3]; }
    204 V=       { v='F'; }
     220T=[0-9]+  { tn=atoi(yytext+2); }
     221S=[0-9]+  { stn=atoi(yytext+2); }
     222D=[0-9]+  { dn=atoi(yytext+2); }
     223V=V[1-8F] { v=yytext[3]; }
    205224ML=[0-9]+ {
    206225        int i;
    … …  
    208227        milestones[i] = atoi(yytext+3);
    209228    }
    210 
    211229BM=[0-9]+ { bm=atoi(yytext+3); }
    212230EM=[0-9]+ { em=atoi(yytext+3); }
     231R=none    { an[0]=0; an[1]=0; an[2]=0; an_comment=0; }
     232R=[0-9:.]+ {
     233        char tmp[1000];
     234        int status = sscanf(yytext+2,"%lf:%lf:%lf:%s",an+0,an+1,an+2,tmp);
     235        if (status<3) {
     236            fprintf(stderr,"%s: is not resource definition, expected format \"N:N:N\" (near D%d%d%d-V%c)\n",
     237               yytext+2,tn,stn,dn,v);
     238            an[0]=0; an[1]=0; an[2]=0; an_comment=0;
     239        } else if (status==3) {
     240            an_comment = 0;
     241        } else
     242            an_comment = strdup(tmp);
     243    }
     244PART="{"[^}]+"}"  {
     245        int i;
     246        partner=-1;
     247        for (i=0; partner_table[i].key!=0 ; i++) {
     248            if (strstr(yytext,partner_table[i].key)!=0 ) {
     249                partner=i;
     250                break;
     251            }
     252        }
     253        if ( partner==-1 ) {
     254            fprintf(stderr,"%s: does not contains a partner key (near D%d%d%d-V%c)\n",
     255               yytext+5,tn,stn,dn,v);
     256            partner=0;
     257        }
     258    }
    213259TITLE=.*\n {
    214260        char* pc=yytext+6;
    … …  
    221267        p->dn = dn;
    222268        p->v  = v;
     269        p->hman[0] = an[0];
     270        p->hman[1] = an[1];
     271        p->hman[2] = an[2];
     272        p->partner = partner;
    223273        p->title = title;
    224274        p->bm = bm;
    … …  
    228278        for (v=0; data_org.ls[tn][stn][dn][v]!=0 ; v++);
    229279        data_org.ls[tn][stn][dn][v] = p;
    230 fprintf(stderr,"ADDED: %d %d %d %d\n",tn,stn,dn,v);
    231 //{int i,tn=0; fprintf(stderr,"CURR:t=%d:: ",tn); for (i=0; i<S_MAX ; i++) fprintf(stderr,"%d:%p ",i,data[tn][i][0][0]); fprintf(stderr,"\n"); }
    232     }
    233 .|\n ;
     280//fprintf(stderr,"ADDED: %d %d %d %d\n",tn,stn,dn,v);
     281    }
     282[ \t\n] ;
     283.   { fprintf(stderr,"%c: unexpected value in anr.gantt file (near D%d%d%d-V%c)\n",
     284        *yytext,tn,stn,dn,v); }
    234285%%
    235286
    … …  
    327378            h += (p->vers[p->nbvers-1]->nbTitleLines-1)*(DELIVRABLE_TITLEHEIGHT/5.);
    328379            if ( h>p->height) p->height=h;
     380        }
     381        Tlivrable* lu= p->vers[p->nbvers-1];
     382        int i;
     383fprintf(stderr,"--------------------\n");
     384        for (i=0 ; i<p->nbvers ; i++) {
     385            Tlivrable* l= p->vers[i];
     386            double bm= l->bm;
     387            double em= l->em;
     388//fprintf(stderr,"  %d%d%d-V%c: bm=%2.f em=%2.f --> %2.1f %2.1f %2.1f\n",l->tn,l->stn,l->dn,l->v,bm,em, lu->nbma[0],lu->nbma[1],lu->nbma[2]);
     389            if (bm<12 && em>0) {
     390                lu->nbma[0] += (em>12?12:em)-bm;
     391                bm=12;
     392            }
     393            if (bm<24 && em>12) {
     394                lu->nbma[1] += (em>24?24:em)-bm;
     395                bm=24;
     396            }
     397            if (bm<36 && em>24) {
     398                lu->nbma[2] += em-bm;
     399            }
     400//fprintf(stderr,"  %d%d%d-V%c: bm=%2.f em=%2.f --> %2.1f %2.1f %2.1f %p\n",l->tn,l->stn,l->dn,l->v,bm,em, lu->nbma[0],lu->nbma[1],lu->nbma[2], lu);
    329401        }
    330402    }
    … …  
    536608    print_milestones(gantt_x,0,gantt_dx,gantt_dy+gantt_y);
    537609    fprintf(curr->os,"\\end{picture}\n");
     610    fclose(curr->os);
     611    curr->os=0;
     612}
     613
     614void do_partner_table(int partner)
     615{
     616    struct partner_def* part = partner_table+partner;
     617    if ( (curr->os=fopen(part->file,"w"))==0 ) {
     618        fprintf(stderr,"can not open %s file for writing.\n",part->file);
     619        fprintf(stderr,"generation of %s partner table is skipped.\n",part->file);
     620        return;
     621    }
     622    fprintf(curr->os,"\\begin{tabular}{|c|p{3.5cm}||r|r|r||r|}\\hline\n");
     623    fprintf(curr->os,
     624        "number & \\multicolumn{1}{c||}{title} & \\multicolumn{3}{c||}{years } & total \\\\\\cline{3-5}\n");
     625    fprintf(curr->os,
     626        " & & \\multicolumn{1}{c|}{1} & \\multicolumn{1}{c|}{2} & "
     627        "\\multicolumn{1}{c||}{3} &  \\\\\\hline\\hline\n");
     628    int tn,stn,dn,v=0;
     629    double an1=0,an2=0,an3=0,an=0;
     630    int newlineadded=1;
     631    for (tn=0 ; tn<T_MAX ; tn++) {
     632        if (curr->ls[tn][0][0][0]==0) break;
     633        if (tn!=0 && newlineadded==0 ) {
     634            newlineadded = 1;
     635            fprintf(curr->os,"\\hline ");
     636        }
     637        for (stn=0; stn<S_MAX; stn++) {
     638            for (dn=0; dn<D_MAX; dn++) {
     639                Tlivrable* top=curr->ls[tn][stn][dn][v];
     640                if (top==0) continue;
     641                Tlivrable* last=top->vers[top->nbvers-1];
     642                if (last->partner!=partner) continue;
     643                double sum1,sum2,sum3,sum=0;
     644                sum1 = last->hman[0]; sum +=sum1;
     645                sum2 = last->hman[1]; sum +=sum2;
     646                sum3 = last->hman[2]; sum +=sum3;
     647                char label[1000],title[1000];
     648                gen_label_base(label,last);
     649                sprintf(title,"\\resstablestyletitle{%s}",last->title);
     650                fprintf(curr->os,"%s & %s & %2.1f & %2.1f & %2.1f & %2.1f \\\\\\hline\n",
     651                   label,title,sum1,sum2,sum3,sum);
     652                an1 += sum1 ;
     653                an2 += sum2 ;
     654                an3 += sum3 ;
     655                an  += sum  ;
     656                newlineadded=0;
     657                if ( (sum1!=0 && sum1>last->nbma[0] ) || (sum1==0 && last->nbma[0]!=0) )
     658                    fprintf(stderr,"ERROR: %s:%s probleme sur l'an 1 (in table=%2.1f, in gantt=%2.1f\n",
     659                        part->name,label,sum1,last->nbma[0]);
     660                if ( (sum2!=0 && sum2>last->nbma[1]) || (sum2==0 && last->nbma[1]!=0) )
     661                    fprintf(stderr,"ERROR: %s:%s probleme sur l'an 2 (in table=%2.1f, in gantt=%2.1f\n",
     662                        part->name,label,sum2,last->nbma[1]);
     663                if ( (sum3!=0 && sum3>last->nbma[2]) || (sum3==0 && last->nbma[2]!=0) )
     664                    fprintf(stderr,"ERROR: %s:%s probleme sur l'an 3 (in table=%2.1f, in gantt=%2.1f\n",
     665                        part->name,label,sum3,last->nbma[2]);
     666            }
     667        }
     668    }
     669    if ( an!=(an1+an2+an3) ) {
     670        fprintf(stderr,"bad computation in %s table.\n",part->file);
     671    }
     672    fprintf(curr->os,"%s & %s & %2.1f & %2.1f & %2.1f & %2.1f \\\\\\hline\n",
     673            "","total",an1,an2,an3,an);
     674
     675    fprintf(curr->os,"\\end{tabular}\n");
     676    fclose(curr->os);
     677    curr->os=0;
    538678}
    539679
    … …  
    548688    do_gantt("gantt2.tex",0,tnmoins);
    549689
     690    curr = data_new(0,0);
     691    prepare0(curr);
     692    prepare1(curr);
     693    prepare2(curr);
     694    prepare3(curr);
     695    do_partner_table(4);
     696    do_partner_table(5);
     697
    550698    return 0;
    551699}

  • anr/section-1.tex

    r49 r52  
    6161    re-engineering by the designer.
    6262\item[Targeted hardware architecture and technology]
    63     COACH will handle both \altera and \xilinx FPGA devives.
     63    COACH will handle both \altera and \xilinx FPGA devices.
    6464    COACH will define architectural templates that can be customized by adding
    6565    dedicated coprocessors and ASIPs and by fixing template parameters such as

  • anr/task-0.tex

    r49 r52  
    1919\end{objectif}
    2020%
    21 \begin{workpackage}{D0}
     21\begin{workpackage}
    2222  \item This \ST consists of the writing of the consortium agreement and of having the
    2323    partners sign it.
    2424    \begin{livrable}
    25     \item{}{0}{6}{d}{\Supmc}{Consortium agreement} A document describing the
    26         consortium agreement, signed by all the partners.
     25    \itemL{0}{6}{d}{\Supmc}{Consortium agreement}{1:0:0}
     26        A document describing the consortium agreement, signed by all the partners.
    2727    \end{livrable}
    2828  \item This \ST consists of the global management of deliverables and of the global
    2929    organization of the project at all the levels.
    3030    \begin{livrable}
    31       \item{}{0}{12}{d}{\Supmc}{First progress report}
    32       \item{}{12}{24}{d}{\Supmc}{Second progress report}
    33       \item{}{24}{36}{d}{\Supmc}{Final report}
    34       \item{}{0}{36}{}{\Supmc}{Global management}
     31      \itemL{0}{12}{d}{\Supmc}{First progress report}{1:0:0}
     32      \itemL{12}{24}{d}{\Supmc}{Second progress report}{0:1:0}
     33      \itemL{24}{36}{d}{\Supmc}{Final report}{0:0:1}
     34      \itemL{0}{36}{}{\Supmc}{Global management}{1:1:1}
    3535        This deliverable corresponds to the global management of the project at all the
    3636        levels: progress monitoring, record keeping, meeting organization, review
    … …  
    4141    project meetings and the communication with the project leader and other partner.
    4242    \begin{livrable}
    43       \item{}{0}{36}{}{\Supmc}{\upmc management} Project management at the partner level.
     43      \itemL{0}{36}{}{\Supmc}{\upmc management}{1:1:1} Project management at the partner level.
    4444    \end{livrable}
    4545  \item This \ST consists firstly in the building and maintenance of the
    … …  
    4747    distributing the COACH releases.
    4848    \begin{livrable}
    49       \item{V1}{0}{6}{}{\Supmc}{development infrastructure setup}
     49      \itemV{0}{6}{}{\Supmc}{development infrastructure setup}
    5050        This deliverable consists of the setup of development infrastructure
    5151        (version control system configuration, wiki).
    52       \item{VF}{7}{36}{}{\Supmc}{development infrastructure}
     52      \itemL{7}{36}{}{\Supmc}{development infrastructure}{1:.5:.5}
    5353        This deliverable corresponds to the standard management of a development
    5454        infrastructure (adding \& suppressing account, retrieving forgotten passwords,
    … …  
    5656    \end{livrable}
    5757\end{workpackage}
    58 
     58%

  • anr/task-1.tex

    r47 r52  
    1111\end{objectif}
    1212%
    13 \begin{workpackage}{D1}
     13\begin{workpackage}
    1414\item This \ST specifies COACH for the system designer. At this
    1515    level COACH is a black box. The deliverables are documents allowing the system
    … …  
    1818    MPSoC and its 3 targets hardware mapping).
    1919    \begin{livrable}
    20     \item{V1}{0}{6}{d}{\Supmc}{COACH user manual} \setMacroInAuxFile{specGenManualI}
     20    \itemV{0}{6}{d}{\Supmc}{COACH user manual} \setMacroInAuxFile{specGenManualI}
    2121        It is the first milestone of the COACH user manual that will allow the demonstrator
    2222        \STs to start.
    … …  
    2626        to the CSG manual (delivrable \specCsgManual) for the COACH input
    2727        descriptions.
    28     \item{VF}{6}{12}{d}{\Supmc}{COACH user manual} \setMacroInAuxFile{specGenManual}
     28    \itemL{6}{12}{d}{\Supmc}{COACH user manual}{1:0:0} \setMacroInAuxFile{specGenManual}
    2929        The COACH user manual of the {\specGenManualI} delivrable updated with the feed-backs
    3030        of the demonstrator \STs.
    31     \item{V1}{0}{6}{d}{\Stima}{CSG user manual} \setMacroInAuxFile{specCsgManualI}
     31    \itemV{0}{6}{d}{\Stima}{CSG user manual} \setMacroInAuxFile{specCsgManualI}
    3232        It is the first milestone of the CSG (COACH System Generator) user manual that
    3333                will allow the demonstrator \STs to start.
    … …  
    3838        Nevertheless, these basic schemes will be enhanced to allow more efficent
    3939        synthesis.
    40     \item{VF}{6}{12}{d}{\Stima}{CSG user manual} \setMacroInAuxFile{specCsgManual}
     40    \itemL{6}{12}{d}{\Stima}{CSG user manual}{1:0:0} \setMacroInAuxFile{specCsgManual}
    4141        The CSG user manual of the {\specGenManualI} delivrable updated with the feed-backs
    4242        of the demonstrator \STs.
    43     \item{V1}{0}{6}{d}{\Subs}{HAS user manual} \setMacroInAuxFile{specHasManualI}
     43    \itemV{0}{6}{d}{\Subs}{HAS user manual} \setMacroInAuxFile{specHasManualI}
    4444        It is the first milestone of the HAS (Hardware Accelerator Synthesis) user manual that
    4545                will allow the demonstrator \STs to start.
    … …  
    4747        communication schemes defined in the {\specCsgManual} delivrable must be described for
    4848        coprocessor synthesis.
    49     \item{VF}{6}{12}{d}{\Subs}{HAS user manual} \setMacroInAuxFile{specHasManual}
     49    \itemL{6}{12}{d}{\Subs}{HAS user manual}{0:0:0} \setMacroInAuxFile{specHasManual}
    5050        The HAS user manual of the {\specGenManualI} delivrable updated with the feed-backs of
    5151        the demonstrator \STs.
    … …  
    5454    document listing all the COACH software components and how they cooperate.
    5555    \begin{livrable}
    56     \item{}{0}{6}{d}{\Supmc}{decription of \ganttlf software architecture}
     56    \itemL{0}{6}{d}{\Supmc}{decription of \ganttlf software architecture}{1:0:0}
    5757        It contains the software list and the data flow among them.
    5858    \end{livrable}
    5959\item This \ST specifies the \xcoach format.
    6060    \begin{livrable}
    61     \item{V1}{0}{6}{d+x}{\Slip}{specification of \xcoach format}
     61    \itemV{0}{6}{d+x}{\Slip}{specification of \xcoach format}
    6262        \setMacroInAuxFile{specXcoachDocI}
    6363        First release of the XML specification of the \xcoach format (DTD)
    6464        and its associated documentation allowing to start HLS tools development.
    65     \item{V2}{6}{12}{d+x}{\Slip}{specification of \xcoach format}
     65    \itemV{6}{12}{d+x}{\Slip}{specification of \xcoach format}
    6666        \setMacroInAuxFile{specXcoachDocII}
    6767        Second release of XML specification of the \xcoach format
    6868        taking into account the corrections and modifications that the
    6969        developers of HAS tools suggested.
    70     \item{VF}{12}{18}{d+x}{\Slip}{specification of \xcoach format}
     70    \itemL{12}{18}{d+x}{\Slip}{specification of \xcoach format}{0:0:0}
    7171        \setMacroInAuxFile{specXcoachDoc}
    7272        Last release of XML specification of the \xcoach format enhanced with
    7373        the expression of loop potential parallelism.
    74     \item{V1}{6}{12}{x}{\Subs}{C++ to/from \xcoach format (1)}
     74    \itemV{6}{12}{x}{\Subs}{C++ to/from \xcoach format (1)}
    7575        \setMacroInAuxFile{specXcoachToCAI}
    7676        Proposition of a GCC plugin that generates a \xcoach description
    7777        (defined in {\specXcoachDocI} deliverable) from a C++ task description
    7878        (defined in {\specHasManual} deliverable).
    79     \item{VF}{12}{18}{x}{\Subs}{C++ to/from \xcoach format step 1}
    80         \setMacroInAuxFile{specXcoachToCA}
     79    \itemL{12}{18}{x}{\Subs}{C++ to/from \xcoach format (1)}{0:0:0}
     80        \setMacroInAuxFile{specXcoachToCA}{::}
    8181        The same software as the former (\specXcoachToCAI) but for \xcoach format defined
    8282        in the {\specXcoachDoc} deliverable and HAS input defined in the {\specHasManual}
    8383        deliverable.
    84     \item{V1}{7}{12}{x}{\Subs}{C++ to/from \xcoach format (2)}
     84    \itemV{7}{12}{x}{\Subs}{C++ to/from \xcoach format (2)}
    8585        \setMacroInAuxFile{specXcoachToCBI}
    8686        This second tool regenerates a C description from a \xcoach
    8787        description.
    88     \item{VF}{12}{18}{x}{\Subs}{C++ to/from \xcoach format (2)}
     88    \itemL{12}{18}{x}{\Subs}{C++ to/from \xcoach format (2)}{0:0:0}
    8989        \setMacroInAuxFile{specXcoachToCB}
    9090        The same software as the former (\specXcoachToCBI) but for the \xcoach format as defined
    9191        in the {\specXcoachDoc} deliverable and HAS input as defined in the {\specHasManual}
    9292        deliverable.
    93     \item{V1}{12}{18}{x}{\Supmc}{\xcoachplus format to SystemC}
     93    \itemV{12}{18}{x}{\Supmc}{\xcoachplus format to SystemC}
    9494        \setMacroInAuxFile{specXcoachToSystemCI}
    9595        The first release of a program that translates \xcoachplus description to CABA
    9696        and TLM-DT SystemC module.
    97     \item{VF}{18}{24}{x}{\Supmc}{\xcoachplus format to SystemC}
     97    \itemL{18}{24}{x}{\Supmc}{\xcoachplus format to SystemC}{0:2:0}
    9898        \setMacroInAuxFile{specXcoachToSystemC}
    9999        Maintenance work of the former software (\specXcoachToSystemCI).
    100     \item{V1}{12}{18}{x}{\Subs}{\xcoachplus format to VHDL}
     100    \itemV{12}{18}{x}{\Subs}{\xcoachplus format to VHDL}
    101101        \setMacroInAuxFile{specXcoachToVhdlI}
    102102        The first release of a program that translates \xcoachplus description to
    103103        synthesizable VHDL description.
    104     \item{VF}{18}{24}{x}{\Subs}{\xcoachplus format to VHDL}
     104    \itemL{18}{24}{x}{\Subs}{\xcoachplus format to VHDL}{0:0:0}
    105105        \setMacroInAuxFile{specXcoachToVhdl}
    106106        Maintenance work of the former software (\specXcoachToVhdlI).
    … …  
    112112    and by extracting their delays. This is done by using RTL synthesis.
    113113    \begin{livrable}
    114     \item{}{0}{6}{d}{\Subs}{macro-cell definition}
     114    \itemL{0}{6}{d}{\Subs}{macro-cell definition}{0:0:0}
    115115        The document define the macro cell and the file format describing them.
    116     \item{}{6}{12}{x}{\Subs}{macro-cell library generator}
     116    \itemL{6}{12}{x}{\Subs}{macro-cell library generator}{0:0:0}
    117117        A program that generates automatically the characterized macro-cell library
    118118        for a FPGA device.

  • anr/task-2.tex

    r49 r52  
    2323\end{objectif}
    2424%
    25 \begin{workpackage}{D2}
     25\begin{workpackage}
    2626\item This \ST corresponds to the Coach System Generator (CSG) software.
    2727    \begin{livrable}
    28     \item{V1}{0}{12}{x}{\Supmc}{CSG} \setMacroInAuxFile{csgCoachArch}
     28    \itemV{0}{12}{x}{\Supmc}{CSG} \setMacroInAuxFile{csgCoachArch}
    2929        The first milestone that will allow demonstrators to start working using the COACH
    3030        hardware architecture template.
    31     \item{V2}{12}{18}{x}{\Supmc}{CSG} \setMacroInAuxFile{csgPrototypingOnly}
     31    \itemV{12}{18}{x}{\Supmc}{CSG} \setMacroInAuxFile{csgPrototypingOnly}
    3232        This milestone adds to CSG the support to the XILINX and ALTERA architectural
    3333        templates and to the enhanced communication system.
    … …  
    3535        and ALTERA architectural template.
    3636        HAS is available.
    37     \item{V3}{18}{24}{x}{\Supmc}{CSG} \setMacroInAuxFile{csgAllArch}
     37    \itemV{18}{24}{x}{\Supmc}{CSG} \setMacroInAuxFile{csgAllArch}
    3838        This milestone extends CSG (\csgPrototypingOnly) to
    3939        FPGA-SoC generation for the XILINX and ALTERA architectural template.
    40     \item{VF}{24}{36}{x}{\Supmc}{CSG} Maintenance work of CSG.
     40    \itemL{24}{36}{x}{\Supmc}{CSG}{6:6:5}
     41        Maintenance work of CSG.
    4142    \end{livrable}
    4243\item This \ST deals with the components of the architectural template.
    … …  
    5152    application.
    5253    \begin{livrable}
    53     \item{}{0}{12}{h}{\Supmc}{COACH architecture} The VHDL synthesizable descriptions
    54         of the SocLib MWMR, TokenRing components.
    55     \item{V1}{6}{18}{x}{\Stima}{XILINX architecture}
     54    \itemL{0}{12}{h}{\Supmc}{COACH architecture}{1:0:0}
     55        The VHDL synthesizable descriptions of the SocLib MWMR, TokenRing components.
     56    \itemV{6}{18}{x}{\Stima}{XILINX architecture}
    5657        \setMacroInAuxFile{csgXilinxSystemC}
    5758        The SystemC simulation module of the MWMR component with a PLB bus interface plus
    5859        the SystemC modules of the components of the XILINX architectural template
    5960        not available in the SocLib component library.
    60     \item{VF}{18}{24}{h}{\Stima}{XILINX architecture}
     61    \itemL{18}{24}{h}{\Stima}{XILINX architecture}{0:0:0}
    6162        The synthesizable VHDL description of the MWMR component corresponding to the
    6263        SystemC module of the former delivrable (\csgXilinxSystemC).
    63     \item{V1}{6}{18}{x}{\Sirisa}{ALTERA architecture}
     64    \itemV{6}{18}{x}{\Sirisa}{ALTERA architecture}
    6465        \setMacroInAuxFile{csgAlteraSystemC}
    6566        The SystemC simulation module of the MWMR component with an AVALON bus interface plus
    6667        the SystemC modules of the components of the ALTERA architectural template
    6768        not available in the SocLib component library.
    68     \item{VF}{18}{24}{h}{\Sirisa}{ALTERA architecture}
     69    \itemL{18}{24}{h}{\Sirisa}{ALTERA architecture}{0:0:0}
    6970        The synthesizable VHDL description of the MWMR component corresponding to the
    7071        SystemC module of the former delivrable (\csgAlteraSystemC);
    71     \item{V1}{6}{12}{d}{\Subs}{UBS architecture}
     72    \itemV{6}{12}{d}{\Subs}{UBS architecture}
    7273\mustbecompleted{FIXME:UBS ARGH!!!!!
    7374    1) Attention si vous touchez au MWMR, ils y a 3 composants MWMR.
    … …  
    7778       Specification of an optimized MWMR component to handle data interleaving (space and time).
    7879       This evolution aims to solve out of order communication weakness of the classical MWMR.
    79     \item{V2}{12}{24}{x}{\Subs}{UBS architecture}
     80    \itemV{12}{24}{x}{\Subs}{UBS architecture}
    8081       Release of the tool that generates the VHDL description of the optimized MWMR component
    8182       and its corresponding SystemC module.
    82     \item{VF}{24}{30}{x}{\Subs}{UBS architecture}
     83    \itemL{24}{30}{x}{\Subs}{UBS architecture}{0:0:0}
    8384       Final release of the tool that generates the VHDL description of the optimized MWMR component
    8485       and its corresponding SystemC module (\gautMWMRoptimization).
    … …  
    9091    the NIOS2 and MICROBLAZE processors.
    9192    \begin{livrable}
    92     \item{V1}{6}{8}{x}{\Supmc}{MUTEK OS} The drivers required for the first CSG
    93     milestone (delivrable \csgCoachArch).
    94     \item{V2}{8}{18}{x}{\Supmc}{MUTEK 0S} The drivers required for the
    95     second CSG milestone ({\csgPrototypingOnly}).
    96     \item{VF}{18}{33}{x}{\Supmc}{MUTEK OS} Maintenance work.
    97     \item{}{6}{18}{x}{\upmc}{Port of MUTEK OS}
     93    \itemV{6}{8}{x}{\Supmc}{MUTEK OS}
     94        The drivers required for the first CSG milestone (delivrable \csgCoachArch).
     95    \itemV{8}{18}{x}{\Supmc}{MUTEK 0S}
     96        The drivers required for the second CSG milestone ({\csgPrototypingOnly}).
     97    \itemL{18}{33}{x}{\Supmc}{MUTEK OS}{1:1:2}
     98        Maintenance work.
     99    \itemL{6}{18}{x}{\Supmc}{Port of MUTEK OS}{1.0:1:0}
    98100        Port of MUTEK OS on the NIOS2 and MICROBLAZE processors.
    99     \item{V1}{6}{8}{x}{\tima}{DNA OS} The drivers required for the first CSG
    100     milestone (delivrable \csgCoachArch).
    101     \item{V2}{8}{18}{x}{\Stima}{DNA 0S} The drivers required for the
    102     second CSG milestone ({\csgPrototypingOnly}).
    103     \item{VF}{18}{33}{x}{\Stima}{DNA OS} Maintenance work.
    104     \item{}{6}{18}{x}{\tima}{Port of DNA OS}
     101    \itemV{6}{8}{x}{\Stima}{DNA OS}
     102        The drivers required for the first CSG milestone (delivrable \csgCoachArch).
     103    \itemV{8}{18}{x}{\Stima}{DNA 0S}
     104        The drivers required for the second CSG milestone ({\csgPrototypingOnly}).
     105    \itemL{18}{33}{x}{\Stima}{DNA OS}{0:0:0}
     106        Maintenance work.
     107    \itemL{6}{18}{x}{\Stima}{Port of DNA OS}{0:0:0}
    105108        Port of MUTEK OS on the NIOS2 and MICROBLAZE processors.
    106109    \end{livrable}

  • anr/task-3.tex

    r43 r52  
    1616\end{objectif}
    1717%
    18 \begin{workpackage}{D3}
    19 \item Extraction de motifs et regénération au format COACH annoté
     18\begin{workpackage}
     19  \item Extraction de motifs et regénération au format COACH annoté
    2020    \mustbecompleted{FIXME:IRISA ........}
    2121    \begin{livrable}
    22         \item{V1}{0}{18}{d}{\Sirisa}{Interation manuelle des motifs} \mustbecompleted{FIXME .....}
    23         \item{VF}{18}{24}{d}{\Sirisa}{Integration manuelle des motifs} \mustbecompleted{FIXME ......}
     22      \itemV{0}{18}{d}{\Sirisa}{Interation manuelle des motifs}
     23        \mustbecompleted{FIXME .....}
     24      \itemL{18}{24}{d}{\Sirisa}{Integration manuelle des motifs}{0:0:0}
     25        \mustbecompleted{FIXME ......}
    2426    \end{livrable}
    25 \item \mustbecompleted{FIXME: la liste des ST est dans wp.txt}
     27  \item \mustbecompleted{FIXME: la liste des ST est dans wp.txt}
    2628    \begin{livrable}
    27         \item{V1}{0}{18}{d}{\Sirisa}{Intégration manuelle des motifs} \mustbecompleted{FIXME ......}
     29        \itemL{0}{18}{d}{\Sirisa}{Intégration manuelle des motifs}{0:0:0}
     30        \mustbecompleted{FIXME ......}
    2831    \end{livrable}
    29 \item Extraction of parallelism in polyhedral loops and conversion into a process network.
     32  \item Extraction of parallelism in polyhedral loops and conversion into a process network.
    3033   \begin{livrable}
    31     \item{V1}{0}{6}{d}{\Slip}{Method, Preliminary Definition}
     34    \itemV{0}{6}{d}{\Slip}{Method, Preliminary Definition}
    3235      Description of the process network construction method. User manual.
    33     \item{VF}{30}{36}{d}{\Slip}{Method}
     36    \itemL{30}{36}{d}{\Slip}{Method}{0:0:0}
    3437      Final assessment of the method and improved version of the user manual.
    35     \item{V1}{6}{12}{x}{\Slip}{Process Construction)}
     38    \itemV{6}{12}{x}{\Slip}{Process Construction)}
    3639      Preliminary implementation in the Syntol framework.  At this step the sofware will
    3740      just implement a single constructor.
    38     \item{V2}{12}{24}{x}{\Slip} {Arrays and FIFO}
     41    \itemV{12}{24}{x}{\Slip} {Arrays and FIFO}
    3942      Implementation of the array contraction and FIFO construction algorithm. Conversion
    4043      of the imput and output to the \xcoach format.
    41     \item{VF}{24}{30}{x}{\Slip} {Process ans FIFO Construction}
     44    \itemL{24}{30}{x}{\Slip} {Process ans FIFO Construction} {0:0:0}
    4245      Final release taking into account the feedbacks from the demonstrator \STs.
    4346   \end{livrable}

  • anr/task-4.tex

    r48 r52  
    2727\end{objectif}
    2828%
    29 \begin{workpackage}{D4}
     29\begin{workpackage}
    3030\item The goal of this \ST is to integrate the UGH HLS tool to the COACH framework. It
    3131    consists of suppressing the C commpiler and the SystemC and VHDL drivers and replacing
    3232    them by \xcoach and \xcoachplus drivers.
    3333    \begin{livrable}
    34     \item{V1}{6}{12}{x}{\Stima}{UGH integration} The UGH software that is able to read
    35         \xcoach format.
    36     \item{V2}{12}{18}{x}{\Supmc}{UGH integration} The UGH software that is able to read
    37         \xcoach format and to write \xcoachplus format.
    38     \item{VF}{18}{33}{x}{\Supmc}{UGH integration} Maintenance work of the UGH software.
     34    \itemL{6}{12}{x}{\Stima}{UGH integration}
     35        The UGH software that is able to read \xcoach format.
     36    \itemV{12}{18}{x}{\Supmc}{UGH integration}
     37        The UGH software that is able to read \xcoach format and to write \xcoachplus format.
     38    \itemL{18}{33}{x}{\Supmc}{UGH integration}{0:2:4.0}
     39        Maintenance work of the UGH software.
    3940    \end{livrable}
    4041\item The goal of this \ST is to integrate the GAUT HLS tool to the COACH framework. It
    … …  
    4243    them by \xcoach and \xcoachplus drivers.
    4344    \begin{livrable}
    44     \item{V1}{6}{12}{x}{\Subs}{GAUT integration} The GAUT software that is able to read
    45         \xcoach format.
    46     \item{VF}{12}{18}{x}{\Subs}{GAUT integration} The GAUT software that is able to read
    47         \xcoach format and to write \xcoachplus format.
    48     \item{VF}{18}{33}{x}{\Subs}{GAUT integration} Maintenance work of the GAUT software.
     45    \itemV{6}{12}{x}{\Subs}{GAUT integration}
     46        The GAUT software that is able to read \xcoach format.
     47    \itemV{12}{18}{x}{\Subs}{GAUT integration}
     48        The GAUT software that is able to read \xcoach format and to write \xcoachplus format.
     49    \itemL{18}{33}{x}{\Subs}{GAUT integration}{0:0:0}
     50        Maintenance work of the GAUT software.
    4951    \end{livrable}
    5052\item The goal of this \ST is to improve the UGH and GAUT HLS tools.
    … …  
    5254    usefull enhancements
    5355    \begin{livrable}
    54     \item{}{18}{24}{x}{\Stima}{UGH enhancement 1} The UGH software whith support for treating
    55         automatically data dominated sections included into a control dominated application.
    56     \item{}{21}{27}{x}{\Stima}{UGH enhancement 2} The UGH software that is able to
    57         generate a micro-architecture without the variable binding currently done by the
    58         designer.
    59     \item{}{6}{18}{x}{\Subs}{GAUT enhancement 1} Release of the GAUT software that supports the control
    60     and data flow formal model.
     56    \itemL{18}{24}{x}{\Stima}{UGH enhancement 1}{0:0:0}
     57        The UGH software whith support for treating automatically data dominated sections
     58        included into a control dominated application.
     59    \itemL{21}{27}{x}{\Stima}{UGH enhancement 2}{0:0:0}
     60        The UGH software that is able to generate a micro-architecture without the
     61        variable binding currently done by the designer.
     62    \itemL{6}{18}{x}{\Subs}{GAUT enhancement 1}{0:0:0}
     63        Release of the GAUT software that supports the control and data flow formal model.
    6164\mustbecompleted{FIXME:USB ca ne va pas avec l'intro de la tache, UGH n'a
    6265plus aucune utilite si ceci reste}
    63     \item{}{18}{30}{x}{\Subs}{GAUT enhancement 2} Release of the GAUT software that supports the control
    64     and data flow formal model and also supports new constraints and objectives defined in \ST1-1 \mustbecompleted{FIXME:UBS: quel
    65     delivrable ??}.
     66    \itemL{18}{30}{x}{\Subs}{GAUT enhancement 2}{0:0:0}
     67        Release of the GAUT software that supports the control and data flow formal model
     68        and also supports new constraints and objectives defined in
     69        \mustbecompleted{FIXME:USB utilise une macro svp: \ST1-1}
     70        \mustbecompleted{FIXME:UBS: quel delivrable ??}.
    6671%   FIXME:USB redondant avec le delivrable "GAUT integration" ou alors
    6772%   c'est en enhancement et il faut le decrire.
    … …  
    7782    synthesis.
    7883    \begin{livrable}
    79     \item{V1}{0}{6}{d}{\Supmc}{frequency calibration} A document describing the set up of
    80         the coprocessor frequency calibration.
    81     \item{V2}{6}{12}{x}{\Supmc}{frequency calibration} A VHDL description of hardware
    82         added to the coprocessor to enable the calibration.
    83     \item{VF}{12}{24}{x}{\Supmc}{frequency calibration} The frequency calibration software
    84         consists of a driver in the FPGA-SoC operating system and of a control software on
    85         a PC.
     84    \itemV{0}{12}{d}{\Supmc}{frequency calibration}
     85        A document describing the set up of the coprocessor frequency calibration.
     86    \itemV{12}{24}{x}{\Supmc}{frequency calibration}
     87        A VHDL description of hardware added to the coprocessor to enable the calibration.
     88    \itemL{24}{33}{x}{\Supmc}{frequency calibration}{2:.5:3.5}
     89        The frequency calibration software consists of a driver in the FPGA-SoC operating
     90        system and of a control software on a PC.
    8691    \end{livrable}
    8792\end{workpackage}

  • anr/task-5.tex

    r40 r52  
    2424\end{objectif}
    2525%
    26 \begin{workpackage}{D5}
     26\begin{workpackage}
    2727\item This \ST is the definition of the communication schemes as a software API
    2828    (Application Programing Interface) between the application part running on the PC and
    2929    the application part running on the FPGA-SoC.
    3030    \begin{livrable}
    31     \item{}{0}{6}{d}{\Supmc}{HPC communication API} User refernce manual describing the API.
    32         \global\edef\hpcCommApi{\name}
     31    \itemL{0}{6}{d}{\Supmc}{HPC communication API}{1.0:0:0}
     32        \setMacroInAuxFile{hpcCommApi}
     33        User refernce manual describing the API.
    3334    \end{livrable}
    3435\item This \ST consists in helping to partition the application.
    … …  
    3637    the partitioned application.
    3738    \begin{livrable}
    38     \item{}{6}{12}{x}{\Supmc}{HPC partionning helper} A library implementing the communication
    39         API defined in the {\hpcCommApi} delivrable.
     39    \itemL{6}{12}{x}{\Supmc}{HPC partionning helper}{1:0:0}
     40        A library implementing the communication API defined in the {\hpcCommApi} delivrable.
    4041    \end{livrable}
    4142\item This \ST deals with the implementation of the communication API on the both sides (PC
    4243    part and FPGA-SoC).
    4344    \begin{livrable}
    44     \item{}{12}{21}{x}{\Supmc}{HPC API for Linux PC} The PC part of the HPC communication API
    45         that comminicates with the FPGA-SOC, a library and probably a LINUX module.
    46     \item{}{12}{21}{x}{\Supmc}{HPC API for MUTEK OS} The FPGA-SoC part of the communication API, a
    47         driver.\global\edef\hpcMutekDriver{\name}
    48     \item{}{21}{24}{x}{\Stima}{HPC API for DNA OS} Port of the {\hpcMutekDriver} driver on the DNA OS.
     45    \itemL{12}{21}{x}{\Supmc}{HPC API for Linux PC}{0:3:0}
     46        The PC part of the HPC communication API that comminicates with the FPGA-SOC, a
     47        library and probably a LINUX module.
     48    \itemL{12}{21}{x}{\Supmc}{HPC API for MUTEK OS}{0:3:0}
     49        \setMacroInAuxFile{hpcMutekDriver}
     50        The FPGA-SoC part of the communication API, a driver.
     51    \itemL{21}{24}{x}{\Stima}{HPC API for DNA OS}{0:0:0}
     52        Port of the {\hpcMutekDriver} driver on the DNA OS.
     53    \itemL{24}{33}{x}{\Supmc}{HPC API}{0:0:1}
     54        Maintenance work of HPC API for both Lunix PC and MUTEK OS.
    4955    \end{livrable}
    5056\item This \ST deals with the implementation of hardware required by the COACH
    5157    architectural template for using the PCI/X IP of \altera and \xilinx.
    5258    \begin{livrable}
    53     \item{}{9}{18}{h}{\Stima}{HPC hardware \xilinx}
     59    \itemL{9}{18}{h}{\Stima}{HPC hardware \xilinx}{0:0:0}
    5460        \setMacroInAuxFile{hpcPlbBridge}
    5561        The synthesizable VHDL description of a PLB/VCI bridge and its corresponding SystemC model.
    56     \item{}{9}{18}{h}{\Saltera}{HPC hardware \altera}
     62    \itemL{9}{18}{h}{\Saltera}{HPC hardware \altera}{0:0:0}
    5763        \setMacroInAuxFile{hpcAvalonBridge}
    5864        The synthesizable VHDL description of an AVALON/VCI bridge and its corresponding SystemC model.
    … …  
    6066\item This \ST deals with the dynamic reconfiguration of an FPGA.
    6167    \begin{livrable}
    62     \item{}{18}{30}{x}{\Stima}{dynamic reconfiguration \ganttlf DNA drivers}
    63         \global\edef\hpcDynconfDriver{\name}
     68    \itemL{18}{30}{x}{\Stima}{dynamic reconfiguration \ganttlf DNA drivers}{0:0:0}
     69        \setMacroInAuxFile{hpcDynconfDriver}
    6470        \mustbecompleted{FIXME:TIMA ....}
    65     \item{}{30}{36}{x}{\Supmc}{dynamic reconfiguration \ganttlf MUTEK drivers}
     71    \itemL{30}{36}{x}{\Supmc}{dynamic reconfiguration \ganttlf MUTEK drivers}{0:0:1}
    6672        Port of the {\hpcDynconfDriver} \mustbecompleted{FIXME:TIMA driver} on the MUTEK OS.
    67     \item{}{24}{36}{x}{\Supmc}{CSG support for \ganttlf dynamic reconfiguration}
     73    \itemL{24}{36}{x}{\Supmc}{CSG support for \ganttlf dynamic reconfiguration}{0:0:2}
    6874        \mustbecompleted{FIXME:TIMA ....}
    69     \item{}{18}{36}{x}{\Stima}{PC support for \ganttlf dynamic reconfiguration}
     75    \itemL{18}{36}{x}{\Stima}{PC support for \ganttlf dynamic reconfiguration}{0:0:0}
    7076        \mustbecompleted{FIXME:TIMA ....}
    7177    \end{livrable}
    … …  
    7480    They are based on \mustbecompleted{FIXME:stratix4} FPGA device of 400,000 LUT.
    7581    \begin{livrable}
    76     \item{}{0}{6}{m}{\Saltera}{HPC development boards} Two PCI/X FPGA boards.
     82    \itemL{0}{6}{m}{\Saltera}{HPC development boards}{0:0:0} Two PCI/X FPGA boards.
    7783    \end{livrable}
    7884\end{workpackage}

  • anr/task-6.tex

    r50 r52  
    1313\end{objectif}
    1414%
    15 \begin{workpackage}{D6}
     15\begin{workpackage}
    1616  \item This \ST relies to the COACH use by \navtel.
    1717    The application is A-COMPLETER-1-A-3-LIGNE .... ....  .... .... ....
    … …  
    2020    ... ...
    2121    \begin{livrable}
    22     \item{V1}{0}{6}{x}{\Snavtel}{\navtel \ganttlf demonstrator specification}
     22    \itemV{0}{6}{x}{\Snavtel}{\navtel \ganttlf demonstrator specification}
    2323        Choice of the demonstrator and its implementation as a PC C/C++ program.
    24     \item{VF}{7}{12}{x}{\Snavtel}{\navtel \ganttlf demonstrator specification}
     24    \itemL{7}{12}{x}{\Snavtel}{\navtel \ganttlf demonstrator specification}{0:0:0}
    2525        The demonstrator is described as a communicating task graph using the
    2626        specification defined in the milestone T0+12.
    27     \item{V1}{13}{15}{d}{\Snavtel}{\navtel \ganttlf demonstrator}
     27    \itemV{13}{15}{d}{\Snavtel}{\navtel \ganttlf demonstrator}
    2828        This deliverable is a report that describes the experimentation done with the
    2929        T0+12 COACH milestone.
    30     \item{V2}{25}{27}{d}{\Snavtel}{\navtel \ganttlf demonstrator}
     30    \itemV{25}{27}{d}{\Snavtel}{\navtel \ganttlf demonstrator}
    3131        This deliverable is a report that describes the experimentation done with the
    3232        T0+24 COACH milestone.
    33     \item{VF}{30}{36}{d}{\Snavtel}{\navtel \ganttlf demonstrator}
     33    \itemL{30}{36}{d}{\Snavtel}{\navtel \ganttlf demonstrator}{0:0:0}
    3434        This deliverable is a report that describes the experimentation done with the
    3535        pre-final COACH release.

  • anr/task-7.tex

    r49 r52  
    1919\end{objectif}
    2020%
    21 \begin{workpackage}{D1}
     21\begin{workpackage}
    2222  \item This \ST relies to the management of the WEB site and to the distribution of
    2323    the COACH releases.
    2424    \begin{livrable}
    25       \item{V1}{0}{6}{d}{\Supmc}{dissemination WEB site}
     25      \itemV{0}{6}{d}{\Supmc}{dissemination WEB site}
    2626        This deliverable consists firstly in providing a WEB site (name, HTTP server
    2727        setup, wiki) and secondly in defining the site map and finally in writting and
    2828        installing the pages.
    29       \item{VF}{6}{36}{}{\Supmc}{dissemination WEB site}
     29      \itemL{6}{36}{}{\Supmc}{dissemination WEB site}{1:.5:.5}
    3030        This deliverable corresponds to the standard management of a WEB site (modifying,
    3131        adding, suppressing, replacing pages).
    3232        Especialy the user reference manuals provided in the other tasks will be published
    3333        in this site. The published articles will be also be installed in this site.
    34       \item{}{6}{36}{}{\Supmc}{release handling}
     34      \itemL{6}{36}{}{\Supmc}{release handling}{1:.5:.5}
    3535        This deliverable deals with the elaboration of the COACH software milestones and
    3636        final releases with their installation manuals and to publish then into the WEB
    … …  
    4444    planets, or a database management system.
    4545  \begin{livrable}
    46     \item{V1}{0}{6}{x}{\Supmc}{tutorial specification}
     46    \itemV{0}{6}{x}{\Supmc}{tutorial specification}
    4747        Choice of the application and its implementation as a C/C++ program.
    48     \item{V2}{6}{12}{d+x}{\Supmc}{tutorial}
     48    \itemV{6}{12}{d+x}{\Supmc}{tutorial}
    4949        The application is split into two communicating parts, the PC part and FPGA-SoC part.
    5050        Using the features the T0+12 milestone provides,
    … …  
    5252        The FPGA-SoC part is described as communicating task graph. The tutorial also describes
    5353        how a promising task graph can be obtained.
    54     \item{V3}{18}{24}{d}{\Supmc}{tutorial}
     54    \itemV{18}{24}{d}{\Supmc}{tutorial}
    5555        This tutorial shows how a task can be migrated to coprocessor using HAS tools and
    5656        how FPGA-SoC can be generated and run to FPGA. This for HAS tools and and
    5757        architectural template available in T0+24 milestone.
    58     \item{VF}{30}{36}{d}{\Supmc}{tutorial}
     58    \itemL{30}{36}{d}{\Supmc}{tutorial}{2:1:1}
    5959        The final release of the tutorial.
    6060    \end{livrable}
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