- Timestamp:
- Apr 5, 2007, 4:17:30 PM (17 years ago)
- Location:
- trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor
- Files:
-
- 47 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/SelfTest/configuration.cfg
r5 r15 1 1 Meta_Predictor 2 0 0+1 # have_meta_predictor2 1 1 +1 # have_meta_predictor 3 3 1 1 +1 # predictor_0_have_bht 4 4 10 10 +1 # predictor_0_bht_size_shifter -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/SelfTest/src/test.cpp
r5 r15 28 28 *********************************************************************/ 29 29 sc_clock * CLOCK ; 30 sc_signal<Tcontrol_t> * NRESET ; 30 31 31 32 // Interface Predict … … 45 46 string rename; 46 47 47 CLOCK = new sc_clock ("clock", 1.0, 0.5); 48 48 CLOCK = new sc_clock ("clock", 1.0, 0.5); 49 NRESET = new sc_signal<Tcontrol_t> ("NRESET"); 50 49 51 PREDICT_VAL = new sc_signal<Tcontrol_t> * [_param._nb_prediction ]; 50 52 PREDICT_ACK = new sc_signal<Tcontrol_t> * [_param._nb_prediction ]; … … 93 95 cout << "<" << name << "> Instanciation of _Meta_Predictor" << endl; 94 96 95 (*(_Meta_Predictor->in_CLOCK)) (*(CLOCK)); 97 (*(_Meta_Predictor->in_CLOCK )) (*(CLOCK )); 98 (*(_Meta_Predictor->in_NRESET)) (*(NRESET)); 96 99 97 100 for (uint32_t i=0; i<_param._nb_prediction; i++) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/Makefile.deps
r2 r15 14 14 include $(DIR_MORPHEO)/Behavioural/Generic/Shifter/Makefile.deps 15 15 endif 16 ifndef RegisterFile 17 include $(DIR_MORPHEO)/Behavioural/Generic/RegisterFile/ Makefile.deps16 ifndef RegisterFile_Monolithic 17 include $(DIR_MORPHEO)/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/Makefile.deps 18 18 endif 19 19 … … 22 22 #-----[ Library ]------------------------------------------ 23 23 Branch_History_Table_LIBRARY = -lBranch_History_Table \ 24 $(RegisterFile_ LIBRARY) \24 $(RegisterFile_Monolithic_LIBRARY) \ 25 25 $(Shifter_LIBRARY) \ 26 26 $(Behavioural_LIBRARY) 27 27 28 28 Branch_History_Table_DIR_LIBRARY = -L$(DIR_MORPHEO)/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/lib \ 29 $(RegisterFile_ DIR_LIBRARY) \29 $(RegisterFile_Monolithic_DIR_LIBRARY) \ 30 30 $(Shifter_DIR_LIBRARY) \ 31 31 $(Behavioural_DIR_LIBRARY) … … 36 36 @$(MAKE) Behavioural_library 37 37 @$(MAKE) Shifter_library 38 @$(MAKE) RegisterFile_ library38 @$(MAKE) RegisterFile_Monolithic_library 39 39 @$(MAKE) --directory=$(DIR_MORPHEO)/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table --makefile=Makefile 40 40 … … 42 42 @$(MAKE) Behavioural_library_clean 43 43 @$(MAKE) Shifter_library_clean 44 @$(MAKE) RegisterFile_ library_clean44 @$(MAKE) RegisterFile_Monolithic_library_clean 45 45 @$(MAKE) --directory=$(DIR_MORPHEO)/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table --makefile=Makefile clean -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/SelfTest/mkf.info
r2 r15 1 2 # Branch_History_Table_03 target_dep all Branch_History_Table_0.ngc4 target_dep Branch_History_Table_0.ngc Branch_History_Table_0.prj5 target_dep Branch_History_Table_0.prj Branch_History_Table_0_Pack.vhdl Branch_History_Table_0_RegisterFile_Pack.vhdl Branch_History_Table_0_RegisterFile.vhdl Branch_History_Table_0_Shifter_Pack.vhdl Branch_History_Table_0_Shifter.vhdl Branch_History_Table_0.vhdl6 7 # Branch_History_Table_108 target_dep all Branch_History_Table_10.ngc9 target_dep Branch_History_Table_10.ngc Branch_History_Table_10.prj10 target_dep Branch_History_Table_10.prj Branch_History_Table_10_Pack.vhdl Branch_History_Table_10_RegisterFile_Pack.vhdl Branch_History_Table_10_RegisterFile.vhdl Branch_History_Table_10_Shifter_Pack.vhdl Branch_History_Table_10_Shifter.vhdl Branch_History_Table_10.vhdl11 12 # Branch_History_Table_1113 target_dep all Branch_History_Table_11.ngc14 target_dep Branch_History_Table_11.ngc Branch_History_Table_11.prj15 target_dep Branch_History_Table_11.prj Branch_History_Table_11_Pack.vhdl Branch_History_Table_11_RegisterFile_Pack.vhdl Branch_History_Table_11_RegisterFile.vhdl Branch_History_Table_11_Shifter_Pack.vhdl Branch_History_Table_11_Shifter.vhdl Branch_History_Table_11.vhdl16 17 # Branch_History_Table_1218 target_dep all Branch_History_Table_12.ngc19 target_dep Branch_History_Table_12.ngc Branch_History_Table_12.prj20 target_dep Branch_History_Table_12.prj Branch_History_Table_12_Pack.vhdl Branch_History_Table_12_RegisterFile_Pack.vhdl Branch_History_Table_12_RegisterFile.vhdl Branch_History_Table_12_Shifter_Pack.vhdl Branch_History_Table_12_Shifter.vhdl Branch_History_Table_12.vhdl21 22 # Branch_History_Table_1323 target_dep all Branch_History_Table_13.ngc24 target_dep Branch_History_Table_13.ngc Branch_History_Table_13.prj25 target_dep Branch_History_Table_13.prj Branch_History_Table_13_Pack.vhdl Branch_History_Table_13_RegisterFile_Pack.vhdl Branch_History_Table_13_RegisterFile.vhdl Branch_History_Table_13_Shifter_Pack.vhdl Branch_History_Table_13_Shifter.vhdl Branch_History_Table_13.vhdl26 27 # Branch_History_Table_1428 target_dep all Branch_History_Table_14.ngc29 target_dep Branch_History_Table_14.ngc Branch_History_Table_14.prj30 target_dep Branch_History_Table_14.prj Branch_History_Table_14_Pack.vhdl Branch_History_Table_14_RegisterFile_Pack.vhdl Branch_History_Table_14_RegisterFile.vhdl Branch_History_Table_14_Shifter_Pack.vhdl Branch_History_Table_14_Shifter.vhdl Branch_History_Table_14.vhdl31 32 # Branch_History_Table_1533 target_dep all Branch_History_Table_15.ngc34 target_dep Branch_History_Table_15.ngc Branch_History_Table_15.prj35 target_dep Branch_History_Table_15.prj Branch_History_Table_15_Pack.vhdl Branch_History_Table_15_RegisterFile_Pack.vhdl Branch_History_Table_15_RegisterFile.vhdl Branch_History_Table_15_Shifter_Pack.vhdl Branch_History_Table_15_Shifter.vhdl Branch_History_Table_15.vhdl36 37 # Branch_History_Table_1638 target_dep all Branch_History_Table_16.ngc39 target_dep Branch_History_Table_16.ngc Branch_History_Table_16.prj40 target_dep Branch_History_Table_16.prj Branch_History_Table_16_Pack.vhdl Branch_History_Table_16_RegisterFile_Pack.vhdl Branch_History_Table_16_RegisterFile.vhdl Branch_History_Table_16_Shifter_Pack.vhdl Branch_History_Table_16_Shifter.vhdl Branch_History_Table_16.vhdl41 42 # Branch_History_Table_1743 target_dep all Branch_History_Table_17.ngc44 target_dep Branch_History_Table_17.ngc Branch_History_Table_17.prj45 target_dep Branch_History_Table_17.prj Branch_History_Table_17_Pack.vhdl Branch_History_Table_17_RegisterFile_Pack.vhdl Branch_History_Table_17_RegisterFile.vhdl Branch_History_Table_17_Shifter_Pack.vhdl Branch_History_Table_17_Shifter.vhdl Branch_History_Table_17.vhdl46 47 # Branch_History_Table_1848 target_dep all Branch_History_Table_18.ngc49 target_dep Branch_History_Table_18.ngc Branch_History_Table_18.prj50 target_dep Branch_History_Table_18.prj Branch_History_Table_18_Pack.vhdl Branch_History_Table_18_RegisterFile_Pack.vhdl Branch_History_Table_18_RegisterFile.vhdl Branch_History_Table_18_Shifter_Pack.vhdl Branch_History_Table_18_Shifter.vhdl Branch_History_Table_18.vhdl51 52 # Branch_History_Table_1953 target_dep all Branch_History_Table_19.ngc54 target_dep Branch_History_Table_19.ngc Branch_History_Table_19.prj55 target_dep Branch_History_Table_19.prj Branch_History_Table_19_Pack.vhdl Branch_History_Table_19_RegisterFile_Pack.vhdl Branch_History_Table_19_RegisterFile.vhdl Branch_History_Table_19_Shifter_Pack.vhdl Branch_History_Table_19_Shifter.vhdl Branch_History_Table_19.vhdl56 57 # Branch_History_Table_158 target_dep all Branch_History_Table_1.ngc59 target_dep Branch_History_Table_1.ngc Branch_History_Table_1.prj60 target_dep Branch_History_Table_1.prj Branch_History_Table_10_Pack.vhdl Branch_History_Table_10_RegisterFile_Pack.vhdl Branch_History_Table_10_RegisterFile.vhdl Branch_History_Table_10_Shifter_Pack.vhdl Branch_History_Table_10_Shifter.vhdl Branch_History_Table_10.vhdl Branch_History_Table_11_Pack.vhdl Branch_History_Table_11_RegisterFile_Pack.vhdl Branch_History_Table_11_RegisterFile.vhdl Branch_History_Table_11_Shifter_Pack.vhdl Branch_History_Table_11_Shifter.vhdl Branch_History_Table_11.vhdl Branch_History_Table_12_Pack.vhdl Branch_History_Table_12_RegisterFile_Pack.vhdl Branch_History_Table_12_RegisterFile.vhdl Branch_History_Table_12_Shifter_Pack.vhdl Branch_History_Table_12_Shifter.vhdl Branch_History_Table_12.vhdl Branch_History_Table_13_Pack.vhdl Branch_History_Table_13_RegisterFile_Pack.vhdl Branch_History_Table_13_RegisterFile.vhdl Branch_History_Table_13_Shifter_Pack.vhdl Branch_History_Table_13_Shifter.vhdl Branch_History_Table_13.vhdl Branch_History_Table_14_Pack.vhdl Branch_History_Table_14_RegisterFile_Pack.vhdl Branch_History_Table_14_RegisterFile.vhdl Branch_History_Table_14_Shifter_Pack.vhdl Branch_History_Table_14_Shifter.vhdl Branch_History_Table_14.vhdl Branch_History_Table_15_Pack.vhdl Branch_History_Table_15_RegisterFile_Pack.vhdl Branch_History_Table_15_RegisterFile.vhdl Branch_History_Table_15_Shifter_Pack.vhdl Branch_History_Table_15_Shifter.vhdl Branch_History_Table_15.vhdl Branch_History_Table_16_Pack.vhdl Branch_History_Table_16_RegisterFile_Pack.vhdl Branch_History_Table_16_RegisterFile.vhdl Branch_History_Table_16_Shifter_Pack.vhdl Branch_History_Table_16_Shifter.vhdl Branch_History_Table_16.vhdl Branch_History_Table_17_Pack.vhdl Branch_History_Table_17_RegisterFile_Pack.vhdl Branch_History_Table_17_RegisterFile.vhdl Branch_History_Table_17_Shifter_Pack.vhdl Branch_History_Table_17_Shifter.vhdl Branch_History_Table_17.vhdl Branch_History_Table_18_Pack.vhdl Branch_History_Table_18_RegisterFile_Pack.vhdl Branch_History_Table_18_RegisterFile.vhdl Branch_History_Table_18_Shifter_Pack.vhdl Branch_History_Table_18_Shifter.vhdl Branch_History_Table_18.vhdl Branch_History_Table_19_Pack.vhdl Branch_History_Table_19_RegisterFile_Pack.vhdl Branch_History_Table_19_RegisterFile.vhdl Branch_History_Table_19_Shifter_Pack.vhdl Branch_History_Table_19_Shifter.vhdl Branch_History_Table_19.vhdl Branch_History_Table_1_Pack.vhdl Branch_History_Table_1_RegisterFile_Pack.vhdl Branch_History_Table_1_RegisterFile.vhdl Branch_History_Table_1_Shifter_Pack.vhdl Branch_History_Table_1_Shifter.vhdl Branch_History_Table_1.vhdl61 62 # Branch_History_Table_2063 target_dep all Branch_History_Table_20.ngc64 target_dep Branch_History_Table_20.ngc Branch_History_Table_20.prj65 target_dep Branch_History_Table_20.prj Branch_History_Table_20_Pack.vhdl Branch_History_Table_20_RegisterFile_Pack.vhdl Branch_History_Table_20_RegisterFile.vhdl Branch_History_Table_20_Shifter_Pack.vhdl Branch_History_Table_20_Shifter.vhdl Branch_History_Table_20.vhdl66 67 # Branch_History_Table_2168 target_dep all Branch_History_Table_21.ngc69 target_dep Branch_History_Table_21.ngc Branch_History_Table_21.prj70 target_dep Branch_History_Table_21.prj Branch_History_Table_21_Pack.vhdl Branch_History_Table_21_RegisterFile_Pack.vhdl Branch_History_Table_21_RegisterFile.vhdl Branch_History_Table_21_Shifter_Pack.vhdl Branch_History_Table_21_Shifter.vhdl Branch_History_Table_21.vhdl71 72 # Branch_History_Table_2273 target_dep all Branch_History_Table_22.ngc74 target_dep Branch_History_Table_22.ngc Branch_History_Table_22.prj75 target_dep Branch_History_Table_22.prj Branch_History_Table_22_Pack.vhdl Branch_History_Table_22_RegisterFile_Pack.vhdl Branch_History_Table_22_RegisterFile.vhdl Branch_History_Table_22_Shifter_Pack.vhdl Branch_History_Table_22_Shifter.vhdl Branch_History_Table_22.vhdl76 77 # Branch_History_Table_2378 target_dep all Branch_History_Table_23.ngc79 target_dep Branch_History_Table_23.ngc Branch_History_Table_23.prj80 target_dep Branch_History_Table_23.prj Branch_History_Table_23_Pack.vhdl Branch_History_Table_23_RegisterFile_Pack.vhdl Branch_History_Table_23_RegisterFile.vhdl Branch_History_Table_23_Shifter_Pack.vhdl Branch_History_Table_23_Shifter.vhdl Branch_History_Table_23.vhdl81 82 # Branch_History_Table_2483 target_dep all Branch_History_Table_24.ngc84 target_dep Branch_History_Table_24.ngc Branch_History_Table_24.prj85 target_dep Branch_History_Table_24.prj Branch_History_Table_24_Pack.vhdl Branch_History_Table_24_RegisterFile_Pack.vhdl Branch_History_Table_24_RegisterFile.vhdl Branch_History_Table_24_Shifter_Pack.vhdl Branch_History_Table_24_Shifter.vhdl Branch_History_Table_24.vhdl86 87 # Branch_History_Table_2588 target_dep all Branch_History_Table_25.ngc89 target_dep Branch_History_Table_25.ngc Branch_History_Table_25.prj90 target_dep Branch_History_Table_25.prj Branch_History_Table_25_Pack.vhdl Branch_History_Table_25_RegisterFile_Pack.vhdl Branch_History_Table_25_RegisterFile.vhdl Branch_History_Table_25_Shifter_Pack.vhdl Branch_History_Table_25_Shifter.vhdl Branch_History_Table_25.vhdl91 92 # Branch_History_Table_2693 target_dep all Branch_History_Table_26.ngc94 target_dep Branch_History_Table_26.ngc Branch_History_Table_26.prj95 target_dep Branch_History_Table_26.prj Branch_History_Table_26_Pack.vhdl Branch_History_Table_26_RegisterFile_Pack.vhdl Branch_History_Table_26_RegisterFile.vhdl Branch_History_Table_26_Shifter_Pack.vhdl Branch_History_Table_26_Shifter.vhdl Branch_History_Table_26.vhdl96 97 # Branch_History_Table_2798 target_dep all Branch_History_Table_27.ngc99 target_dep Branch_History_Table_27.ngc Branch_History_Table_27.prj100 target_dep Branch_History_Table_27.prj Branch_History_Table_27_Pack.vhdl Branch_History_Table_27_RegisterFile_Pack.vhdl Branch_History_Table_27_RegisterFile.vhdl Branch_History_Table_27_Shifter_Pack.vhdl Branch_History_Table_27_Shifter.vhdl Branch_History_Table_27.vhdl101 102 # Branch_History_Table_28103 target_dep all Branch_History_Table_28.ngc104 target_dep Branch_History_Table_28.ngc Branch_History_Table_28.prj105 target_dep Branch_History_Table_28.prj Branch_History_Table_28_Pack.vhdl Branch_History_Table_28_RegisterFile_Pack.vhdl Branch_History_Table_28_RegisterFile.vhdl Branch_History_Table_28_Shifter_Pack.vhdl Branch_History_Table_28_Shifter.vhdl Branch_History_Table_28.vhdl106 107 # Branch_History_Table_29108 target_dep all Branch_History_Table_29.ngc109 target_dep Branch_History_Table_29.ngc Branch_History_Table_29.prj110 target_dep Branch_History_Table_29.prj Branch_History_Table_29_Pack.vhdl Branch_History_Table_29_RegisterFile_Pack.vhdl Branch_History_Table_29_RegisterFile.vhdl Branch_History_Table_29_Shifter_Pack.vhdl Branch_History_Table_29_Shifter.vhdl Branch_History_Table_29.vhdl111 112 # Branch_History_Table_2113 target_dep all Branch_History_Table_2.ngc114 target_dep Branch_History_Table_2.ngc Branch_History_Table_2.prj115 target_dep Branch_History_Table_2.prj Branch_History_Table_20_Pack.vhdl Branch_History_Table_20_RegisterFile_Pack.vhdl Branch_History_Table_20_RegisterFile.vhdl Branch_History_Table_20_Shifter_Pack.vhdl Branch_History_Table_20_Shifter.vhdl Branch_History_Table_20.vhdl Branch_History_Table_21_Pack.vhdl Branch_History_Table_21_RegisterFile_Pack.vhdl Branch_History_Table_21_RegisterFile.vhdl Branch_History_Table_21_Shifter_Pack.vhdl Branch_History_Table_21_Shifter.vhdl Branch_History_Table_21.vhdl Branch_History_Table_22_Pack.vhdl Branch_History_Table_22_RegisterFile_Pack.vhdl Branch_History_Table_22_RegisterFile.vhdl Branch_History_Table_22_Shifter_Pack.vhdl Branch_History_Table_22_Shifter.vhdl Branch_History_Table_22.vhdl Branch_History_Table_23_Pack.vhdl Branch_History_Table_23_RegisterFile_Pack.vhdl Branch_History_Table_23_RegisterFile.vhdl Branch_History_Table_23_Shifter_Pack.vhdl Branch_History_Table_23_Shifter.vhdl Branch_History_Table_23.vhdl Branch_History_Table_24_Pack.vhdl Branch_History_Table_24_RegisterFile_Pack.vhdl Branch_History_Table_24_RegisterFile.vhdl Branch_History_Table_24_Shifter_Pack.vhdl Branch_History_Table_24_Shifter.vhdl Branch_History_Table_24.vhdl Branch_History_Table_25_Pack.vhdl Branch_History_Table_25_RegisterFile_Pack.vhdl Branch_History_Table_25_RegisterFile.vhdl Branch_History_Table_25_Shifter_Pack.vhdl Branch_History_Table_25_Shifter.vhdl Branch_History_Table_25.vhdl Branch_History_Table_26_Pack.vhdl Branch_History_Table_26_RegisterFile_Pack.vhdl Branch_History_Table_26_RegisterFile.vhdl Branch_History_Table_26_Shifter_Pack.vhdl Branch_History_Table_26_Shifter.vhdl Branch_History_Table_26.vhdl Branch_History_Table_27_Pack.vhdl Branch_History_Table_27_RegisterFile_Pack.vhdl Branch_History_Table_27_RegisterFile.vhdl Branch_History_Table_27_Shifter_Pack.vhdl Branch_History_Table_27_Shifter.vhdl Branch_History_Table_27.vhdl Branch_History_Table_28_Pack.vhdl Branch_History_Table_28_RegisterFile_Pack.vhdl Branch_History_Table_28_RegisterFile.vhdl Branch_History_Table_28_Shifter_Pack.vhdl Branch_History_Table_28_Shifter.vhdl Branch_History_Table_28.vhdl Branch_History_Table_29_Pack.vhdl Branch_History_Table_29_RegisterFile_Pack.vhdl Branch_History_Table_29_RegisterFile.vhdl Branch_History_Table_29_Shifter_Pack.vhdl Branch_History_Table_29_Shifter.vhdl Branch_History_Table_29.vhdl Branch_History_Table_2_Pack.vhdl Branch_History_Table_2_RegisterFile_Pack.vhdl Branch_History_Table_2_RegisterFile.vhdl Branch_History_Table_2_Shifter_Pack.vhdl Branch_History_Table_2_Shifter.vhdl Branch_History_Table_2.vhdl116 117 # Branch_History_Table_30118 target_dep all Branch_History_Table_30.ngc119 target_dep Branch_History_Table_30.ngc Branch_History_Table_30.prj120 target_dep Branch_History_Table_30.prj Branch_History_Table_30_Pack.vhdl Branch_History_Table_30_RegisterFile_Pack.vhdl Branch_History_Table_30_RegisterFile.vhdl Branch_History_Table_30_Shifter_Pack.vhdl Branch_History_Table_30_Shifter.vhdl Branch_History_Table_30.vhdl121 122 # Branch_History_Table_31123 target_dep all Branch_History_Table_31.ngc124 target_dep Branch_History_Table_31.ngc Branch_History_Table_31.prj125 target_dep Branch_History_Table_31.prj Branch_History_Table_31_Pack.vhdl Branch_History_Table_31_RegisterFile_Pack.vhdl Branch_History_Table_31_RegisterFile.vhdl Branch_History_Table_31_Shifter_Pack.vhdl Branch_History_Table_31_Shifter.vhdl Branch_History_Table_31.vhdl126 127 # Branch_History_Table_32128 target_dep all Branch_History_Table_32.ngc129 target_dep Branch_History_Table_32.ngc Branch_History_Table_32.prj130 target_dep Branch_History_Table_32.prj Branch_History_Table_32_Pack.vhdl Branch_History_Table_32_RegisterFile_Pack.vhdl Branch_History_Table_32_RegisterFile.vhdl Branch_History_Table_32_Shifter_Pack.vhdl Branch_History_Table_32_Shifter.vhdl Branch_History_Table_32.vhdl131 132 # Branch_History_Table_33133 target_dep all Branch_History_Table_33.ngc134 target_dep Branch_History_Table_33.ngc Branch_History_Table_33.prj135 target_dep Branch_History_Table_33.prj Branch_History_Table_33_Pack.vhdl Branch_History_Table_33_RegisterFile_Pack.vhdl Branch_History_Table_33_RegisterFile.vhdl Branch_History_Table_33_Shifter_Pack.vhdl Branch_History_Table_33_Shifter.vhdl Branch_History_Table_33.vhdl136 137 # Branch_History_Table_34138 target_dep all Branch_History_Table_34.ngc139 target_dep Branch_History_Table_34.ngc Branch_History_Table_34.prj140 target_dep Branch_History_Table_34.prj Branch_History_Table_34_Pack.vhdl Branch_History_Table_34_RegisterFile_Pack.vhdl Branch_History_Table_34_RegisterFile.vhdl Branch_History_Table_34_Shifter_Pack.vhdl Branch_History_Table_34_Shifter.vhdl Branch_History_Table_34.vhdl141 142 # Branch_History_Table_35143 target_dep all Branch_History_Table_35.ngc144 target_dep Branch_History_Table_35.ngc Branch_History_Table_35.prj145 target_dep Branch_History_Table_35.prj Branch_History_Table_35_Pack.vhdl Branch_History_Table_35_RegisterFile_Pack.vhdl Branch_History_Table_35_RegisterFile.vhdl Branch_History_Table_35_Shifter_Pack.vhdl Branch_History_Table_35_Shifter.vhdl Branch_History_Table_35.vhdl146 147 # Branch_History_Table_3148 target_dep all Branch_History_Table_3.ngc149 target_dep Branch_History_Table_3.ngc Branch_History_Table_3.prj150 target_dep Branch_History_Table_3.prj Branch_History_Table_30_Pack.vhdl Branch_History_Table_30_RegisterFile_Pack.vhdl Branch_History_Table_30_RegisterFile.vhdl Branch_History_Table_30_Shifter_Pack.vhdl Branch_History_Table_30_Shifter.vhdl Branch_History_Table_30.vhdl Branch_History_Table_31_Pack.vhdl Branch_History_Table_31_RegisterFile_Pack.vhdl Branch_History_Table_31_RegisterFile.vhdl Branch_History_Table_31_Shifter_Pack.vhdl Branch_History_Table_31_Shifter.vhdl Branch_History_Table_31.vhdl Branch_History_Table_32_Pack.vhdl Branch_History_Table_32_RegisterFile_Pack.vhdl Branch_History_Table_32_RegisterFile.vhdl Branch_History_Table_32_Shifter_Pack.vhdl Branch_History_Table_32_Shifter.vhdl Branch_History_Table_32.vhdl Branch_History_Table_33_Pack.vhdl Branch_History_Table_33_RegisterFile_Pack.vhdl Branch_History_Table_33_RegisterFile.vhdl Branch_History_Table_33_Shifter_Pack.vhdl Branch_History_Table_33_Shifter.vhdl Branch_History_Table_33.vhdl Branch_History_Table_34_Pack.vhdl Branch_History_Table_34_RegisterFile_Pack.vhdl Branch_History_Table_34_RegisterFile.vhdl Branch_History_Table_34_Shifter_Pack.vhdl Branch_History_Table_34_Shifter.vhdl Branch_History_Table_34.vhdl Branch_History_Table_35_Pack.vhdl Branch_History_Table_35_RegisterFile_Pack.vhdl Branch_History_Table_35_RegisterFile.vhdl Branch_History_Table_35_Shifter_Pack.vhdl Branch_History_Table_35_Shifter.vhdl Branch_History_Table_35.vhdl Branch_History_Table_3_Pack.vhdl Branch_History_Table_3_RegisterFile_Pack.vhdl Branch_History_Table_3_RegisterFile.vhdl Branch_History_Table_3_Shifter_Pack.vhdl Branch_History_Table_3_Shifter.vhdl Branch_History_Table_3.vhdl151 152 # Branch_History_Table_4153 target_dep all Branch_History_Table_4.ngc154 target_dep Branch_History_Table_4.ngc Branch_History_Table_4.prj155 target_dep Branch_History_Table_4.prj Branch_History_Table_4_Pack.vhdl Branch_History_Table_4_RegisterFile_Pack.vhdl Branch_History_Table_4_RegisterFile.vhdl Branch_History_Table_4_Shifter_Pack.vhdl Branch_History_Table_4_Shifter.vhdl Branch_History_Table_4.vhdl156 157 # Branch_History_Table_5158 target_dep all Branch_History_Table_5.ngc159 target_dep Branch_History_Table_5.ngc Branch_History_Table_5.prj160 target_dep Branch_History_Table_5.prj Branch_History_Table_5_Pack.vhdl Branch_History_Table_5_RegisterFile_Pack.vhdl Branch_History_Table_5_RegisterFile.vhdl Branch_History_Table_5_Shifter_Pack.vhdl Branch_History_Table_5_Shifter.vhdl Branch_History_Table_5.vhdl161 162 # Branch_History_Table_6163 target_dep all Branch_History_Table_6.ngc164 target_dep Branch_History_Table_6.ngc Branch_History_Table_6.prj165 target_dep Branch_History_Table_6.prj Branch_History_Table_6_Pack.vhdl Branch_History_Table_6_RegisterFile_Pack.vhdl Branch_History_Table_6_RegisterFile.vhdl Branch_History_Table_6_Shifter_Pack.vhdl Branch_History_Table_6_Shifter.vhdl Branch_History_Table_6.vhdl166 167 # Branch_History_Table_7168 target_dep all Branch_History_Table_7.ngc169 target_dep Branch_History_Table_7.ngc Branch_History_Table_7.prj170 target_dep Branch_History_Table_7.prj Branch_History_Table_7_Pack.vhdl Branch_History_Table_7_RegisterFile_Pack.vhdl Branch_History_Table_7_RegisterFile.vhdl Branch_History_Table_7_Shifter_Pack.vhdl Branch_History_Table_7_Shifter.vhdl Branch_History_Table_7.vhdl171 172 # Branch_History_Table_8173 target_dep all Branch_History_Table_8.ngc174 target_dep Branch_History_Table_8.ngc Branch_History_Table_8.prj175 target_dep Branch_History_Table_8.prj Branch_History_Table_8_Pack.vhdl Branch_History_Table_8_RegisterFile_Pack.vhdl Branch_History_Table_8_RegisterFile.vhdl Branch_History_Table_8_Shifter_Pack.vhdl Branch_History_Table_8_Shifter.vhdl Branch_History_Table_8.vhdl176 177 # Branch_History_Table_9178 target_dep all Branch_History_Table_9.ngc179 target_dep Branch_History_Table_9.ngc Branch_History_Table_9.prj180 target_dep Branch_History_Table_9.prj Branch_History_Table_9_Pack.vhdl Branch_History_Table_9_RegisterFile_Pack.vhdl Branch_History_Table_9_RegisterFile.vhdl Branch_History_Table_9_Shifter_Pack.vhdl Branch_History_Table_9_Shifter.vhdl Branch_History_Table_9.vhdl181 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/SelfTest/src/test.cpp
r3 r15 46 46 *********************************************************************/ 47 47 sc_clock CLOCK ("clock", 1.0, 0.5); 48 sc_signal<Tcontrol_t> NRESET; 48 49 sc_signal<Tcontrol_t> PREDICT_VAL [param._nb_prediction]; 49 50 sc_signal<Tcontrol_t> PREDICT_ACK [param._nb_prediction]; … … 64 65 65 66 (*(_Branch_History_Table->in_CLOCK)) (CLOCK); 67 (*(_Branch_History_Table->in_NRESET)) (NRESET); 66 68 67 69 for (uint32_t i=0; i<param._nb_prediction; i++) … … 97 99 cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} Initialisation" << endl; 98 100 101 NRESET.write(1); 99 102 for (uint32_t i=0; i<param._nb_prediction; i++) 100 103 PREDICT_VAL [i].write(0); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/include/Branch_History_Table.h
r3 r15 18 18 // Internal structure 19 19 #include "Behavioural/Generic/Shifter/include/Shifter.h" 20 #include "Behavioural/Generic/RegisterFile/include/RegisterFile.h" 21 20 #include "Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/include/RegisterFile_Monolithic.h" 22 21 #include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/include/Parameters.h" 23 22 #include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/include/Types.h" … … 68 67 // Interface 69 68 public : SC_CLOCK * in_CLOCK ; 69 public : SC_IN (Tcontrol_t) * in_NRESET ; 70 70 71 71 public : SC_IN (Tcontrol_t) ** in_PREDICT_VAL ; … … 88 88 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 89 89 public : morpheo::behavioural::generic::shifter::Shifter * component_Shifter ; 90 public : morpheo::behavioural::generic::registerfile:: RegisterFile* component_RegisterFile;90 public : morpheo::behavioural::generic::registerfile::registerfile_monolithic::RegisterFile_Monolithic * component_RegisterFile; 91 91 92 92 // -----[ methods ]--------------------------------------------------- -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/include/Parameters.h
r2 r15 13 13 // Internal structure 14 14 #include "Behavioural/Generic/Shifter/include/Parameters.h" 15 #include "Behavioural/Generic/RegisterFile/ include/Parameters.h"15 #include "Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/include/Parameters.h" 16 16 #include <math.h> 17 17 … … 34 34 35 35 public : morpheo::behavioural::generic::shifter::Parameters * _param_shifter; 36 public : morpheo::behavioural::generic::registerfile:: Parameters * _param_registerfile;36 public : morpheo::behavioural::generic::registerfile::registerfile_monolithic::Parameters * _param_registerfile; 37 37 38 38 //-----[ methods ]----------------------------------------------------------- -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/include/Statistics.h
r2 r15 14 14 #include "Behavioural/include/Parameters_Statistics.h" 15 15 #include "Behavioural/Generic/Shifter/include/Statistics.h" 16 #include "Behavioural/Generic/RegisterFile/ include/Statistics.h"16 #include "Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/include/Statistics.h" 17 17 //#include "Behavioural/Generic/Group/include/Statistics.h" 18 18 #include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/include/Parameters.h" -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table.cpp
r2 r15 56 56 allocation (); 57 57 58 // Constant59 for (uint32_t i=0; i<_param._nb_prediction ; i++)60 PORT_WRITE(out_PREDICT_ACK [i],1);61 for (uint32_t i=0; i<_param._nb_branch_complete; i++)62 PORT_WRITE(out_BRANCH_COMPLETE_ACK [i],1);58 // // Constant 59 // for (uint32_t i=0; i<_param._nb_prediction ; i++) 60 // PORT_WRITE(out_PREDICT_ACK [i],1); 61 // for (uint32_t i=0; i<_param._nb_branch_complete; i++) 62 // PORT_WRITE(out_BRANCH_COMPLETE_ACK [i],1); 63 63 64 64 #if (defined(STATISTICS) || defined (VHDL_TESTBENCH)) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_allocation.cpp
r3 r15 23 23 24 24 in_CLOCK = new SC_CLOCK ("in_CLOCK"); 25 in_NRESET = new SC_IN (Tcontrol_t) ("in_NRESET"); 25 26 26 27 in_PREDICT_VAL = new SC_IN (Tcontrol_t) * [_param._nb_prediction]; … … 102 103 name_component = _name+"_RegisterFile"; 103 104 104 component_RegisterFile = new morpheo::behavioural::generic::registerfile:: RegisterFile(name_component.c_str(),105 component_RegisterFile = new morpheo::behavioural::generic::registerfile::registerfile_monolithic::RegisterFile_Monolithic(name_component.c_str(), 105 106 #ifdef STATISTICS 106 107 _param_statistics , … … 109 110 110 111 // Instantiation 111 (*(component_RegisterFile->in_CLOCK)) (*(in_CLOCK)); 112 (*(component_RegisterFile->in_CLOCK )) (*(in_CLOCK )); 113 (*(component_RegisterFile->in_NRESET)) (*(in_NRESET)); 112 114 113 115 for (uint32_t i=0; i<_param._nb_prediction; i++) 114 116 { 115 (*(component_RegisterFile-> in_READ_ENABLE [i])) (*( in_PREDICT_VAL [i])); 117 (*(component_RegisterFile-> in_READ_VAL [i])) (*( in_PREDICT_VAL [i])); 118 (*(component_RegisterFile->out_READ_ACK [i])) (*(out_PREDICT_ACK [i])); 116 119 (*(component_RegisterFile-> in_READ_ADDRESS [i])) (*( in_PREDICT_ADDRESS [i])); 117 120 (*(component_RegisterFile->out_READ_DATA [i])) (*(out_PREDICT_HISTORY [i])); … … 120 123 for (uint32_t i=0; i<_param._nb_branch_complete; i++) 121 124 { 122 (*(component_RegisterFile-> in_WRITE_ENABLE [i])) (*( in_BRANCH_COMPLETE_VAL [i])); 125 (*(component_RegisterFile-> in_WRITE_VAL [i])) (*( in_BRANCH_COMPLETE_VAL [i])); 126 (*(component_RegisterFile->out_WRITE_ACK [i])) (*( out_BRANCH_COMPLETE_ACK [i])); 123 127 (*(component_RegisterFile-> in_WRITE_ADDRESS [i])) (*( in_BRANCH_COMPLETE_ADDRESS [i])); 124 128 (*(component_RegisterFile-> in_WRITE_DATA [i])) (*(signal_BRANCH_COMPLETE_HISTORY [i])); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_deallocation.cpp
r3 r15 20 20 { 21 21 delete in_CLOCK; 22 delete in_NRESET; 22 23 23 24 for (uint32_t i=0; i<_param._nb_prediction; i++) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_vhdl_body.cpp
r3 r15 20 20 void Branch_History_Table::vhdl_body (Vhdl & vhdl) 21 21 { 22 vhdl.set_body ("-- Output : always at '1'");23 for (uint32_t i=0; i<_param._nb_branch_complete; i++)24 vhdl.set_body ("out_BRANCH_COMPLETE_ACK_"+toString(i)+" <= '1';");25 for (uint32_t i=0; i<_param._nb_prediction ; i++)26 vhdl.set_body ("out_PREDICT_ACK_"+toString(i)+" <= '1';");27 vhdl.set_body ("");22 // vhdl.set_body ("-- Output : always at '1'"); 23 // for (uint32_t i=0; i<_param._nb_branch_complete; i++) 24 // vhdl.set_body ("out_BRANCH_COMPLETE_ACK_"+toString(i)+" <= '1';"); 25 // for (uint32_t i=0; i<_param._nb_prediction ; i++) 26 // vhdl.set_body ("out_PREDICT_ACK_"+toString(i)+" <= '1';"); 27 // vhdl.set_body (""); 28 28 29 29 list<string> list_port_map; … … 40 40 list_port_map.clear(); 41 41 vhdl.set_body_component_port_map (list_port_map,"in_CLOCK","in_CLOCK"); 42 vhdl.set_body_component_port_map (list_port_map,"in_NRESET","in_NRESET"); 43 42 44 for (uint32_t i=0; i<_param._nb_prediction; i++) 43 45 { 44 vhdl.set_body_component_port_map (list_port_map," in_READ_ENABLE_"+toString(i)+" "," in_PREDICT_VAL_"+toString(i)); 46 vhdl.set_body_component_port_map (list_port_map," in_READ_VAL_"+toString(i)+" "," in_PREDICT_VAL_"+toString(i)); 47 vhdl.set_body_component_port_map (list_port_map,"out_READ_ACK_"+toString(i)+" ","out_PREDICT_ACK_"+toString(i)); 45 48 vhdl.set_body_component_port_map (list_port_map," in_READ_ADDRESS_"+toString(i)+" "," in_PREDICT_ADDRESS_"+toString(i)); 46 49 vhdl.set_body_component_port_map (list_port_map,"out_READ_DATA_"+toString(i)+" ","out_PREDICT_HISTORY_"+toString(i)); … … 49 52 for (uint32_t i=0; i<_param._nb_branch_complete; i++) 50 53 { 51 vhdl.set_body_component_port_map (list_port_map," in_WRITE_ENABLE_"+toString(i)+" "," in_BRANCH_COMPLETE_VAL_"+toString(i)+""); 54 vhdl.set_body_component_port_map (list_port_map," in_WRITE_VAL_"+toString(i)+" "," in_BRANCH_COMPLETE_VAL_"+toString(i)+""); 55 vhdl.set_body_component_port_map (list_port_map,"out_WRITE_ACK_"+toString(i)+" "," out_BRANCH_COMPLETE_ACK_"+toString(i)+""); 52 56 vhdl.set_body_component_port_map (list_port_map," in_WRITE_ADDRESS_"+toString(i)+""," in_BRANCH_COMPLETE_ADDRESS_"+toString(i)); 53 57 vhdl.set_body_component_port_map (list_port_map," in_WRITE_DATA_"+toString(i)+" ","signal_BRANCH_COMPLETE_HISTORY_"+toString(i)); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_vhdl_port.cpp
r3 r15 21 21 { 22 22 vhdl.set_port (" in_CLOCK" , IN, 1); 23 vhdl.set_port (" in_NRESET", IN, 1); 23 24 24 25 for (uint32_t i=0; i<_param._nb_prediction; i++) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_vhdl_testbench_port.cpp
r3 r15 19 19 void Branch_History_Table::vhdl_testbench_port (void) 20 20 { 21 _vhdl_testbench->set_port (" in_NRESET", IN, 1); 21 22 for (uint32_t i=0; i<_param._nb_prediction; i++) 22 23 { -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_vhdl_testbench_transition.cpp
r3 r15 25 25 #endif 26 26 27 _vhdl_testbench->add_input (PORT_READ( in_NRESET)); 28 27 29 for (uint32_t i=0; i<_param._nb_prediction; i++) 28 30 { 29 31 _vhdl_testbench->add_input (PORT_READ( in_PREDICT_VAL [i])); 30 _vhdl_testbench->add_output (PORT_READ( out_PREDICT_ACK[i]));32 _vhdl_testbench->add_output (PORT_READ(component_RegisterFile->out_READ_ACK [i])); 31 33 _vhdl_testbench->add_input (PORT_READ( in_PREDICT_ADDRESS [i])); 32 34 _vhdl_testbench->add_output (PORT_READ(component_RegisterFile->out_READ_DATA [i])); … … 37 39 { 38 40 _vhdl_testbench->add_input (PORT_READ( in_BRANCH_COMPLETE_VAL [i])); 39 _vhdl_testbench->add_output (PORT_READ( out_BRANCH_COMPLETE_ACK[i]));41 _vhdl_testbench->add_output (PORT_READ(component_RegisterFile->out_WRITE_ACK [i])); 40 42 _vhdl_testbench->add_input (PORT_READ( in_BRANCH_COMPLETE_ADDRESS [i])); 41 43 _vhdl_testbench->add_input (PORT_READ( in_BRANCH_COMPLETE_HISTORY [i])); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Parameters.cpp
r2 r15 32 32 morpheo::behavioural::generic::shifter::internal_left_shift, 33 33 morpheo::behavioural::generic::shifter::external_completion), 34 _param_registerfile = new morpheo::behavioural::generic::registerfile:: Parameters (nb_prediction ,35 36 37 34 _param_registerfile = new morpheo::behavioural::generic::registerfile::registerfile_monolithic::Parameters (nb_prediction , 35 nb_branch_complete , 36 nb_shifter , 37 size_shifter ); 38 38 39 39 test(); … … 54 54 true), 55 55 56 _param_registerfile = new morpheo::behavioural::generic::registerfile:: Parameters (param._nb_prediction ,57 58 59 56 _param_registerfile = new morpheo::behavioural::generic::registerfile::registerfile_monolithic::Parameters (param._nb_prediction , 57 param._nb_branch_complete , 58 param._nb_shifter , 59 param._size_shifter ); 60 60 61 61 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/Makefile.deps
r2 r15 14 14 include $(DIR_MORPHEO)/Behavioural/Generic/Counter/Makefile.deps 15 15 endif 16 ifndef RegisterFile 17 include $(DIR_MORPHEO)/Behavioural/Generic/RegisterFile/ Makefile.deps16 ifndef RegisterFile_Monolithic 17 include $(DIR_MORPHEO)/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/Makefile.deps 18 18 endif 19 19 … … 22 22 #-----[ Library ]------------------------------------------ 23 23 Pattern_History_Table_LIBRARY = -lPattern_History_Table \ 24 $(RegisterFile_ LIBRARY) \24 $(RegisterFile_Monolithic_LIBRARY) \ 25 25 $(Counter_LIBRARY) \ 26 26 $(Behavioural_LIBRARY) 27 27 28 28 Pattern_History_Table_DIR_LIBRARY = -L$(DIR_MORPHEO)/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/lib \ 29 $(RegisterFile_ DIR_LIBRARY) \29 $(RegisterFile_Monolithic_DIR_LIBRARY) \ 30 30 $(Counter_DIR_LIBRARY) \ 31 31 $(Behavioural_DIR_LIBRARY) … … 36 36 @$(MAKE) Behavioural_library 37 37 @$(MAKE) Counter_library 38 @$(MAKE) RegisterFile_ library38 @$(MAKE) RegisterFile_Monolithic_library 39 39 @$(MAKE) --directory=$(DIR_MORPHEO)/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table --makefile=Makefile 40 40 … … 42 42 @$(MAKE) Behavioural_library_clean 43 43 @$(MAKE) Counter_library_clean 44 @$(MAKE) RegisterFile_ library_clean44 @$(MAKE) RegisterFile_Monolithic_library_clean 45 45 @$(MAKE) --directory=$(DIR_MORPHEO)/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table --makefile=Makefile clean -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/SelfTest/mkf.info
r2 r15 1 2 # Pattern_History_Table_03 target_dep all Pattern_History_Table_0.ngc4 target_dep Pattern_History_Table_0.ngc Pattern_History_Table_0.prj5 target_dep Pattern_History_Table_0.prj Pattern_History_Table_0_Counter_Pack.vhdl Pattern_History_Table_0_Counter.vhdl Pattern_History_Table_0_Pack.vhdl Pattern_History_Table_0_RegisterFile_Pack.vhdl Pattern_History_Table_0_RegisterFile.vhdl Pattern_History_Table_0.vhdl6 7 # Pattern_History_Table_108 target_dep all Pattern_History_Table_10.ngc9 target_dep Pattern_History_Table_10.ngc Pattern_History_Table_10.prj10 target_dep Pattern_History_Table_10.prj Pattern_History_Table_10_Counter_Pack.vhdl Pattern_History_Table_10_Counter.vhdl Pattern_History_Table_10_Pack.vhdl Pattern_History_Table_10_RegisterFile_Pack.vhdl Pattern_History_Table_10_RegisterFile.vhdl Pattern_History_Table_10.vhdl11 12 # Pattern_History_Table_1113 target_dep all Pattern_History_Table_11.ngc14 target_dep Pattern_History_Table_11.ngc Pattern_History_Table_11.prj15 target_dep Pattern_History_Table_11.prj Pattern_History_Table_11_Counter_Pack.vhdl Pattern_History_Table_11_Counter.vhdl Pattern_History_Table_11_Pack.vhdl Pattern_History_Table_11_RegisterFile_Pack.vhdl Pattern_History_Table_11_RegisterFile.vhdl Pattern_History_Table_11.vhdl16 17 # Pattern_History_Table_1218 target_dep all Pattern_History_Table_12.ngc19 target_dep Pattern_History_Table_12.ngc Pattern_History_Table_12.prj20 target_dep Pattern_History_Table_12.prj Pattern_History_Table_12_Counter_Pack.vhdl Pattern_History_Table_12_Counter.vhdl Pattern_History_Table_12_Pack.vhdl Pattern_History_Table_12_RegisterFile_Pack.vhdl Pattern_History_Table_12_RegisterFile.vhdl Pattern_History_Table_12.vhdl21 22 # Pattern_History_Table_1323 target_dep all Pattern_History_Table_13.ngc24 target_dep Pattern_History_Table_13.ngc Pattern_History_Table_13.prj25 target_dep Pattern_History_Table_13.prj Pattern_History_Table_13_Counter_Pack.vhdl Pattern_History_Table_13_Counter.vhdl Pattern_History_Table_13_Pack.vhdl Pattern_History_Table_13_RegisterFile_Pack.vhdl Pattern_History_Table_13_RegisterFile.vhdl Pattern_History_Table_13.vhdl26 27 # Pattern_History_Table_1428 target_dep all Pattern_History_Table_14.ngc29 target_dep Pattern_History_Table_14.ngc Pattern_History_Table_14.prj30 target_dep Pattern_History_Table_14.prj Pattern_History_Table_14_Counter_Pack.vhdl Pattern_History_Table_14_Counter.vhdl Pattern_History_Table_14_Pack.vhdl Pattern_History_Table_14_RegisterFile_Pack.vhdl Pattern_History_Table_14_RegisterFile.vhdl Pattern_History_Table_14.vhdl31 32 # Pattern_History_Table_1533 target_dep all Pattern_History_Table_15.ngc34 target_dep Pattern_History_Table_15.ngc Pattern_History_Table_15.prj35 target_dep Pattern_History_Table_15.prj Pattern_History_Table_15_Counter_Pack.vhdl Pattern_History_Table_15_Counter.vhdl Pattern_History_Table_15_Pack.vhdl Pattern_History_Table_15_RegisterFile_Pack.vhdl Pattern_History_Table_15_RegisterFile.vhdl Pattern_History_Table_15.vhdl36 37 # Pattern_History_Table_1638 target_dep all Pattern_History_Table_16.ngc39 target_dep Pattern_History_Table_16.ngc Pattern_History_Table_16.prj40 target_dep Pattern_History_Table_16.prj Pattern_History_Table_16_Counter_Pack.vhdl Pattern_History_Table_16_Counter.vhdl Pattern_History_Table_16_Pack.vhdl Pattern_History_Table_16_RegisterFile_Pack.vhdl Pattern_History_Table_16_RegisterFile.vhdl Pattern_History_Table_16.vhdl41 42 # Pattern_History_Table_1743 target_dep all Pattern_History_Table_17.ngc44 target_dep Pattern_History_Table_17.ngc Pattern_History_Table_17.prj45 target_dep Pattern_History_Table_17.prj Pattern_History_Table_17_Counter_Pack.vhdl Pattern_History_Table_17_Counter.vhdl Pattern_History_Table_17_Pack.vhdl Pattern_History_Table_17_RegisterFile_Pack.vhdl Pattern_History_Table_17_RegisterFile.vhdl Pattern_History_Table_17.vhdl46 47 # Pattern_History_Table_1848 target_dep all Pattern_History_Table_18.ngc49 target_dep Pattern_History_Table_18.ngc Pattern_History_Table_18.prj50 target_dep Pattern_History_Table_18.prj Pattern_History_Table_18_Counter_Pack.vhdl Pattern_History_Table_18_Counter.vhdl Pattern_History_Table_18_Pack.vhdl Pattern_History_Table_18_RegisterFile_Pack.vhdl Pattern_History_Table_18_RegisterFile.vhdl Pattern_History_Table_18.vhdl51 52 # Pattern_History_Table_1953 target_dep all Pattern_History_Table_19.ngc54 target_dep Pattern_History_Table_19.ngc Pattern_History_Table_19.prj55 target_dep Pattern_History_Table_19.prj Pattern_History_Table_19_Counter_Pack.vhdl Pattern_History_Table_19_Counter.vhdl Pattern_History_Table_19_Pack.vhdl Pattern_History_Table_19_RegisterFile_Pack.vhdl Pattern_History_Table_19_RegisterFile.vhdl Pattern_History_Table_19.vhdl56 57 # Pattern_History_Table_158 target_dep all Pattern_History_Table_1.ngc59 target_dep Pattern_History_Table_1.ngc Pattern_History_Table_1.prj60 target_dep Pattern_History_Table_1.prj Pattern_History_Table_10_Counter_Pack.vhdl Pattern_History_Table_10_Counter.vhdl Pattern_History_Table_10_Pack.vhdl Pattern_History_Table_10_RegisterFile_Pack.vhdl Pattern_History_Table_10_RegisterFile.vhdl Pattern_History_Table_10.vhdl Pattern_History_Table_11_Counter_Pack.vhdl Pattern_History_Table_11_Counter.vhdl Pattern_History_Table_11_Pack.vhdl Pattern_History_Table_11_RegisterFile_Pack.vhdl Pattern_History_Table_11_RegisterFile.vhdl Pattern_History_Table_11.vhdl Pattern_History_Table_12_Counter_Pack.vhdl Pattern_History_Table_12_Counter.vhdl Pattern_History_Table_12_Pack.vhdl Pattern_History_Table_12_RegisterFile_Pack.vhdl Pattern_History_Table_12_RegisterFile.vhdl Pattern_History_Table_12.vhdl Pattern_History_Table_13_Counter_Pack.vhdl Pattern_History_Table_13_Counter.vhdl Pattern_History_Table_13_Pack.vhdl Pattern_History_Table_13_RegisterFile_Pack.vhdl Pattern_History_Table_13_RegisterFile.vhdl Pattern_History_Table_13.vhdl Pattern_History_Table_14_Counter_Pack.vhdl Pattern_History_Table_14_Counter.vhdl Pattern_History_Table_14_Pack.vhdl Pattern_History_Table_14_RegisterFile_Pack.vhdl Pattern_History_Table_14_RegisterFile.vhdl Pattern_History_Table_14.vhdl Pattern_History_Table_15_Counter_Pack.vhdl Pattern_History_Table_15_Counter.vhdl Pattern_History_Table_15_Pack.vhdl Pattern_History_Table_15_RegisterFile_Pack.vhdl Pattern_History_Table_15_RegisterFile.vhdl Pattern_History_Table_15.vhdl Pattern_History_Table_16_Counter_Pack.vhdl Pattern_History_Table_16_Counter.vhdl Pattern_History_Table_16_Pack.vhdl Pattern_History_Table_16_RegisterFile_Pack.vhdl Pattern_History_Table_16_RegisterFile.vhdl Pattern_History_Table_16.vhdl Pattern_History_Table_17_Counter_Pack.vhdl Pattern_History_Table_17_Counter.vhdl Pattern_History_Table_17_Pack.vhdl Pattern_History_Table_17_RegisterFile_Pack.vhdl Pattern_History_Table_17_RegisterFile.vhdl Pattern_History_Table_17.vhdl Pattern_History_Table_18_Counter_Pack.vhdl Pattern_History_Table_18_Counter.vhdl Pattern_History_Table_18_Pack.vhdl Pattern_History_Table_18_RegisterFile_Pack.vhdl Pattern_History_Table_18_RegisterFile.vhdl Pattern_History_Table_18.vhdl Pattern_History_Table_19_Counter_Pack.vhdl Pattern_History_Table_19_Counter.vhdl Pattern_History_Table_19_Pack.vhdl Pattern_History_Table_19_RegisterFile_Pack.vhdl Pattern_History_Table_19_RegisterFile.vhdl Pattern_History_Table_19.vhdl Pattern_History_Table_1_Counter_Pack.vhdl Pattern_History_Table_1_Counter.vhdl Pattern_History_Table_1_Pack.vhdl Pattern_History_Table_1_RegisterFile_Pack.vhdl Pattern_History_Table_1_RegisterFile.vhdl Pattern_History_Table_1.vhdl61 62 # Pattern_History_Table_2063 target_dep all Pattern_History_Table_20.ngc64 target_dep Pattern_History_Table_20.ngc Pattern_History_Table_20.prj65 target_dep Pattern_History_Table_20.prj Pattern_History_Table_20_Counter_Pack.vhdl Pattern_History_Table_20_Counter.vhdl Pattern_History_Table_20_Pack.vhdl Pattern_History_Table_20_RegisterFile_Pack.vhdl Pattern_History_Table_20_RegisterFile.vhdl Pattern_History_Table_20.vhdl66 67 # Pattern_History_Table_2168 target_dep all Pattern_History_Table_21.ngc69 target_dep Pattern_History_Table_21.ngc Pattern_History_Table_21.prj70 target_dep Pattern_History_Table_21.prj Pattern_History_Table_21_Counter_Pack.vhdl Pattern_History_Table_21_Counter.vhdl Pattern_History_Table_21_Pack.vhdl Pattern_History_Table_21_RegisterFile_Pack.vhdl Pattern_History_Table_21_RegisterFile.vhdl Pattern_History_Table_21.vhdl71 72 # Pattern_History_Table_2273 target_dep all Pattern_History_Table_22.ngc74 target_dep Pattern_History_Table_22.ngc Pattern_History_Table_22.prj75 target_dep Pattern_History_Table_22.prj Pattern_History_Table_22_Counter_Pack.vhdl Pattern_History_Table_22_Counter.vhdl Pattern_History_Table_22_Pack.vhdl Pattern_History_Table_22_RegisterFile_Pack.vhdl Pattern_History_Table_22_RegisterFile.vhdl Pattern_History_Table_22.vhdl76 77 # Pattern_History_Table_2378 target_dep all Pattern_History_Table_23.ngc79 target_dep Pattern_History_Table_23.ngc Pattern_History_Table_23.prj80 target_dep Pattern_History_Table_23.prj Pattern_History_Table_23_Counter_Pack.vhdl Pattern_History_Table_23_Counter.vhdl Pattern_History_Table_23_Pack.vhdl Pattern_History_Table_23_RegisterFile_Pack.vhdl Pattern_History_Table_23_RegisterFile.vhdl Pattern_History_Table_23.vhdl81 82 # Pattern_History_Table_2483 target_dep all Pattern_History_Table_24.ngc84 target_dep Pattern_History_Table_24.ngc Pattern_History_Table_24.prj85 target_dep Pattern_History_Table_24.prj Pattern_History_Table_24_Counter_Pack.vhdl Pattern_History_Table_24_Counter.vhdl Pattern_History_Table_24_Pack.vhdl Pattern_History_Table_24_RegisterFile_Pack.vhdl Pattern_History_Table_24_RegisterFile.vhdl Pattern_History_Table_24.vhdl86 87 # Pattern_History_Table_2588 target_dep all Pattern_History_Table_25.ngc89 target_dep Pattern_History_Table_25.ngc Pattern_History_Table_25.prj90 target_dep Pattern_History_Table_25.prj Pattern_History_Table_25_Counter_Pack.vhdl Pattern_History_Table_25_Counter.vhdl Pattern_History_Table_25_Pack.vhdl Pattern_History_Table_25_RegisterFile_Pack.vhdl Pattern_History_Table_25_RegisterFile.vhdl Pattern_History_Table_25.vhdl91 92 # Pattern_History_Table_2693 target_dep all Pattern_History_Table_26.ngc94 target_dep Pattern_History_Table_26.ngc Pattern_History_Table_26.prj95 target_dep Pattern_History_Table_26.prj Pattern_History_Table_26_Counter_Pack.vhdl Pattern_History_Table_26_Counter.vhdl Pattern_History_Table_26_Pack.vhdl Pattern_History_Table_26_RegisterFile_Pack.vhdl Pattern_History_Table_26_RegisterFile.vhdl Pattern_History_Table_26.vhdl96 97 # Pattern_History_Table_2798 target_dep all Pattern_History_Table_27.ngc99 target_dep Pattern_History_Table_27.ngc Pattern_History_Table_27.prj100 target_dep Pattern_History_Table_27.prj Pattern_History_Table_27_Counter_Pack.vhdl Pattern_History_Table_27_Counter.vhdl Pattern_History_Table_27_Pack.vhdl Pattern_History_Table_27_RegisterFile_Pack.vhdl Pattern_History_Table_27_RegisterFile.vhdl Pattern_History_Table_27.vhdl101 102 # Pattern_History_Table_28103 target_dep all Pattern_History_Table_28.ngc104 target_dep Pattern_History_Table_28.ngc Pattern_History_Table_28.prj105 target_dep Pattern_History_Table_28.prj Pattern_History_Table_28_Counter_Pack.vhdl Pattern_History_Table_28_Counter.vhdl Pattern_History_Table_28_Pack.vhdl Pattern_History_Table_28_RegisterFile_Pack.vhdl Pattern_History_Table_28_RegisterFile.vhdl Pattern_History_Table_28.vhdl106 107 # Pattern_History_Table_29108 target_dep all Pattern_History_Table_29.ngc109 target_dep Pattern_History_Table_29.ngc Pattern_History_Table_29.prj110 target_dep Pattern_History_Table_29.prj Pattern_History_Table_29_Counter_Pack.vhdl Pattern_History_Table_29_Counter.vhdl Pattern_History_Table_29_Pack.vhdl Pattern_History_Table_29_RegisterFile_Pack.vhdl Pattern_History_Table_29_RegisterFile.vhdl Pattern_History_Table_29.vhdl111 112 # Pattern_History_Table_2113 target_dep all Pattern_History_Table_2.ngc114 target_dep Pattern_History_Table_2.ngc Pattern_History_Table_2.prj115 target_dep Pattern_History_Table_2.prj Pattern_History_Table_20_Counter_Pack.vhdl Pattern_History_Table_20_Counter.vhdl Pattern_History_Table_20_Pack.vhdl Pattern_History_Table_20_RegisterFile_Pack.vhdl Pattern_History_Table_20_RegisterFile.vhdl Pattern_History_Table_20.vhdl Pattern_History_Table_21_Counter_Pack.vhdl Pattern_History_Table_21_Counter.vhdl Pattern_History_Table_21_Pack.vhdl Pattern_History_Table_21_RegisterFile_Pack.vhdl Pattern_History_Table_21_RegisterFile.vhdl Pattern_History_Table_21.vhdl Pattern_History_Table_22_Counter_Pack.vhdl Pattern_History_Table_22_Counter.vhdl Pattern_History_Table_22_Pack.vhdl Pattern_History_Table_22_RegisterFile_Pack.vhdl Pattern_History_Table_22_RegisterFile.vhdl Pattern_History_Table_22.vhdl Pattern_History_Table_23_Counter_Pack.vhdl Pattern_History_Table_23_Counter.vhdl Pattern_History_Table_23_Pack.vhdl Pattern_History_Table_23_RegisterFile_Pack.vhdl Pattern_History_Table_23_RegisterFile.vhdl Pattern_History_Table_23.vhdl Pattern_History_Table_24_Counter_Pack.vhdl Pattern_History_Table_24_Counter.vhdl Pattern_History_Table_24_Pack.vhdl Pattern_History_Table_24_RegisterFile_Pack.vhdl Pattern_History_Table_24_RegisterFile.vhdl Pattern_History_Table_24.vhdl Pattern_History_Table_25_Counter_Pack.vhdl Pattern_History_Table_25_Counter.vhdl Pattern_History_Table_25_Pack.vhdl Pattern_History_Table_25_RegisterFile_Pack.vhdl Pattern_History_Table_25_RegisterFile.vhdl Pattern_History_Table_25.vhdl Pattern_History_Table_26_Counter_Pack.vhdl Pattern_History_Table_26_Counter.vhdl Pattern_History_Table_26_Pack.vhdl Pattern_History_Table_26_RegisterFile_Pack.vhdl Pattern_History_Table_26_RegisterFile.vhdl Pattern_History_Table_26.vhdl Pattern_History_Table_27_Counter_Pack.vhdl Pattern_History_Table_27_Counter.vhdl Pattern_History_Table_27_Pack.vhdl Pattern_History_Table_27_RegisterFile_Pack.vhdl Pattern_History_Table_27_RegisterFile.vhdl Pattern_History_Table_27.vhdl Pattern_History_Table_28_Counter_Pack.vhdl Pattern_History_Table_28_Counter.vhdl Pattern_History_Table_28_Pack.vhdl Pattern_History_Table_28_RegisterFile_Pack.vhdl Pattern_History_Table_28_RegisterFile.vhdl Pattern_History_Table_28.vhdl Pattern_History_Table_29_Counter_Pack.vhdl Pattern_History_Table_29_Counter.vhdl Pattern_History_Table_29_Pack.vhdl Pattern_History_Table_29_RegisterFile_Pack.vhdl Pattern_History_Table_29_RegisterFile.vhdl Pattern_History_Table_29.vhdl Pattern_History_Table_2_Counter_Pack.vhdl Pattern_History_Table_2_Counter.vhdl Pattern_History_Table_2_Pack.vhdl Pattern_History_Table_2_RegisterFile_Pack.vhdl Pattern_History_Table_2_RegisterFile.vhdl Pattern_History_Table_2.vhdl116 117 # Pattern_History_Table_30118 target_dep all Pattern_History_Table_30.ngc119 target_dep Pattern_History_Table_30.ngc Pattern_History_Table_30.prj120 target_dep Pattern_History_Table_30.prj Pattern_History_Table_30_Counter_Pack.vhdl Pattern_History_Table_30_Counter.vhdl Pattern_History_Table_30_Pack.vhdl Pattern_History_Table_30_RegisterFile_Pack.vhdl Pattern_History_Table_30_RegisterFile.vhdl Pattern_History_Table_30.vhdl121 122 # Pattern_History_Table_31123 target_dep all Pattern_History_Table_31.ngc124 target_dep Pattern_History_Table_31.ngc Pattern_History_Table_31.prj125 target_dep Pattern_History_Table_31.prj Pattern_History_Table_31_Counter_Pack.vhdl Pattern_History_Table_31_Counter.vhdl Pattern_History_Table_31_Pack.vhdl Pattern_History_Table_31_RegisterFile_Pack.vhdl Pattern_History_Table_31_RegisterFile.vhdl Pattern_History_Table_31.vhdl126 127 # Pattern_History_Table_32128 target_dep all Pattern_History_Table_32.ngc129 target_dep Pattern_History_Table_32.ngc Pattern_History_Table_32.prj130 target_dep Pattern_History_Table_32.prj Pattern_History_Table_32_Counter_Pack.vhdl Pattern_History_Table_32_Counter.vhdl Pattern_History_Table_32_Pack.vhdl Pattern_History_Table_32_RegisterFile_Pack.vhdl Pattern_History_Table_32_RegisterFile.vhdl Pattern_History_Table_32.vhdl131 132 # Pattern_History_Table_33133 target_dep all Pattern_History_Table_33.ngc134 target_dep Pattern_History_Table_33.ngc Pattern_History_Table_33.prj135 target_dep Pattern_History_Table_33.prj Pattern_History_Table_33_Counter_Pack.vhdl Pattern_History_Table_33_Counter.vhdl Pattern_History_Table_33_Pack.vhdl Pattern_History_Table_33_RegisterFile_Pack.vhdl Pattern_History_Table_33_RegisterFile.vhdl Pattern_History_Table_33.vhdl136 137 # Pattern_History_Table_34138 target_dep all Pattern_History_Table_34.ngc139 target_dep Pattern_History_Table_34.ngc Pattern_History_Table_34.prj140 target_dep Pattern_History_Table_34.prj Pattern_History_Table_34_Counter_Pack.vhdl Pattern_History_Table_34_Counter.vhdl Pattern_History_Table_34_Pack.vhdl Pattern_History_Table_34_RegisterFile_Pack.vhdl Pattern_History_Table_34_RegisterFile.vhdl Pattern_History_Table_34.vhdl141 142 # Pattern_History_Table_35143 target_dep all Pattern_History_Table_35.ngc144 target_dep Pattern_History_Table_35.ngc Pattern_History_Table_35.prj145 target_dep Pattern_History_Table_35.prj Pattern_History_Table_35_Counter_Pack.vhdl Pattern_History_Table_35_Counter.vhdl Pattern_History_Table_35_Pack.vhdl Pattern_History_Table_35_RegisterFile_Pack.vhdl Pattern_History_Table_35_RegisterFile.vhdl Pattern_History_Table_35.vhdl146 147 # Pattern_History_Table_3148 target_dep all Pattern_History_Table_3.ngc149 target_dep Pattern_History_Table_3.ngc Pattern_History_Table_3.prj150 target_dep Pattern_History_Table_3.prj Pattern_History_Table_30_Counter_Pack.vhdl Pattern_History_Table_30_Counter.vhdl Pattern_History_Table_30_Pack.vhdl Pattern_History_Table_30_RegisterFile_Pack.vhdl Pattern_History_Table_30_RegisterFile.vhdl Pattern_History_Table_30.vhdl Pattern_History_Table_31_Counter_Pack.vhdl Pattern_History_Table_31_Counter.vhdl Pattern_History_Table_31_Pack.vhdl Pattern_History_Table_31_RegisterFile_Pack.vhdl Pattern_History_Table_31_RegisterFile.vhdl Pattern_History_Table_31.vhdl Pattern_History_Table_32_Counter_Pack.vhdl Pattern_History_Table_32_Counter.vhdl Pattern_History_Table_32_Pack.vhdl Pattern_History_Table_32_RegisterFile_Pack.vhdl Pattern_History_Table_32_RegisterFile.vhdl Pattern_History_Table_32.vhdl Pattern_History_Table_33_Counter_Pack.vhdl Pattern_History_Table_33_Counter.vhdl Pattern_History_Table_33_Pack.vhdl Pattern_History_Table_33_RegisterFile_Pack.vhdl Pattern_History_Table_33_RegisterFile.vhdl Pattern_History_Table_33.vhdl Pattern_History_Table_34_Counter_Pack.vhdl Pattern_History_Table_34_Counter.vhdl Pattern_History_Table_34_Pack.vhdl Pattern_History_Table_34_RegisterFile_Pack.vhdl Pattern_History_Table_34_RegisterFile.vhdl Pattern_History_Table_34.vhdl Pattern_History_Table_35_Counter_Pack.vhdl Pattern_History_Table_35_Counter.vhdl Pattern_History_Table_35_Pack.vhdl Pattern_History_Table_35_RegisterFile_Pack.vhdl Pattern_History_Table_35_RegisterFile.vhdl Pattern_History_Table_35.vhdl Pattern_History_Table_3_Counter_Pack.vhdl Pattern_History_Table_3_Counter.vhdl Pattern_History_Table_3_Pack.vhdl Pattern_History_Table_3_RegisterFile_Pack.vhdl Pattern_History_Table_3_RegisterFile.vhdl Pattern_History_Table_3.vhdl151 152 # Pattern_History_Table_4153 target_dep all Pattern_History_Table_4.ngc154 target_dep Pattern_History_Table_4.ngc Pattern_History_Table_4.prj155 target_dep Pattern_History_Table_4.prj Pattern_History_Table_4_Counter_Pack.vhdl Pattern_History_Table_4_Counter.vhdl Pattern_History_Table_4_Pack.vhdl Pattern_History_Table_4_RegisterFile_Pack.vhdl Pattern_History_Table_4_RegisterFile.vhdl Pattern_History_Table_4.vhdl156 157 # Pattern_History_Table_5158 target_dep all Pattern_History_Table_5.ngc159 target_dep Pattern_History_Table_5.ngc Pattern_History_Table_5.prj160 target_dep Pattern_History_Table_5.prj Pattern_History_Table_5_Counter_Pack.vhdl Pattern_History_Table_5_Counter.vhdl Pattern_History_Table_5_Pack.vhdl Pattern_History_Table_5_RegisterFile_Pack.vhdl Pattern_History_Table_5_RegisterFile.vhdl Pattern_History_Table_5.vhdl161 162 # Pattern_History_Table_6163 target_dep all Pattern_History_Table_6.ngc164 target_dep Pattern_History_Table_6.ngc Pattern_History_Table_6.prj165 target_dep Pattern_History_Table_6.prj Pattern_History_Table_6_Counter_Pack.vhdl Pattern_History_Table_6_Counter.vhdl Pattern_History_Table_6_Pack.vhdl Pattern_History_Table_6_RegisterFile_Pack.vhdl Pattern_History_Table_6_RegisterFile.vhdl Pattern_History_Table_6.vhdl166 167 # Pattern_History_Table_7168 target_dep all Pattern_History_Table_7.ngc169 target_dep Pattern_History_Table_7.ngc Pattern_History_Table_7.prj170 target_dep Pattern_History_Table_7.prj Pattern_History_Table_7_Counter_Pack.vhdl Pattern_History_Table_7_Counter.vhdl Pattern_History_Table_7_Pack.vhdl Pattern_History_Table_7_RegisterFile_Pack.vhdl Pattern_History_Table_7_RegisterFile.vhdl Pattern_History_Table_7.vhdl171 172 # Pattern_History_Table_8173 target_dep all Pattern_History_Table_8.ngc174 target_dep Pattern_History_Table_8.ngc Pattern_History_Table_8.prj175 target_dep Pattern_History_Table_8.prj Pattern_History_Table_8_Counter_Pack.vhdl Pattern_History_Table_8_Counter.vhdl Pattern_History_Table_8_Pack.vhdl Pattern_History_Table_8_RegisterFile_Pack.vhdl Pattern_History_Table_8_RegisterFile.vhdl Pattern_History_Table_8.vhdl176 177 # Pattern_History_Table_9178 target_dep all Pattern_History_Table_9.ngc179 target_dep Pattern_History_Table_9.ngc Pattern_History_Table_9.prj180 target_dep Pattern_History_Table_9.prj Pattern_History_Table_9_Counter_Pack.vhdl Pattern_History_Table_9_Counter.vhdl Pattern_History_Table_9_Pack.vhdl Pattern_History_Table_9_RegisterFile_Pack.vhdl Pattern_History_Table_9_RegisterFile.vhdl Pattern_History_Table_9.vhdl181 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/SelfTest/src/test.cpp
r3 r15 43 43 *********************************************************************/ 44 44 sc_clock CLOCK ("clock", 1.0, 0.5); 45 sc_signal<Tcontrol_t> NRESET; 46 45 47 sc_signal<Tcontrol_t> PREDICT_VAL [param._nb_prediction]; 46 48 sc_signal<Tcontrol_t> PREDICT_ACK [param._nb_prediction]; … … 61 63 62 64 (*(_Pattern_History_Table->in_CLOCK)) (CLOCK); 65 (*(_Pattern_History_Table->in_NRESET)) (NRESET); 63 66 64 67 for (uint32_t i=0; i<param._nb_prediction; i++) … … 92 95 _Pattern_History_Table->vhdl_testbench_label("Initialisation"); 93 96 cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} Initialisation" << endl; 94 97 98 NRESET.write(1); 95 99 96 100 for (uint32_t i=0; i<param._nb_prediction; i++) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/include/Parameters.h
r2 r15 13 13 // Internal structure 14 14 #include "Behavioural/Generic/Counter/include/Parameters.h" 15 #include "Behavioural/Generic/RegisterFile/ include/Parameters.h"15 #include "Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/include/Parameters.h" 16 16 #include <math.h> 17 17 … … 34 34 35 35 public : morpheo::behavioural::generic::counter::Parameters * _param_counter; 36 public : morpheo::behavioural::generic::registerfile:: Parameters * _param_registerfile;36 public : morpheo::behavioural::generic::registerfile::registerfile_monolithic::Parameters * _param_registerfile; 37 37 38 38 //-----[ methods ]----------------------------------------------------------- -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/include/Pattern_History_Table.h
r3 r15 19 19 // Internal structure 20 20 #include "Behavioural/Generic/Counter/include/Counter.h" 21 #include "Behavioural/Generic/RegisterFile/ include/RegisterFile.h"21 #include "Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/include/RegisterFile_Monolithic.h" 22 22 23 23 #include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/include/Parameters.h" … … 70 70 // Interface 71 71 public : SC_CLOCK * in_CLOCK ; 72 public : SC_IN (Tcontrol_t) * in_NRESET ; 72 73 73 74 public : SC_IN (Tcontrol_t) ** in_PREDICT_VAL ; … … 90 91 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 91 92 public : morpheo::behavioural::generic::counter::Counter * component_Counter ; 92 public : morpheo::behavioural::generic::registerfile:: RegisterFile* component_RegisterFile;93 public : morpheo::behavioural::generic::registerfile::registerfile_monolithic::RegisterFile_Monolithic * component_RegisterFile; 93 94 94 95 // -----[ methods ]--------------------------------------------------- -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/include/Statistics.h
r2 r15 14 14 #include "Behavioural/include/Parameters_Statistics.h" 15 15 #include "Behavioural/Generic/Counter/include/Statistics.h" 16 #include "Behavioural/Generic/RegisterFile/ include/Statistics.h"16 #include "Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/include/Statistics.h" 17 17 //#include "Behavioural/Generic/Group/include/Statistics.h" 18 18 #include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/include/Parameters.h" -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Parameters.cpp
r2 r15 30 30 _param_counter = new morpheo::behavioural::generic::counter::Parameters (size_counter , 31 31 nb_branch_complete ); 32 _param_registerfile = new morpheo::behavioural::generic::registerfile:: Parameters (nb_prediction ,33 34 35 32 _param_registerfile = new morpheo::behavioural::generic::registerfile::registerfile_monolithic::Parameters (nb_prediction , 33 nb_branch_complete , 34 nb_counter , 35 size_counter ); 36 36 37 37 … … 51 51 param._nb_branch_complete ); 52 52 53 _param_registerfile = new morpheo::behavioural::generic::registerfile:: Parameters (param._nb_prediction ,54 55 56 57 53 _param_registerfile = new morpheo::behavioural::generic::registerfile::registerfile_monolithic::Parameters (param._nb_prediction , 54 param._nb_branch_complete , 55 param._nb_counter , 56 param._size_counter ); 57 58 58 test(); 59 59 log_printf(FUNC,Pattern_History_Table,"Parameters","End"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table.cpp
r2 r15 58 58 allocation (); 59 59 60 // Constant61 for (uint32_t i=0; i<_param._nb_prediction ; i++)62 PORT_WRITE(out_PREDICT_ACK [i],1);63 for (uint32_t i=0; i<_param._nb_branch_complete; i++)64 PORT_WRITE(out_BRANCH_COMPLETE_ACK [i],1);60 // // Constant 61 // for (uint32_t i=0; i<_param._nb_prediction ; i++) 62 // PORT_WRITE(out_PREDICT_ACK [i],1); 63 // for (uint32_t i=0; i<_param._nb_branch_complete; i++) 64 // PORT_WRITE(out_BRANCH_COMPLETE_ACK [i],1); 65 65 66 66 #if (defined(STATISTICS) || defined (VHDL_TESTBENCH)) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_allocation.cpp
r3 r15 25 25 26 26 in_CLOCK = new SC_CLOCK ("in_CLOCK"); 27 in_NRESET = new SC_IN (Tcontrol_t) ("in_NRESET"); 27 28 28 29 in_PREDICT_VAL = new SC_IN (Tcontrol_t) * [_param._nb_prediction]; … … 104 105 name_component = _name+"_RegisterFile"; 105 106 106 component_RegisterFile = new morpheo::behavioural::generic::registerfile:: RegisterFile(name_component.c_str(),107 component_RegisterFile = new morpheo::behavioural::generic::registerfile::registerfile_monolithic::RegisterFile_Monolithic (name_component.c_str(), 107 108 #ifdef STATISTICS 108 109 _param_statistics , 109 110 #endif 110 111 111 *(_param._param_registerfile)); 112 112 113 // Instantiation 113 114 (*(component_RegisterFile->in_CLOCK)) (*(in_CLOCK)); 114 115 (*(component_RegisterFile->in_NRESET)) (*(in_NRESET)); 116 115 117 for (uint32_t i=0; i<_param._nb_prediction; i++) 116 118 { 117 (*(component_RegisterFile-> in_READ_ENABLE [i])) (*( in_PREDICT_VAL [i])); 119 (*(component_RegisterFile-> in_READ_VAL [i])) (*( in_PREDICT_VAL [i])); 120 (*(component_RegisterFile->out_READ_ACK [i])) (*(out_PREDICT_ACK [i])); 118 121 (*(component_RegisterFile-> in_READ_ADDRESS [i])) (*( in_PREDICT_ADDRESS [i])); 119 122 (*(component_RegisterFile->out_READ_DATA [i])) (*(out_PREDICT_HISTORY [i])); … … 122 125 for (uint32_t i=0; i<_param._nb_branch_complete; i++) 123 126 { 124 (*(component_RegisterFile-> in_WRITE_ENABLE [i])) (*( in_BRANCH_COMPLETE_VAL [i])); 127 (*(component_RegisterFile-> in_WRITE_VAL [i])) (*( in_BRANCH_COMPLETE_VAL [i])); 128 (*(component_RegisterFile->out_WRITE_ACK [i])) (*( out_BRANCH_COMPLETE_ACK [i])); 125 129 (*(component_RegisterFile-> in_WRITE_ADDRESS [i])) (*( in_BRANCH_COMPLETE_ADDRESS [i])); 126 130 (*(component_RegisterFile-> in_WRITE_DATA [i])) (*(signal_BRANCH_COMPLETE_HISTORY [i])); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_deallocation.cpp
r3 r15 23 23 24 24 delete in_CLOCK; 25 delete in_NRESET; 25 26 26 27 for (uint32_t i=0; i<_param._nb_prediction; i++) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_vhdl_body.cpp
r3 r15 22 22 log_printf(FUNC,Pattern_History_Table,"vhdl_body","Begin"); 23 23 24 vhdl.set_body ("-- Output : always at '1'");25 for (uint32_t i=0; i<_param._nb_branch_complete; i++)26 vhdl.set_body ("out_BRANCH_COMPLETE_ACK_"+toString(i)+" <= '1';");27 for (uint32_t i=0; i<_param._nb_prediction ; i++)28 vhdl.set_body ("out_PREDICT_ACK_"+toString(i)+" <= '1';");29 vhdl.set_body ("");24 // vhdl.set_body ("-- Output : always at '1'"); 25 // for (uint32_t i=0; i<_param._nb_branch_complete; i++) 26 // vhdl.set_body ("out_BRANCH_COMPLETE_ACK_"+toString(i)+" <= '1';"); 27 // for (uint32_t i=0; i<_param._nb_prediction ; i++) 28 // vhdl.set_body ("out_PREDICT_ACK_"+toString(i)+" <= '1';"); 29 // vhdl.set_body (""); 30 30 31 31 list<string> list_port_map; … … 41 41 42 42 list_port_map.clear(); 43 vhdl.set_body_component_port_map (list_port_map,"in_CLOCK","in_CLOCK"); 43 vhdl.set_body_component_port_map (list_port_map,"in_CLOCK ","in_CLOCK "); 44 vhdl.set_body_component_port_map (list_port_map,"in_NRESET","in_NRESET"); 45 44 46 for (uint32_t i=0; i<_param._nb_prediction; i++) 45 47 { 46 vhdl.set_body_component_port_map (list_port_map," in_READ_ENABLE_"+toString(i)+" "," in_PREDICT_VAL_"+toString(i)); 48 vhdl.set_body_component_port_map (list_port_map," in_READ_VAL_"+toString(i)+" "," in_PREDICT_VAL_"+toString(i)); 49 vhdl.set_body_component_port_map (list_port_map,"out_READ_ACK_"+toString(i)+" ","out_PREDICT_ACK_"+toString(i)); 47 50 vhdl.set_body_component_port_map (list_port_map," in_READ_ADDRESS_"+toString(i)+" "," in_PREDICT_ADDRESS_"+toString(i)); 48 51 vhdl.set_body_component_port_map (list_port_map,"out_READ_DATA_"+toString(i)+" ","out_PREDICT_HISTORY_"+toString(i)); … … 51 54 for (uint32_t i=0; i<_param._nb_branch_complete; i++) 52 55 { 53 vhdl.set_body_component_port_map (list_port_map," in_WRITE_ENABLE_"+toString(i)+" "," in_BRANCH_COMPLETE_VAL_"+toString(i)+""); 56 vhdl.set_body_component_port_map (list_port_map," in_WRITE_VAL_"+toString(i)+" "," in_BRANCH_COMPLETE_VAL_"+toString(i)+""); 57 vhdl.set_body_component_port_map (list_port_map,"out_WRITE_ACK_"+toString(i)+" "," out_BRANCH_COMPLETE_ACK_"+toString(i)+""); 54 58 vhdl.set_body_component_port_map (list_port_map," in_WRITE_ADDRESS_"+toString(i)+""," in_BRANCH_COMPLETE_ADDRESS_"+toString(i)); 55 59 vhdl.set_body_component_port_map (list_port_map," in_WRITE_DATA_"+toString(i)+" ","signal_BRANCH_COMPLETE_HISTORY_"+toString(i)); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_vhdl_port.cpp
r3 r15 23 23 24 24 vhdl.set_port (" in_CLOCK" , IN, 1); 25 vhdl.set_port (" in_NRESET", IN, 1); 25 26 26 27 for (uint32_t i=0; i<_param._nb_prediction; i++) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_vhdl_testbench_port.cpp
r3 r15 21 21 { 22 22 log_printf(FUNC,Pattern_History_Table,"vhdl_testbench_port","Begin"); 23 24 _vhdl_testbench->set_port (" in_NRESET", IN, 1); 23 25 24 26 for (uint32_t i=0; i<_param._nb_prediction; i++) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_vhdl_testbench_transition.cpp
r3 r15 30 30 // (because we have no control on the ordonnancer's policy) 31 31 32 _vhdl_testbench->add_input (PORT_READ( in_NRESET)); 33 32 34 for (uint32_t i=0; i<_param._nb_prediction; i++) 33 35 { 34 36 _vhdl_testbench->add_input (PORT_READ( in_PREDICT_VAL [i])); 35 _vhdl_testbench->add_output (PORT_READ( out_PREDICT_ACK[i]));37 _vhdl_testbench->add_output (PORT_READ(component_RegisterFile->out_READ_ACK [i])); 36 38 _vhdl_testbench->add_input (PORT_READ( in_PREDICT_ADDRESS [i])); 37 39 _vhdl_testbench->add_output (PORT_READ(component_RegisterFile->out_READ_DATA [i])); … … 42 44 { 43 45 _vhdl_testbench->add_input (PORT_READ( in_BRANCH_COMPLETE_VAL [i])); 44 _vhdl_testbench->add_output (PORT_READ( out_BRANCH_COMPLETE_ACK[i]));46 _vhdl_testbench->add_output (PORT_READ(component_RegisterFile->out_WRITE_ACK [i])); 45 47 _vhdl_testbench->add_input (PORT_READ( in_BRANCH_COMPLETE_ADDRESS [i])); 46 48 _vhdl_testbench->add_input (PORT_READ( in_BRANCH_COMPLETE_HISTORY [i])); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/SelfTest/mkf.info
r3 r15 1 2 # Two_Level_Branch_Predictor_03 target_dep all Two_Level_Branch_Predictor_0.ngc4 target_dep Two_Level_Branch_Predictor_0.ngc Two_Level_Branch_Predictor_0.prj5 target_dep Two_Level_Branch_Predictor_0.prj Two_Level_Branch_Predictor_0_Branch_History_Table_Pack.vhdl Two_Level_Branch_Predictor_0_Branch_History_Table_RegisterFile_Pack.vhdl Two_Level_Branch_Predictor_0_Branch_History_Table_RegisterFile.vhdl Two_Level_Branch_Predictor_0_Branch_History_Table_Shifter_Pack.vhdl Two_Level_Branch_Predictor_0_Branch_History_Table_Shifter.vhdl Two_Level_Branch_Predictor_0_Branch_History_Table.vhdl Two_Level_Branch_Predictor_0_Pack.vhdl Two_Level_Branch_Predictor_0_Pattern_History_Table_Counter_Pack.vhdl Two_Level_Branch_Predictor_0_Pattern_History_Table_Counter.vhdl Two_Level_Branch_Predictor_0_Pattern_History_Table_Pack.vhdl Two_Level_Branch_Predictor_0_Pattern_History_Table_RegisterFile_Pack.vhdl Two_Level_Branch_Predictor_0_Pattern_History_Table_RegisterFile.vhdl Two_Level_Branch_Predictor_0_Pattern_History_Table.vhdl Two_Level_Branch_Predictor_0_Two_Level_Branch_Predictor_Glue_Pack.vhdl Two_Level_Branch_Predictor_0_Two_Level_Branch_Predictor_Glue.vhdl Two_Level_Branch_Predictor_0.vhdl6 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/SelfTest/src/test.cpp
r5 r15 29 29 *********************************************************************/ 30 30 sc_clock * CLOCK; 31 sc_signal<Tcontrol_t> * NRESET; 31 32 32 33 sc_signal<Tcontrol_t> * PREDICT_VAL [param._nb_prediction]; … … 47 48 string rename; 48 49 49 CLOCK = new sc_clock ("clock", 1.0, 0.5); 50 CLOCK = new sc_clock ("clock", 1.0, 0.5); 51 NRESET = new sc_signal<Tcontrol_t> ("NRESET"); 50 52 51 53 for (uint32_t i=0; i<param._nb_prediction; i++) … … 85 87 cout << "<" << name << "> Instanciation of _Two_Level_Branch_Predictor" << endl; 86 88 87 (*(_Two_Level_Branch_Predictor->in_CLOCK)) (*(CLOCK)); 89 (*(_Two_Level_Branch_Predictor->in_CLOCK )) (*(CLOCK )); 90 (*(_Two_Level_Branch_Predictor->in_NRESET)) (*(NRESET)); 88 91 89 92 for (uint32_t i=0; i<param._nb_prediction; i++) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/SelfTest/mkf.info
r2 r15 1 2 # Two_Level_Branch_Predictor_Glue_03 target_dep all Two_Level_Branch_Predictor_Glue_0.ngc4 target_dep Two_Level_Branch_Predictor_Glue_0.ngc Two_Level_Branch_Predictor_Glue_0.prj5 target_dep Two_Level_Branch_Predictor_Glue_0.prj Two_Level_Branch_Predictor_Glue_0_Pack.vhdl Two_Level_Branch_Predictor_Glue_0.vhdl6 7 # Two_Level_Branch_Predictor_Glue_108 target_dep all Two_Level_Branch_Predictor_Glue_10.ngc9 target_dep Two_Level_Branch_Predictor_Glue_10.ngc Two_Level_Branch_Predictor_Glue_10.prj10 target_dep Two_Level_Branch_Predictor_Glue_10.prj Two_Level_Branch_Predictor_Glue_10_Pack.vhdl Two_Level_Branch_Predictor_Glue_10.vhdl11 12 # Two_Level_Branch_Predictor_Glue_1113 target_dep all Two_Level_Branch_Predictor_Glue_11.ngc14 target_dep Two_Level_Branch_Predictor_Glue_11.ngc Two_Level_Branch_Predictor_Glue_11.prj15 target_dep Two_Level_Branch_Predictor_Glue_11.prj Two_Level_Branch_Predictor_Glue_11_Pack.vhdl Two_Level_Branch_Predictor_Glue_11.vhdl16 17 # Two_Level_Branch_Predictor_Glue_1218 target_dep all Two_Level_Branch_Predictor_Glue_12.ngc19 target_dep Two_Level_Branch_Predictor_Glue_12.ngc Two_Level_Branch_Predictor_Glue_12.prj20 target_dep Two_Level_Branch_Predictor_Glue_12.prj Two_Level_Branch_Predictor_Glue_12_Pack.vhdl Two_Level_Branch_Predictor_Glue_12.vhdl21 22 # Two_Level_Branch_Predictor_Glue_1323 target_dep all Two_Level_Branch_Predictor_Glue_13.ngc24 target_dep Two_Level_Branch_Predictor_Glue_13.ngc Two_Level_Branch_Predictor_Glue_13.prj25 target_dep Two_Level_Branch_Predictor_Glue_13.prj Two_Level_Branch_Predictor_Glue_13_Pack.vhdl Two_Level_Branch_Predictor_Glue_13.vhdl26 27 # Two_Level_Branch_Predictor_Glue_1428 target_dep all Two_Level_Branch_Predictor_Glue_14.ngc29 target_dep Two_Level_Branch_Predictor_Glue_14.ngc Two_Level_Branch_Predictor_Glue_14.prj30 target_dep Two_Level_Branch_Predictor_Glue_14.prj Two_Level_Branch_Predictor_Glue_14_Pack.vhdl Two_Level_Branch_Predictor_Glue_14.vhdl31 32 # Two_Level_Branch_Predictor_Glue_1533 target_dep all Two_Level_Branch_Predictor_Glue_15.ngc34 target_dep Two_Level_Branch_Predictor_Glue_15.ngc Two_Level_Branch_Predictor_Glue_15.prj35 target_dep Two_Level_Branch_Predictor_Glue_15.prj Two_Level_Branch_Predictor_Glue_15_Pack.vhdl Two_Level_Branch_Predictor_Glue_15.vhdl36 37 # Two_Level_Branch_Predictor_Glue_1638 target_dep all Two_Level_Branch_Predictor_Glue_16.ngc39 target_dep Two_Level_Branch_Predictor_Glue_16.ngc Two_Level_Branch_Predictor_Glue_16.prj40 target_dep Two_Level_Branch_Predictor_Glue_16.prj Two_Level_Branch_Predictor_Glue_16_Pack.vhdl Two_Level_Branch_Predictor_Glue_16.vhdl41 42 # Two_Level_Branch_Predictor_Glue_1743 target_dep all Two_Level_Branch_Predictor_Glue_17.ngc44 target_dep Two_Level_Branch_Predictor_Glue_17.ngc Two_Level_Branch_Predictor_Glue_17.prj45 target_dep Two_Level_Branch_Predictor_Glue_17.prj Two_Level_Branch_Predictor_Glue_17_Pack.vhdl Two_Level_Branch_Predictor_Glue_17.vhdl46 47 # Two_Level_Branch_Predictor_Glue_1848 target_dep all Two_Level_Branch_Predictor_Glue_18.ngc49 target_dep Two_Level_Branch_Predictor_Glue_18.ngc Two_Level_Branch_Predictor_Glue_18.prj50 target_dep Two_Level_Branch_Predictor_Glue_18.prj Two_Level_Branch_Predictor_Glue_18_Pack.vhdl Two_Level_Branch_Predictor_Glue_18.vhdl51 52 # Two_Level_Branch_Predictor_Glue_1953 target_dep all Two_Level_Branch_Predictor_Glue_19.ngc54 target_dep Two_Level_Branch_Predictor_Glue_19.ngc Two_Level_Branch_Predictor_Glue_19.prj55 target_dep Two_Level_Branch_Predictor_Glue_19.prj Two_Level_Branch_Predictor_Glue_19_Pack.vhdl Two_Level_Branch_Predictor_Glue_19.vhdl56 57 # Two_Level_Branch_Predictor_Glue_158 target_dep all Two_Level_Branch_Predictor_Glue_1.ngc59 target_dep Two_Level_Branch_Predictor_Glue_1.ngc Two_Level_Branch_Predictor_Glue_1.prj60 target_dep Two_Level_Branch_Predictor_Glue_1.prj Two_Level_Branch_Predictor_Glue_10_Pack.vhdl Two_Level_Branch_Predictor_Glue_10.vhdl Two_Level_Branch_Predictor_Glue_11_Pack.vhdl Two_Level_Branch_Predictor_Glue_11.vhdl Two_Level_Branch_Predictor_Glue_12_Pack.vhdl Two_Level_Branch_Predictor_Glue_12.vhdl Two_Level_Branch_Predictor_Glue_13_Pack.vhdl Two_Level_Branch_Predictor_Glue_13.vhdl Two_Level_Branch_Predictor_Glue_14_Pack.vhdl Two_Level_Branch_Predictor_Glue_14.vhdl Two_Level_Branch_Predictor_Glue_15_Pack.vhdl Two_Level_Branch_Predictor_Glue_15.vhdl Two_Level_Branch_Predictor_Glue_16_Pack.vhdl Two_Level_Branch_Predictor_Glue_16.vhdl Two_Level_Branch_Predictor_Glue_17_Pack.vhdl Two_Level_Branch_Predictor_Glue_17.vhdl Two_Level_Branch_Predictor_Glue_18_Pack.vhdl Two_Level_Branch_Predictor_Glue_18.vhdl Two_Level_Branch_Predictor_Glue_19_Pack.vhdl Two_Level_Branch_Predictor_Glue_19.vhdl Two_Level_Branch_Predictor_Glue_1_Pack.vhdl Two_Level_Branch_Predictor_Glue_1.vhdl61 62 # Two_Level_Branch_Predictor_Glue_2063 target_dep all Two_Level_Branch_Predictor_Glue_20.ngc64 target_dep Two_Level_Branch_Predictor_Glue_20.ngc Two_Level_Branch_Predictor_Glue_20.prj65 target_dep Two_Level_Branch_Predictor_Glue_20.prj Two_Level_Branch_Predictor_Glue_20_Pack.vhdl Two_Level_Branch_Predictor_Glue_20.vhdl66 67 # Two_Level_Branch_Predictor_Glue_2168 target_dep all Two_Level_Branch_Predictor_Glue_21.ngc69 target_dep Two_Level_Branch_Predictor_Glue_21.ngc Two_Level_Branch_Predictor_Glue_21.prj70 target_dep Two_Level_Branch_Predictor_Glue_21.prj Two_Level_Branch_Predictor_Glue_21_Pack.vhdl Two_Level_Branch_Predictor_Glue_21.vhdl71 72 # Two_Level_Branch_Predictor_Glue_2273 target_dep all Two_Level_Branch_Predictor_Glue_22.ngc74 target_dep Two_Level_Branch_Predictor_Glue_22.ngc Two_Level_Branch_Predictor_Glue_22.prj75 target_dep Two_Level_Branch_Predictor_Glue_22.prj Two_Level_Branch_Predictor_Glue_22_Pack.vhdl Two_Level_Branch_Predictor_Glue_22.vhdl76 77 # Two_Level_Branch_Predictor_Glue_2378 target_dep all Two_Level_Branch_Predictor_Glue_23.ngc79 target_dep Two_Level_Branch_Predictor_Glue_23.ngc Two_Level_Branch_Predictor_Glue_23.prj80 target_dep Two_Level_Branch_Predictor_Glue_23.prj Two_Level_Branch_Predictor_Glue_23_Pack.vhdl Two_Level_Branch_Predictor_Glue_23.vhdl81 82 # Two_Level_Branch_Predictor_Glue_283 target_dep all Two_Level_Branch_Predictor_Glue_2.ngc84 target_dep Two_Level_Branch_Predictor_Glue_2.ngc Two_Level_Branch_Predictor_Glue_2.prj85 target_dep Two_Level_Branch_Predictor_Glue_2.prj Two_Level_Branch_Predictor_Glue_20_Pack.vhdl Two_Level_Branch_Predictor_Glue_20.vhdl Two_Level_Branch_Predictor_Glue_21_Pack.vhdl Two_Level_Branch_Predictor_Glue_21.vhdl Two_Level_Branch_Predictor_Glue_22_Pack.vhdl Two_Level_Branch_Predictor_Glue_22.vhdl Two_Level_Branch_Predictor_Glue_23_Pack.vhdl Two_Level_Branch_Predictor_Glue_23.vhdl Two_Level_Branch_Predictor_Glue_2_Pack.vhdl Two_Level_Branch_Predictor_Glue_2.vhdl86 87 # Two_Level_Branch_Predictor_Glue_388 target_dep all Two_Level_Branch_Predictor_Glue_3.ngc89 target_dep Two_Level_Branch_Predictor_Glue_3.ngc Two_Level_Branch_Predictor_Glue_3.prj90 target_dep Two_Level_Branch_Predictor_Glue_3.prj Two_Level_Branch_Predictor_Glue_3_Pack.vhdl Two_Level_Branch_Predictor_Glue_3.vhdl91 92 # Two_Level_Branch_Predictor_Glue_493 target_dep all Two_Level_Branch_Predictor_Glue_4.ngc94 target_dep Two_Level_Branch_Predictor_Glue_4.ngc Two_Level_Branch_Predictor_Glue_4.prj95 target_dep Two_Level_Branch_Predictor_Glue_4.prj Two_Level_Branch_Predictor_Glue_4_Pack.vhdl Two_Level_Branch_Predictor_Glue_4.vhdl96 97 # Two_Level_Branch_Predictor_Glue_598 target_dep all Two_Level_Branch_Predictor_Glue_5.ngc99 target_dep Two_Level_Branch_Predictor_Glue_5.ngc Two_Level_Branch_Predictor_Glue_5.prj100 target_dep Two_Level_Branch_Predictor_Glue_5.prj Two_Level_Branch_Predictor_Glue_5_Pack.vhdl Two_Level_Branch_Predictor_Glue_5.vhdl101 102 # Two_Level_Branch_Predictor_Glue_6103 target_dep all Two_Level_Branch_Predictor_Glue_6.ngc104 target_dep Two_Level_Branch_Predictor_Glue_6.ngc Two_Level_Branch_Predictor_Glue_6.prj105 target_dep Two_Level_Branch_Predictor_Glue_6.prj Two_Level_Branch_Predictor_Glue_6_Pack.vhdl Two_Level_Branch_Predictor_Glue_6.vhdl106 107 # Two_Level_Branch_Predictor_Glue_7108 target_dep all Two_Level_Branch_Predictor_Glue_7.ngc109 target_dep Two_Level_Branch_Predictor_Glue_7.ngc Two_Level_Branch_Predictor_Glue_7.prj110 target_dep Two_Level_Branch_Predictor_Glue_7.prj Two_Level_Branch_Predictor_Glue_7_Pack.vhdl Two_Level_Branch_Predictor_Glue_7.vhdl111 112 # Two_Level_Branch_Predictor_Glue_8113 target_dep all Two_Level_Branch_Predictor_Glue_8.ngc114 target_dep Two_Level_Branch_Predictor_Glue_8.ngc Two_Level_Branch_Predictor_Glue_8.prj115 target_dep Two_Level_Branch_Predictor_Glue_8.prj Two_Level_Branch_Predictor_Glue_8_Pack.vhdl Two_Level_Branch_Predictor_Glue_8.vhdl116 117 # Two_Level_Branch_Predictor_Glue_9118 target_dep all Two_Level_Branch_Predictor_Glue_9.ngc119 target_dep Two_Level_Branch_Predictor_Glue_9.ngc Two_Level_Branch_Predictor_Glue_9.prj120 target_dep Two_Level_Branch_Predictor_Glue_9.prj Two_Level_Branch_Predictor_Glue_9_Pack.vhdl Two_Level_Branch_Predictor_Glue_9.vhdl121 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/include/Two_Level_Branch_Predictor.h
r3 r15 70 70 // Interface 71 71 public : SC_CLOCK * in_CLOCK ; 72 72 public : SC_IN (Tcontrol_t) * in_NRESET ; 73 73 // Interface Predict 74 74 public : SC_IN (Tcontrol_t) ** in_PREDICT_VAL ; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_allocation.cpp
r3 r15 23 23 24 24 in_CLOCK = new SC_CLOCK ("in_CLOCK"); 25 in_NRESET = new SC_IN (Tcontrol_t) ("in_NRESET"); 25 26 26 27 in_PREDICT_VAL = new SC_IN (Tcontrol_t) * [_param._nb_prediction ]; … … 161 162 162 163 // Instantiation 163 (*(component_Branch_History_Table->in_CLOCK)) (*(in_CLOCK)); 164 (*(component_Branch_History_Table->in_CLOCK )) (*(in_CLOCK )); 165 (*(component_Branch_History_Table->in_NRESET)) (*(in_NRESET)); 164 166 165 167 for (uint32_t i=0; i<_param._nb_prediction; i++) … … 196 198 // Instantiation 197 199 (*(component_Pattern_History_Table->in_CLOCK)) (*(in_CLOCK)); 200 (*(component_Pattern_History_Table->in_NRESET)) (*(in_NRESET)); 198 201 199 202 for (uint32_t i=0; i<_param._nb_prediction; i++) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_deallocation.cpp
r3 r15 21 21 22 22 delete in_CLOCK; 23 delete in_NRESET; 23 24 24 25 for (uint32_t i=0; i<_param._nb_prediction; i++) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_vhdl_body.cpp
r3 r15 27 27 list_port_map.clear(); 28 28 29 vhdl.set_body_component_port_map (list_port_map,"in_CLOCK","in_CLOCK"); 29 vhdl.set_body_component_port_map (list_port_map,"in_CLOCK ","in_CLOCK "); 30 vhdl.set_body_component_port_map (list_port_map,"in_NRESET","in_NRESET"); 30 31 31 32 for (uint32_t i=0; i<_param._nb_prediction; i++) … … 53 54 list_port_map.clear(); 54 55 55 vhdl.set_body_component_port_map (list_port_map,"in_CLOCK","in_CLOCK"); 56 vhdl.set_body_component_port_map (list_port_map,"in_CLOCK ","in_CLOCK "); 57 vhdl.set_body_component_port_map (list_port_map,"in_NRESET","in_NRESET"); 56 58 57 59 for (uint32_t i=0; i<_param._nb_prediction; i++) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_vhdl_port.cpp
r3 r15 20 20 log_printf(FUNC,Two_Level_Branch_Predictor,"vhdl_port","Begin"); 21 21 22 vhdl.set_port (" in_CLOCK" , IN, 1); 22 vhdl.set_port (" in_CLOCK ", IN, 1); 23 vhdl.set_port (" in_NRESET", IN, 1); 23 24 24 25 for (uint32_t i=0; i<_param._nb_prediction; i++) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_vhdl_testbench_port.cpp
r3 r15 20 20 { 21 21 log_printf(FUNC,Two_Level_Branch_Predictor,"vhdl_testbench_port","Begin"); 22 23 _vhdl_testbench->set_port (" in_NRESET", IN, 1); 22 24 23 25 for (uint32_t i=0; i<_param._nb_prediction; i++) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_vhdl_testbench_transition.cpp
r3 r15 25 25 #endif 26 26 27 _vhdl_testbench->add_input (PORT_READ( in_NRESET)); 28 27 29 // In order with file Two_Level_Branch_Predictor_vhdl_testbench_port.cpp 28 30 // Warning : if a output depend of a subcomponent, take directly the port of subcomponent -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/include/Meta_Predictor.h
r5 r15 68 68 // Interface 69 69 public : SC_CLOCK * in_CLOCK ; 70 public : SC_IN (Tcontrol_t) * in_NRESET ; 70 71 71 72 // Interface Predict -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/src/Meta_Predictor_allocation.cpp
r5 r15 23 23 24 24 in_CLOCK = new SC_CLOCK ("in_CLOCK"); 25 in_NRESET = new SC_IN (Tcontrol_t) ("in_NRESET"); 25 26 26 27 in_PREDICT_VAL = new SC_IN (Tcontrol_t) * [_param._nb_prediction ]; … … 235 236 236 237 // Instantiation 237 (*(component_Meta_Predictor_Glue->in_CLOCK)) (*(in_CLOCK)); 238 238 #if defined(STATISTICS) or defined(VHDL_TESTBENCH) 239 (*(component_Meta_Predictor_Glue->in_CLOCK )) (*(in_CLOCK )); 240 #endif 241 239 242 // Interface Predict 240 243 for (uint32_t i=0; i<_param._nb_prediction; i++) … … 317 320 318 321 // Instantiation 319 (*(component_Two_Level_Branch_Predictor_2->in_CLOCK)) (*(in_CLOCK)); 322 (*(component_Two_Level_Branch_Predictor_2->in_CLOCK )) (*(in_CLOCK )); 323 (*(component_Two_Level_Branch_Predictor_2->in_NRESET)) (*(in_NRESET)); 320 324 321 325 for (uint32_t i=0; i<_param._nb_prediction; i++) … … 363 367 364 368 // Instantiation 365 (*(component_Two_Level_Branch_Predictor_1->in_CLOCK)) (*(in_CLOCK)); 369 (*(component_Two_Level_Branch_Predictor_1->in_CLOCK )) (*(in_CLOCK )); 370 (*(component_Two_Level_Branch_Predictor_1->in_NRESET)) (*(in_NRESET)); 366 371 367 372 for (uint32_t i=0; i<_param._nb_prediction; i++) … … 401 406 402 407 // Instantiation 403 (*(component_Two_Level_Branch_Predictor_0->in_CLOCK)) (*(in_CLOCK)); 408 (*(component_Two_Level_Branch_Predictor_0->in_CLOCK )) (*(in_CLOCK )); 409 (*(component_Two_Level_Branch_Predictor_0->in_NRESET)) (*(in_NRESET)); 404 410 405 411 for (uint32_t i=0; i<_param._nb_prediction; i++) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/src/Meta_Predictor_deallocation.cpp
r5 r15 20 20 21 21 delete in_CLOCK; 22 delete in_NRESET; 22 23 23 24 for (uint32_t i=0; i<_param._nb_prediction; i++) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/src/Meta_Predictor_vhdl_body.cpp
r5 r15 105 105 106 106 // Instantiation 107 vhdl.set_body_component_port_map (list_port_map,"in_CLOCK","in_CLOCK"); 107 vhdl.set_body_component_port_map (list_port_map,"in_CLOCK ","in_CLOCK "); 108 vhdl.set_body_component_port_map (list_port_map,"in_NRESET","in_NRESET"); 108 109 109 110 for (uint32_t i=0; i<_param._nb_prediction; i++) … … 146 147 147 148 // Instantiation 148 vhdl.set_body_component_port_map (list_port_map,"in_CLOCK","in_CLOCK"); 149 vhdl.set_body_component_port_map (list_port_map,"in_CLOCK ","in_CLOCK "); 150 vhdl.set_body_component_port_map (list_port_map,"in_NRESET","in_NRESET"); 149 151 150 152 for (uint32_t i=0; i<_param._nb_prediction; i++) … … 179 181 180 182 // Instantiation 181 vhdl.set_body_component_port_map (list_port_map,"in_CLOCK","in_CLOCK"); 183 vhdl.set_body_component_port_map (list_port_map,"in_CLOCK ","in_CLOCK "); 184 vhdl.set_body_component_port_map (list_port_map,"in_NRESET","in_NRESET"); 182 185 183 186 for (uint32_t i=0; i<_param._nb_prediction; i++) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/src/Meta_Predictor_vhdl_port.cpp
r5 r15 20 20 log_printf(FUNC,Meta_Predictor,"vhdl_port","Begin"); 21 21 22 vhdl.set_port (" in_CLOCK" , IN, 1); 22 vhdl.set_port (" in_CLOCK ", IN, 1); 23 vhdl.set_port (" in_NRESET", IN, 1); 23 24 24 25 for (uint32_t i=0; i<_param._nb_prediction; i++) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/src/Meta_Predictor_vhdl_testbench_port.cpp
r5 r15 19 19 { 20 20 log_printf(FUNC,Meta_Predictor,"vhdl_testbench_port","Begin"); 21 22 _vhdl_testbench->set_port (" in_NRESET", IN, 1); 21 23 22 24 for (uint32_t i=0; i<_param._nb_prediction; i++) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/src/Meta_Predictor_vhdl_testbench_transition.cpp
r5 r15 26 26 // Warning : if a output depend of a subcomponent, take directly the port of subcomponent 27 27 // (because we have no control on the ordonnancer's policy) 28 29 _vhdl_testbench->add_input (PORT_READ( in_NRESET)); 28 30 29 31 for (uint32_t i=0; i<_param._nb_prediction; i++)
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