- Timestamp:
- Dec 19, 2008, 4:34:00 PM (16 years ago)
- Location:
- trunk
- Files:
-
- 1 added
- 3 deleted
- 151 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/SelfTest/src/test.cpp
r88 r97 10 10 #include "Behavioural/Custom/include/Custom_default.h" 11 11 #include "Behavioural/Custom/include/Custom_example.h" 12 #include "Common/include/Time.h" 12 13 13 14 void test (string name) 14 15 { 16 Time * timing = new Time (false); 17 15 18 morpheo::behavioural::custom::custom_information_t (*_get_custom_information) (void) = &(morpheo::behavioural::custom::default_get_custom_information); 16 19 … … 81 84 delete generator1; 82 85 delete simulator1; 83 84 86 delete timing; 85 87 } -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/include/Configuration.h
r88 r97 46 46 public : ~Configuration (); 47 47 48 public : std::string header (void); 48 49 public : std::string getName (void); 49 50 public : Tusage_t getUsage (void); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/include/Parameters.h
r88 r97 30 30 public : uint32_t * _ras_size_queue ;//[nb_thread] 31 31 public : uint32_t * _upt_size_queue ;//[nb_thread] 32 public : uint32_t * _ufpt_size_queue ;//[nb_thread] 32 33 33 34 // Decod bloc -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Configuration.cpp
r88 r97 23 23 log_begin(Configuration,FUNCTION); 24 24 25 //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 26 // Simulator configuration 27 //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 28 25 29 _simulator = new Simulator (filename_simulator); 26 _generator = new Generator (filename_generator);27 _instance = new Instance (filename_instance ,28 _generator,29 get_custom_information);30 30 31 31 //-------------------------------------------------- 32 // Name32 // Directory 33 33 //-------------------------------------------------- 34 _name = _instance->getName(); 34 directory_init (_simulator->getParam("directory_statistics"), 35 _simulator->getParam("directory_vhdl" ), 36 _simulator->getParam("directory_position" ), 37 _simulator->getParam("directory_log" )); 35 38 36 39 //-------------------------------------------------- 37 // Parameters40 // Debug & Log File 38 41 //-------------------------------------------------- 39 _param = _instance->_param; 42 debug_init (fromString<debug_verbosity_t>(_simulator->getParam("debug_level"))); 43 44 log_init(fromString<bool>(_simulator->getParam("debug_have_log_file")), 45 MORPHEO_LOG); 40 46 41 47 //-------------------------------------------------- … … 64 70 65 71 //-------------------------------------------------- 72 // Header 73 //-------------------------------------------------- 74 75 if (usage_is_set(_usage,USE_HEADER)) 76 std::cout << header(); 77 78 //-------------------------------------------------- 66 79 // Parameters_Statistics 67 80 //-------------------------------------------------- … … 75 88 fromString<double>(_simulator->getParam("simulation_nb_instruction"))); 76 89 90 91 //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 92 // Generator configuration + Instance 93 //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 94 95 _generator = new Generator (filename_generator); 96 _instance = new Instance (filename_instance , 97 _generator, 98 get_custom_information); 99 77 100 //-------------------------------------------------- 78 // Directory101 // Name 79 102 //-------------------------------------------------- 80 directory_init (_simulator->getParam("directory_statistics"), 81 _simulator->getParam("directory_vhdl" ), 82 _simulator->getParam("directory_position" ), 83 _simulator->getParam("directory_log" )); 103 _name = _instance->getName(); 104 105 //-------------------------------------------------- 106 // Parameters 107 //-------------------------------------------------- 108 _param = _instance->_param; 109 84 110 85 111 log_end(Configuration,FUNCTION); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Instance.cpp
r88 r97 164 164 DELETE1(_param->_nb_inst_decod ,_param->_nb_decod_bloc); 165 165 DELETE1(_param->_size_decod_queue ,_param->_nb_decod_bloc); 166 DELETE1(_param->_ufpt_size_queue ,_param->_nb_thread); 166 167 DELETE1(_param->_upt_size_queue ,_param->_nb_thread); 167 168 DELETE1(_param->_ras_size_queue ,_param->_nb_thread); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Instance_fromInternalStructure.cpp
r88 r97 21 21 // Common 22 22 //----------------------------------------------------- 23 23 //log_printf(INFO,Configuration,FUNCTION,_("COMMON")); 24 24 25 25 _param->_size_general_data = fromString<uint32_t>(getParam("size_data" , "")); … … 46 46 ALLOC1(_param->_ras_size_queue ,uint32_t,_param->_nb_thread); 47 47 ALLOC1(_param->_upt_size_queue ,uint32_t,_param->_nb_thread); 48 ALLOC1(_param->_ufpt_size_queue ,uint32_t,_param->_nb_thread); 48 49 49 50 for (uint32_t i=0; i<_param->_nb_thread; ++i) 50 51 { 51 52 //log_printf(INFO,Configuration,FUNCTION,_("THREAD [%d]"),i); 52 53 53 54 _param->_size_ifetch_queue [i] = fromString<uint32_t>(getParam("size_ifetch_queue", "thread",toString(i).c_str(),"")); … … 55 56 _param->_ras_size_queue [i] = fromString<uint32_t>(getParam("ras_size_queue" , "thread",toString(i).c_str(),"")); 56 57 _param->_upt_size_queue [i] = fromString<uint32_t>(getParam("upt_size_queue" , "thread",toString(i).c_str(),"")); 58 _param->_ufpt_size_queue [i] = fromString<uint32_t>(getParam("ufpt_size_queue" , "thread",toString(i).c_str(),"")); 57 59 58 60 // just read !!! … … 85 87 for (uint32_t i=0; i<_param->_nb_decod_bloc; ++i) 86 88 { 87 89 //log_printf(INFO,Configuration,FUNCTION,_("DECOD_BLOC [%d]"),i); 88 90 89 91 _param->_size_decod_queue [i] = fromString<uint32_t > (getParam("size_decod_queue" , "decod_bloc",toString(i).c_str(),"")); … … 111 113 for (uint32_t i=0; i<_param->_nb_rename_bloc; ++i) 112 114 { 113 115 //log_printf(INFO,Configuration,FUNCTION,_("RENAME_BLOC [%d]"),i); 114 116 115 117 _param->_nb_inst_insert [i] = fromString<uint32_t > (getParam("nb_inst_insert" , "rename_bloc",toString(i).c_str(),"")); … … 134 136 for (uint32_t i=0; i<_param->_nb_read_bloc; ++i) 135 137 { 136 138 //log_printf(INFO,Configuration,FUNCTION,_("READ_BLOC [%d]"),i); 137 139 138 140 _param->_size_read_queue [i] = fromString<uint32_t> (getParam("size_read_queue" ,"read_bloc",toString(i).c_str(),"")); … … 150 152 for (uint32_t i=0; i<_param->_nb_write_bloc; ++i) 151 153 { 152 154 //log_printf(INFO,Configuration,FUNCTION,_("WRITE_BLOC [%d]"),i); 153 155 154 156 _param->_size_write_queue [i] = fromString<uint32_t> (getParam("size_write_queue" ,"write_bloc",toString(i).c_str(),"")); … … 171 173 for (uint32_t i=0; i<_param->_nb_load_store_unit; ++i) 172 174 { 173 175 //log_printf(INFO,Configuration,FUNCTION,_("LOAD_STORE_UNIT [%d]"),i); 174 176 175 177 _param->_size_store_queue [i] = fromString<uint32_t> (getParam("size_store_queue" ,"load_store_unit",toString(i).c_str(),"")); … … 192 194 for (uint32_t i=0; i<_param->_nb_functionnal_unit; ++i) 193 195 { 194 196 //log_printf(INFO,Configuration,FUNCTION,_("FUNCTIONNAL_UNIT [%d]"),i); 195 197 196 198 _param->_nb_inst_functionnal_unit [i] = fromString<uint32_t> (getParam("nb_inst_functionnal_unit","functionnal_unit",toString(i).c_str(),"")); … … 243 245 //----------------------------------------------------- 244 246 245 247 //log_printf(INFO,Configuration,FUNCTION,_("ICACHE_PORT")); 246 248 247 249 _param->_nb_icache_port = fromString<uint32_t >(getParam("nb_icache_port" , "")); … … 252 254 // dcache_port 253 255 //----------------------------------------------------- 254 256 //log_printf(INFO,Configuration,FUNCTION,_("DCACHE_PORT")); 255 257 256 258 _param->_nb_dcache_port = fromString<uint32_t >(getParam("nb_dcache_port" , "")); … … 282 284 for (uint32_t i=0; i<_param->_nb_front_end; ++i) 283 285 { 284 286 //log_printf(INFO,Configuration,FUNCTION,_("FRONT_END [%d]"),i); 285 287 286 288 _param->_nb_context [i] = fromString<uint32_t >(getParam("nb_context" ,"front_end",toString(i).c_str(), "")); … … 306 308 for (uint32_t j=0; j<3; ++j) 307 309 { 308 310 //log_printf(INFO,Configuration,FUNCTION,_("PREDICTOR [%d][%d]"),i,j); 309 311 310 312 _param->_dir_have_bht [i][j] = fromString<bool >(getParam("dir_have_bht" ,"front_end",toString(i).c_str(),"predictor",toString(j).c_str(), "")); … … 343 345 for (uint32_t i=0; i<_param->_nb_ooo_engine; ++i) 344 346 { 345 347 //log_printf(INFO,Configuration,FUNCTION,_("OOO_ENGINE [%d]"),i); 346 348 347 349 _param->_nb_rename_unit [i] = fromString<uint32_t >(getParam("nb_rename_unit" ,"ooo_engine",toString(i).c_str(), "")); … … 383 385 for (uint32_t i=0; i<_param->_nb_execute_loop; ++i) 384 386 { 385 387 //log_printf(INFO,Configuration,FUNCTION,_("EXECUTE_LOOP [%d]"),i); 386 388 387 389 _param->_nb_read_unit [i] = fromString<uint32_t >(getParam("nb_read_unit" ,"execute_loop",toString(i).c_str(), "")); … … 402 404 //----------------------------------------------------- 403 405 404 406 //log_printf(INFO,Configuration,FUNCTION,_("LINK")); 405 407 406 408 _param->_dispatch_priority = fromString<Tpriority_t >(getParam("dispatch_priority" , "")); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Instance_getLink.cpp
r88 r97 74 74 { 75 75 _return = link2array(dest); 76 76 //log_printf(INFO,Configuration,FUNCTION,_("Link \"%s[%s]\"= %s."),name,src.c_str(),dest.c_str()); 77 77 } 78 78 else 79 79 { 80 80 _return.clear(); 81 81 //log_printf(INFO,Configuration,FUNCTION,_("Link \"%s[%s]\" not find."),name,src.c_str()); 82 82 } 83 83 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Instance_getParam.cpp
r88 r97 48 48 if (it == ((*list_components)[component]).end()) 49 49 { 50 50 //log_printf(INFO,Configuration,FUNCTION,_("Component \"%s[%s]\" is not define, take default value for parameter \"%s\"."),component.c_str(),id.c_str(),name); 51 51 52 52 value = _generator->getParam(name)->_default; … … 68 68 if (it == (*list_parameters).end()) 69 69 { 70 70 //log_printf(INFO,Configuration,FUNCTION,_("Component \"%s[%s]\" is define, but parameter \"%s\" is not define. Take default value."),component.c_str(),id.c_str(),name); 71 71 72 72 value = _generator->getParam(name)->_default; … … 85 85 } 86 86 87 87 //log_printf(INFO,Configuration,FUNCTION,_("Parameters \"%s\" = %s."),name,value.c_str()); 88 88 89 89 log_end(Configuration,FUNCTION); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/SelfTest/src/test.cpp
r88 r97 74 74 ALLOC1_SC_SIGNAL(out_COMMIT_EVENT_FRONT_END_ADDRESS_EPCR ,"out_COMMIT_EVENT_FRONT_END_ADDRESS_EPCR ",Taddress_t ,_param->_nb_front_end); 75 75 ALLOC1_SC_SIGNAL(out_COMMIT_EVENT_FRONT_END_ADDRESS_EEAR_VAL ,"out_COMMIT_EVENT_FRONT_END_ADDRESS_EEAR_VAL ",Tcontrol_t ,_param->_nb_front_end); 76 ALLOC1_SC_SIGNAL(out_COMMIT_EVENT_FRONT_END_ADDRESS_EEAR ,"out_COMMIT_EVENT_FRONT_END_ADDRESS_EEAR ",T address_t,_param->_nb_front_end);76 ALLOC1_SC_SIGNAL(out_COMMIT_EVENT_FRONT_END_ADDRESS_EEAR ,"out_COMMIT_EVENT_FRONT_END_ADDRESS_EEAR ",Tgeneral_data_t ,_param->_nb_front_end); 77 77 ALLOC1_SC_SIGNAL( in_COMMIT_EVENT_OOO_ENGINE_VAL ," in_COMMIT_EVENT_OOO_ENGINE_VAL ",Tcontrol_t ,_param->_nb_ooo_engine); 78 78 ALLOC1_SC_SIGNAL(out_COMMIT_EVENT_OOO_ENGINE_ACK ,"out_COMMIT_EVENT_OOO_ENGINE_ACK ",Tcontrol_t ,_param->_nb_ooo_engine); … … 85 85 ALLOC1_SC_SIGNAL( in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EPCR ," in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EPCR ",Taddress_t ,_param->_nb_ooo_engine); 86 86 ALLOC1_SC_SIGNAL( in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EEAR_VAL ," in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EEAR_VAL ",Tcontrol_t ,_param->_nb_ooo_engine); 87 ALLOC1_SC_SIGNAL( in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EEAR ," in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EEAR ",T address_t,_param->_nb_ooo_engine);87 ALLOC1_SC_SIGNAL( in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EEAR ," in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EEAR ",Tgeneral_data_t ,_param->_nb_ooo_engine); 88 88 ALLOC2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_VAL ," in_ISSUE_OOO_ENGINE_VAL ",Tcontrol_t ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); 89 89 ALLOC2_SC_SIGNAL(out_ISSUE_OOO_ENGINE_ACK ,"out_ISSUE_OOO_ENGINE_ACK ",Tcontrol_t ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); … … 139 139 ALLOC3_SC_SIGNAL(out_EXECUTE_OOO_ENGINE_EXCEPTION ,"out_EXECUTE_OOO_ENGINE_EXCEPTION ",Texception_t ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_execute_loop[it1],_param->_nb_inst_execute[it1][it2]); 140 140 ALLOC3_SC_SIGNAL(out_EXECUTE_OOO_ENGINE_NO_SEQUENCE ,"out_EXECUTE_OOO_ENGINE_NO_SEQUENCE ",Tcontrol_t ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_execute_loop[it1],_param->_nb_inst_execute[it1][it2]); 141 ALLOC3_SC_SIGNAL(out_EXECUTE_OOO_ENGINE_ADDRESS ,"out_EXECUTE_OOO_ENGINE_ADDRESS ",T general_data_t,_param->_nb_ooo_engine,_param->_ooo_engine_nb_execute_loop[it1],_param->_nb_inst_execute[it1][it2]);141 ALLOC3_SC_SIGNAL(out_EXECUTE_OOO_ENGINE_ADDRESS ,"out_EXECUTE_OOO_ENGINE_ADDRESS ",Taddress_t ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_execute_loop[it1],_param->_nb_inst_execute[it1][it2]); 142 142 ALLOC3_SC_SIGNAL(out_EXECUTE_OOO_ENGINE_DATA ,"out_EXECUTE_OOO_ENGINE_DATA ",Tgeneral_data_t ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_execute_loop[it1],_param->_nb_inst_execute[it1][it2]); 143 143 ALLOC2_SC_SIGNAL( in_EXECUTE_EXECUTE_LOOP_VAL ," in_EXECUTE_EXECUTE_LOOP_VAL ",Tcontrol_t ,_param->_nb_execute_loop,_param->_nb_write_unit[it1]); … … 152 152 ALLOC2_SC_SIGNAL( in_EXECUTE_EXECUTE_LOOP_EXCEPTION ," in_EXECUTE_EXECUTE_LOOP_EXCEPTION ",Texception_t ,_param->_nb_execute_loop,_param->_nb_write_unit[it1]); 153 153 ALLOC2_SC_SIGNAL( in_EXECUTE_EXECUTE_LOOP_NO_SEQUENCE ," in_EXECUTE_EXECUTE_LOOP_NO_SEQUENCE ",Tcontrol_t ,_param->_nb_execute_loop,_param->_nb_write_unit[it1]); 154 ALLOC2_SC_SIGNAL( in_EXECUTE_EXECUTE_LOOP_ADDRESS ," in_EXECUTE_EXECUTE_LOOP_ADDRESS ",T general_data_t,_param->_nb_execute_loop,_param->_nb_write_unit[it1]);154 ALLOC2_SC_SIGNAL( in_EXECUTE_EXECUTE_LOOP_ADDRESS ," in_EXECUTE_EXECUTE_LOOP_ADDRESS ",Taddress_t ,_param->_nb_execute_loop,_param->_nb_write_unit[it1]); 155 155 ALLOC2_SC_SIGNAL( in_EXECUTE_EXECUTE_LOOP_DATA ," in_EXECUTE_EXECUTE_LOOP_DATA ",Tgeneral_data_t ,_param->_nb_execute_loop,_param->_nb_write_unit[it1]); 156 156 ALLOC2_SC_SIGNAL( in_INSERT_OOO_ENGINE_VAL ," in_INSERT_OOO_ENGINE_VAL ",Tcontrol_t ,_param->_nb_ooo_engine,_param->_nb_inst_insert[it1]); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/include/Core_Glue.h
r88 r97 95 95 public : SC_OUT(Taddress_t ) ** out_COMMIT_EVENT_FRONT_END_ADDRESS_EPCR ;//[nb_front_end] 96 96 public : SC_OUT(Tcontrol_t ) ** out_COMMIT_EVENT_FRONT_END_ADDRESS_EEAR_VAL ;//[nb_front_end] 97 public : SC_OUT(T address_t) ** out_COMMIT_EVENT_FRONT_END_ADDRESS_EEAR ;//[nb_front_end]97 public : SC_OUT(Tgeneral_data_t ) ** out_COMMIT_EVENT_FRONT_END_ADDRESS_EEAR ;//[nb_front_end] 98 98 99 99 public : SC_IN (Tcontrol_t ) ** in_COMMIT_EVENT_OOO_ENGINE_VAL ;//[nb_ooo_engine] … … 107 107 public : SC_IN (Taddress_t ) ** in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EPCR ;//[nb_ooo_engine] 108 108 public : SC_IN (Tcontrol_t ) ** in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EEAR_VAL ;//[nb_ooo_engine] 109 public : SC_IN (T address_t) ** in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EEAR ;//[nb_ooo_engine]109 public : SC_IN (Tgeneral_data_t ) ** in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EEAR ;//[nb_ooo_engine] 110 110 111 111 … … 168 168 public : SC_OUT(Texception_t ) **** out_EXECUTE_OOO_ENGINE_EXCEPTION ;//[nb_ooo_engine][ooo_engine_nb_execute_loop][nb_inst_execute] 169 169 public : SC_OUT(Tcontrol_t ) **** out_EXECUTE_OOO_ENGINE_NO_SEQUENCE ;//[nb_ooo_engine][ooo_engine_nb_execute_loop][nb_inst_execute] 170 public : SC_OUT(T general_data_t) **** out_EXECUTE_OOO_ENGINE_ADDRESS ;//[nb_ooo_engine][ooo_engine_nb_execute_loop][nb_inst_execute]170 public : SC_OUT(Taddress_t ) **** out_EXECUTE_OOO_ENGINE_ADDRESS ;//[nb_ooo_engine][ooo_engine_nb_execute_loop][nb_inst_execute] 171 171 public : SC_OUT(Tgeneral_data_t ) **** out_EXECUTE_OOO_ENGINE_DATA ;//[nb_ooo_engine][ooo_engine_nb_execute_loop][nb_inst_execute] 172 172 … … 182 182 public : SC_IN (Texception_t ) *** in_EXECUTE_EXECUTE_LOOP_EXCEPTION ;//[nb_execute_loop][nb_write_unit] 183 183 public : SC_IN (Tcontrol_t ) *** in_EXECUTE_EXECUTE_LOOP_NO_SEQUENCE ;//[nb_execute_loop][nb_write_unit] 184 public : SC_IN (T general_data_t) *** in_EXECUTE_EXECUTE_LOOP_ADDRESS ;//[nb_execute_loop][nb_write_unit]184 public : SC_IN (Taddress_t ) *** in_EXECUTE_EXECUTE_LOOP_ADDRESS ;//[nb_execute_loop][nb_write_unit] 185 185 public : SC_IN (Tgeneral_data_t ) *** in_EXECUTE_EXECUTE_LOOP_DATA ;//[nb_execute_loop][nb_write_unit] 186 186 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_allocation.cpp
r88 r97 97 97 ALLOC1_SIGNAL_OUT(out_COMMIT_EVENT_FRONT_END_IS_DELAY_SLOT ,"IS_DELAY_SLOT" ,Tcontrol_t ,1); 98 98 ALLOC1_SIGNAL_OUT(out_COMMIT_EVENT_FRONT_END_ADDRESS ,"ADDRESS" ,Taddress_t ,_param->_size_instruction_address); 99 ALLOC1_SIGNAL_OUT(out_COMMIT_EVENT_FRONT_END_ADDRESS_EPCR ,"ADDRESS_EPCR" ,Taddress_t ,_param->_size_ spr);99 ALLOC1_SIGNAL_OUT(out_COMMIT_EVENT_FRONT_END_ADDRESS_EPCR ,"ADDRESS_EPCR" ,Taddress_t ,_param->_size_instruction_address); 100 100 ALLOC1_SIGNAL_OUT(out_COMMIT_EVENT_FRONT_END_ADDRESS_EEAR_VAL ,"ADDRESS_EEAR_VAL" ,Tcontrol_t ,1); 101 ALLOC1_SIGNAL_OUT(out_COMMIT_EVENT_FRONT_END_ADDRESS_EEAR ,"ADDRESS_EEAR" ,T address_t ,_param->_size_spr);101 ALLOC1_SIGNAL_OUT(out_COMMIT_EVENT_FRONT_END_ADDRESS_EEAR ,"ADDRESS_EEAR" ,Tgeneral_data_t ,_param->_size_general_data); 102 102 } 103 103 … … 113 113 ALLOC1_SIGNAL_IN ( in_COMMIT_EVENT_OOO_ENGINE_IS_DELAY_SLOT ,"IS_DELAY_SLOT" ,Tcontrol_t ,1); 114 114 ALLOC1_SIGNAL_IN ( in_COMMIT_EVENT_OOO_ENGINE_ADDRESS ,"ADDRESS" ,Taddress_t ,_param->_size_instruction_address); 115 ALLOC1_SIGNAL_IN ( in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EPCR ,"ADDRESS_EPCR" ,Taddress_t ,_param->_size_ spr);115 ALLOC1_SIGNAL_IN ( in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EPCR ,"ADDRESS_EPCR" ,Taddress_t ,_param->_size_instruction_address); 116 116 ALLOC1_SIGNAL_IN ( in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EEAR_VAL ,"ADDRESS_EEAR_VAL" ,Tcontrol_t ,1); 117 ALLOC1_SIGNAL_IN ( in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EEAR ,"ADDRESS_EEAR" ,T address_t ,_param->_size_spr);117 ALLOC1_SIGNAL_IN ( in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EEAR ,"ADDRESS_EEAR" ,Tgeneral_data_t ,_param->_size_general_data); 118 118 } 119 119 … … 186 186 _ALLOC3_SIGNAL_OUT(out_EXECUTE_OOO_ENGINE_EXCEPTION ,"EXCEPTION" ,Texception_t ,_param->_size_exception ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_execute_loop[it1],_param->_nb_inst_execute[it1][it2]); 187 187 _ALLOC3_SIGNAL_OUT(out_EXECUTE_OOO_ENGINE_NO_SEQUENCE ,"NO_SEQUENCE" ,Tcontrol_t ,1 ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_execute_loop[it1],_param->_nb_inst_execute[it1][it2]); 188 _ALLOC3_SIGNAL_OUT(out_EXECUTE_OOO_ENGINE_ADDRESS ,"ADDRESS" ,T general_data_t ,_param->_size_general_data,_param->_nb_ooo_engine,_param->_ooo_engine_nb_execute_loop[it1],_param->_nb_inst_execute[it1][it2]);188 _ALLOC3_SIGNAL_OUT(out_EXECUTE_OOO_ENGINE_ADDRESS ,"ADDRESS" ,Taddress_t ,_param->_size_instruction_address,_param->_nb_ooo_engine,_param->_ooo_engine_nb_execute_loop[it1],_param->_nb_inst_execute[it1][it2]); 189 189 _ALLOC3_SIGNAL_OUT(out_EXECUTE_OOO_ENGINE_DATA ,"DATA" ,Tgeneral_data_t ,_param->_size_general_data,_param->_nb_ooo_engine,_param->_ooo_engine_nb_execute_loop[it1],_param->_nb_inst_execute[it1][it2]); 190 190 } … … 204 204 _ALLOC2_SIGNAL_IN ( in_EXECUTE_EXECUTE_LOOP_EXCEPTION ,"EXCEPTION" ,Texception_t ,_param->_size_exception ,_param->_nb_execute_loop,_param->_nb_write_unit[it1]); 205 205 _ALLOC2_SIGNAL_IN ( in_EXECUTE_EXECUTE_LOOP_NO_SEQUENCE ,"NO_SEQUENCE" ,Tcontrol_t ,1 ,_param->_nb_execute_loop,_param->_nb_write_unit[it1]); 206 _ALLOC2_SIGNAL_IN ( in_EXECUTE_EXECUTE_LOOP_ADDRESS ,"ADDRESS" ,T general_data_t ,_param->_size_general_data,_param->_nb_execute_loop,_param->_nb_write_unit[it1]);206 _ALLOC2_SIGNAL_IN ( in_EXECUTE_EXECUTE_LOOP_ADDRESS ,"ADDRESS" ,Taddress_t ,_param->_size_instruction_address,_param->_nb_execute_loop,_param->_nb_write_unit[it1]); 207 207 _ALLOC2_SIGNAL_IN ( in_EXECUTE_EXECUTE_LOOP_DATA ,"DATA" ,Tgeneral_data_t ,_param->_size_general_data ,_param->_nb_execute_loop,_param->_nb_write_unit[it1]); 208 208 } -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/Operation/include/Types.h
r81 r97 67 67 Texception_t _exception ; 68 68 Tcontrol_t _no_sequence ; 69 T general_data_t_address ;69 Taddress_t _address ; 70 70 } execute_operation_t; 71 71 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/SelfTest/src/test.cpp
r88 r97 145 145 sc_signal<Tpacket_t > out_EXECUTE_OUT_PACKET_ID (rename.c_str()); 146 146 //sc_signal<Toperation_t > out_EXECUTE_OUT_OPERATION (rename.c_str()); 147 147 //sc_signal<Ttype_t > out_EXECUTE_OUT_TYPE (rename.c_str()); 148 148 sc_signal<Tcontrol_t > out_EXECUTE_OUT_WRITE_RD (rename.c_str()); 149 149 sc_signal<Tgeneral_address_t> out_EXECUTE_OUT_NUM_REG_RD (rename.c_str()); … … 200 200 (*(_Functionnal_unit->out_EXECUTE_OUT_PACKET_ID )) (out_EXECUTE_OUT_PACKET_ID ); 201 201 //(*(_Functionnal_unit->out_EXECUTE_OUT_OPERATION )) (out_EXECUTE_OUT_OPERATION ); 202 202 //(*(_Functionnal_unit->out_EXECUTE_OUT_TYPE )) (out_EXECUTE_OUT_TYPE ); 203 203 (*(_Functionnal_unit->out_EXECUTE_OUT_WRITE_RD )) (out_EXECUTE_OUT_WRITE_RD ); 204 204 (*(_Functionnal_unit->out_EXECUTE_OUT_NUM_REG_RD )) (out_EXECUTE_OUT_NUM_REG_RD ); … … 632 632 TEST(Tcontext_t , out_EXECUTE_OUT_OOO_ENGINE_ID.read(), transaction_out.front()._ooo_engine_id); 633 633 //TEST(Toperation_t , out_EXECUTE_OUT_OPERATION .read(), transaction_out.front()._operation ); 634 634 //TEST(Ttype_t , out_EXECUTE_OUT_TYPE .read(), transaction_out.front()._type ); 635 635 TEST(Tcontrol_t , out_EXECUTE_OUT_WRITE_RE .read(), transaction_out.front()._write_re ); 636 636 TEST(Tgeneral_address_t, out_EXECUTE_OUT_NUM_REG_RD .read(), transaction_out.front()._num_reg_rd ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/include/Functionnal_unit.h
r88 r97 106 106 public : SC_OUT(Tpacket_t ) * out_EXECUTE_OUT_PACKET_ID ; 107 107 //public : SC_OUT(Toperation_t ) * out_EXECUTE_OUT_OPERATION ; 108 108 //public : SC_OUT(Ttype_t ) * out_EXECUTE_OUT_TYPE ; 109 109 public : SC_OUT(Tcontrol_t ) * out_EXECUTE_OUT_WRITE_RD ; 110 110 public : SC_OUT(Tgeneral_address_t) * out_EXECUTE_OUT_NUM_REG_RD ; … … 115 115 public : SC_OUT(Texception_t ) * out_EXECUTE_OUT_EXCEPTION ; 116 116 public : SC_OUT(Tcontrol_t ) * out_EXECUTE_OUT_NO_SEQUENCE ; 117 public : SC_OUT(T general_data_t) * out_EXECUTE_OUT_ADDRESS ;117 public : SC_OUT(Taddress_t ) * out_EXECUTE_OUT_ADDRESS ; 118 118 119 119 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_allocation.cpp
r88 r97 105 105 out_EXECUTE_OUT_PACKET_ID = interface->set_signal_out<Tpacket_t > ("packet_id" ,_param->_size_rob_ptr ); 106 106 //out_EXECUTE_OUT_OPERATION = interface->set_signal_out<Toperation_t > ("operation" ,_param->_size_operation ); 107 107 //out_EXECUTE_OUT_TYPE = interface->set_signal_out<Ttype_t > ("type" ,_param->_size_type ); 108 108 out_EXECUTE_OUT_WRITE_RD = interface->set_signal_out<Tcontrol_t > ("write_rd" ,1); 109 109 out_EXECUTE_OUT_NUM_REG_RD = interface->set_signal_out<Tgeneral_address_t> ("num_reg_rd" ,_param->_size_general_register); … … 114 114 out_EXECUTE_OUT_EXCEPTION = interface->set_signal_out<Texception_t > ("exception" ,_param->_size_exception); 115 115 out_EXECUTE_OUT_NO_SEQUENCE = interface->set_signal_out<Tcontrol_t > ("no_sequence" ,1); 116 out_EXECUTE_OUT_ADDRESS = interface->set_signal_out<T general_data_t > ("address" ,_param->_size_general_data);116 out_EXECUTE_OUT_ADDRESS = interface->set_signal_out<Taddress_t > ("address" ,_param->_size_instruction_address); 117 117 } 118 118 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_deallocation.cpp
r88 r97 64 64 if (_param->_have_port_rob_ptr) 65 65 delete out_EXECUTE_OUT_PACKET_ID ; 66 //delete out_EXECUTE_OUT_OPERATION ;67 delete out_EXECUTE_OUT_TYPE ;66 // delete out_EXECUTE_OUT_OPERATION ; 67 // delete out_EXECUTE_OUT_TYPE ; 68 68 delete out_EXECUTE_OUT_WRITE_RD ; 69 69 delete out_EXECUTE_OUT_NUM_REG_RD ; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_genMoore.cpp
r88 r97 45 45 PORT_WRITE(out_EXECUTE_OUT_PACKET_ID ,_execute_operation_out->_packet_id ); 46 46 // PORT_WRITE(out_EXECUTE_OUT_OPERATION ,_execute_operation_out->_operation ); 47 47 // PORT_WRITE(out_EXECUTE_OUT_TYPE ,_execute_operation_out->_type ); 48 48 PORT_WRITE(out_EXECUTE_OUT_WRITE_RD ,_execute_operation_out->_write_rd ); 49 49 PORT_WRITE(out_EXECUTE_OUT_NUM_REG_RD ,_execute_operation_out->_num_reg_rd ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_transition.cpp
r88 r97 95 95 log_printf(TRACE,Functionnal_unit,FUNCTION," * packet_id : %d",_execute_operation_in->_packet_id ); 96 96 log_printf(TRACE,Functionnal_unit,FUNCTION," * operation : %d",_execute_operation_in->_operation ); 97 log_printf(TRACE,Functionnal_unit,FUNCTION," * type : %s",toString _type(_execute_operation_in->_type).c_str());97 log_printf(TRACE,Functionnal_unit,FUNCTION," * type : %s",toString(_execute_operation_in->_type).c_str()); 98 98 log_printf(TRACE,Functionnal_unit,FUNCTION," * has_immediat : %d",_execute_operation_in->_has_immediat ); 99 99 log_printf(TRACE,Functionnal_unit,FUNCTION," * immediat : %.8x",_execute_operation_in->_immediat ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Parameters.cpp
r88 r97 75 75 if (is_toplevel) 76 76 { 77 _size_instruction_address= size_general_data-2; 77 78 _size_context_id = log2(nb_context ); 78 79 _size_front_end_id = log2(nb_front_end ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/src/test2.cpp
r88 r97 97 97 ALLOC1_SC_SIGNAL(out_MEMORY_OUT_PACKET_ID ,"out_MEMORY_OUT_PACKET_ID ",Tpacket_t ,_param->_nb_inst_memory); 98 98 //ALLOC1_SC_SIGNAL(out_MEMORY_OUT_OPERATION ,"out_MEMORY_OUT_OPERATION ",Toperation_t ,_param->_nb_inst_memory); 99 99 //ALLOC1_SC_SIGNAL(out_MEMORY_OUT_TYPE ,"out_MEMORY_OUT_TYPE ",Ttype_t ,_param->_nb_inst_memory); 100 100 ALLOC1_SC_SIGNAL(out_MEMORY_OUT_WRITE_RD ,"out_MEMORY_OUT_WRITE_RD ",Tcontrol_t ,_param->_nb_inst_memory); // = (operation==load) 101 101 ALLOC1_SC_SIGNAL(out_MEMORY_OUT_NUM_REG_RD ,"out_MEMORY_OUT_NUM_REG_RD ",Tgeneral_address_t,_param->_nb_inst_memory); // destination (load) … … 106 106 ALLOC1_SC_SIGNAL(out_MEMORY_OUT_EXCEPTION ,"out_MEMORY_OUT_EXCEPTION ",Texception_t ,_param->_nb_inst_memory); 107 107 ALLOC1_SC_SIGNAL(out_MEMORY_OUT_NO_SEQUENCE ,"out_MEMORY_OUT_NO_SEQUENCE ",Tcontrol_t ,_param->_nb_inst_memory); 108 ALLOC1_SC_SIGNAL(out_MEMORY_OUT_ADDRESS ,"out_MEMORY_OUT_ADDRESS ",T general_data_t,_param->_nb_inst_memory);108 ALLOC1_SC_SIGNAL(out_MEMORY_OUT_ADDRESS ,"out_MEMORY_OUT_ADDRESS ",Taddress_t ,_param->_nb_inst_memory); 109 109 ALLOC1_SC_SIGNAL(out_DCACHE_REQ_VAL ,"out_DCACHE_REQ_VAL ",Tcontrol_t ,_param->_nb_cache_port); 110 110 ALLOC1_SC_SIGNAL( in_DCACHE_REQ_ACK ," in_DCACHE_REQ_ACK ",Tcontrol_t ,_param->_nb_cache_port); … … 169 169 INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_PACKET_ID ,_param->_nb_inst_memory); 170 170 //INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_OPERATION ,_param->_nb_inst_memory); 171 171 //INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_TYPE ,_param->_nb_inst_memory); 172 172 INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_WRITE_RD ,_param->_nb_inst_memory); 173 173 INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_NUM_REG_RD ,_param->_nb_inst_memory); … … 520 520 TEST(Tcontext_t , out_MEMORY_OUT_OOO_ENGINE_ID[0]->read(), tab_request[packet_id]._ooo_engine_id); 521 521 // TEST(Toperation_t , out_MEMORY_OUT_OPERATION [0]->read(), tab_request[packet_id]._operation ); 522 TEST(Ttype_t , out_MEMORY_OUT_TYPE [0]->read(), TYPE_MEMORY );522 // TEST(Ttype_t , out_MEMORY_OUT_TYPE [0]->read(), TYPE_MEMORY ); 523 523 524 524 if (is_operation_memory_load (tab_request[packet_id]._operation)) … … 730 730 DELETE1_SC_SIGNAL(out_MEMORY_OUT_PACKET_ID ,_param->_nb_inst_memory); 731 731 //DELETE1_SC_SIGNAL(out_MEMORY_OUT_OPERATION ,_param->_nb_inst_memory); 732 732 //DELETE1_SC_SIGNAL(out_MEMORY_OUT_TYPE ,_param->_nb_inst_memory); 733 733 DELETE1_SC_SIGNAL(out_MEMORY_OUT_WRITE_RD ,_param->_nb_inst_memory); 734 734 DELETE1_SC_SIGNAL(out_MEMORY_OUT_NUM_REG_RD ,_param->_nb_inst_memory); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h
r88 r97 118 118 public : SC_OUT(Tpacket_t ) ** out_MEMORY_OUT_PACKET_ID ;//[nb_inst_memory] 119 119 //public : SC_OUT(Toperation_t ) ** out_MEMORY_OUT_OPERATION ;//[nb_inst_memory] 120 120 //public : SC_OUT(Ttype_t ) ** out_MEMORY_OUT_TYPE ;//[nb_inst_memory] 121 121 public : SC_OUT(Tcontrol_t ) ** out_MEMORY_OUT_WRITE_RD ;//[nb_inst_memory] // = (operation==load) 122 122 public : SC_OUT(Tgeneral_address_t) ** out_MEMORY_OUT_NUM_REG_RD ;//[nb_inst_memory] // destination (load) … … 127 127 public : SC_OUT(Texception_t ) ** out_MEMORY_OUT_EXCEPTION ;//[nb_inst_memory] 128 128 public : SC_OUT(Tcontrol_t ) ** out_MEMORY_OUT_NO_SEQUENCE ;//[nb_inst_memory] 129 public : SC_OUT(T general_data_t) ** out_MEMORY_OUT_ADDRESS ;//[nb_inst_memory]129 public : SC_OUT(Taddress_t ) ** out_MEMORY_OUT_ADDRESS ;//[nb_inst_memory] 130 130 131 131 // ~~~~~[ Interface "dcache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Types.h
r81 r97 235 235 }; 236 236 237 238 template<> inline std::string toString<morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Tstore_queue_state_t>(const morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Tstore_queue_state_t& x) 239 { 240 switch (x) 241 { 242 case morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::STORE_QUEUE_EMPTY : return "empty" ; break; 243 case morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::STORE_QUEUE_NO_VALID_NO_SPECULATIVE : return "no_valid_no_speculative"; break; 244 case morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::STORE_QUEUE_VALID_SPECULATIVE : return "valid_speculative" ; break; 245 case morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::STORE_QUEUE_VALID_NO_SPECULATIVE : return "valid_no_speculative" ; break; 246 case morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::STORE_QUEUE_COMMIT : return "commit" ; break; 247 default : return "" ; break; 248 } 249 }; 250 251 template<> inline std::string toString<morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Tspeculative_access_queue_state_t>(const morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Tspeculative_access_queue_state_t& x) 252 { 253 switch (x) 254 { 255 case morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::SPECULATIVE_ACCESS_QUEUE_EMPTY : return "empty" ; break; 256 case morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::SPECULATIVE_ACCESS_QUEUE_WAIT_CACHE : return "wait_cache" ; break; 257 case morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::SPECULATIVE_ACCESS_QUEUE_WAIT_LOAD_QUEUE : return "wait_load_queue"; break; 258 default : return "" ; break; 259 } 260 }; 261 262 template<> inline std::string toString<morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Tload_queue_state_t>(const morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Tload_queue_state_t& x) 263 { 264 switch (x) 265 { 266 case morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::LOAD_QUEUE_EMPTY : return "empty" ; break; 267 case morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::LOAD_QUEUE_WAIT_CHECK : return "wait_check" ; break; 268 case morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::LOAD_QUEUE_WAIT : return "wait" ; break; 269 case morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::LOAD_QUEUE_COMMIT_CHECK : return "commit_check"; break; 270 case morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::LOAD_QUEUE_CHECK : return "check" ; break; 271 case morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::LOAD_QUEUE_COMMIT : return "commit" ; break; 272 default : return "" ; break; 273 } 274 }; 275 237 276 }; // end namespace morpheo 238 277 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_allocation.cpp
r88 r97 72 72 ALLOC1_SIGNAL_IN ( in_MEMORY_IN_DATA_RC ,"data_rc" ,Tspecial_data_t ,_param->_size_special_data ); 73 73 ALLOC1_SIGNAL_IN ( in_MEMORY_IN_WRITE_RD ,"write_rd" ,Tcontrol_t ,1 ); 74 ALLOC1_SIGNAL_IN ( in_MEMORY_IN_NUM_REG_RD ,"num_reg_rd" ,Tgeneral_address_t, 1);74 ALLOC1_SIGNAL_IN ( in_MEMORY_IN_NUM_REG_RD ,"num_reg_rd" ,Tgeneral_address_t,_param->_size_general_register ); 75 75 ALLOC1_SIGNAL_IN ( in_MEMORY_IN_WRITE_RE ,"write_re" ,Tcontrol_t ,1 ); 76 ALLOC1_SIGNAL_IN ( in_MEMORY_IN_NUM_REG_RE ,"num_reg_re" ,Tspecial_address_t, 1);76 ALLOC1_SIGNAL_IN ( in_MEMORY_IN_NUM_REG_RE ,"num_reg_re" ,Tspecial_address_t,_param->_size_special_register ); 77 77 } 78 78 … … 88 88 ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_rob_ptr ); 89 89 // ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation ); 90 90 // ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_TYPE ,"type" ,Ttype_t ,_param->_size_type ); 91 91 ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_WRITE_RD ,"write_rd" ,Tcontrol_t ,1 ); 92 92 ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_NUM_REG_RD ,"num_reg_rd" ,Tgeneral_address_t,_param->_size_general_register ); 93 93 ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_DATA_RD ,"data_rd" ,Tgeneral_data_t ,_param->_size_general_data ); 94 94 ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_WRITE_RE ,"write_re" ,Tcontrol_t ,1 ); 95 ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_NUM_REG_RE ,"num_reg_re" ,Tspecial_address_t,_param->_size_ general_register );96 ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_DATA_RE ,"data_re" ,Tspecial_data_t ,_param->_size_ general_data );95 ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_NUM_REG_RE ,"num_reg_re" ,Tspecial_address_t,_param->_size_special_register ); 96 ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_DATA_RE ,"data_re" ,Tspecial_data_t ,_param->_size_special_data ); 97 97 ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception ); 98 98 ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_NO_SEQUENCE ,"no_sequence" ,Tcontrol_t ,1 ); 99 ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_ADDRESS ,"address" ,T general_data_t ,_param->_size_general_data);99 ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address); 100 100 } 101 101 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_deallocation.cpp
r88 r97 63 63 DELETE1_SIGNAL(out_MEMORY_OUT_PACKET_ID ,_param->_nb_inst_memory,_param->_size_rob_ptr ); 64 64 // DELETE1_SIGNAL(out_MEMORY_OUT_OPERATION ,_param->_nb_inst_memory,_param->_size_operation ); 65 65 // DELETE1_SIGNAL(out_MEMORY_OUT_TYPE ,_param->_nb_inst_memory,_param->_size_type ); 66 66 DELETE1_SIGNAL(out_MEMORY_OUT_WRITE_RD ,_param->_nb_inst_memory,1 ); 67 67 DELETE1_SIGNAL(out_MEMORY_OUT_NUM_REG_RD ,_param->_nb_inst_memory,_param->_size_general_register ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMoore.cpp
r88 r97 121 121 PORT_WRITE(out_MEMORY_OUT_PACKET_ID [0], memory_out_packet_id ); 122 122 // PORT_WRITE(out_MEMORY_OUT_OPERATION [0], memory_out_operation ); 123 123 // PORT_WRITE(out_MEMORY_OUT_TYPE [0], TYPE_MEMORY ); 124 124 PORT_WRITE(out_MEMORY_OUT_WRITE_RD [0], memory_out_write_rd ); 125 125 PORT_WRITE(out_MEMORY_OUT_NUM_REG_RD [0], memory_out_num_reg_rd ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_transition.cpp
r88 r97 23 23 void Load_store_unit::function_speculative_load_commit_transition (void) 24 24 { 25 log_printf(FUNC,Load_store_unit,FUNCTION,"Begin"); 25 log_begin(Load_store_unit,FUNCTION); 26 log_function(Load_store_unit,FUNCTION,_name.c_str()); 26 27 27 28 if (PORT_READ(in_NRESET) == 0) … … 53 54 54 55 // solution 1) 55 log_printf(TRACE,Load_store_unit,FUNCTION," CHECK");56 log_printf(TRACE,Load_store_unit,FUNCTION," * CHECK"); 56 57 for (uint32_t i=0, nb_check=0; (nb_check<_param->_nb_port_check) and (i<_param->_size_load_queue); i++) 57 58 { … … 63 64 is_operation_memory_load(_load_queue[index_load]._operation)) 64 65 { 65 log_printf(TRACE,Load_store_unit,FUNCTION," * Find a load : %d",index_load);66 log_printf(TRACE,Load_store_unit,FUNCTION," * Find a load : %d",index_load); 66 67 67 68 nb_check++; // use one port … … 283 284 // - second is the information of re order buffer : the store become not speculative and can access at the data cache 284 285 285 log_printf(TRACE,Load_store_unit,FUNCTION," store_queue");286 log_printf(TRACE,Load_store_unit,FUNCTION," * PUSH");286 log_printf(TRACE,Load_store_unit,FUNCTION," * store_queue"); 287 log_printf(TRACE,Load_store_unit,FUNCTION," * PUSH"); 287 288 288 289 // Write pointer is define in rename stage : 289 290 Tlsq_ptr_t index = PORT_READ(in_MEMORY_IN_STORE_QUEUE_PTR_WRITE[internal_MEMORY_IN_PORT]); 290 log_printf(TRACE,Load_store_unit,FUNCTION," * index : %d",index);291 log_printf(TRACE,Load_store_unit,FUNCTION," * index : %d",index); 291 292 292 293 // Need read : state and exception. … … 373 374 if (update_info == true) 374 375 { 375 log_printf(TRACE,Load_store_unit,FUNCTION," * Update information");376 log_printf(TRACE,Load_store_unit,FUNCTION," * Update information"); 376 377 377 378 _store_queue [index]._context_id = (not _param->_have_port_context_id )?0:PORT_READ(in_MEMORY_IN_CONTEXT_ID [internal_MEMORY_IN_PORT]); … … 395 396 396 397 // In speculative access queue, they are many type's request 397 log_printf(TRACE,Load_store_unit,FUNCTION," speculative_access_queue");398 log_printf(TRACE,Load_store_unit,FUNCTION," * PUSH");398 log_printf(TRACE,Load_store_unit,FUNCTION," * speculative_access_queue"); 399 log_printf(TRACE,Load_store_unit,FUNCTION," * PUSH"); 399 400 400 401 // Write in reservation station 401 402 uint32_t index = _speculative_access_queue_control->push(); 402 403 403 log_printf(TRACE,Load_store_unit,FUNCTION," * index : %d", index);404 log_printf(TRACE,Load_store_unit,FUNCTION," * index : %d", index); 404 405 405 406 Texception_t exception; … … 428 429 _speculative_access_queue [index]._exception = exception; 429 430 430 log_printf(TRACE,Load_store_unit,FUNCTION," * index : %d",index);431 log_printf(TRACE,Load_store_unit,FUNCTION," * index : %d",index); 431 432 } 432 433 } … … 439 440 (PORT_READ(in_MEMORY_OUT_ACK[0]) == 1)) 440 441 { 441 log_printf(TRACE,Load_store_unit,FUNCTION," MEMORY_OUT transaction");442 log_printf(TRACE,Load_store_unit,FUNCTION," * MEMORY_OUT transaction"); 442 443 443 444 switch (internal_MEMORY_OUT_SELECT_QUEUE) … … 449 450 // ======================= 450 451 451 log_printf(TRACE,Load_store_unit,FUNCTION," * store_queue [%d]",reg_STORE_QUEUE_PTR_READ);452 log_printf(TRACE,Load_store_unit,FUNCTION," * store_queue [%d]",reg_STORE_QUEUE_PTR_READ); 452 453 453 454 // Entry flush and increase the read pointer … … 464 465 // ====================== 465 466 466 log_printf(TRACE,Load_store_unit,FUNCTION," * load_queue [%d]",internal_MEMORY_OUT_PTR);467 log_printf(TRACE,Load_store_unit,FUNCTION," * load_queue [%d]",internal_MEMORY_OUT_PTR); 467 468 468 469 // Entry flush and increase the read pointer … … 476 477 case SELECT_LOAD_QUEUE_SPECULATIVE : 477 478 { 478 log_printf(TRACE,Load_store_unit,FUNCTION," * load_queue [%d] (speculative)",internal_MEMORY_OUT_PTR);479 log_printf(TRACE,Load_store_unit,FUNCTION," * load_queue [%d] (speculative)",internal_MEMORY_OUT_PTR); 479 480 480 481 _load_queue [internal_MEMORY_OUT_PTR]._state = LOAD_QUEUE_CHECK; … … 497 498 (PORT_READ(in_DCACHE_REQ_ACK[0]) == 1)) 498 499 { 499 log_printf(TRACE,Load_store_unit,FUNCTION," DCACHE_REQ");500 log_printf(TRACE,Load_store_unit,FUNCTION," * DCACHE_REQ"); 500 501 501 502 switch (internal_DCACHE_REQ_SELECT_QUEUE) … … 587 588 _load_queue [ptr_write]._rdata = address; // to the exception 588 589 589 log_printf(TRACE,Load_store_unit,FUNCTION," * speculative_access_queue");590 log_printf(TRACE,Load_store_unit,FUNCTION," * POP[%d]",(*_speculative_access_queue_control)[0]);590 log_printf(TRACE,Load_store_unit,FUNCTION," * speculative_access_queue"); 591 log_printf(TRACE,Load_store_unit,FUNCTION," * POP[%d]",(*_speculative_access_queue_control)[0]); 591 592 592 593 _speculative_access_queue [(*_speculative_access_queue_control)[0]]._state = SPECULATIVE_ACCESS_QUEUE_EMPTY; … … 601 602 ( internal_DCACHE_RSP_ACK == 1)) 602 603 { 603 log_printf(TRACE,Load_store_unit,FUNCTION," DCACHE_RSP");604 log_printf(TRACE,Load_store_unit,FUNCTION," * DCACHE_RSP"); 604 605 605 606 // don't use context_id : because there are one queue for all thread … … 609 610 Tdcache_error_t error = PORT_READ(in_DCACHE_RSP_ERROR [0]); 610 611 611 log_printf(TRACE,Load_store_unit,FUNCTION," * original packet_id : %d", packet_id);612 log_printf(TRACE,Load_store_unit,FUNCTION," * original packet_id : %d", packet_id); 612 613 613 614 if (DCACHE_RSP_IS_LOAD(packet_id) == 1) … … 615 616 packet_id >>= 1; 616 617 617 log_printf(TRACE,Load_store_unit,FUNCTION," * packet is a LOAD : %d", packet_id);618 log_printf(TRACE,Load_store_unit,FUNCTION," * packet is a LOAD : %d", packet_id); 618 619 619 620 … … 626 627 if (error != DCACHE_ERROR_NONE) 627 628 { 628 log_printf(TRACE,Load_store_unit,FUNCTION," * have a bus error !!!");629 log_printf(TRACE,Load_store_unit,FUNCTION," * have a bus error !!!"); 629 630 630 631 _load_queue [packet_id]._exception = EXCEPTION_MEMORY_BUS_ERROR; … … 633 634 else 634 635 { 635 log_printf(TRACE,Load_store_unit,FUNCTION," * have no bus error.");636 log_printf(TRACE,Load_store_unit,FUNCTION," * previous state : %d.",_load_queue [packet_id]._state);636 log_printf(TRACE,Load_store_unit,FUNCTION," * have no bus error."); 637 log_printf(TRACE,Load_store_unit,FUNCTION," * previous state : %d.",_load_queue [packet_id]._state); 637 638 638 639 // FIXME : convention : if bus error, the cache return the fautive address ! … … 650 651 else 651 652 { 652 log_printf(TRACE,Load_store_unit,FUNCTION," * packet is a STORE");653 log_printf(TRACE,Load_store_unit,FUNCTION," * packet is a STORE"); 653 654 654 655 // TODO : les stores ne génére pas de réponse sauf quand c'est un bus error !!! … … 664 665 #if defined(DEBUG) and (DEBUG>=DEBUG_TRACE) 665 666 // ***** dump store queue 666 std::cout << "Dump STORE_QUEUE :" << std::endl 667 << "ptr_read : " << toString(static_cast<uint32_t>(reg_STORE_QUEUE_PTR_READ)) << std::endl;667 log_printf(TRACE,Load_store_unit,FUNCTION," * Dump STORE_QUEUE"); 668 log_printf(TRACE,Load_store_unit,FUNCTION," * ptr_read : %d",reg_STORE_QUEUE_PTR_READ); 668 669 669 670 for (uint32_t i=0; i<_param->_size_store_queue; i++) 670 671 { 671 672 uint32_t j = (reg_STORE_QUEUE_PTR_READ+i)%_param->_size_store_queue; 672 std::cout << "{" << j << "}" << std::endl 673 << _store_queue[j] << std::endl; 673 674 log_printf(TRACE,Load_store_unit,FUNCTION," [%.4d] %.4d %.4d %.4d, %.4d, %.4d, %.4d, %.8x %.8x, %.2d, %s", 675 j, 676 _store_queue[j]._context_id , 677 _store_queue[j]._front_end_id , 678 _store_queue[j]._ooo_engine_id , 679 _store_queue[j]._packet_id , 680 _store_queue[j]._operation , 681 _store_queue[j]._load_queue_ptr_write, 682 _store_queue[j]._address , 683 _store_queue[j]._wdata , 684 //_store_queue[j]._write_rd , 685 //_store_queue[j]._num_reg_rd , 686 _store_queue[j]._exception , 687 toString(_store_queue[j]._state).c_str()); 674 688 } 675 689 676 690 // ***** dump speculative_access queue 677 std::cout << "Dump SPECULATIVE_ACCESS_QUEUE :" << std::endl;691 log_printf(TRACE,Load_store_unit,FUNCTION," * Dump SPECULATIVE_ACCESS_QUEUE"); 678 692 679 693 for (uint32_t i=0; i<_param->_size_speculative_access_queue; i++) 680 694 { 681 695 uint32_t j = (*_speculative_access_queue_control)[i]; 682 std::cout << "{" << j << "}" << std::endl 683 << _speculative_access_queue[j] << std::endl; 696 697 log_printf(TRACE,Load_store_unit,FUNCTION," [%.4d] %.4d %.4d %.4d, %.4d, %.4d, %.4d %.4d, %.8x, %.1d %.6d, %.2d, %s", 698 j, 699 _speculative_access_queue[j]._context_id , 700 _speculative_access_queue[j]._front_end_id , 701 _speculative_access_queue[j]._ooo_engine_id , 702 _speculative_access_queue[j]._packet_id , 703 _speculative_access_queue[j]._operation , 704 _speculative_access_queue[j]._load_queue_ptr_write, 705 _speculative_access_queue[j]._store_queue_ptr_write, 706 _speculative_access_queue[j]._address , 707 _speculative_access_queue[j]._write_rd , 708 _speculative_access_queue[j]._num_reg_rd , 709 _speculative_access_queue[j]._exception , 710 toString(_speculative_access_queue[j]._state).c_str()); 684 711 } 685 712 686 713 // ***** dump load queue 687 std::cout << "Dump LOAD_QUEUE :" << std::endl688 << "ptr_read_check_priority : " << toString(static_cast<uint32_t>(reg_LOAD_QUEUE_CHECK_PRIORITY)) << std::endl;714 log_printf(TRACE,Load_store_unit,FUNCTION," * Dump LOAD_QUEUE"); 715 log_printf(TRACE,Load_store_unit,FUNCTION," * ptr_read_check_priority : %d",reg_LOAD_QUEUE_CHECK_PRIORITY); 689 716 690 717 for (uint32_t i=0; i<_param->_size_load_queue; i++) 691 718 { 692 719 uint32_t j = i; 693 std::cout << "{" << j << "}" << std::endl 694 << _load_queue[j] << std::endl; 720 721 log_printf(TRACE,Load_store_unit,FUNCTION," [%.4d] %.4d %.4d %.4d, %.4d, %.4d, %.4d, %.8x %.1x %.1d %.2d %.1d %.2d, %.8x, %.1d %.6d, %.2d, %s", 722 j, 723 _load_queue[j]._context_id , 724 _load_queue[j]._front_end_id , 725 _load_queue[j]._ooo_engine_id , 726 _load_queue[j]._packet_id , 727 _load_queue[j]._operation , 728 _load_queue[j]._store_queue_ptr_write, 729 _load_queue[j]._address , 730 _load_queue[j]._check_hit_byte , 731 _load_queue[j]._check_hit , 732 _load_queue[j]._shift , 733 _load_queue[j]._is_load_signed , 734 _load_queue[j]._access_size , 735 _load_queue[j]._rdata , 736 _load_queue[j]._write_rd , 737 _load_queue[j]._num_reg_rd , 738 _load_queue[j]._exception , 739 toString(_load_queue[j]._state).c_str()); 695 740 } 696 741 #endif … … 712 757 } 713 758 714 log_ printf(FUNC,Load_store_unit,FUNCTION,"End");759 log_end(Load_store_unit,FUNCTION); 715 760 }; 716 761 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Parameters.cpp
r88 r97 69 69 if (is_toplevel) 70 70 { 71 _size_instruction_address = size_general_data-2; 71 72 _size_context_id = log2(nb_context ); 72 73 _size_front_end_id = log2(nb_front_end ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_transition.cpp
r88 r97 190 190 _queue_head->_num_reg_re , 191 191 192 toString _type(_queue_head->_type).c_str());192 toString(_queue_head->_type).c_str()); 193 193 194 194 … … 240 240 (*it)->_num_reg_re , 241 241 242 toString _type((*it)->_type).c_str());242 toString((*it)->_type).c_str()); 243 243 244 244 ++i; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_vhdl_body.cpp
r81 r97 22 22 { 23 23 log_printf(FUNC,Read_queue,"vhdl_body","Begin"); 24 vhdl->set_body ("");25 vhdl->set_body( "");26 vhdl->set_body( "-----------------------------------");27 vhdl->set_body( "-- Instance queue ");28 vhdl->set_body( "-----------------------------------");29 vhdl->set_body( "");30 31 vhdl->set_body( "instance_"+_name+"_queue : "+_name+"_queue");32 vhdl->set_body( "port map (");33 vhdl->set_body( "\tin_CLOCK \t=>\t in_CLOCK ");34 vhdl->set_body( "\t, in_NRESET \t=>\t in_NRESET");35 vhdl->set_body( "\t, in_INSERT_VAL \t=>\tinternal_QUEUE_INSERT_VAL");36 vhdl->set_body( "\t,out_INSERT_ACK \t=>\tinternal_QUEUE_INSERT_ACK");37 vhdl->set_body( "\t, in_INSERT_DATA \t=>\tinternal_QUEUE_INSERT_DATA");38 vhdl->set_body( "\t,out_RETIRE_VAL \t=>\tinternal_QUEUE_RETIRE_VAL");39 vhdl->set_body( "\t, in_RETIRE_ACK \t=>\tinternal_QUEUE_RETIRE_ACK");40 vhdl->set_body( "\t,out_RETIRE_DATA \t=>\tinternal_QUEUE_RETIRE_DATA");41 vhdl->set_body( ");");42 43 vhdl->set_body( "");44 vhdl->set_body( "-----------------------------------");45 vhdl->set_body( "-- Queue_data ");46 vhdl->set_body( "-----------------------------------");47 vhdl->set_body( "");24 vhdl->set_body(0,""); 25 vhdl->set_body(0,""); 26 vhdl->set_body(0,"-----------------------------------"); 27 vhdl->set_body(0,"-- Instance queue "); 28 vhdl->set_body(0,"-----------------------------------"); 29 vhdl->set_body(0,""); 30 31 vhdl->set_body(0,"instance_"+_name+"_queue : "+_name+"_queue"); 32 vhdl->set_body(0,"port map ("); 33 vhdl->set_body(1," in_CLOCK \t=>\t in_CLOCK "); 34 vhdl->set_body(1,", in_NRESET \t=>\t in_NRESET"); 35 vhdl->set_body(1,", in_INSERT_VAL \t=>\tinternal_QUEUE_INSERT_VAL"); 36 vhdl->set_body(1,",out_INSERT_ACK \t=>\tinternal_QUEUE_INSERT_ACK"); 37 vhdl->set_body(1,", in_INSERT_DATA \t=>\tinternal_QUEUE_INSERT_DATA"); 38 vhdl->set_body(1,",out_RETIRE_VAL \t=>\tinternal_QUEUE_RETIRE_VAL"); 39 vhdl->set_body(1,", in_RETIRE_ACK \t=>\tinternal_QUEUE_RETIRE_ACK"); 40 vhdl->set_body(1,",out_RETIRE_DATA \t=>\tinternal_QUEUE_RETIRE_DATA"); 41 vhdl->set_body(0,");"); 42 43 vhdl->set_body(0,""); 44 vhdl->set_body(0,"-----------------------------------"); 45 vhdl->set_body(0,"-- Queue_data "); 46 vhdl->set_body(0,"-----------------------------------"); 47 vhdl->set_body(0,""); 48 48 49 49 uint32_t min = 0; … … 53 53 { 54 54 max = min-1+_param->_size_context_id; 55 vhdl->set_body ("internal_QUEUE_INSERT_DATA"+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_READ_QUEUE_IN_CONTEXT_ID;");55 vhdl->set_body(0,"internal_QUEUE_INSERT_DATA"+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_READ_QUEUE_IN_CONTEXT_ID;"); 56 56 min = max+1; 57 57 } … … 59 59 { 60 60 max = min-1+_param->_size_front_end_id; 61 vhdl->set_body ("internal_QUEUE_INSERT_DATA"+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_READ_QUEUE_IN_FRONT_END_ID;");61 vhdl->set_body(0,"internal_QUEUE_INSERT_DATA"+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_READ_QUEUE_IN_FRONT_END_ID;"); 62 62 min = max+1; 63 63 } … … 65 65 { 66 66 max = min-1+_param->_size_ooo_engine_id; 67 vhdl->set_body ("internal_QUEUE_INSERT_DATA"+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_READ_QUEUE_IN_OOO_ENGINE_ID;");67 vhdl->set_body(0,"internal_QUEUE_INSERT_DATA"+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_READ_QUEUE_IN_OOO_ENGINE_ID;"); 68 68 min = max+1; 69 69 } 70 if(_param->_have_port_rob_ id)71 { 72 max = min-1+_param->_size_rob_ id;73 vhdl->set_body ("internal_QUEUE_INSERT_DATA"+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_READ_QUEUE_IN_ROB_ID;");70 if(_param->_have_port_rob_ptr ) 71 { 72 max = min-1+_param->_size_rob_ptr ; 73 vhdl->set_body(0,"internal_QUEUE_INSERT_DATA"+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_READ_QUEUE_IN_ROB_ID;"); 74 74 min = max+1; 75 75 } 76 76 77 77 max = min-1+_param->_size_operation; 78 vhdl->set_body ("internal_QUEUE_INSERT_DATA"+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_READ_QUEUE_IN_OPERATION;");78 vhdl->set_body(0,"internal_QUEUE_INSERT_DATA"+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_READ_QUEUE_IN_OPERATION;"); 79 79 min = max+1; 80 80 81 81 max = min-1+_param->_size_type; 82 vhdl->set_body ("internal_QUEUE_INSERT_DATA"+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_READ_QUEUE_IN_TYPE;");83 min = max+1; 84 85 max = min; 86 vhdl->set_body ("internal_QUEUE_INSERT_DATA"+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_READ_QUEUE_IN_HAS_IMMEDIAT;");82 vhdl->set_body(0,"internal_QUEUE_INSERT_DATA"+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_READ_QUEUE_IN_TYPE;"); 83 min = max+1; 84 85 max = min; 86 vhdl->set_body(0,"internal_QUEUE_INSERT_DATA"+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_READ_QUEUE_IN_HAS_IMMEDIAT;"); 87 87 min = max+1; 88 88 89 89 max = min-1+_param->_size_general_data; 90 vhdl->set_body ("internal_QUEUE_INSERT_DATA"+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_READ_QUEUE_IN_IMMEDIAT;");91 min = max+1; 92 93 max = min; 94 vhdl->set_body ("internal_QUEUE_INSERT_DATA"+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_READ_QUEUE_IN_READ_RA;");90 vhdl->set_body(0,"internal_QUEUE_INSERT_DATA"+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_READ_QUEUE_IN_IMMEDIAT;"); 91 min = max+1; 92 93 max = min; 94 vhdl->set_body(0,"internal_QUEUE_INSERT_DATA"+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_READ_QUEUE_IN_READ_RA;"); 95 95 min = max+1; 96 96 97 97 max = min-1+_param->_size_general_register; 98 vhdl->set_body ("internal_QUEUE_INSERT_DATA"+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_READ_QUEUE_IN_NUM_REG_RA;");99 min = max+1; 100 101 max = min; 102 vhdl->set_body ("internal_QUEUE_INSERT_DATA"+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_READ_QUEUE_IN_READ_RB;");98 vhdl->set_body(0,"internal_QUEUE_INSERT_DATA"+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_READ_QUEUE_IN_NUM_REG_RA;"); 99 min = max+1; 100 101 max = min; 102 vhdl->set_body(0,"internal_QUEUE_INSERT_DATA"+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_READ_QUEUE_IN_READ_RB;"); 103 103 min = max+1; 104 104 105 105 max = min-1+_param->_size_general_register; 106 vhdl->set_body ("internal_QUEUE_INSERT_DATA"+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_READ_QUEUE_IN_NUM_REG_RB;");107 min = max+1; 108 109 max = min; 110 vhdl->set_body ("internal_QUEUE_INSERT_DATA"+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_READ_QUEUE_IN_READ_RC;");106 vhdl->set_body(0,"internal_QUEUE_INSERT_DATA"+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_READ_QUEUE_IN_NUM_REG_RB;"); 107 min = max+1; 108 109 max = min; 110 vhdl->set_body(0,"internal_QUEUE_INSERT_DATA"+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_READ_QUEUE_IN_READ_RC;"); 111 111 min = max+1; 112 112 113 113 max = min-1+_param->_size_special_register; 114 vhdl->set_body ("internal_QUEUE_INSERT_DATA"+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_READ_QUEUE_IN_NUM_REG_RC;");115 min = max+1; 116 117 max = min; 118 vhdl->set_body ("internal_QUEUE_INSERT_DATA"+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_READ_QUEUE_IN_WRITE_RD;");114 vhdl->set_body(0,"internal_QUEUE_INSERT_DATA"+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_READ_QUEUE_IN_NUM_REG_RC;"); 115 min = max+1; 116 117 max = min; 118 vhdl->set_body(0,"internal_QUEUE_INSERT_DATA"+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_READ_QUEUE_IN_WRITE_RD;"); 119 119 min = max+1; 120 120 121 121 max = min-1+_param->_size_general_register; 122 vhdl->set_body ("internal_QUEUE_INSERT_DATA"+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_READ_QUEUE_IN_NUM_REG_RD;");123 min = max+1; 124 125 max = min; 126 vhdl->set_body ("internal_QUEUE_INSERT_DATA"+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_READ_QUEUE_IN_WRITE_RE;");122 vhdl->set_body(0,"internal_QUEUE_INSERT_DATA"+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_READ_QUEUE_IN_NUM_REG_RD;"); 123 min = max+1; 124 125 max = min; 126 vhdl->set_body(0,"internal_QUEUE_INSERT_DATA"+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_READ_QUEUE_IN_WRITE_RE;"); 127 127 min = max+1; 128 128 129 129 max = min-1+_param->_size_special_register; 130 vhdl->set_body ("internal_QUEUE_INSERT_DATA"+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_READ_QUEUE_IN_NUM_REG_RE;");131 min = max+1; 132 133 vhdl->set_body ("internal_QUEUE_RETIRE_ACK <= internal_READ_QUEUE_OUT_VAL and in_READ_QUEUE_OUT_ACK;");134 135 vhdl->set_body( "");136 vhdl->set_body( "-----------------------------------");137 vhdl->set_body( "-- Interface read");138 vhdl->set_body( "-----------------------------------");139 vhdl->set_body( "");140 vhdl->set_body( "-- GPR");141 vhdl->set_body ("out_GPR_READ_0_VAL <= internal_QUEUE_RETIRE_VAL and internal_READ_RA_VAL;");142 vhdl->set_body ("out_GPR_READ_1_VAL <= internal_QUEUE_RETIRE_VAL and internal_READ_RB_VAL;");130 vhdl->set_body(0,"internal_QUEUE_INSERT_DATA"+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_READ_QUEUE_IN_NUM_REG_RE;"); 131 min = max+1; 132 133 vhdl->set_body(0,"internal_QUEUE_RETIRE_ACK <= internal_READ_QUEUE_OUT_VAL and in_READ_QUEUE_OUT_ACK;"); 134 135 vhdl->set_body(0,""); 136 vhdl->set_body(0,"-----------------------------------"); 137 vhdl->set_body(0,"-- Interface read"); 138 vhdl->set_body(0,"-----------------------------------"); 139 vhdl->set_body(0,""); 140 vhdl->set_body(0,"-- GPR"); 141 vhdl->set_body(0,"out_GPR_READ_0_VAL <= internal_QUEUE_RETIRE_VAL and internal_READ_RA_VAL;"); 142 vhdl->set_body(0,"out_GPR_READ_1_VAL <= internal_QUEUE_RETIRE_VAL and internal_READ_RB_VAL;"); 143 143 if(_param->_have_port_ooo_engine_id) 144 144 { 145 vhdl->set_body ("out_GPR_READ_0_OOO_ENGINE_ID <= internal_OOO_ENGINE_ID;");146 vhdl->set_body ("out_GPR_READ_1_OOO_ENGINE_ID <= internal_OOO_ENGINE_ID;");147 } 148 vhdl->set_body ("out_GPR_READ_0_NUM_REG <= internal_NUM_REG_RA;");149 vhdl->set_body ("out_GPR_READ_1_NUM_REG <= internal_NUM_REG_RB;");150 vhdl->set_body( "");151 152 vhdl->set_body( "-- SPR");153 vhdl->set_body ("out_SPR_READ_0_VAL <= internal_QUEUE_RETIRE_VAL and internal_READ_RC_VAL;");145 vhdl->set_body(0,"out_GPR_READ_0_OOO_ENGINE_ID <= internal_OOO_ENGINE_ID;"); 146 vhdl->set_body(0,"out_GPR_READ_1_OOO_ENGINE_ID <= internal_OOO_ENGINE_ID;"); 147 } 148 vhdl->set_body(0,"out_GPR_READ_0_NUM_REG <= internal_NUM_REG_RA;"); 149 vhdl->set_body(0,"out_GPR_READ_1_NUM_REG <= internal_NUM_REG_RB;"); 150 vhdl->set_body(0,""); 151 152 vhdl->set_body(0,"-- SPR"); 153 vhdl->set_body(0,"out_SPR_READ_0_VAL <= internal_QUEUE_RETIRE_VAL and internal_READ_RC_VAL;"); 154 154 if(_param->_have_port_ooo_engine_id) 155 155 { 156 vhdl->set_body ("out_SPR_READ_0_OOO_ENGINE_ID <= internal_OOO_ENGINE_ID;");157 } 158 vhdl->set_body ("out_SPR_READ_0_NUM_REG <= internal_NUM_REG_RC;");159 160 vhdl->set_body( "");161 vhdl->set_body( "-----------------------------------");162 vhdl->set_body( "-- Interface read_queue_out");163 vhdl->set_body( "-----------------------------------");164 vhdl->set_body( "");156 vhdl->set_body(0,"out_SPR_READ_0_OOO_ENGINE_ID <= internal_OOO_ENGINE_ID;"); 157 } 158 vhdl->set_body(0,"out_SPR_READ_0_NUM_REG <= internal_NUM_REG_RC;"); 159 160 vhdl->set_body(0,""); 161 vhdl->set_body(0,"-----------------------------------"); 162 vhdl->set_body(0,"-- Interface read_queue_out"); 163 vhdl->set_body(0,"-----------------------------------"); 164 vhdl->set_body(0,""); 165 165 166 166 if(_param->_have_port_context_id ) 167 vhdl->set_body ("out_READ_QUEUE_OUT_CONTEXT_ID <= internal_CONTEXT_ID ;");167 vhdl->set_body(0,"out_READ_QUEUE_OUT_CONTEXT_ID <= internal_CONTEXT_ID ;"); 168 168 if(_param->_have_port_front_end_id ) 169 vhdl->set_body ("out_READ_QUEUE_OUT_FRONT_END_ID <= internal_FRONT_END_ID ;");169 vhdl->set_body(0,"out_READ_QUEUE_OUT_FRONT_END_ID <= internal_FRONT_END_ID ;"); 170 170 if(_param->_have_port_ooo_engine_id ) 171 vhdl->set_body ("out_READ_QUEUE_OUT_OOO_ENGINE_ID <= internal_OOO_ENGINE_ID;");172 if(_param->_have_port_rob_ id)173 vhdl->set_body ("out_READ_QUEUE_OUT_ROB_ID <= internal_ROB_ID ;");174 vhdl->set_body ("out_READ_QUEUE_OUT_OPERATION <= internal_OPERATION ;");175 vhdl->set_body ("out_READ_QUEUE_OUT_TYPE <= internal_TYPE ;");176 vhdl->set_body ("out_READ_QUEUE_OUT_HAS_IMMEDIAT <= internal_HAS_IMMEDIAT ;");177 vhdl->set_body ("out_READ_QUEUE_OUT_IMMEDIAT <= internal_IMMEDIAT ;");178 vhdl->set_body ("out_READ_QUEUE_OUT_READ_RA <= internal_READ_RA ;");179 vhdl->set_body ("out_READ_QUEUE_OUT_NUM_REG_RA <= internal_NUM_REG_RA ;");180 vhdl->set_body ("out_READ_QUEUE_OUT_DATA_RA_VAL <= internal_NEXT_DATA_RA_VAL;");181 vhdl->set_body ("out_READ_QUEUE_OUT_DATA_RA <= internal_NEXT_DATA_RA ;");182 vhdl->set_body ("out_READ_QUEUE_OUT_READ_RB <= internal_READ_RB ;");183 vhdl->set_body ("out_READ_QUEUE_OUT_NUM_REG_RB <= internal_NUM_REG_RB ;");184 vhdl->set_body ("out_READ_QUEUE_OUT_DATA_RB_VAL <= internal_NEXT_DATA_RB_VAL;");185 vhdl->set_body ("out_READ_QUEUE_OUT_DATA_RB <= internal_NEXT_DATA_RB ;");186 vhdl->set_body ("out_READ_QUEUE_OUT_READ_RC <= internal_READ_RC ;");187 vhdl->set_body ("out_READ_QUEUE_OUT_NUM_REG_RC <= internal_NUM_REG_RC ;");188 vhdl->set_body ("out_READ_QUEUE_OUT_DATA_RC_VAL <= internal_NEXT_DATA_RC_VAL;");189 vhdl->set_body ("out_READ_QUEUE_OUT_DATA_RC <= internal_NEXT_DATA_RC ;");190 vhdl->set_body ("out_READ_QUEUE_OUT_WRITE_RD <= internal_WRITE_RD ;");191 vhdl->set_body ("out_READ_QUEUE_OUT_NUM_REG_RD <= internal_NUM_REG_RD ;");192 vhdl->set_body ("out_READ_QUEUE_OUT_WRITE_RE <= internal_WRITE_RE ;");193 vhdl->set_body ("out_READ_QUEUE_OUT_NUM_REG_RE <= internal_NUM_REG_RE ;");194 195 vhdl->set_body( "");196 vhdl->set_body( "-----------------------------------");197 vhdl->set_body( "-- next reg update");198 vhdl->set_body( "-----------------------------------");199 vhdl->set_body( "");200 vhdl->set_body( "-- read_rx_val - 1 : must access at the registerFile (after access, is set at 0)");201 202 { 203 vhdl->set_body( "");204 vhdl->set_body( "internal_NEXT_READ_RA_VAL <=");205 vhdl->set_body( "\t'0' when");206 // bypass 207 vhdl->set_body( "\t\t-- check bypass");208 for (int32_t i=_param->_nb_gpr_write-1; i>=0 ; i--) 209 { 210 std::string cmp; 211 212 if (_param->_have_port_ooo_engine_id) 213 cmp = "and (in_GPR_WRITE_"+toString(i)+"_OOO_ENGINE_ID=internal_OOO_ENGINE_ID) "; 214 else 215 cmp = ""; 216 217 vhdl->set_body( "\t\t((in_GPR_WRITE_"+toString(i)+"_VAL='1') "+cmp+"and (internal_NUM_REG_RA=in_GPR_WRITE_"+toString(i)+"_NUM_REG)) or");218 } 219 vhdl->set_body( "\t\tfalse else");220 vhdl->set_body( "\tinternal_READ_RA_VAL and not in_GPR_READ_0_ACK;");221 } 222 { 223 vhdl->set_body( "");224 vhdl->set_body( "internal_NEXT_READ_RB_VAL <=");225 vhdl->set_body( "\t'0' when");226 // bypass 227 vhdl->set_body( "\t\t-- check bypass");228 for (int32_t i=_param->_nb_gpr_write-1; i>=0 ; i--) 229 { 230 std::string cmp; 231 232 if (_param->_have_port_ooo_engine_id) 233 cmp = "and (in_GPR_WRITE_"+toString(i)+"_OOO_ENGINE_ID=internal_OOO_ENGINE_ID) "; 234 else 235 cmp = ""; 236 237 vhdl->set_body( "\t\t((in_GPR_WRITE_"+toString(i)+"_VAL='1') "+cmp+"and (internal_NUM_REG_RB=in_GPR_WRITE_"+toString(i)+"_NUM_REG)) or");238 } 239 vhdl->set_body( "\t\tfalse else");240 vhdl->set_body( "\tinternal_READ_RB_VAL and not in_GPR_READ_1_ACK;");241 } 242 { 243 vhdl->set_body( "");244 vhdl->set_body( "internal_NEXT_READ_RC_VAL <=");245 vhdl->set_body( "\t'0' when");246 // bypass 247 vhdl->set_body( "\t\t-- check bypass");171 vhdl->set_body(0,"out_READ_QUEUE_OUT_OOO_ENGINE_ID <= internal_OOO_ENGINE_ID;"); 172 if(_param->_have_port_rob_ptr ) 173 vhdl->set_body(0,"out_READ_QUEUE_OUT_ROB_ID <= internal_ROB_ID ;"); 174 vhdl->set_body(0,"out_READ_QUEUE_OUT_OPERATION <= internal_OPERATION ;"); 175 vhdl->set_body(0,"out_READ_QUEUE_OUT_TYPE <= internal_TYPE ;"); 176 vhdl->set_body(0,"out_READ_QUEUE_OUT_HAS_IMMEDIAT <= internal_HAS_IMMEDIAT ;"); 177 vhdl->set_body(0,"out_READ_QUEUE_OUT_IMMEDIAT <= internal_IMMEDIAT ;"); 178 // vhdl->set_body(0,"out_READ_QUEUE_OUT_READ_RA <= internal_READ_RA ;"); 179 vhdl->set_body(0,"out_READ_QUEUE_OUT_NUM_REG_RA <= internal_NUM_REG_RA ;"); 180 vhdl->set_body(0,"out_READ_QUEUE_OUT_DATA_RA_VAL <= internal_NEXT_DATA_RA_VAL;"); 181 vhdl->set_body(0,"out_READ_QUEUE_OUT_DATA_RA <= internal_NEXT_DATA_RA ;"); 182 // vhdl->set_body(0,"out_READ_QUEUE_OUT_READ_RB <= internal_READ_RB ;"); 183 vhdl->set_body(0,"out_READ_QUEUE_OUT_NUM_REG_RB <= internal_NUM_REG_RB ;"); 184 vhdl->set_body(0,"out_READ_QUEUE_OUT_DATA_RB_VAL <= internal_NEXT_DATA_RB_VAL;"); 185 vhdl->set_body(0,"out_READ_QUEUE_OUT_DATA_RB <= internal_NEXT_DATA_RB ;"); 186 // vhdl->set_body(0,"out_READ_QUEUE_OUT_READ_RC <= internal_READ_RC ;"); 187 vhdl->set_body(0,"out_READ_QUEUE_OUT_NUM_REG_RC <= internal_NUM_REG_RC ;"); 188 vhdl->set_body(0,"out_READ_QUEUE_OUT_DATA_RC_VAL <= internal_NEXT_DATA_RC_VAL;"); 189 vhdl->set_body(0,"out_READ_QUEUE_OUT_DATA_RC <= internal_NEXT_DATA_RC ;"); 190 vhdl->set_body(0,"out_READ_QUEUE_OUT_WRITE_RD <= internal_WRITE_RD ;"); 191 vhdl->set_body(0,"out_READ_QUEUE_OUT_NUM_REG_RD <= internal_NUM_REG_RD ;"); 192 vhdl->set_body(0,"out_READ_QUEUE_OUT_WRITE_RE <= internal_WRITE_RE ;"); 193 vhdl->set_body(0,"out_READ_QUEUE_OUT_NUM_REG_RE <= internal_NUM_REG_RE ;"); 194 195 vhdl->set_body(0,""); 196 vhdl->set_body(0,"-----------------------------------"); 197 vhdl->set_body(0,"-- next reg update"); 198 vhdl->set_body(0,"-----------------------------------"); 199 vhdl->set_body(0,""); 200 vhdl->set_body(0,"-- read_rx_val - 1 : must access at the registerFile (after access, is set at 0)"); 201 202 { 203 vhdl->set_body(0,""); 204 vhdl->set_body(0,"internal_NEXT_READ_RA_VAL <="); 205 vhdl->set_body(1,"'0' when"); 206 // bypass 207 vhdl->set_body(2,"-- check bypass"); 208 for (int32_t i=_param->_nb_gpr_write-1; i>=0 ; i--) 209 { 210 std::string cmp; 211 212 if (_param->_have_port_ooo_engine_id) 213 cmp = "and (in_GPR_WRITE_"+toString(i)+"_OOO_ENGINE_ID=internal_OOO_ENGINE_ID) "; 214 else 215 cmp = ""; 216 217 vhdl->set_body(2,"((in_GPR_WRITE_"+toString(i)+"_VAL='1') "+cmp+"and (internal_NUM_REG_RA=in_GPR_WRITE_"+toString(i)+"_NUM_REG)) or"); 218 } 219 vhdl->set_body(2,"false else"); 220 vhdl->set_body(1,"internal_READ_RA_VAL and not in_GPR_READ_0_ACK;"); 221 } 222 { 223 vhdl->set_body(0,""); 224 vhdl->set_body(0,"internal_NEXT_READ_RB_VAL <="); 225 vhdl->set_body(1,"'0' when"); 226 // bypass 227 vhdl->set_body(2,"-- check bypass"); 228 for (int32_t i=_param->_nb_gpr_write-1; i>=0 ; i--) 229 { 230 std::string cmp; 231 232 if (_param->_have_port_ooo_engine_id) 233 cmp = "and (in_GPR_WRITE_"+toString(i)+"_OOO_ENGINE_ID=internal_OOO_ENGINE_ID) "; 234 else 235 cmp = ""; 236 237 vhdl->set_body(2,"((in_GPR_WRITE_"+toString(i)+"_VAL='1') "+cmp+"and (internal_NUM_REG_RB=in_GPR_WRITE_"+toString(i)+"_NUM_REG)) or"); 238 } 239 vhdl->set_body(2,"false else"); 240 vhdl->set_body(1,"internal_READ_RB_VAL and not in_GPR_READ_1_ACK;"); 241 } 242 { 243 vhdl->set_body(0,""); 244 vhdl->set_body(0,"internal_NEXT_READ_RC_VAL <="); 245 vhdl->set_body(1,"'0' when"); 246 // bypass 247 vhdl->set_body(2,"-- check bypass"); 248 248 for (int32_t i=_param->_nb_spr_write-1; i>=0 ; i--) 249 249 { … … 255 255 cmp = ""; 256 256 257 vhdl->set_body( "\t\t((in_SPR_WRITE_"+toString(i)+"_VAL='1') "+cmp+"and (internal_NUM_REG_RC=in_SPR_WRITE_"+toString(i)+"_NUM_REG)) or");258 } 259 vhdl->set_body( "\t\tfalse else");260 vhdl->set_body( "\tinternal_READ_RC_VAL and not in_SPR_READ_0_ACK;");261 } 262 { 263 vhdl->set_body( "");264 vhdl->set_body( "internal_READ_QUEUE_OUT_VAL <= not internal_NEXT_READ_RA_VAL and not internal_NEXT_READ_RB_VAL and not internal_NEXT_READ_RC_VAL;");265 vhdl->set_body( " out_READ_QUEUE_OUT_VAL <= internal_READ_QUEUE_OUT_VAL and internal_QUEUE_RETIRE_VAL;");257 vhdl->set_body(2,"((in_SPR_WRITE_"+toString(i)+"_VAL='1') "+cmp+"and (internal_NUM_REG_RC=in_SPR_WRITE_"+toString(i)+"_NUM_REG)) or"); 258 } 259 vhdl->set_body(2,"false else"); 260 vhdl->set_body(1,"internal_READ_RC_VAL and not in_SPR_READ_0_ACK;"); 261 } 262 { 263 vhdl->set_body(0,""); 264 vhdl->set_body(0,"internal_READ_QUEUE_OUT_VAL <= not internal_NEXT_READ_RA_VAL and not internal_NEXT_READ_RB_VAL and not internal_NEXT_READ_RC_VAL;"); 265 vhdl->set_body(0," out_READ_QUEUE_OUT_VAL <= internal_READ_QUEUE_OUT_VAL and internal_QUEUE_RETIRE_VAL;"); 266 266 267 267 } 268 268 269 vhdl->set_body( "");270 vhdl->set_body( "-- data_rx_val - 1 : the read of registerFile is valid");271 272 { 273 vhdl->set_body( "");274 vhdl->set_body( "internal_NEXT_DATA_RA_VAL <=");275 vhdl->set_body( "\t'1' when");276 // bypass 277 vhdl->set_body( "\t\t-- check bypass");269 vhdl->set_body(0,""); 270 vhdl->set_body(0,"-- data_rx_val - 1 : the read of registerFile is valid"); 271 272 { 273 vhdl->set_body(0,""); 274 vhdl->set_body(0,"internal_NEXT_DATA_RA_VAL <="); 275 vhdl->set_body(1,"'1' when"); 276 // bypass 277 vhdl->set_body(2,"-- check bypass"); 278 278 for (int32_t i=_param->_nb_gpr_write-1; i>=0 ; i--) 279 279 { … … 285 285 cmp = ""; 286 286 287 vhdl->set_body( "\t\t((in_GPR_WRITE_"+toString(i)+"_VAL='1') "+cmp+"and (internal_NUM_REG_RA=in_GPR_WRITE_"+toString(i)+"_NUM_REG)) or");288 } 289 vhdl->set_body( "\t\tfalse else");290 vhdl->set_body( "\tinternal_DATA_RA_VAL or (internal_READ_RA_VAL and in_GPR_READ_0_ACK and in_GPR_READ_0_DATA_VAL);");291 } 292 { 293 vhdl->set_body( "");294 vhdl->set_body( "internal_NEXT_DATA_RB_VAL <=");295 vhdl->set_body( "\t'1' when");296 // bypass 297 vhdl->set_body( "\t\t-- check bypass");287 vhdl->set_body(2,"((in_GPR_WRITE_"+toString(i)+"_VAL='1') "+cmp+"and (internal_NUM_REG_RA=in_GPR_WRITE_"+toString(i)+"_NUM_REG)) or"); 288 } 289 vhdl->set_body(2,"false else"); 290 vhdl->set_body(1,"internal_DATA_RA_VAL or (internal_READ_RA_VAL and in_GPR_READ_0_ACK and in_GPR_READ_0_DATA_VAL);"); 291 } 292 { 293 vhdl->set_body(0,""); 294 vhdl->set_body(0,"internal_NEXT_DATA_RB_VAL <="); 295 vhdl->set_body(1,"'1' when"); 296 // bypass 297 vhdl->set_body(2,"-- check bypass"); 298 298 for (int32_t i=_param->_nb_gpr_write-1; i>=0 ; i--) 299 299 { … … 305 305 cmp = ""; 306 306 307 vhdl->set_body( "\t\t((in_GPR_WRITE_"+toString(i)+"_VAL='1') "+cmp+"and (internal_NUM_REG_RB=in_GPR_WRITE_"+toString(i)+"_NUM_REG)) or");308 } 309 vhdl->set_body( "\t\tfalse else");310 vhdl->set_body( "\tinternal_DATA_RB_VAL or (internal_READ_RB_VAL and in_GPR_READ_1_ACK and in_GPR_READ_1_DATA_VAL);");311 } 312 { 313 vhdl->set_body( "");314 vhdl->set_body( "internal_NEXT_DATA_RC_VAL <=");315 vhdl->set_body( "\t'1' when");316 // bypass 317 vhdl->set_body( "\t\t-- check bypass");307 vhdl->set_body(2,"((in_GPR_WRITE_"+toString(i)+"_VAL='1') "+cmp+"and (internal_NUM_REG_RB=in_GPR_WRITE_"+toString(i)+"_NUM_REG)) or"); 308 } 309 vhdl->set_body(2,"false else"); 310 vhdl->set_body(1,"internal_DATA_RB_VAL or (internal_READ_RB_VAL and in_GPR_READ_1_ACK and in_GPR_READ_1_DATA_VAL);"); 311 } 312 { 313 vhdl->set_body(0,""); 314 vhdl->set_body(0,"internal_NEXT_DATA_RC_VAL <="); 315 vhdl->set_body(1,"'1' when"); 316 // bypass 317 vhdl->set_body(2,"-- check bypass"); 318 318 for (int32_t i=_param->_nb_spr_write-1; i>=0 ; i--) 319 319 { … … 325 325 cmp = ""; 326 326 327 vhdl->set_body( "\t\t((in_SPR_WRITE_"+toString(i)+"_VAL='1') "+cmp+"and (internal_NUM_REG_RC=in_SPR_WRITE_"+toString(i)+"_NUM_REG)) or");328 } 329 vhdl->set_body( "\t\tfalse else");330 vhdl->set_body( "\tinternal_DATA_RC_VAL or (internal_READ_RC_VAL and in_SPR_READ_0_ACK and in_SPR_READ_0_DATA_VAL);");331 } 332 333 vhdl->set_body( "");334 vhdl->set_body( "-- data_rx - data read");335 { 336 vhdl->set_body( "");337 vhdl->set_body( "internal_NEXT_DATA_RA <=");327 vhdl->set_body(2,"((in_SPR_WRITE_"+toString(i)+"_VAL='1') "+cmp+"and (internal_NUM_REG_RC=in_SPR_WRITE_"+toString(i)+"_NUM_REG)) or"); 328 } 329 vhdl->set_body(2,"false else"); 330 vhdl->set_body(1,"internal_DATA_RC_VAL or (internal_READ_RC_VAL and in_SPR_READ_0_ACK and in_SPR_READ_0_DATA_VAL);"); 331 } 332 333 vhdl->set_body(0,""); 334 vhdl->set_body(0,"-- data_rx - data read"); 335 { 336 vhdl->set_body(0,""); 337 vhdl->set_body(0,"internal_NEXT_DATA_RA <="); 338 338 #ifdef SYSTEMC_VHDL_COMPATIBILITY 339 vhdl->set_body( "\t"+std_logic_others(_param->_size_general_data,0)+" when internal_READ_RA='0' else");339 vhdl->set_body(1,""+std_logic_others(_param->_size_general_data,0)+" when internal_READ_RA='0' else"); 340 340 #endif 341 341 // bypass 342 vhdl->set_body( "\t\t-- check bypass");342 vhdl->set_body(2,"-- check bypass"); 343 343 for (int32_t i=_param->_nb_gpr_write-1; i>=0 ; i--) 344 344 { … … 350 350 cmp = ""; 351 351 352 vhdl->set_body( "\tin_GPR_WRITE_"+toString(i)+"_DATA when ((in_GPR_WRITE_"+toString(i)+"_VAL='1') "+cmp+"and (internal_NUM_REG_RA=in_GPR_WRITE_"+toString(i)+"_NUM_REG)) else");353 } 354 vhdl->set_body( "\treg_DATA_RA when (internal_DATA_RA_VAL='1') else");355 vhdl->set_body( "\tin_GPR_READ_0_DATA;");356 } 357 { 358 vhdl->set_body( "");359 vhdl->set_body( "internal_NEXT_DATA_RB <=");352 vhdl->set_body(1,"in_GPR_WRITE_"+toString(i)+"_DATA when ((in_GPR_WRITE_"+toString(i)+"_VAL='1') "+cmp+"and (internal_NUM_REG_RA=in_GPR_WRITE_"+toString(i)+"_NUM_REG)) else"); 353 } 354 vhdl->set_body(1,"reg_DATA_RA when (internal_DATA_RA_VAL='1') else"); 355 vhdl->set_body(1,"in_GPR_READ_0_DATA;"); 356 } 357 { 358 vhdl->set_body(0,""); 359 vhdl->set_body(0,"internal_NEXT_DATA_RB <="); 360 360 #ifdef SYSTEMC_VHDL_COMPATIBILITY 361 vhdl->set_body( "\t"+std_logic_others(_param->_size_general_data,0)+" when internal_READ_RB='0' else");361 vhdl->set_body(1,""+std_logic_others(_param->_size_general_data,0)+" when internal_READ_RB='0' else"); 362 362 #endif 363 363 // bypass 364 vhdl->set_body( "\t\t-- check bypass");364 vhdl->set_body(2,"-- check bypass"); 365 365 for (int32_t i=_param->_nb_gpr_write-1; i>=0 ; i--) 366 366 { … … 372 372 cmp = ""; 373 373 374 vhdl->set_body( "\tin_GPR_WRITE_"+toString(i)+"_DATA when ((in_GPR_WRITE_"+toString(i)+"_VAL='1') "+cmp+"and (internal_NUM_REG_RB=in_GPR_WRITE_"+toString(i)+"_NUM_REG)) else");375 } 376 vhdl->set_body( "\treg_DATA_RB when (internal_DATA_RB_VAL='1') else");377 vhdl->set_body( "\tin_GPR_READ_1_DATA;");378 } 379 { 380 vhdl->set_body( "");381 vhdl->set_body( "internal_NEXT_DATA_RC <=");374 vhdl->set_body(1,"in_GPR_WRITE_"+toString(i)+"_DATA when ((in_GPR_WRITE_"+toString(i)+"_VAL='1') "+cmp+"and (internal_NUM_REG_RB=in_GPR_WRITE_"+toString(i)+"_NUM_REG)) else"); 375 } 376 vhdl->set_body(1,"reg_DATA_RB when (internal_DATA_RB_VAL='1') else"); 377 vhdl->set_body(1,"in_GPR_READ_1_DATA;"); 378 } 379 { 380 vhdl->set_body(0,""); 381 vhdl->set_body(0,"internal_NEXT_DATA_RC <="); 382 382 #ifdef SYSTEMC_VHDL_COMPATIBILITY 383 vhdl->set_body( "\t"+std_logic_others(_param->_size_special_data,0)+" when internal_READ_RC='0' else");383 vhdl->set_body(1,""+std_logic_others(_param->_size_special_data,0)+" when internal_READ_RC='0' else"); 384 384 #endif 385 385 // bypass 386 vhdl->set_body( "\t\t-- check bypass");386 vhdl->set_body(2,"-- check bypass"); 387 387 for (int32_t i=_param->_nb_spr_write-1; i>=0 ; i--) 388 388 { … … 394 394 cmp = ""; 395 395 396 vhdl->set_body( "\tin_SPR_WRITE_"+toString(i)+"_DATA when ((in_SPR_WRITE_"+toString(i)+"_VAL='1') "+cmp+"and (in_SPR_WRITE_"+toString(i)+"_NUM_REG=internal_NUM_REG_RC)) else");397 } 398 vhdl->set_body( "\treg_DATA_RC when (internal_DATA_RC_VAL='1') else");399 vhdl->set_body( "\tin_SPR_READ_0_DATA;");400 401 vhdl->set_body( "");402 vhdl->set_body( "-----------------------------------");403 vhdl->set_body( "-- transition");404 vhdl->set_body( "-----------------------------------");405 vhdl->set_body( "");406 vhdl->set_body( "-- need a new head if :");407 vhdl->set_body( "-- * queue is empty");408 vhdl->set_body( "-- * pop with queue");409 vhdl->set_body ("internal_NEXT_NEED_NEW_HEAD <= not internal_QUEUE_RETIRE_VAL or (internal_QUEUE_RETIRE_VAL and internal_QUEUE_RETIRE_ACK);");410 411 vhdl->set_body ("internal_READ_RA_VAL <= internal_READ_RA when reg_NEED_NEW_HEAD='1' else reg_READ_RA_VAL;");412 vhdl->set_body ("internal_READ_RB_VAL <= internal_READ_RB when reg_NEED_NEW_HEAD='1' else reg_READ_RB_VAL;");413 vhdl->set_body ("internal_READ_RC_VAL <= internal_READ_RC when reg_NEED_NEW_HEAD='1' else reg_READ_RC_VAL;");414 vhdl->set_body ("internal_DATA_RA_VAL <= not internal_READ_RA when reg_NEED_NEW_HEAD='1' else reg_DATA_RA_VAL;");415 vhdl->set_body ("internal_DATA_RB_VAL <= not internal_READ_RB when reg_NEED_NEW_HEAD='1' else reg_DATA_RB_VAL;");416 vhdl->set_body ("internal_DATA_RC_VAL <= not internal_READ_RC when reg_NEED_NEW_HEAD='1' else reg_DATA_RC_VAL;");417 418 419 vhdl->set_body ("");420 vhdl->set_body ("transition: process (in_CLOCK)");421 vhdl->set_body ("begin -- process transition");422 vhdl->set_body ("\tif in_CLOCK'event and in_CLOCK = '1' then");423 vhdl->set_body ("");424 vhdl->set_body ("\t\tif (in_NRESET = '0') then");425 vhdl->set_body ("\t\t\treg_NEED_NEW_HEAD <= '1';");426 vhdl->set_body ("\t\telse");427 vhdl->set_body ("\t\t\treg_NEED_NEW_HEAD <= internal_NEXT_NEED_NEW_HEAD;");428 vhdl->set_body ("\t\t\treg_READ_RA_VAL <= internal_NEXT_READ_RA_VAL;");429 vhdl->set_body ("\t\t\treg_READ_RB_VAL <= internal_NEXT_READ_RB_VAL;");430 vhdl->set_body ("\t\t\treg_READ_RC_VAL <= internal_NEXT_READ_RC_VAL;");431 vhdl->set_body ("\t\t\treg_DATA_RA_VAL <= internal_NEXT_DATA_RA_VAL;");432 vhdl->set_body ("\t\t\treg_DATA_RB_VAL <= internal_NEXT_DATA_RB_VAL;");433 vhdl->set_body ("\t\t\treg_DATA_RC_VAL <= internal_NEXT_DATA_RC_VAL;");434 vhdl->set_body ("\t\t\treg_DATA_RA <= internal_NEXT_DATA_RA ;");435 vhdl->set_body ("\t\t\treg_DATA_RB <= internal_NEXT_DATA_RB ;");436 vhdl->set_body ("\t\t\treg_DATA_RC <= internal_NEXT_DATA_RC ;");437 438 vhdl->set_body ("\t\tend if;");439 vhdl->set_body ("");440 vhdl->set_body ("\tend if;");441 vhdl->set_body ("end process transition;");396 vhdl->set_body(1,"in_SPR_WRITE_"+toString(i)+"_DATA when ((in_SPR_WRITE_"+toString(i)+"_VAL='1') "+cmp+"and (in_SPR_WRITE_"+toString(i)+"_NUM_REG=internal_NUM_REG_RC)) else"); 397 } 398 vhdl->set_body(1,"reg_DATA_RC when (internal_DATA_RC_VAL='1') else"); 399 vhdl->set_body(1,"in_SPR_READ_0_DATA;"); 400 401 vhdl->set_body(0,""); 402 vhdl->set_body(0,"-----------------------------------"); 403 vhdl->set_body(0,"-- transition"); 404 vhdl->set_body(0,"-----------------------------------"); 405 vhdl->set_body(0,""); 406 vhdl->set_body(0,"-- need a new head if :"); 407 vhdl->set_body(0,"-- * queue is empty"); 408 vhdl->set_body(0,"-- * pop with queue"); 409 vhdl->set_body(0,"internal_NEXT_NEED_NEW_HEAD <= not internal_QUEUE_RETIRE_VAL or (internal_QUEUE_RETIRE_VAL and internal_QUEUE_RETIRE_ACK);"); 410 411 vhdl->set_body(0,"internal_READ_RA_VAL <= internal_READ_RA when reg_NEED_NEW_HEAD='1' else reg_READ_RA_VAL;"); 412 vhdl->set_body(0,"internal_READ_RB_VAL <= internal_READ_RB when reg_NEED_NEW_HEAD='1' else reg_READ_RB_VAL;"); 413 vhdl->set_body(0,"internal_READ_RC_VAL <= internal_READ_RC when reg_NEED_NEW_HEAD='1' else reg_READ_RC_VAL;"); 414 vhdl->set_body(0,"internal_DATA_RA_VAL <= not internal_READ_RA when reg_NEED_NEW_HEAD='1' else reg_DATA_RA_VAL;"); 415 vhdl->set_body(0,"internal_DATA_RB_VAL <= not internal_READ_RB when reg_NEED_NEW_HEAD='1' else reg_DATA_RB_VAL;"); 416 vhdl->set_body(0,"internal_DATA_RC_VAL <= not internal_READ_RC when reg_NEED_NEW_HEAD='1' else reg_DATA_RC_VAL;"); 417 418 419 vhdl->set_body(0,""); 420 vhdl->set_body(0,"transition: process (in_CLOCK)"); 421 vhdl->set_body(0,"begin -- process transition"); 422 vhdl->set_body(1,"if in_CLOCK'event and in_CLOCK = '1' then"); 423 vhdl->set_body(0,""); 424 vhdl->set_body(2,"if (in_NRESET = '0') then"); 425 vhdl->set_body(3,"reg_NEED_NEW_HEAD <= '1';"); 426 vhdl->set_body(2,"else"); 427 vhdl->set_body(3,"reg_NEED_NEW_HEAD <= internal_NEXT_NEED_NEW_HEAD;"); 428 vhdl->set_body(3,"reg_READ_RA_VAL <= internal_NEXT_READ_RA_VAL;"); 429 vhdl->set_body(3,"reg_READ_RB_VAL <= internal_NEXT_READ_RB_VAL;"); 430 vhdl->set_body(3,"reg_READ_RC_VAL <= internal_NEXT_READ_RC_VAL;"); 431 vhdl->set_body(3,"reg_DATA_RA_VAL <= internal_NEXT_DATA_RA_VAL;"); 432 vhdl->set_body(3,"reg_DATA_RB_VAL <= internal_NEXT_DATA_RB_VAL;"); 433 vhdl->set_body(3,"reg_DATA_RC_VAL <= internal_NEXT_DATA_RC_VAL;"); 434 vhdl->set_body(3,"reg_DATA_RA <= internal_NEXT_DATA_RA ;"); 435 vhdl->set_body(3,"reg_DATA_RB <= internal_NEXT_DATA_RB ;"); 436 vhdl->set_body(3,"reg_DATA_RC <= internal_NEXT_DATA_RC ;"); 437 438 vhdl->set_body(2,"end if;"); 439 vhdl->set_body(0,""); 440 vhdl->set_body(1,"end if;"); 441 vhdl->set_body(0,"end process transition;"); 442 442 443 443 } -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_vhdl_declaration.cpp
r81 r97 87 87 min = max+1; 88 88 } 89 if(_param->_have_port_rob_ id)89 if(_param->_have_port_rob_ptr) 90 90 { 91 size = _param->_size_rob_ id;91 size = _param->_size_rob_ptr; 92 92 max = min-1+size; 93 93 vhdl->set_alias ("internal_ROB_ID ",std_logic(size),"internal_QUEUE_RETIRE_DATA",std_logic_range(_param->_size_internal_queue,max,min)); 94 94 min = max+1; 95 95 } -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/SelfTest/src/test.cpp
r88 r97 6 6 * Test 7 7 */ 8 #define NB_ITERATION 28 #define NB_ITERATION 1 9 9 #define CYCLE_MAX (2048*NB_ITERATION) 10 10 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/src/Reservation_station_allocation.cpp
r88 r97 231 231 in_BYPASS_WRITE_GPR_DATA [i] = interface->set_signal_in <Tgeneral_data_t > ("gpr_data" ,_param->_size_general_data); 232 232 in_BYPASS_WRITE_SPR_VAL [i] = interface->set_signal_valack_in ("spr_val",VAL); 233 in_BYPASS_WRITE_SPR_NUM_REG [i] = interface->set_signal_in <Tspecial_address_t> ("spr_num_reg" ,_param->_size_ general_register);234 in_BYPASS_WRITE_SPR_DATA [i] = interface->set_signal_in <Tspecial_data_t > ("spr_data" ,_param->_size_ general_data);233 in_BYPASS_WRITE_SPR_NUM_REG [i] = interface->set_signal_in <Tspecial_address_t> ("spr_num_reg" ,_param->_size_special_register); 234 in_BYPASS_WRITE_SPR_DATA [i] = interface->set_signal_in <Tspecial_data_t > ("spr_data" ,_param->_size_special_data); 235 235 } 236 236 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/src/Reservation_station_transition.cpp
r88 r97 50 50 _queue[it_dump]._write_re , \ 51 51 _queue[it_dump]._num_reg_re , \ 52 toString _type(_queue[it_dump]._type).c_str()); \52 toString(_queue[it_dump]._type).c_str()); \ 53 53 } while (0) 54 54 #else … … 84 84 _queue[(*_queue_control)[it_dump]]._write_re , \ 85 85 _queue[(*_queue_control)[it_dump]]._num_reg_re , \ 86 toString _type(_queue[(*_queue_control)[it_dump]]._type).c_str()); \86 toString(_queue[(*_queue_control)[it_dump]]._type).c_str()); \ 87 87 } while (0) 88 88 #endif -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/src/Reservation_station_vhdl_body.cpp
r81 r97 88 88 if (_param->_have_port_ooo_engine_id) 89 89 vhdl->set_body ("out_RETIRE_"+toString(i)+"_OOO_ENGINE_ID <= reg_OOO_ENGINE_ID"+range_retire+";"); 90 if (_param->_have_port_rob_ id)90 if (_param->_have_port_rob_ptr) 91 91 vhdl->set_body ("out_RETIRE_"+toString(i)+"_ROB_ID <= reg_ROB_ID "+range_retire+";"); 92 92 vhdl->set_body ("out_RETIRE_"+toString(i)+"_OPERATION <= reg_OPERATION "+range_retire+";"); … … 268 268 if (_param->_have_port_ooo_engine_id) 269 269 vhdl->set_body ("\t\t\t\treg_OOO_ENGINE_ID "+range_insert+" <= in_INSERT_OOO_ENGINE_ID;"); 270 if (_param->_have_port_rob_ id)270 if (_param->_have_port_rob_ptr) 271 271 vhdl->set_body ("\t\t\t\treg_ROB_ID "+range_insert+" <= in_INSERT_ROB_ID ;"); 272 272 vhdl->set_body ("\t\t\t\treg_OPERATION "+range_insert+" <= in_INSERT_OPERATION ;"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/src/Reservation_station_vhdl_declaration.cpp
r81 r97 32 32 if (_param->_have_port_ooo_engine_id) 33 33 vhdl->set_type ("Tooo_engine_id ","array (" + toString(_param->_size_queue-1) + " downto 0) of " + std_logic(_param->_size_ooo_engine_id)); 34 if (_param->_have_port_rob_ id)35 vhdl->set_type ("Trob_id ","array (" + toString(_param->_size_queue-1) + " downto 0) of " + std_logic(_param->_size_rob_ id));34 if (_param->_have_port_rob_ptr) 35 vhdl->set_type ("Trob_id ","array (" + toString(_param->_size_queue-1) + " downto 0) of " + std_logic(_param->_size_rob_ptr)); 36 36 vhdl->set_type ("Toperation ","array (" + toString(_param->_size_queue-1) + " downto 0) of " + std_logic(_param->_size_operation)); 37 37 vhdl->set_type ("Ttype ","array (" + toString(_param->_size_queue-1) + " downto 0) of " + std_logic(_param->_size_type)); … … 48 48 if (_param->_have_port_ooo_engine_id) 49 49 vhdl->set_signal("reg_OOO_ENGINE_ID ","Tooo_engine_id"); 50 if (_param->_have_port_rob_ id)50 if (_param->_have_port_rob_ptr) 51 51 vhdl->set_signal("reg_ROB_ID ","Trob_id"); 52 52 vhdl->set_signal("reg_OPERATION ","Toperation"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/src/Read_unit_allocation.cpp
r88 r97 1 1 /* 2 * $ Id$2 * $id: Read_unit_allocation.cpp 88 2008-12-10 18:31:39Z rosiere $ 3 3 * 4 4 * [ Description ] … … 115 115 ALLOC1_VALACK_IN ( in_GPR_READ_ACK,ACK); 116 116 ALLOC1_SIGNAL_OUT(out_GPR_READ_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id ); 117 ALLOC1_SIGNAL_OUT(out_GPR_READ_NUM_REG ,"num_reg" ,Tgeneral_address_t,_param->_size_general_ data);118 ALLOC1_SIGNAL_IN ( in_GPR_READ_DATA ,"data" ,Tgeneral_data_t ,_param->_size_general_ register);117 ALLOC1_SIGNAL_OUT(out_GPR_READ_NUM_REG ,"num_reg" ,Tgeneral_address_t,_param->_size_general_register); 118 ALLOC1_SIGNAL_IN ( in_GPR_READ_DATA ,"data" ,Tgeneral_data_t ,_param->_size_general_data ); 119 119 ALLOC1_SIGNAL_IN ( in_GPR_READ_DATA_VAL ,"data_val" ,Tcontrol_t ,1); 120 120 } … … 127 127 ALLOC1_VALACK_IN ( in_SPR_READ_ACK,ACK); 128 128 ALLOC1_SIGNAL_OUT(out_SPR_READ_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id ); 129 ALLOC1_SIGNAL_OUT(out_SPR_READ_NUM_REG ,"num_reg" ,Tspecial_address_t,_param->_size_special_ data);130 ALLOC1_SIGNAL_IN ( in_SPR_READ_DATA ,"data" ,Tspecial_data_t ,_param->_size_special_ register);129 ALLOC1_SIGNAL_OUT(out_SPR_READ_NUM_REG ,"num_reg" ,Tspecial_address_t,_param->_size_special_register); 130 ALLOC1_SIGNAL_IN ( in_SPR_READ_DATA ,"data" ,Tspecial_data_t ,_param->_size_special_data ); 131 131 ALLOC1_SIGNAL_IN ( in_SPR_READ_DATA_VAL ,"data_val" ,Tcontrol_t ,1); 132 132 } … … 138 138 ALLOC1_VALACK_IN ( in_GPR_WRITE_VAL,VAL); 139 139 ALLOC1_SIGNAL_IN ( in_GPR_WRITE_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id ); 140 ALLOC1_SIGNAL_IN ( in_GPR_WRITE_NUM_REG ,"num_reg" ,Tgeneral_address_t,_param->_size_general_ data);141 ALLOC1_SIGNAL_IN ( in_GPR_WRITE_DATA ,"data" ,Tgeneral_data_t ,_param->_size_general_ register);140 ALLOC1_SIGNAL_IN ( in_GPR_WRITE_NUM_REG ,"num_reg" ,Tgeneral_address_t,_param->_size_general_register); 141 ALLOC1_SIGNAL_IN ( in_GPR_WRITE_DATA ,"data" ,Tgeneral_data_t ,_param->_size_general_data); 142 142 } 143 143 … … 148 148 ALLOC1_VALACK_IN ( in_SPR_WRITE_VAL,VAL); 149 149 ALLOC1_SIGNAL_IN ( in_SPR_WRITE_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id ); 150 ALLOC1_SIGNAL_IN ( in_SPR_WRITE_NUM_REG ,"num_reg" ,Tspecial_address_t,_param->_size_special_ data);151 ALLOC1_SIGNAL_IN ( in_SPR_WRITE_DATA ,"data" ,Tspecial_data_t ,_param->_size_special_ register);150 ALLOC1_SIGNAL_IN ( in_SPR_WRITE_NUM_REG ,"num_reg" ,Tspecial_address_t,_param->_size_special_register); 151 ALLOC1_SIGNAL_IN ( in_SPR_WRITE_DATA ,"data" ,Tspecial_data_t ,_param->_size_special_data); 152 152 } 153 153 … … 158 158 ALLOC1_SIGNAL_IN ( in_BYPASS_WRITE_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id ); 159 159 ALLOC1_SIGNAL_IN ( in_BYPASS_WRITE_GPR_VAL ,"gpr_val" ,Tcontrol_t ,1); 160 ALLOC1_SIGNAL_IN ( in_BYPASS_WRITE_GPR_NUM_REG ,"gpr_num_reg" ,Tgeneral_address_t,_param->_size_general_ data);161 ALLOC1_SIGNAL_IN ( in_BYPASS_WRITE_GPR_DATA ,"gpr_data" ,Tgeneral_data_t ,_param->_size_general_ register);160 ALLOC1_SIGNAL_IN ( in_BYPASS_WRITE_GPR_NUM_REG ,"gpr_num_reg" ,Tgeneral_address_t,_param->_size_general_register); 161 ALLOC1_SIGNAL_IN ( in_BYPASS_WRITE_GPR_DATA ,"gpr_data" ,Tgeneral_data_t ,_param->_size_general_data ); 162 162 ALLOC1_SIGNAL_IN ( in_BYPASS_WRITE_SPR_VAL ,"spr_val" ,Tcontrol_t ,1); 163 ALLOC1_SIGNAL_IN ( in_BYPASS_WRITE_SPR_NUM_REG ,"spr_num_reg" ,Tspecial_address_t,_param->_size_special_ data);164 ALLOC1_SIGNAL_IN ( in_BYPASS_WRITE_SPR_DATA ,"spr_data" ,Tspecial_data_t ,_param->_size_special_ register);163 ALLOC1_SIGNAL_IN ( in_BYPASS_WRITE_SPR_NUM_REG ,"spr_num_reg" ,Tspecial_address_t,_param->_size_special_register); 164 ALLOC1_SIGNAL_IN ( in_BYPASS_WRITE_SPR_DATA ,"spr_data" ,Tspecial_data_t ,_param->_size_special_data ); 165 165 } 166 166 … … 171 171 ALLOC1_SIGNAL_IN ( in_BYPASS_MEMORY_VAL ,"val" ,Tcontrol_t ,1); 172 172 ALLOC1_SIGNAL_IN ( in_BYPASS_MEMORY_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id ); 173 ALLOC1_SIGNAL_IN ( in_BYPASS_MEMORY_NUM_REG ,"num_reg" ,Tgeneral_address_t,_param->_size_general_ data);174 ALLOC1_SIGNAL_IN ( in_BYPASS_MEMORY_DATA ,"data" ,Tgeneral_data_t ,_param->_size_general_ register);173 ALLOC1_SIGNAL_IN ( in_BYPASS_MEMORY_NUM_REG ,"num_reg" ,Tgeneral_address_t,_param->_size_general_register); 174 ALLOC1_SIGNAL_IN ( in_BYPASS_MEMORY_DATA ,"data" ,Tgeneral_data_t ,_param->_size_general_data ); 175 175 } 176 176 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/SelfTest/src/test.cpp
r96 r97 123 123 ALLOC_SC_SIGNAL ( in_EXECUTE_QUEUE_IN_EXCEPTION ," in_EXECUTE_QUEUE_IN_EXCEPTION" , Texception_t ); 124 124 ALLOC_SC_SIGNAL ( in_EXECUTE_QUEUE_IN_NO_SEQUENCE ," in_EXECUTE_QUEUE_IN_NO_SEQUENCE" , Tcontrol_t ); 125 ALLOC_SC_SIGNAL ( in_EXECUTE_QUEUE_IN_ADDRESS ," in_EXECUTE_QUEUE_IN_ADDRESS" , T general_data_t);125 ALLOC_SC_SIGNAL ( in_EXECUTE_QUEUE_IN_ADDRESS ," in_EXECUTE_QUEUE_IN_ADDRESS" , Taddress_t ); 126 126 ALLOC_SC_SIGNAL ( in_EXECUTE_QUEUE_IN_DATA ," in_EXECUTE_QUEUE_IN_DATA" , Tgeneral_data_t ); 127 127 ALLOC_SC_SIGNAL (out_EXECUTE_QUEUE_OUT_VAL ,"out_EXECUTE_QUEUE_OUT_VAL" , Tcontrol_t ); … … 136 136 ALLOC_SC_SIGNAL (out_EXECUTE_QUEUE_OUT_EXCEPTION ,"out_EXECUTE_QUEUE_OUT_EXCEPTION" , Texception_t ); 137 137 ALLOC_SC_SIGNAL (out_EXECUTE_QUEUE_OUT_NO_SEQUENCE ,"out_EXECUTE_QUEUE_OUT_NO_SEQUENCE" , Tcontrol_t ); 138 ALLOC_SC_SIGNAL (out_EXECUTE_QUEUE_OUT_ADDRESS ,"out_EXECUTE_QUEUE_OUT_ADDRESS" , T general_data_t);138 ALLOC_SC_SIGNAL (out_EXECUTE_QUEUE_OUT_ADDRESS ,"out_EXECUTE_QUEUE_OUT_ADDRESS" , Taddress_t ); 139 139 ALLOC_SC_SIGNAL (out_EXECUTE_QUEUE_OUT_DATA ,"out_EXECUTE_QUEUE_OUT_DATA" , Tgeneral_data_t ); 140 140 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/include/Execute_queue.h
r88 r97 78 78 public : SC_IN (Texception_t ) * in_EXECUTE_QUEUE_IN_EXCEPTION ; 79 79 public : SC_IN (Tcontrol_t ) * in_EXECUTE_QUEUE_IN_NO_SEQUENCE ; 80 public : SC_IN (T general_data_t) * in_EXECUTE_QUEUE_IN_ADDRESS ;80 public : SC_IN (Taddress_t ) * in_EXECUTE_QUEUE_IN_ADDRESS ; 81 81 public : SC_IN (Tgeneral_data_t ) * in_EXECUTE_QUEUE_IN_DATA ; 82 82 … … 93 93 public : SC_OUT(Texception_t ) * out_EXECUTE_QUEUE_OUT_EXCEPTION ; 94 94 public : SC_OUT(Tcontrol_t ) * out_EXECUTE_QUEUE_OUT_NO_SEQUENCE ; 95 public : SC_OUT(T general_data_t) * out_EXECUTE_QUEUE_OUT_ADDRESS ;95 public : SC_OUT(Taddress_t ) * out_EXECUTE_QUEUE_OUT_ADDRESS ; 96 96 public : SC_OUT(Tgeneral_data_t ) * out_EXECUTE_QUEUE_OUT_DATA ; 97 97 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/src/Execute_queue_allocation.cpp
r88 r97 67 67 ALLOC_SIGNAL_IN ( in_EXECUTE_QUEUE_IN_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception ); 68 68 ALLOC_SIGNAL_IN ( in_EXECUTE_QUEUE_IN_NO_SEQUENCE ,"no_sequence" ,Tcontrol_t ,1 ); 69 ALLOC_SIGNAL_IN ( in_EXECUTE_QUEUE_IN_ADDRESS ,"address" ,T general_data_t ,_param->_size_general_data);69 ALLOC_SIGNAL_IN ( in_EXECUTE_QUEUE_IN_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address); 70 70 ALLOC_SIGNAL_IN ( in_EXECUTE_QUEUE_IN_DATA ,"data" ,Tgeneral_data_t ,_param->_size_general_data ); 71 71 } … … 90 90 ALLOC_SIGNAL_OUT(out_EXECUTE_QUEUE_OUT_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception ); 91 91 ALLOC_SIGNAL_OUT(out_EXECUTE_QUEUE_OUT_NO_SEQUENCE ,"no_sequence" ,Tcontrol_t ,1 ); 92 ALLOC_SIGNAL_OUT(out_EXECUTE_QUEUE_OUT_ADDRESS ,"address" ,T general_data_t,_param->_size_general_data);92 ALLOC_SIGNAL_OUT(out_EXECUTE_QUEUE_OUT_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address); 93 93 ALLOC_SIGNAL_OUT(out_EXECUTE_QUEUE_OUT_DATA ,"data" ,Tgeneral_data_t,_param->_size_general_data ); 94 94 } -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/src/Parameters.cpp
r96 r97 41 41 if (is_toplevel) 42 42 { 43 _size_instruction_address= size_general_data-2; 43 44 _size_context_id = log2(_nb_context ); 44 45 _size_front_end_id = log2(_nb_front_end ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/SelfTest/src/test.cpp
r88 r97 22 22 public : Tpacket_t _packet_id ; 23 23 //public : Toperation_t _operation ; 24 24 //public : Ttype_t _type ; 25 25 public : Tcontrol_t _write_rd ; 26 26 public : Tgeneral_address_t _num_reg_rd ; … … 37 37 Tcontext_t ooo_engine_id, 38 38 Tpacket_t packet_id , 39 //Toperation_t operation ,40 Ttype_t type ,39 // Toperation_t operation , 40 // Ttype_t type , 41 41 Tcontrol_t write_rd , 42 42 Tgeneral_address_t num_reg_rd , … … 53 53 _ooo_engine_id = ooo_engine_id; 54 54 _packet_id = packet_id ; 55 //_operation = operation ;56 55 // _operation = operation ; 56 // _type = type ; 57 57 _write_rd = write_rd ; 58 58 _num_reg_rd = num_reg_rd ; … … 74 74 << " * _packet_id : " << toString(x._packet_id ) << std::endl 75 75 //<< " * _operation : " << toString(x._operation ) << std::endl 76 76 //<< " * _type : " << toString(x._type ) << std::endl 77 77 << " * _write_rd : " << toString(x._write_rd ) << std::endl 78 78 << " * _num_reg_rd : " << toString(x._num_reg_rd ) << std::endl … … 133 133 ALLOC_SC_SIGNAL ( in_WRITE_UNIT_IN_PACKET_ID ," in_WRITE_UNIT_IN_PACKET_ID" , Tpacket_t ); 134 134 //ALLOC_SC_SIGNAL ( in_WRITE_UNIT_IN_OPERATION ," in_WRITE_UNIT_IN_OPERATION" , Toperation_t ); 135 135 //ALLOC_SC_SIGNAL ( in_WRITE_UNIT_IN_TYPE ," in_WRITE_UNIT_IN_TYPE" , Ttype_t ); 136 136 ALLOC_SC_SIGNAL ( in_WRITE_UNIT_IN_WRITE_RD ," in_WRITE_UNIT_IN_WRITE_RD" , Tcontrol_t ); 137 137 ALLOC_SC_SIGNAL ( in_WRITE_UNIT_IN_NUM_REG_RD ," in_WRITE_UNIT_IN_NUM_REG_RD" , Tgeneral_address_t); … … 142 142 ALLOC_SC_SIGNAL ( in_WRITE_UNIT_IN_EXCEPTION ," in_WRITE_UNIT_IN_EXCEPTION" , Texception_t ); 143 143 ALLOC_SC_SIGNAL ( in_WRITE_UNIT_IN_NO_SEQUENCE ," in_WRITE_UNIT_IN_NO_SEQUENCE" , Tcontrol_t ); 144 ALLOC_SC_SIGNAL ( in_WRITE_UNIT_IN_ADDRESS ," in_WRITE_UNIT_IN_ADDRESS" , T general_data_t);144 ALLOC_SC_SIGNAL ( in_WRITE_UNIT_IN_ADDRESS ," in_WRITE_UNIT_IN_ADDRESS" , Taddress_t ); 145 145 ALLOC_SC_SIGNAL (out_WRITE_UNIT_OUT_VAL ,"out_WRITE_UNIT_OUT_VAL" , Tcontrol_t ); 146 146 ALLOC_SC_SIGNAL ( in_WRITE_UNIT_OUT_ACK ," in_WRITE_UNIT_OUT_ACK" , Tcontrol_t ); … … 154 154 ALLOC_SC_SIGNAL (out_WRITE_UNIT_OUT_EXCEPTION ,"out_WRITE_UNIT_OUT_EXCEPTION" , Texception_t ); 155 155 ALLOC_SC_SIGNAL (out_WRITE_UNIT_OUT_NO_SEQUENCE ,"out_WRITE_UNIT_OUT_NO_SEQUENCE" , Tcontrol_t ); 156 ALLOC_SC_SIGNAL (out_WRITE_UNIT_OUT_ADDRESS ,"out_WRITE_UNIT_OUT_ADDRESS" , T general_data_t);156 ALLOC_SC_SIGNAL (out_WRITE_UNIT_OUT_ADDRESS ,"out_WRITE_UNIT_OUT_ADDRESS" , Taddress_t ); 157 157 ALLOC_SC_SIGNAL (out_WRITE_UNIT_OUT_DATA ,"out_WRITE_UNIT_OUT_DATA" , Tgeneral_data_t ); 158 158 ALLOC1_SC_SIGNAL(out_GPR_WRITE_VAL ,"out_GPR_WRITE_VAL" , Tcontrol_t , _param->_nb_gpr_write); … … 195 195 INSTANCE_SC_SIGNAL (_Write_unit, in_WRITE_UNIT_IN_PACKET_ID ); 196 196 //INSTANCE_SC_SIGNAL (_Write_unit, in_WRITE_UNIT_IN_OPERATION ); 197 197 //INSTANCE_SC_SIGNAL (_Write_unit, in_WRITE_UNIT_IN_TYPE ); 198 198 INSTANCE_SC_SIGNAL (_Write_unit, in_WRITE_UNIT_IN_WRITE_RD ); 199 199 INSTANCE_SC_SIGNAL (_Write_unit, in_WRITE_UNIT_IN_NUM_REG_RD ); … … 309 309 i, 310 310 //range<Toperation_t >(rand(),_param->_size_operation ), 311 311 //range<Ttype_t >(rand(),_param->_size_type ), 312 312 range<Tcontrol_t >(rand(),1 ), 313 313 range<Tgeneral_address_t>(rand(),_param->_size_general_register), … … 316 316 range<Tspecial_address_t>(rand(),_param->_size_special_register), 317 317 range<Tspecial_data_t >(rand(),_param->_size_special_data ), 318 range<Texception_t >(rand(), _param->_size_exception),318 range<Texception_t >(rand(),0 ), 319 319 range<Tcontrol_t >(rand(),1 ), 320 320 range<Tgeneral_data_t >(rand(),_param->_size_general_data )); … … 341 341 in_WRITE_UNIT_IN_PACKET_ID ->write(request [nb_request_in]->_packet_id ); 342 342 //in_WRITE_UNIT_IN_OPERATION ->write(request [nb_request_in]->_operation ); 343 343 //in_WRITE_UNIT_IN_TYPE ->write(request [nb_request_in]->_type ); 344 344 in_WRITE_UNIT_IN_WRITE_RD ->write(request [nb_request_in]->_write_rd ); 345 345 in_WRITE_UNIT_IN_NUM_REG_RD ->write(request [nb_request_in]->_num_reg_rd ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/SelfTest/src/test.cpp
r88 r97 22 22 public : Tpacket_t _packet_id ; 23 23 //public : Toperation_t _operation ; 24 24 //public : Ttype_t _type ; 25 25 public : Tcontrol_t _write_rd ; 26 26 public : Tgeneral_address_t _num_reg_rd ; … … 37 37 Tcontext_t ooo_engine_id, 38 38 Tpacket_t packet_id , 39 //Toperation_t operation ,40 Ttype_t type ,39 // Toperation_t operation , 40 // Ttype_t type , 41 41 Tcontrol_t write_rd , 42 42 Tgeneral_address_t num_reg_rd , … … 54 54 _packet_id = packet_id ; 55 55 //_operation = operation ; 56 56 //_type = type ; 57 57 _write_rd = write_rd ; 58 58 _num_reg_rd = num_reg_rd ; … … 74 74 << " * _packet_id : " << toString(x._packet_id ) << std::endl 75 75 //<< " * _operation : " << toString(x._operation ) << std::endl 76 76 //<< " * _type : " << toString(x._type ) << std::endl 77 77 << " * _write_rd : " << toString(x._write_rd ) << std::endl 78 78 << " * _num_reg_rd : " << toString(x._num_reg_rd ) << std::endl … … 132 132 ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_PACKET_ID ," in_WRITE_QUEUE_IN_PACKET_ID" , Tpacket_t ); 133 133 //ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_OPERATION ," in_WRITE_QUEUE_IN_OPERATION" , Toperation_t ); 134 134 //ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_TYPE ," in_WRITE_QUEUE_IN_TYPE" , Ttype_t ); 135 135 ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_WRITE_RD ," in_WRITE_QUEUE_IN_WRITE_RD" , Tcontrol_t ); 136 136 ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_NUM_REG_RD ," in_WRITE_QUEUE_IN_NUM_REG_RD" , Tgeneral_address_t); … … 141 141 ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_EXCEPTION ," in_WRITE_QUEUE_IN_EXCEPTION" , Texception_t ); 142 142 ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_NO_SEQUENCE ," in_WRITE_QUEUE_IN_NO_SEQUENCE" , Tcontrol_t ); 143 ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_ADDRESS ," in_WRITE_QUEUE_IN_ADDRESS" , T general_data_t);143 ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_ADDRESS ," in_WRITE_QUEUE_IN_ADDRESS" , Taddress_t ); 144 144 ALLOC_SC_SIGNAL (out_WRITE_QUEUE_OUT_VAL ,"out_WRITE_QUEUE_OUT_VAL" , Tcontrol_t ); 145 145 ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_OUT_ACK ," in_WRITE_QUEUE_OUT_ACK" , Tcontrol_t ); … … 154 154 ALLOC_SC_SIGNAL (out_WRITE_QUEUE_OUT_NO_SEQUENCE ,"out_WRITE_QUEUE_OUT_NO_SEQUENCE" , Tcontrol_t ); 155 155 ALLOC_SC_SIGNAL (out_WRITE_QUEUE_OUT_ADDRESS ,"out_WRITE_QUEUE_OUT_ADDRESS" , Tgeneral_data_t ); 156 ALLOC_SC_SIGNAL (out_WRITE_QUEUE_OUT_DATA ,"out_WRITE_QUEUE_OUT_DATA" , T general_data_t);156 ALLOC_SC_SIGNAL (out_WRITE_QUEUE_OUT_DATA ,"out_WRITE_QUEUE_OUT_DATA" , Taddress_t ); 157 157 ALLOC1_SC_SIGNAL(out_GPR_WRITE_VAL ,"out_GPR_WRITE_VAL" , Tcontrol_t , _param->_nb_gpr_write); 158 158 ALLOC1_SC_SIGNAL( in_GPR_WRITE_ACK ," in_GPR_WRITE_ACK" , Tcontrol_t , _param->_nb_gpr_write); … … 193 193 INSTANCE_SC_SIGNAL (_Write_queue, in_WRITE_QUEUE_IN_PACKET_ID ); 194 194 //INSTANCE_SC_SIGNAL (_Write_queue, in_WRITE_QUEUE_IN_OPERATION ); 195 195 //INSTANCE_SC_SIGNAL (_Write_queue, in_WRITE_QUEUE_IN_TYPE ); 196 196 INSTANCE_SC_SIGNAL (_Write_queue, in_WRITE_QUEUE_IN_WRITE_RD ); 197 197 INSTANCE_SC_SIGNAL (_Write_queue, in_WRITE_QUEUE_IN_NUM_REG_RD ); … … 307 307 i, 308 308 //range<Toperation_t >(rand(),_param->_size_operation ), 309 309 //range<Ttype_t >(rand(),_param->_size_type ), 310 310 range<Tcontrol_t >(rand(),1 ), 311 311 range<Tgeneral_address_t>(rand(),_param->_size_general_register), … … 314 314 range<Tspecial_address_t>(rand(),_param->_size_special_register), 315 315 range<Tspecial_data_t >(rand(),_param->_size_special_data ), 316 range<Texception_t >(rand(), _param->_size_exception),316 range<Texception_t >(rand(),0 ), 317 317 range<Tcontrol_t >(rand(),1 ), 318 318 range<Tgeneral_data_t >(rand(),_param->_size_general_data )); … … 339 339 in_WRITE_QUEUE_IN_PACKET_ID ->write(request [nb_request_in]->_packet_id ); 340 340 //in_WRITE_QUEUE_IN_OPERATION ->write(request [nb_request_in]->_operation ); 341 341 //in_WRITE_QUEUE_IN_TYPE ->write(request [nb_request_in]->_type ); 342 342 in_WRITE_QUEUE_IN_WRITE_RD ->write(request [nb_request_in]->_write_rd ); 343 343 in_WRITE_QUEUE_IN_NUM_REG_RD ->write(request [nb_request_in]->_num_reg_rd ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/include/Types.h
r82 r97 27 27 public : Tpacket_t _packet_id ; 28 28 //public : Toperation_t _operation ; 29 29 //public : Ttype_t _type ; 30 30 public : Tcontrol_t _write_rd ; 31 31 public : Tgeneral_address_t _num_reg_rd ; … … 42 42 Tcontext_t ooo_engine_id, 43 43 Tpacket_t packet_id , 44 //Toperation_t operation ,45 Ttype_t type ,44 // Toperation_t operation , 45 // Ttype_t type , 46 46 Tcontrol_t write_rd , 47 47 Tgeneral_address_t num_reg_rd , … … 59 59 _packet_id = packet_id ; 60 60 //_operation = operation ; 61 61 //_type = type ; 62 62 _write_rd = write_rd ; 63 63 _num_reg_rd = num_reg_rd ; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/include/Write_queue.h
r88 r97 76 76 public : SC_IN (Tpacket_t ) * in_WRITE_QUEUE_IN_PACKET_ID ; 77 77 //public : SC_IN (Toperation_t ) * in_WRITE_QUEUE_IN_OPERATION ; 78 78 //public : SC_IN (Ttype_t ) * in_WRITE_QUEUE_IN_TYPE ; 79 79 public : SC_IN (Tcontrol_t ) * in_WRITE_QUEUE_IN_WRITE_RD ; 80 80 public : SC_IN (Tgeneral_address_t) * in_WRITE_QUEUE_IN_NUM_REG_RD ; … … 85 85 public : SC_IN (Texception_t ) * in_WRITE_QUEUE_IN_EXCEPTION ; 86 86 public : SC_IN (Tcontrol_t ) * in_WRITE_QUEUE_IN_NO_SEQUENCE ; 87 public : SC_IN (T general_data_t) * in_WRITE_QUEUE_IN_ADDRESS ;87 public : SC_IN (Taddress_t ) * in_WRITE_QUEUE_IN_ADDRESS ; 88 88 89 89 // -----[ Interface "Write_queue_out" ]------------------------------- … … 99 99 public : SC_OUT(Texception_t ) * out_WRITE_QUEUE_OUT_EXCEPTION ; 100 100 public : SC_OUT(Tcontrol_t ) * out_WRITE_QUEUE_OUT_NO_SEQUENCE ; 101 public : SC_OUT(T general_data_t) * out_WRITE_QUEUE_OUT_ADDRESS ;101 public : SC_OUT(Taddress_t ) * out_WRITE_QUEUE_OUT_ADDRESS ; 102 102 public : SC_OUT(Tgeneral_data_t ) * out_WRITE_QUEUE_OUT_DATA ; 103 103 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Parameters.cpp
r88 r97 50 50 if (is_toplevel) 51 51 { 52 _size_instruction_address= size_general_data-2; 52 53 _size_context_id = log2(_nb_context ); 53 54 _size_front_end_id = log2(_nb_front_end ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue_allocation.cpp
r88 r97 60 60 ALLOC_SIGNAL_IN ( in_WRITE_QUEUE_IN_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_rob_ptr ); 61 61 // ALLOC_SIGNAL_IN ( in_WRITE_QUEUE_IN_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation ); 62 62 // ALLOC_SIGNAL_IN ( in_WRITE_QUEUE_IN_TYPE ,"type" ,Ttype_t ,_param->_size_type ); 63 63 ALLOC_SIGNAL_IN ( in_WRITE_QUEUE_IN_WRITE_RD ,"write_rd" ,Tcontrol_t ,1 ); 64 64 ALLOC_SIGNAL_IN ( in_WRITE_QUEUE_IN_NUM_REG_RD ,"num_reg_rd" ,Tgeneral_address_t,_param->_size_general_register ); … … 69 69 ALLOC_SIGNAL_IN ( in_WRITE_QUEUE_IN_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception ); 70 70 ALLOC_SIGNAL_IN ( in_WRITE_QUEUE_IN_NO_SEQUENCE ,"no_sequence" ,Tcontrol_t ,1 ); 71 ALLOC_SIGNAL_IN ( in_WRITE_QUEUE_IN_ADDRESS ,"address" ,T general_data_t ,_param->_size_general_data);71 ALLOC_SIGNAL_IN ( in_WRITE_QUEUE_IN_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address); 72 72 } 73 73 … … 87 87 ALLOC_SIGNAL_OUT(out_WRITE_QUEUE_OUT_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception ); 88 88 ALLOC_SIGNAL_OUT(out_WRITE_QUEUE_OUT_NO_SEQUENCE ,"no_sequence" ,Tcontrol_t ,1 ); 89 ALLOC_SIGNAL_OUT(out_WRITE_QUEUE_OUT_ADDRESS ,"address" ,T general_data_t,_param->_size_general_data);89 ALLOC_SIGNAL_OUT(out_WRITE_QUEUE_OUT_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address); 90 90 ALLOC_SIGNAL_OUT(out_WRITE_QUEUE_OUT_DATA ,"data" ,Tgeneral_data_t,_param->_size_general_data ); 91 91 } -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue_deallocation.cpp
r88 r97 41 41 delete in_WRITE_QUEUE_IN_PACKET_ID ; 42 42 // delete in_WRITE_QUEUE_IN_OPERATION ; 43 delete in_WRITE_QUEUE_IN_TYPE ;43 // delete in_WRITE_QUEUE_IN_TYPE ; 44 44 delete in_WRITE_QUEUE_IN_WRITE_RD ; 45 45 delete in_WRITE_QUEUE_IN_NUM_REG_RD ; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue_transition.cpp
r88 r97 53 53 (_param->_have_port_rob_ptr )?PORT_READ(in_WRITE_QUEUE_IN_PACKET_ID ):0, 54 54 //PORT_READ(in_WRITE_QUEUE_IN_OPERATION ), 55 55 //PORT_READ(in_WRITE_QUEUE_IN_TYPE ), 56 56 PORT_READ(in_WRITE_QUEUE_IN_WRITE_RD ), 57 57 PORT_READ(in_WRITE_QUEUE_IN_NUM_REG_RD ), … … 72 72 if ( (internal_WRITE_QUEUE_OUT_VAL and PORT_READ(in_WRITE_QUEUE_OUT_ACK)) or 73 73 ((_queue->empty() == false) and 74 (_queue->front()->_type == TYPE_MEMORY) and75 (_queue->front()->_exception == EXCEPTION_MEMORY_LOAD_SPECULATIVE) and 74 // (_queue->front()->_type == TYPE_MEMORY) and 75 (_queue->front()->_exception == EXCEPTION_MEMORY_LOAD_SPECULATIVE) and // this exception code must be uniq 76 76 (_queue->front()->_write_rd == 0) and 77 77 (_queue->front()->_write_re == 0))) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/include/Write_unit.h
r88 r97 71 71 public : SC_IN (Tpacket_t ) * in_WRITE_UNIT_IN_PACKET_ID ; 72 72 //public : SC_IN (Toperation_t ) * in_WRITE_UNIT_IN_OPERATION ; 73 73 //public : SC_IN (Ttype_t ) * in_WRITE_UNIT_IN_TYPE ; 74 74 public : SC_IN (Tcontrol_t ) * in_WRITE_UNIT_IN_WRITE_RD ; 75 75 public : SC_IN (Tgeneral_address_t) * in_WRITE_UNIT_IN_NUM_REG_RD ; … … 80 80 public : SC_IN (Texception_t ) * in_WRITE_UNIT_IN_EXCEPTION ; 81 81 public : SC_IN (Tcontrol_t ) * in_WRITE_UNIT_IN_NO_SEQUENCE ; 82 public : SC_IN (T general_data_t) * in_WRITE_UNIT_IN_ADDRESS ;82 public : SC_IN (Taddress_t ) * in_WRITE_UNIT_IN_ADDRESS ; 83 83 84 84 // -----[ Interface "write_unit_out" ]-------------------------------- … … 94 94 public : SC_OUT(Texception_t ) * out_WRITE_UNIT_OUT_EXCEPTION ; 95 95 public : SC_OUT(Tcontrol_t ) * out_WRITE_UNIT_OUT_NO_SEQUENCE ; 96 public : SC_OUT(T general_data_t) * out_WRITE_UNIT_OUT_ADDRESS ;96 public : SC_OUT(Taddress_t ) * out_WRITE_UNIT_OUT_ADDRESS ; 97 97 public : SC_OUT(Tgeneral_data_t ) * out_WRITE_UNIT_OUT_DATA ; 98 98 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/src/Parameters.cpp
r88 r97 73 73 if (is_toplevel) 74 74 { 75 _size_instruction_address = size_general_data-2; 75 76 _size_context_id = log2(_nb_context ); 76 77 _size_front_end_id = log2(_nb_front_end ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/src/Write_unit_allocation.cpp
r88 r97 66 66 ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_rob_ptr ); 67 67 // ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation ); 68 68 // ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_TYPE ,"type" ,Ttype_t ,_param->_size_type ); 69 69 ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_WRITE_RD ,"write_rd" ,Tcontrol_t ,1 ); 70 70 ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_NUM_REG_RD ,"num_reg_rd" ,Tgeneral_address_t,_param->_size_general_register ); … … 75 75 ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception ); 76 76 ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_NO_SEQUENCE ,"no_sequence" ,Tcontrol_t ,1 ); 77 ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_ADDRESS ,"address" ,T general_data_t ,_param->_size_general_data);77 ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address); 78 78 } 79 79 … … 93 93 ALLOC_SIGNAL_OUT(out_WRITE_UNIT_OUT_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception ); 94 94 ALLOC_SIGNAL_OUT(out_WRITE_UNIT_OUT_NO_SEQUENCE ,"no_sequence" ,Tcontrol_t ,1 ); 95 ALLOC_SIGNAL_OUT(out_WRITE_UNIT_OUT_ADDRESS ,"address" ,T general_data_t,_param->_size_general_data);95 ALLOC_SIGNAL_OUT(out_WRITE_UNIT_OUT_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address); 96 96 ALLOC_SIGNAL_OUT(out_WRITE_UNIT_OUT_DATA ,"data" ,Tgeneral_data_t,_param->_size_general_data ); 97 97 } … … 206 206 _component->port_map(name, "in_WRITE_QUEUE_IN_PACKET_ID" , _name, "in_WRITE_UNIT_IN_PACKET_ID" ); 207 207 //_component->port_map(name, "in_WRITE_QUEUE_IN_OPERATION" , _name, "in_WRITE_UNIT_IN_OPERATION" ); 208 208 //_component->port_map(name, "in_WRITE_QUEUE_IN_TYPE" , _name, "in_WRITE_UNIT_IN_TYPE" ); 209 209 _component->port_map(name, "in_WRITE_QUEUE_IN_WRITE_RD" , _name, "in_WRITE_UNIT_IN_WRITE_RD" ); 210 210 _component->port_map(name, "in_WRITE_QUEUE_IN_NUM_REG_RD" , _name, "in_WRITE_UNIT_IN_NUM_REG_RD" ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/src/Write_unit_deallocation.cpp
r88 r97 40 40 delete in_WRITE_UNIT_IN_PACKET_ID ; 41 41 // delete in_WRITE_UNIT_IN_OPERATION ; 42 delete in_WRITE_UNIT_IN_TYPE ;42 // delete in_WRITE_UNIT_IN_TYPE ; 43 43 delete in_WRITE_UNIT_IN_WRITE_RD ; 44 44 delete in_WRITE_UNIT_IN_NUM_REG_RD ; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/SelfTest/src/test.cpp
r88 r97 20 20 public : Tpacket_t _packet_id ; 21 21 //public : Toperation_t _operation ; 22 22 //public : Ttype_t _type ; 23 23 public : Tcontrol_t _write_rd ; 24 24 public : Tgeneral_address_t _num_reg_rd ; … … 36 36 Tpacket_t packet_id , 37 37 // Toperation_t operation , 38 Ttype_t type ,38 // Ttype_t type , 39 39 Tcontrol_t write_rd , 40 40 Tgeneral_address_t num_reg_rd , … … 52 52 _packet_id = packet_id ; 53 53 // _operation = operation ; 54 54 // _type = type ; 55 55 _write_rd = write_rd ; 56 56 _num_reg_rd = num_reg_rd ; … … 108 108 ALLOC2_SC_SIGNAL( in_EXECUTE_UNIT_OUT_PACKET_ID ," in_EXECUTE_UNIT_OUT_PACKET_ID ",Tpacket_t ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); 109 109 //ALLOC2_SC_SIGNAL( in_EXECUTE_UNIT_OUT_OPERATION ," in_EXECUTE_UNIT_OUT_OPERATION ",Toperation_t ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); 110 110 //ALLOC2_SC_SIGNAL( in_EXECUTE_UNIT_OUT_TYPE ," in_EXECUTE_UNIT_OUT_TYPE ",Ttype_t ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); 111 111 ALLOC2_SC_SIGNAL( in_EXECUTE_UNIT_OUT_WRITE_RD ," in_EXECUTE_UNIT_OUT_WRITE_RD ",Tcontrol_t ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); 112 112 ALLOC2_SC_SIGNAL( in_EXECUTE_UNIT_OUT_NUM_REG_RD ," in_EXECUTE_UNIT_OUT_NUM_REG_RD ",Tgeneral_address_t,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); … … 117 117 ALLOC2_SC_SIGNAL( in_EXECUTE_UNIT_OUT_EXCEPTION ," in_EXECUTE_UNIT_OUT_EXCEPTION ",Texception_t ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); 118 118 ALLOC2_SC_SIGNAL( in_EXECUTE_UNIT_OUT_NO_SEQUENCE ," in_EXECUTE_UNIT_OUT_NO_SEQUENCE ",Tcontrol_t ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); 119 ALLOC2_SC_SIGNAL( in_EXECUTE_UNIT_OUT_ADDRESS ," in_EXECUTE_UNIT_OUT_ADDRESS ",T general_data_t,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]);119 ALLOC2_SC_SIGNAL( in_EXECUTE_UNIT_OUT_ADDRESS ," in_EXECUTE_UNIT_OUT_ADDRESS ",Taddress_t ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); 120 120 121 121 ALLOC1_SC_SIGNAL(out_WRITE_UNIT_IN_VAL ,"out_WRITE_UNIT_IN_VAL ",Tcontrol_t ,_param->_nb_write_unit ); … … 126 126 ALLOC1_SC_SIGNAL(out_WRITE_UNIT_IN_PACKET_ID ,"out_WRITE_UNIT_IN_PACKET_ID ",Tpacket_t ,_param->_nb_write_unit ); 127 127 //ALLOC1_SC_SIGNAL(out_WRITE_UNIT_IN_OPERATION ,"out_WRITE_UNIT_IN_OPERATION ",Toperation_t ,_param->_nb_write_unit ); 128 128 //ALLOC1_SC_SIGNAL(out_WRITE_UNIT_IN_TYPE ,"out_WRITE_UNIT_IN_TYPE ",Ttype_t ,_param->_nb_write_unit ); 129 129 ALLOC1_SC_SIGNAL(out_WRITE_UNIT_IN_WRITE_RD ,"out_WRITE_UNIT_IN_WRITE_RD ",Tcontrol_t ,_param->_nb_write_unit ); 130 130 ALLOC1_SC_SIGNAL(out_WRITE_UNIT_IN_NUM_REG_RD ,"out_WRITE_UNIT_IN_NUM_REG_RD ",Tgeneral_address_t,_param->_nb_write_unit ); … … 135 135 ALLOC1_SC_SIGNAL(out_WRITE_UNIT_IN_EXCEPTION ,"out_WRITE_UNIT_IN_EXCEPTION ",Texception_t ,_param->_nb_write_unit ); 136 136 ALLOC1_SC_SIGNAL(out_WRITE_UNIT_IN_NO_SEQUENCE ,"out_WRITE_UNIT_IN_NO_SEQUENCE ",Tcontrol_t ,_param->_nb_write_unit ); 137 ALLOC1_SC_SIGNAL(out_WRITE_UNIT_IN_ADDRESS ,"out_WRITE_UNIT_IN_ADDRESS ",T general_data_t,_param->_nb_write_unit );137 ALLOC1_SC_SIGNAL(out_WRITE_UNIT_IN_ADDRESS ,"out_WRITE_UNIT_IN_ADDRESS ",Taddress_t ,_param->_nb_write_unit ); 138 138 139 139 /******************************************************** … … 157 157 INSTANCE2_SC_SIGNAL(_Execution_unit_to_Write_unit, in_EXECUTE_UNIT_OUT_PACKET_ID ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); 158 158 //INSTANCE2_SC_SIGNAL(_Execution_unit_to_Write_unit, in_EXECUTE_UNIT_OUT_OPERATION ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); 159 159 //INSTANCE2_SC_SIGNAL(_Execution_unit_to_Write_unit, in_EXECUTE_UNIT_OUT_TYPE ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); 160 160 INSTANCE2_SC_SIGNAL(_Execution_unit_to_Write_unit, in_EXECUTE_UNIT_OUT_WRITE_RD ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); 161 161 INSTANCE2_SC_SIGNAL(_Execution_unit_to_Write_unit, in_EXECUTE_UNIT_OUT_NUM_REG_RD ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); … … 179 179 INSTANCE1_SC_SIGNAL(_Execution_unit_to_Write_unit,out_WRITE_UNIT_IN_PACKET_ID ,_param->_nb_write_unit ); 180 180 //INSTANCE1_SC_SIGNAL(_Execution_unit_to_Write_unit,out_WRITE_UNIT_IN_OPERATION ,_param->_nb_write_unit ); 181 181 //INSTANCE1_SC_SIGNAL(_Execution_unit_to_Write_unit,out_WRITE_UNIT_IN_TYPE ,_param->_nb_write_unit ); 182 182 INSTANCE1_SC_SIGNAL(_Execution_unit_to_Write_unit,out_WRITE_UNIT_IN_WRITE_RD ,_param->_nb_write_unit ); 183 183 INSTANCE1_SC_SIGNAL(_Execution_unit_to_Write_unit,out_WRITE_UNIT_IN_NUM_REG_RD ,_param->_nb_write_unit ); … … 265 265 ooo_engine_id, 266 266 nb_request_in, 267 //range<Toperation_t > (rand(), _param->_size_operation ),268 range<Ttype_t > (rand(), _param->_size_type ),267 // range<Toperation_t > (rand(), _param->_size_operation ), 268 // range<Ttype_t > (rand(), _param->_size_type ), 269 269 range<Tcontrol_t > (rand(), 2 ), 270 270 range<Tgeneral_address_t> (rand(), _param->_size_general_register), … … 299 299 in_EXECUTE_UNIT_OUT_PACKET_ID [i][j] ->write(request[i][j].front()._packet_id ); 300 300 // in_EXECUTE_UNIT_OUT_OPERATION [i][j] ->write(request[i][j].front()._operation ); 301 in_EXECUTE_UNIT_OUT_TYPE [i][j] ->write(request[i][j].front()._type );301 // in_EXECUTE_UNIT_OUT_TYPE [i][j] ->write(request[i][j].front()._type ); 302 302 in_EXECUTE_UNIT_OUT_WRITE_RD [i][j] ->write(request[i][j].front()._write_rd ); 303 303 in_EXECUTE_UNIT_OUT_NUM_REG_RD [i][j] ->write(request[i][j].front()._num_reg_rd ); … … 367 367 TEST(Tcontext_t ,out_WRITE_UNIT_IN_OOO_ENGINE_ID [i]->read(), request[x][y].front()._ooo_engine_id ); 368 368 // TEST(Toperation_t ,out_WRITE_UNIT_IN_OPERATION [i]->read(), request[x][y].front()._operation ); 369 TEST(Ttype_t ,out_WRITE_UNIT_IN_TYPE [i]->read(), request[x][y].front()._type );369 // TEST(Ttype_t ,out_WRITE_UNIT_IN_TYPE [i]->read(), request[x][y].front()._type ); 370 370 TEST(Tcontrol_t ,out_WRITE_UNIT_IN_WRITE_RD [i]->read(), request[x][y].front()._write_rd ); 371 371 TEST(Tgeneral_address_t,out_WRITE_UNIT_IN_NUM_REG_RD [i]->read(), request[x][y].front()._num_reg_rd ); … … 404 404 DELETE2_SC_SIGNAL( in_EXECUTE_UNIT_OUT_PACKET_ID ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); 405 405 //DELETE2_SC_SIGNAL( in_EXECUTE_UNIT_OUT_OPERATION ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); 406 406 //DELETE2_SC_SIGNAL( in_EXECUTE_UNIT_OUT_TYPE ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); 407 407 DELETE2_SC_SIGNAL( in_EXECUTE_UNIT_OUT_WRITE_RD ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); 408 408 DELETE2_SC_SIGNAL( in_EXECUTE_UNIT_OUT_NUM_REG_RD ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); … … 422 422 DELETE1_SC_SIGNAL(out_WRITE_UNIT_IN_PACKET_ID ,_param->_nb_write_unit ); 423 423 //DELETE1_SC_SIGNAL(out_WRITE_UNIT_IN_OPERATION ,_param->_nb_write_unit ); 424 424 //DELETE1_SC_SIGNAL(out_WRITE_UNIT_IN_TYPE ,_param->_nb_write_unit ); 425 425 DELETE1_SC_SIGNAL(out_WRITE_UNIT_IN_WRITE_RD ,_param->_nb_write_unit ); 426 426 DELETE1_SC_SIGNAL(out_WRITE_UNIT_IN_NUM_REG_RD ,_param->_nb_write_unit ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/include/Execution_unit_to_Write_unit.h
r88 r97 72 72 public : SC_IN (Tpacket_t ) *** in_EXECUTE_UNIT_OUT_PACKET_ID ; 73 73 //public : SC_IN (Toperation_t ) *** in_EXECUTE_UNIT_OUT_OPERATION ; 74 74 //public : SC_IN (Ttype_t ) *** in_EXECUTE_UNIT_OUT_TYPE ; 75 75 public : SC_IN (Tcontrol_t ) *** in_EXECUTE_UNIT_OUT_WRITE_RD ; 76 76 public : SC_IN (Tgeneral_address_t) *** in_EXECUTE_UNIT_OUT_NUM_REG_RD ; … … 81 81 public : SC_IN (Texception_t ) *** in_EXECUTE_UNIT_OUT_EXCEPTION ; 82 82 public : SC_IN (Tcontrol_t ) *** in_EXECUTE_UNIT_OUT_NO_SEQUENCE ; 83 public : SC_IN (T general_data_t) *** in_EXECUTE_UNIT_OUT_ADDRESS ;83 public : SC_IN (Taddress_t ) *** in_EXECUTE_UNIT_OUT_ADDRESS ; 84 84 85 85 // ~~~~~[ Interface "write_unit_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ … … 91 91 public : SC_OUT(Tpacket_t ) ** out_WRITE_UNIT_IN_PACKET_ID ; 92 92 //public : SC_OUT(Toperation_t ) ** out_WRITE_UNIT_IN_OPERATION ; 93 93 //public : SC_OUT(Ttype_t ) ** out_WRITE_UNIT_IN_TYPE ; 94 94 public : SC_OUT(Tcontrol_t ) ** out_WRITE_UNIT_IN_WRITE_RD ; 95 95 public : SC_OUT(Tgeneral_address_t) ** out_WRITE_UNIT_IN_NUM_REG_RD ; … … 100 100 public : SC_OUT(Texception_t ) ** out_WRITE_UNIT_IN_EXCEPTION ; 101 101 public : SC_OUT(Tcontrol_t ) ** out_WRITE_UNIT_IN_NO_SEQUENCE ; 102 public : SC_OUT(T general_data_t) ** out_WRITE_UNIT_IN_ADDRESS ;102 public : SC_OUT(Taddress_t ) ** out_WRITE_UNIT_IN_ADDRESS ; 103 103 104 104 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/src/Execution_unit_to_Write_unit_allocation.cpp
r88 r97 67 67 _ALLOC2_SIGNAL_IN ( in_EXECUTE_UNIT_OUT_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_rob_ptr , _param->_nb_execute_unit, _param->_nb_execute_unit_port[it1]); 68 68 //_ALLOC2_SIGNAL_IN ( in_EXECUTE_UNIT_OUT_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation , _param->_nb_execute_unit, _param->_nb_execute_unit_port[it1]); 69 69 //_ALLOC2_SIGNAL_IN ( in_EXECUTE_UNIT_OUT_TYPE ,"type" ,Ttype_t ,_param->_size_type , _param->_nb_execute_unit, _param->_nb_execute_unit_port[it1]); 70 70 _ALLOC2_SIGNAL_IN ( in_EXECUTE_UNIT_OUT_WRITE_RD ,"write_rd" ,Tcontrol_t ,1 , _param->_nb_execute_unit, _param->_nb_execute_unit_port[it1]); 71 71 _ALLOC2_SIGNAL_IN ( in_EXECUTE_UNIT_OUT_NUM_REG_RD ,"num_reg_rd" ,Tgeneral_address_t,_param->_size_general_register, _param->_nb_execute_unit, _param->_nb_execute_unit_port[it1]); … … 76 76 _ALLOC2_SIGNAL_IN ( in_EXECUTE_UNIT_OUT_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception , _param->_nb_execute_unit, _param->_nb_execute_unit_port[it1]); 77 77 _ALLOC2_SIGNAL_IN ( in_EXECUTE_UNIT_OUT_NO_SEQUENCE ,"no_sequence" ,Tcontrol_t ,1 , _param->_nb_execute_unit, _param->_nb_execute_unit_port[it1]); 78 _ALLOC2_SIGNAL_IN ( in_EXECUTE_UNIT_OUT_ADDRESS ,"address" ,T general_data_t ,_param->_size_general_data, _param->_nb_execute_unit, _param->_nb_execute_unit_port[it1]);78 _ALLOC2_SIGNAL_IN ( in_EXECUTE_UNIT_OUT_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address, _param->_nb_execute_unit, _param->_nb_execute_unit_port[it1]); 79 79 } 80 80 … … 90 90 ALLOC1_SIGNAL_OUT(out_WRITE_UNIT_IN_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_rob_ptr ); 91 91 //ALLOC1_SIGNAL_OUT(out_WRITE_UNIT_IN_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation ); 92 92 //ALLOC1_SIGNAL_OUT(out_WRITE_UNIT_IN_TYPE ,"type" ,Ttype_t ,_param->_size_type ); 93 93 ALLOC1_SIGNAL_OUT(out_WRITE_UNIT_IN_WRITE_RD ,"write_rd" ,Tcontrol_t ,1 ); 94 94 ALLOC1_SIGNAL_OUT(out_WRITE_UNIT_IN_NUM_REG_RD ,"num_reg_rd" ,Tgeneral_address_t,_param->_size_general_register); … … 99 99 ALLOC1_SIGNAL_OUT(out_WRITE_UNIT_IN_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception ); 100 100 ALLOC1_SIGNAL_OUT(out_WRITE_UNIT_IN_NO_SEQUENCE ,"no_sequence" ,Tcontrol_t ,1 ); 101 ALLOC1_SIGNAL_OUT(out_WRITE_UNIT_IN_ADDRESS ,"address" ,T general_data_t ,_param->_size_general_data);101 ALLOC1_SIGNAL_OUT(out_WRITE_UNIT_IN_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address); 102 102 } 103 103 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/src/Execution_unit_to_Write_unit_deallocation.cpp
r88 r97 36 36 DELETE2_SIGNAL( in_EXECUTE_UNIT_OUT_PACKET_ID , _param->_nb_execute_unit, _param->_nb_execute_unit_port[it1],_param->_size_rob_ptr ); 37 37 // DELETE2_SIGNAL( in_EXECUTE_UNIT_OUT_OPERATION , _param->_nb_execute_unit, _param->_nb_execute_unit_port[it1],_param->_size_operation ); 38 38 // DELETE2_SIGNAL( in_EXECUTE_UNIT_OUT_TYPE , _param->_nb_execute_unit, _param->_nb_execute_unit_port[it1],_param->_size_type ); 39 39 DELETE2_SIGNAL( in_EXECUTE_UNIT_OUT_WRITE_RD , _param->_nb_execute_unit, _param->_nb_execute_unit_port[it1],1 ); 40 40 DELETE2_SIGNAL( in_EXECUTE_UNIT_OUT_NUM_REG_RD , _param->_nb_execute_unit, _param->_nb_execute_unit_port[it1],_param->_size_general_register); … … 54 54 DELETE1_SIGNAL(out_WRITE_UNIT_IN_PACKET_ID , _param->_nb_write_unit,_param->_size_rob_ptr ); 55 55 // DELETE1_SIGNAL(out_WRITE_UNIT_IN_OPERATION , _param->_nb_write_unit,_param->_size_operation ); 56 56 // DELETE1_SIGNAL(out_WRITE_UNIT_IN_TYPE , _param->_nb_write_unit,_param->_size_type ); 57 57 DELETE1_SIGNAL(out_WRITE_UNIT_IN_WRITE_RD , _param->_nb_write_unit,1 ); 58 58 DELETE1_SIGNAL(out_WRITE_UNIT_IN_NUM_REG_RD , _param->_nb_write_unit,_param->_size_general_register); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/src/Execution_unit_to_Write_unit_genMealy.cpp
r88 r97 75 75 if (_param->_have_port_rob_ptr ) 76 76 PORT_WRITE(out_WRITE_UNIT_IN_PACKET_ID [dest], PORT_READ(in_EXECUTE_UNIT_OUT_PACKET_ID [i][j])); 77 //PORT_WRITE(out_WRITE_UNIT_IN_OPERATION [dest], PORT_READ(in_EXECUTE_UNIT_OUT_OPERATION [i][j]));78 PORT_WRITE(out_WRITE_UNIT_IN_TYPE [dest], PORT_READ(in_EXECUTE_UNIT_OUT_TYPE [i][j]));77 // PORT_WRITE(out_WRITE_UNIT_IN_OPERATION [dest], PORT_READ(in_EXECUTE_UNIT_OUT_OPERATION [i][j])); 78 // PORT_WRITE(out_WRITE_UNIT_IN_TYPE [dest], PORT_READ(in_EXECUTE_UNIT_OUT_TYPE [i][j])); 79 79 PORT_WRITE(out_WRITE_UNIT_IN_WRITE_RD [dest], PORT_READ(in_EXECUTE_UNIT_OUT_WRITE_RD [i][j])); 80 80 PORT_WRITE(out_WRITE_UNIT_IN_NUM_REG_RD [dest], PORT_READ(in_EXECUTE_UNIT_OUT_NUM_REG_RD [i][j])); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/src/Parameters.cpp
r88 r97 58 58 if (is_toplevel) 59 59 { 60 _size_instruction_address= size_general_data-2; 60 61 _size_context_id = log2(nb_context ); 61 62 _size_front_end_id = log2(nb_front_end ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/src/Parameters_msg_error.cpp
r88 r97 95 95 // Test uniq type 96 96 if (type_present [j][k] and type_uniq[k]) 97 test.error(toString(_("The execute_unit '%d' can execute operation of type '%s' at the thread '%d'. But an another execute_unit can be execute the same type for the same thread. And the type must be single !.\n"),i,toString _type(k).c_str(),j));97 test.error(toString(_("The execute_unit '%d' can execute operation of type '%s' at the thread '%d'. But an another execute_unit can be execute the same type for the same thread. And the type must be single !.\n"),i,toString(k).c_str(),j)); 98 98 99 99 type_present [j][k] = true; … … 104 104 for (uint32_t i=0; i<_nb_thread; i++) 105 105 if (type_present [i][j]) 106 test.error(toString(_("The thread '%d' can execute the type's operation '%s' but this type is invalid.\n"),i,toString _type(j).c_str()));106 test.error(toString(_("The thread '%d' can execute the type's operation '%s' but this type is invalid.\n"),i,toString(j).c_str())); 107 107 108 108 for (Ttype_t j=0; j<_nb_type; j++) … … 110 110 for (uint32_t i=0; i<_nb_thread; i++) 111 111 if (not type_present [i][j]) 112 test.error(toString(_("The thread '%d' can't access at the execute_unit to execute the type's operation '%s' (and this type is not optional !).\n"),i,toString _type(j).c_str()));112 test.error(toString(_("The thread '%d' can't access at the execute_unit to execute the type's operation '%s' (and this type is not optional !).\n"),i,toString(j).c_str())); 113 113 114 114 // Test all excluve type … … 119 119 if ((j != k) and (_table_execute_type[i][k] == true)) 120 120 { 121 test.error(toString(_("The execute_unit [%d] implement the type '%s', and this type is exclusive with all others type.\n"),i,toString _type(j).c_str()));121 test.error(toString(_("The execute_unit [%d] implement the type '%s', and this type is exclusive with all others type.\n"),i,toString(j).c_str())); 122 122 break; 123 123 } -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/src/Read_unit_to_Execution_unit_genMealy.cpp
r88 r97 51 51 #ifdef DEBUG_TEST 52 52 if (_destination[i][num_thread][type].empty()) 53 throw ERRORMORPHEO(FUNCTION,"Invalid Operation : They have no execute_unit to receive a operation from the read_unit ["+toString(i)+"], thread ["+toString(num_thread)+"] and a operation's type ["+toString _type(type)+"].");53 throw ERRORMORPHEO(FUNCTION,"Invalid Operation : They have no execute_unit to receive a operation from the read_unit ["+toString(i)+"], thread ["+toString(num_thread)+"] and a operation's type ["+toString(type)+"]."); 54 54 #endif 55 55 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/src/test.cpp
r88 r97 84 84 ALLOC1_SC_SIGNAL(out_EXECUTE_LOOP_OUT_EXCEPTION ,"out_EXECUTE_LOOP_OUT_EXCEPTION ",Texception_t ,_param->_nb_write_unit); 85 85 ALLOC1_SC_SIGNAL(out_EXECUTE_LOOP_OUT_NO_SEQUENCE ,"out_EXECUTE_LOOP_OUT_NO_SEQUENCE ",Tcontrol_t ,_param->_nb_write_unit); 86 ALLOC1_SC_SIGNAL(out_EXECUTE_LOOP_OUT_ADDRESS ,"out_EXECUTE_LOOP_OUT_ADDRESS ",T general_data_t,_param->_nb_write_unit);86 ALLOC1_SC_SIGNAL(out_EXECUTE_LOOP_OUT_ADDRESS ,"out_EXECUTE_LOOP_OUT_ADDRESS ",Taddress_t ,_param->_nb_write_unit); 87 87 ALLOC1_SC_SIGNAL(out_EXECUTE_LOOP_OUT_DATA ,"out_EXECUTE_LOOP_OUT_DATA ",Tgeneral_data_t ,_param->_nb_write_unit); 88 88 ALLOC2_SC_SIGNAL(out_DCACHE_REQ_VAL ,"out_DCACHE_REQ_VAL ",Tcontrol_t ,_param->_nb_load_store_unit,_param->_nb_cache_port[it1]); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/include/Execute_loop.h
r88 r97 107 107 public : SC_OUT(Texception_t ) ** out_EXECUTE_LOOP_OUT_EXCEPTION ;//[nb_write_unit] 108 108 public : SC_OUT(Tcontrol_t ) ** out_EXECUTE_LOOP_OUT_NO_SEQUENCE ;//[nb_write_unit] 109 public : SC_OUT(T general_data_t) ** out_EXECUTE_LOOP_OUT_ADDRESS ;//[nb_write_unit]109 public : SC_OUT(Taddress_t ) ** out_EXECUTE_LOOP_OUT_ADDRESS ;//[nb_write_unit] 110 110 public : SC_OUT(Tgeneral_data_t ) ** out_EXECUTE_LOOP_OUT_DATA ;//[nb_write_unit] 111 111 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/src/Execute_loop_allocation.cpp
r88 r97 96 96 ALLOC1_SIGNAL_OUT(out_EXECUTE_LOOP_OUT_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception); 97 97 ALLOC1_SIGNAL_OUT(out_EXECUTE_LOOP_OUT_NO_SEQUENCE ,"no_sequence" ,Tcontrol_t ,1); 98 ALLOC1_SIGNAL_OUT(out_EXECUTE_LOOP_OUT_ADDRESS ,"address" ,T general_data_t,_param->_size_general_data);98 ALLOC1_SIGNAL_OUT(out_EXECUTE_LOOP_OUT_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address); 99 99 ALLOC1_SIGNAL_OUT(out_EXECUTE_LOOP_OUT_DATA ,"data" ,Tgeneral_data_t,_param->_size_general_data); 100 100 } … … 850 850 // COMPONENT_MAP(_component ,src ,"out_EXECUTE_OUT_OPERATION" , 851 851 // dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_0_OPERATION" ); 852 COMPONENT_MAP(_component ,src ,"out_EXECUTE_OUT_TYPE" ,853 dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_0_TYPE" );852 // COMPONENT_MAP(_component ,src ,"out_EXECUTE_OUT_TYPE" , 853 // dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_0_TYPE" ); 854 854 COMPONENT_MAP(_component ,src ,"out_EXECUTE_OUT_WRITE_RD" , 855 855 dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_0_WRITE_RD" ); … … 975 975 // COMPONENT_MAP(_component ,src ,"out_MEMORY_OUT_"+toString(j)+"_OPERATION" , 976 976 // dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_"+toString(j)+"_OPERATION" ); 977 COMPONENT_MAP(_component ,src ,"out_MEMORY_OUT_"+toString(j)+"_TYPE" ,978 dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_"+toString(j)+"_TYPE" );977 // COMPONENT_MAP(_component ,src ,"out_MEMORY_OUT_"+toString(j)+"_TYPE" , 978 // dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_"+toString(j)+"_TYPE" ); 979 979 COMPONENT_MAP(_component ,src ,"out_MEMORY_OUT_"+toString(j)+"_WRITE_RD" , 980 980 dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_"+toString(j)+"_WRITE_RD" ); … … 1085 1085 // COMPONENT_MAP(_component ,src , "in_WRITE_UNIT_IN_OPERATION" , 1086 1086 // dest,"out_WRITE_UNIT_IN_"+toString(i)+"_OPERATION" ); 1087 COMPONENT_MAP(_component ,src , "in_WRITE_UNIT_IN_TYPE" ,1088 dest,"out_WRITE_UNIT_IN_"+toString(i)+"_TYPE" );1087 // COMPONENT_MAP(_component ,src , "in_WRITE_UNIT_IN_TYPE" , 1088 // dest,"out_WRITE_UNIT_IN_"+toString(i)+"_TYPE" ); 1089 1089 COMPONENT_MAP(_component ,src , "in_WRITE_UNIT_IN_WRITE_RD" , 1090 1090 dest,"out_WRITE_UNIT_IN_"+toString(i)+"_WRITE_RD" ); … … 1597 1597 // // PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_OPERATION" , 1598 1598 // // dest,"out_EXECUTE_OUT_OPERATION" ); 1599 // PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_TYPE" ,1600 // dest,"out_EXECUTE_OUT_TYPE" );1599 // // PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_TYPE" , 1600 // // dest,"out_EXECUTE_OUT_TYPE" ); 1601 1601 // PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_WRITE_RD" , 1602 1602 // dest,"out_EXECUTE_OUT_WRITE_RD" ); … … 1644 1644 // // PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_OPERATION" , 1645 1645 // // dest,"out_MEMORY_OUT_OPERATION" ); 1646 // PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_TYPE" ,1647 // dest,"out_MEMORY_OUT_TYPE" );1646 // // PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_TYPE" , 1647 // // dest,"out_MEMORY_OUT_TYPE" ); 1648 1648 // PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_WRITE_RD" , 1649 1649 // dest,"out_MEMORY_OUT_WRITE_RD" ); … … 1695 1695 // // PORT_MAP(_component ,src ,"out_WRITE_UNIT_IN_"+toString(i)+"_OPERATION" , 1696 1696 // // dest, "in_WRITE_UNIT_IN_OPERATION" ); 1697 // PORT_MAP(_component ,src ,"out_WRITE_UNIT_IN_"+toString(i)+"_TYPE" ,1698 // dest, "in_WRITE_UNIT_IN_TYPE" );1697 // // PORT_MAP(_component ,src ,"out_WRITE_UNIT_IN_"+toString(i)+"_TYPE" , 1698 // // dest, "in_WRITE_UNIT_IN_TYPE" ); 1699 1699 // PORT_MAP(_component ,src ,"out_WRITE_UNIT_IN_"+toString(i)+"_WRITE_RD" , 1700 1700 // dest, "in_WRITE_UNIT_IN_WRITE_RD" ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/src/Parameters.cpp
r88 r97 156 156 if (timing[x][j][k]._latence > 0) 157 157 { 158 log_printf(TRACE,Execute_loop,FUNCTION,"Execute unit '%d' (functional unit '%d') can execute type '%s'.",i,x,toString _type(j).c_str());158 log_printf(TRACE,Execute_loop,FUNCTION,"Execute unit '%d' (functional unit '%d') can execute type '%s'.",i,x,toString(j).c_str()); 159 159 _read_unit_to_execution_unit_table_execute_type [i][j] = true; 160 160 break; // find an operation … … 524 524 if (is_toplevel) 525 525 { 526 _size_instruction_address= size_general_data-2; 526 527 _size_context_id = log2(nb_context); 527 528 _size_front_end_id = log2(nb_front_end); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/src/test.cpp
r95 r97 75 75 ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EPCR ," in_COMMIT_EVENT_ADDRESS_EPCR ",Taddress_t ); 76 76 ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EEAR_VAL ," in_COMMIT_EVENT_ADDRESS_EEAR_VAL ",Tcontrol_t ); 77 ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EEAR ," in_COMMIT_EVENT_ADDRESS_EEAR ",T address_t);77 ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EEAR ," in_COMMIT_EVENT_ADDRESS_EEAR ",Tgeneral_data_t); 78 78 79 79 ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_VAL ," in_BRANCH_COMPLETE_VAL ",Tcontrol_t ,_param->_nb_inst_branch_complete); … … 97 97 ALLOC1_SC_SIGNAL(out_EVENT_ADDRESS_NEXT_VAL ,"out_EVENT_ADDRESS_NEXT_VAL ",Tcontrol_t ,_param->_nb_context ); 98 98 ALLOC1_SC_SIGNAL(out_EVENT_IS_DS_TAKE ,"out_EVENT_IS_DS_TAKE ",Tcontrol_t ,_param->_nb_context ); 99 99 ALLOC1_SC_SIGNAL(out_EVENT_TYPE ,"out_EVENT_TYPE ",Tevent_type_t,_param->_nb_context ); 100 ALLOC1_SC_SIGNAL(out_EVENT_DEPTH ,"out_EVENT_DEPTH ",Tdepth_t ,_param->_nb_context ); 101 100 102 ALLOC1_SC_SIGNAL(out_SPR_EVENT_VAL ,"out_SPR_EVENT_VAL ",Tcontrol_t ,_param->_nb_context ); 101 103 ALLOC1_SC_SIGNAL( in_SPR_EVENT_ACK ," in_SPR_EVENT_ACK ",Tcontrol_t ,_param->_nb_context ); … … 177 179 INSTANCE1_SC_SIGNAL(_Context_State,out_EVENT_ADDRESS_NEXT_VAL ,_param->_nb_context ); 178 180 INSTANCE1_SC_SIGNAL(_Context_State,out_EVENT_IS_DS_TAKE ,_param->_nb_context ); 181 INSTANCE1_SC_SIGNAL(_Context_State,out_EVENT_TYPE ,_param->_nb_context ); 182 if (_param->_have_port_depth) 183 INSTANCE1_SC_SIGNAL(_Context_State,out_EVENT_DEPTH ,_param->_nb_context ); 179 184 180 185 INSTANCE1_SC_SIGNAL(_Context_State,out_SPR_EVENT_VAL ,_param->_nb_context ); … … 1273 1278 DELETE1_SC_SIGNAL(out_EVENT_ADDRESS_NEXT_VAL ,_param->_nb_context ); 1274 1279 DELETE1_SC_SIGNAL(out_EVENT_IS_DS_TAKE ,_param->_nb_context ); 1280 DELETE1_SC_SIGNAL(out_EVENT_TYPE ,_param->_nb_context ); 1281 DELETE1_SC_SIGNAL(out_EVENT_DEPTH ,_param->_nb_context ); 1275 1282 DELETE1_SC_SIGNAL(out_SPR_EVENT_VAL ,_param->_nb_context ); 1276 1283 DELETE1_SC_SIGNAL( in_SPR_EVENT_ACK ,_param->_nb_context ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Context_State.h
r95 r97 93 93 public : SC_IN (Taddress_t ) * in_COMMIT_EVENT_ADDRESS_EPCR ; 94 94 public : SC_IN (Tcontrol_t ) * in_COMMIT_EVENT_ADDRESS_EEAR_VAL ; 95 public : SC_IN (T address_t) * in_COMMIT_EVENT_ADDRESS_EEAR ;95 public : SC_IN (Tgeneral_data_t ) * in_COMMIT_EVENT_ADDRESS_EEAR ; 96 96 97 97 // ~~~~~[ Interface : "branch_complete" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_allocation.cpp
r95 r97 97 97 ALLOC_SIGNAL_IN ( in_COMMIT_EVENT_ADDRESS_EPCR ,"address_epcr" ,Taddress_t ,_param->_size_instruction_address); 98 98 ALLOC_SIGNAL_IN ( in_COMMIT_EVENT_ADDRESS_EEAR_VAL ,"address_eear_val",Tcontrol_t ,1); 99 ALLOC_SIGNAL_IN ( in_COMMIT_EVENT_ADDRESS_EEAR ,"address_eear" ,T address_t ,_param->_size_instruction_address);99 ALLOC_SIGNAL_IN ( in_COMMIT_EVENT_ADDRESS_EEAR ,"address_eear" ,Tgeneral_data_t ,_param->_size_general_data); 100 100 } 101 101 … … 133 133 ALLOC1_SIGNAL_OUT(out_EVENT_ADDRESS_NEXT_VAL ,"address_next_val",Tcontrol_t ,1); 134 134 ALLOC1_SIGNAL_OUT(out_EVENT_IS_DS_TAKE ,"is_ds_take" ,Tcontrol_t ,1); 135 ALLOC1_SIGNAL_OUT(out_EVENT_TYPE ,"type" ,Tevent_type_t ,_param->_size_event_type); 136 ALLOC1_SIGNAL_OUT(out_EVENT_DEPTH ,"depth" ,Tdepth_t ,_param->_size_depth); 137 135 138 } 136 139 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_deallocation.cpp
r95 r97 76 76 DELETE1_SIGNAL(out_EVENT_ADDRESS_NEXT_VAL ,_param->_nb_context,1); 77 77 DELETE1_SIGNAL(out_EVENT_IS_DS_TAKE ,_param->_nb_context,1); 78 78 DELETE1_SIGNAL(out_EVENT_TYPE ,_param->_nb_context,_param->_size_event_type); 79 DELETE1_SIGNAL(out_EVENT_DEPTH ,_param->_nb_context,_param->_size_depth); 80 79 81 DELETE1_SIGNAL(out_SPR_EVENT_VAL ,_param->_nb_context,1); 80 82 DELETE1_SIGNAL( in_SPR_EVENT_ACK ,_param->_nb_context,1); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_genMoore.cpp
r88 r97 38 38 // SR can't change in this cycle 39 39 // Exception Prefix High 40 Taddress_t address = reg_EVENT_ADDRESS [i] | (((state == CONTEXT_STATE_KO_EXCEP_ADDR) and PORT_READ(in_SPR_SR_EPH [i]))?(0xF000000>>2):0);41 Taddress_t address_next = reg_EVENT_ADDRESS_EPCR [i];42 Tcontrol_t address_next_val = (state == CONTEXT_STATE_KO_MISS_ADDR) and (reg_EVENT_ADDRESS_EPCR_VAL [i]);43 Tcontrol_t is_ds_take = (state == CONTEXT_STATE_KO_MISS_ADDR) and (reg_EVENT_IS_DS_TAKE [i]);40 Taddress_t address = reg_EVENT_ADDRESS [i] | (((state == CONTEXT_STATE_KO_EXCEP_ADDR) and PORT_READ(in_SPR_SR_EPH [i]))?(0xF000000>>2):0); 41 Taddress_t address_next = reg_EVENT_ADDRESS_EPCR [i]; 42 Tcontrol_t address_next_val = (state == CONTEXT_STATE_KO_MISS_ADDR) and (reg_EVENT_ADDRESS_EPCR_VAL [i]); 43 Tcontrol_t is_ds_take = (state == CONTEXT_STATE_KO_MISS_ADDR) and (reg_EVENT_IS_DS_TAKE [i]); 44 44 // excep : address exception 45 45 // miss : address delay_slot, and address dest 46 46 // psync : address next 47 47 // csync : address next 48 Tevent_type_t type ;//[nb_context] 49 Tdepth_t depth = reg_EVENT_DEPTH [i]; 50 51 switch (state) 52 { 53 case CONTEXT_STATE_KO_EXCEP_ADDR : (type = EVENT_TYPE_EXCEPTION ); break; 54 case CONTEXT_STATE_KO_MISS_ADDR : (type = EVENT_TYPE_MISS_SPECULATION ); break; 55 case CONTEXT_STATE_KO_PSYNC_ADDR : (type = EVENT_TYPE_PSYNC ); break; 56 case CONTEXT_STATE_KO_CSYNC_ADDR : (type = EVENT_TYPE_CSYNC ); break; 57 default : (type = EVENT_TYPE_NONE ); break; 58 } 59 // (type = EVENT_TYPE_SPR_ACCESS ); 60 // (type = EVENT_TYPE_MSYNC ); 61 // (type = EVENT_TYPE_BRANCH_NO_ACCURATE); 62 48 63 internal_EVENT_VAL [i] = val; 49 64 PORT_WRITE(out_EVENT_VAL [i], val); … … 52 67 PORT_WRITE(out_EVENT_ADDRESS_NEXT_VAL [i], address_next_val); 53 68 PORT_WRITE(out_EVENT_IS_DS_TAKE [i], is_ds_take); 69 PORT_WRITE(out_EVENT_TYPE [i], type); 70 if (_param->_have_port_depth) 71 PORT_WRITE(out_EVENT_DEPTH [i], depth); 54 72 55 73 log_printf(TRACE,Context_State,FUNCTION," * EVENT Context : %d", i); … … 59 77 log_printf(TRACE,Context_State,FUNCTION," * ADDRESS_NEXT_VAL : %d", address_next_val); 60 78 log_printf(TRACE,Context_State,FUNCTION," * IS_DS_TAKE : %d", is_ds_take); 79 log_printf(TRACE,Context_State,FUNCTION," * TYPE : %d", type); 80 log_printf(TRACE,Context_State,FUNCTION," * DEPTH : %d", depth); 61 81 } 62 82 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/Instruction/src/Instruction.cpp
r88 r97 255 255 inst->_operation = instruction_information(INSTRUCTION_L_ADD)._operation; //OPERATION_ALU_L_ADD; 256 256 inst->_has_immediat = 0; 257 // inst->_immediat = ; 258 inst->_read_ra = 1; 259 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 260 inst->_read_rb = 1; 261 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 262 inst->_read_rc = 0; 263 // inst->_num_reg_rc = ; 257 inst->_immediat = 0; // unnecessary 258 inst->_read_ra = 1; 259 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 260 inst->_read_rb = 1; 261 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 262 inst->_read_rc = 0; 263 inst->_num_reg_rc = 0; //unnecessary 264 264 inst->_write_rd = 1; 265 265 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); … … 271 271 // inst->_branch_stack_write = ; 272 272 // inst->_branch_direction = ; 273 // inst->_address_next = ; 273 // inst->_address_next = ; // already define : PC+4 274 274 inst->_no_execute = 0; 275 275 inst->_event_type = EVENT_TYPE_NONE; … … 283 283 inst->_operation = instruction_information(INSTRUCTION_L_ADDC)._operation; //OPERATION_ALU_L_ADD; 284 284 inst->_has_immediat = 0; 285 // inst->_immediat = ; 285 inst->_immediat = 0; // unnecessary 286 286 inst->_read_ra = 1; 287 287 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); … … 299 299 // inst->_branch_stack_write = ; 300 300 // inst->_branch_direction = ; 301 // inst->_address_next = ; 301 // inst->_address_next = ; // already define : PC+4 302 302 inst->_no_execute = 0; 303 303 inst->_event_type = EVENT_TYPE_NONE; … … 315 315 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 316 316 inst->_read_rb = 0; 317 // inst->_num_reg_rb = ; 318 inst->_read_rc = 0; 319 // inst->_num_reg_rc = ; 317 inst->_num_reg_rb = 0; //unnecessary 318 inst->_read_rc = 0; 319 inst->_num_reg_rc = 0; //unnecessary 320 320 inst->_write_rd = 1; 321 321 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); … … 327 327 // inst->_branch_stack_write = ; 328 328 // inst->_branch_direction = ; 329 // inst->_address_next = ; 329 // inst->_address_next = ; // already define : PC+4 330 330 inst->_no_execute = 0; 331 331 inst->_event_type = EVENT_TYPE_NONE; … … 343 343 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 344 344 inst->_read_rb = 0; 345 // inst->_num_reg_rb = ; 345 inst->_num_reg_rb = 0; //unnecessary 346 346 inst->_read_rc = 1; 347 347 inst->_num_reg_rc = SPR_LOGIC_SR_CY_OV; … … 355 355 // inst->_branch_stack_write = ; 356 356 // inst->_branch_direction = ; 357 // inst->_address_next = ; 357 // inst->_address_next = ; // already define : PC+4 358 358 inst->_no_execute = 0; 359 359 inst->_event_type = EVENT_TYPE_NONE; … … 367 367 inst->_operation = instruction_information(INSTRUCTION_L_AND)._operation; //OPERATION_ALU_L_AND; 368 368 inst->_has_immediat = 0; 369 // inst->_immediat = ; 370 inst->_read_ra = 1; 371 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 372 inst->_read_rb = 1; 373 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 374 inst->_read_rc = 0; 375 // inst->_num_reg_rc = ; 376 inst->_write_rd = 1; 377 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 378 inst->_write_re = 0; 379 // inst->_num_reg_re = ; 380 inst->_exception_use = EXCEPTION_USE_NONE; 381 inst->_exception = EXCEPTION_DECOD_NONE; 382 // inst->_branch_condition = ; 383 // inst->_branch_stack_write = ; 384 // inst->_branch_direction = ; 385 // inst->_address_next = ; 369 inst->_immediat = 0; // unnecessary 370 inst->_read_ra = 1; 371 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 372 inst->_read_rb = 1; 373 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 374 inst->_read_rc = 0; 375 inst->_num_reg_rc = 0; //unnecessary 376 inst->_write_rd = 1; 377 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 378 inst->_write_re = 0; 379 inst->_num_reg_re = 0; //unnecessary 380 inst->_exception_use = EXCEPTION_USE_NONE; 381 inst->_exception = EXCEPTION_DECOD_NONE; 382 // inst->_branch_condition = ; 383 // inst->_branch_stack_write = ; 384 // inst->_branch_direction = ; 385 // inst->_address_next = ; // already define : PC+4 386 386 inst->_no_execute = 0; 387 387 inst->_event_type = EVENT_TYPE_NONE; … … 399 399 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 400 400 inst->_read_rb = 0; 401 // inst->_num_reg_rb = ; 402 inst->_read_rc = 0; 403 // inst->_num_reg_rc = ; 404 inst->_write_rd = 1; 405 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 406 inst->_write_re = 0; 407 // inst->_num_reg_re = ; 408 inst->_exception_use = EXCEPTION_USE_NONE; 409 inst->_exception = EXCEPTION_DECOD_NONE; 410 // inst->_branch_condition = ; 411 // inst->_branch_stack_write = ; 412 // inst->_branch_direction = ; 413 // inst->_address_next = ; 401 inst->_num_reg_rb = 0; //unnecessary 402 inst->_read_rc = 0; 403 inst->_num_reg_rc = 0; //unnecessary 404 inst->_write_rd = 1; 405 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 406 inst->_write_re = 0; 407 inst->_num_reg_re = 0; //unnecessary 408 inst->_exception_use = EXCEPTION_USE_NONE; 409 inst->_exception = EXCEPTION_DECOD_NONE; 410 // inst->_branch_condition = ; 411 // inst->_branch_stack_write = ; 412 // inst->_branch_direction = ; 413 // inst->_address_next = ; // already define : PC+4 414 414 inst->_no_execute = 0; 415 415 inst->_event_type = EVENT_TYPE_NONE; … … 428 428 inst->_immediat = address_next; 429 429 inst->_read_ra = 0; 430 // inst->_num_reg_ra = ; 431 inst->_read_rb = 0; 432 // inst->_num_reg_rb = ; 430 inst->_num_reg_ra = 0; //unnecessary 431 inst->_read_rb = 0; 432 inst->_num_reg_rb = 0; //unnecessary 433 433 inst->_read_rc = 1; 434 434 inst->_num_reg_rc = SPR_LOGIC_SR_F; 435 435 inst->_write_rd = 0; 436 // inst->_num_reg_rd = ; 437 inst->_write_re = 0; 438 // inst->_num_reg_re = ; 436 inst->_num_reg_rd = 0; //unnecessary 437 inst->_write_re = 0; 438 inst->_num_reg_re = 0; //unnecessary 439 439 inst->_exception_use = EXCEPTION_USE_NONE; 440 440 inst->_exception = EXCEPTION_DECOD_NONE; … … 460 460 inst->_immediat = address_next; 461 461 inst->_read_ra = 0; 462 // inst->_num_reg_ra = ; 463 inst->_read_rb = 0; 464 // inst->_num_reg_rb = ; 462 inst->_num_reg_ra = 0; //unnecessary 463 inst->_read_rb = 0; 464 inst->_num_reg_rb = 0; //unnecessary 465 465 inst->_read_rc = 1; 466 466 inst->_num_reg_rc = SPR_LOGIC_SR_F; … … 468 468 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 469 469 inst->_write_re = 0; 470 // inst->_num_reg_re = ; 470 inst->_num_reg_re = 0; //unnecessary 471 471 inst->_exception_use = EXCEPTION_USE_NONE; 472 472 inst->_exception = EXCEPTION_DECOD_NONE; … … 486 486 inst->_operation = instruction_information(INSTRUCTION_L_CMOV)._operation; //OPERATION_MOVE_L_CMOV; 487 487 inst->_has_immediat = 0; 488 // inst->_immediat = ; 488 inst->_immediat = 0; // unnecessary 489 489 inst->_read_ra = 1; 490 490 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); … … 496 496 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 497 497 inst->_write_re = 0; 498 // inst->_num_reg_re = ; 499 inst->_exception_use = EXCEPTION_USE_NONE; 500 inst->_exception = EXCEPTION_DECOD_NONE; 501 // inst->_branch_condition = ; 502 // inst->_branch_stack_write = ; 503 // inst->_branch_direction = ; 504 // inst->_address_next = ; 498 inst->_num_reg_re = 0; //unnecessary 499 inst->_exception_use = EXCEPTION_USE_NONE; 500 inst->_exception = EXCEPTION_DECOD_NONE; 501 // inst->_branch_condition = ; 502 // inst->_branch_stack_write = ; 503 // inst->_branch_direction = ; 504 // inst->_address_next = ; // already define : PC+4 505 505 inst->_no_execute = 0; 506 506 inst->_event_type = EVENT_TYPE_NONE; … … 520 520 inst->_operation = instruction_information(INSTRUCTION_L_CSYNC)._operation; //OPERATION_SPECIAL_L_CSYNC; 521 521 inst->_has_immediat = 0; 522 // inst->_immediat = ; 522 inst->_immediat = 0; // unnecessary 523 523 inst->_read_ra = 0; 524 // inst->_num_reg_ra = ; 525 inst->_read_rb = 0; 526 // inst->_num_reg_rb = ; 527 inst->_read_rc = 0; 528 // inst->_num_reg_rc = ; 529 inst->_write_rd = 0; 530 // inst->_num_reg_rd = ; 531 inst->_write_re = 0; 532 // inst->_num_reg_re = ; 533 inst->_exception_use = EXCEPTION_USE_NONE; 534 inst->_exception = EXCEPTION_DECOD_NONE; 535 // inst->_branch_condition = ; 536 // inst->_branch_stack_write = ; 537 // inst->_branch_direction = ; 538 // inst->_address_next = ; // don't change524 inst->_num_reg_ra = 0; //unnecessary 525 inst->_read_rb = 0; 526 inst->_num_reg_rb = 0; //unnecessary 527 inst->_read_rc = 0; 528 inst->_num_reg_rc = 0; //unnecessary 529 inst->_write_rd = 0; 530 inst->_num_reg_rd = 0; //unnecessary 531 inst->_write_re = 0; 532 inst->_num_reg_re = 0; //unnecessary 533 inst->_exception_use = EXCEPTION_USE_NONE; 534 inst->_exception = EXCEPTION_DECOD_NONE; 535 // inst->_branch_condition = ; 536 // inst->_branch_stack_write = ; 537 // inst->_branch_direction = ; 538 // inst->_address_next = ; // already define : PC+4 // don't change 539 539 inst->_no_execute = 0; 540 540 inst->_event_type = EVENT_TYPE_CSYNC; … … 558 558 inst->_operation = instruction_information(INSTRUCTION_L_DIV)._operation; //OPERATION_DIV_L_DIV; 559 559 inst->_has_immediat = 0; 560 // inst->_immediat = ; 561 inst->_read_ra = 1; 562 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 563 inst->_read_rb = 1; 564 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 565 inst->_read_rc = 0; 566 // inst->_num_reg_rc = ; 560 inst->_immediat = 0; // unnecessary 561 inst->_read_ra = 1; 562 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 563 inst->_read_rb = 1; 564 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 565 inst->_read_rc = 0; 566 inst->_num_reg_rc = 0; //unnecessary 567 567 inst->_write_rd = 1; 568 568 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); … … 574 574 // inst->_branch_stack_write = ; 575 575 // inst->_branch_direction = ; 576 // inst->_address_next = ; 576 // inst->_address_next = ; // already define : PC+4 577 577 inst->_no_execute = 0; 578 578 inst->_event_type = EVENT_TYPE_NONE; … … 586 586 inst->_operation = instruction_information(INSTRUCTION_L_DIVU)._operation; //OPERATION_DIV_L_DIVU; 587 587 inst->_has_immediat = 0; 588 // inst->_immediat = ; 589 inst->_read_ra = 1; 590 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 591 inst->_read_rb = 1; 592 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 593 inst->_read_rc = 0; 594 // inst->_num_reg_rc = ; 588 inst->_immediat = 0; // unnecessary 589 inst->_read_ra = 1; 590 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 591 inst->_read_rb = 1; 592 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 593 inst->_read_rc = 0; 594 inst->_num_reg_rc = 0; //unnecessary 595 595 inst->_write_rd = 1; 596 596 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); … … 602 602 // inst->_branch_stack_write = ; 603 603 // inst->_branch_direction = ; 604 // inst->_address_next = ; 604 // inst->_address_next = ; // already define : PC+4 605 605 inst->_no_execute = 0; 606 606 inst->_event_type = EVENT_TYPE_NONE; … … 618 618 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 619 619 inst->_read_rb = 0; 620 // inst->_num_reg_rb = ; 621 inst->_read_rc = 0; 622 // inst->_num_reg_rc = ; 623 inst->_write_rd = 1; 624 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 625 inst->_write_re = 0; 626 // inst->_num_reg_re = ; 627 inst->_exception_use = EXCEPTION_USE_NONE; 628 inst->_exception = EXCEPTION_DECOD_NONE; 629 // inst->_branch_condition = ; 630 // inst->_branch_stack_write = ; 631 // inst->_branch_direction = ; 632 // inst->_address_next = ; 620 inst->_num_reg_rb = 0; //unnecessary 621 inst->_read_rc = 0; 622 inst->_num_reg_rc = 0; //unnecessary 623 inst->_write_rd = 1; 624 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 625 inst->_write_re = 0; 626 inst->_num_reg_re = 0; //unnecessary 627 inst->_exception_use = EXCEPTION_USE_NONE; 628 inst->_exception = EXCEPTION_DECOD_NONE; 629 // inst->_branch_condition = ; 630 // inst->_branch_stack_write = ; 631 // inst->_branch_direction = ; 632 // inst->_address_next = ; // already define : PC+4 633 633 inst->_no_execute = 0; 634 634 inst->_event_type = EVENT_TYPE_NONE; … … 646 646 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 647 647 inst->_read_rb = 0; 648 // inst->_num_reg_rb = ; 649 inst->_read_rc = 0; 650 // inst->_num_reg_rc = ; 651 inst->_write_rd = 1; 652 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 653 inst->_write_re = 0; 654 // inst->_num_reg_re = ; 655 inst->_exception_use = EXCEPTION_USE_NONE; 656 inst->_exception = EXCEPTION_DECOD_NONE; 657 // inst->_branch_condition = ; 658 // inst->_branch_stack_write = ; 659 // inst->_branch_direction = ; 660 // inst->_address_next = ; 648 inst->_num_reg_rb = 0; //unnecessary 649 inst->_read_rc = 0; 650 inst->_num_reg_rc = 0; //unnecessary 651 inst->_write_rd = 1; 652 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 653 inst->_write_re = 0; 654 inst->_num_reg_re = 0; //unnecessary 655 inst->_exception_use = EXCEPTION_USE_NONE; 656 inst->_exception = EXCEPTION_DECOD_NONE; 657 // inst->_branch_condition = ; 658 // inst->_branch_stack_write = ; 659 // inst->_branch_direction = ; 660 // inst->_address_next = ; // already define : PC+4 661 661 inst->_no_execute = 0; 662 662 inst->_event_type = EVENT_TYPE_NONE; … … 674 674 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 675 675 inst->_read_rb = 0; 676 // inst->_num_reg_rb = ; 677 inst->_read_rc = 0; 678 // inst->_num_reg_rc = ; 679 inst->_write_rd = 1; 680 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 681 inst->_write_re = 0; 682 // inst->_num_reg_re = ; 683 inst->_exception_use = EXCEPTION_USE_NONE; 684 inst->_exception = EXCEPTION_DECOD_NONE; 685 // inst->_branch_condition = ; 686 // inst->_branch_stack_write = ; 687 // inst->_branch_direction = ; 688 // inst->_address_next = ; 676 inst->_num_reg_rb = 0; //unnecessary 677 inst->_read_rc = 0; 678 inst->_num_reg_rc = 0; //unnecessary 679 inst->_write_rd = 1; 680 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 681 inst->_write_re = 0; 682 inst->_num_reg_re = 0; //unnecessary 683 inst->_exception_use = EXCEPTION_USE_NONE; 684 inst->_exception = EXCEPTION_DECOD_NONE; 685 // inst->_branch_condition = ; 686 // inst->_branch_stack_write = ; 687 // inst->_branch_direction = ; 688 // inst->_address_next = ; // already define : PC+4 689 689 inst->_no_execute = 0; 690 690 inst->_event_type = EVENT_TYPE_NONE; … … 702 702 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 703 703 inst->_read_rb = 0; 704 // inst->_num_reg_rb = ; 705 inst->_read_rc = 0; 706 // inst->_num_reg_rc = ; 707 inst->_write_rd = 1; 708 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 709 inst->_write_re = 0; 710 // inst->_num_reg_re = ; 711 inst->_exception_use = EXCEPTION_USE_NONE; 712 inst->_exception = EXCEPTION_DECOD_NONE; 713 // inst->_branch_condition = ; 714 // inst->_branch_stack_write = ; 715 // inst->_branch_direction = ; 716 // inst->_address_next = ; 704 inst->_num_reg_rb = 0; //unnecessary 705 inst->_read_rc = 0; 706 inst->_num_reg_rc = 0; //unnecessary 707 inst->_write_rd = 1; 708 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 709 inst->_write_re = 0; 710 inst->_num_reg_re = 0; //unnecessary 711 inst->_exception_use = EXCEPTION_USE_NONE; 712 inst->_exception = EXCEPTION_DECOD_NONE; 713 // inst->_branch_condition = ; 714 // inst->_branch_stack_write = ; 715 // inst->_branch_direction = ; 716 // inst->_address_next = ; // already define : PC+4 717 717 inst->_no_execute = 0; 718 718 inst->_event_type = EVENT_TYPE_NONE; … … 730 730 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 731 731 inst->_read_rb = 0; 732 // inst->_num_reg_rb = ; 733 inst->_read_rc = 0; 734 // inst->_num_reg_rc = ; 735 inst->_write_rd = 1; 736 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 737 inst->_write_re = 0; 738 // inst->_num_reg_re = ; 739 inst->_exception_use = EXCEPTION_USE_NONE; 740 inst->_exception = EXCEPTION_DECOD_NONE; 741 // inst->_branch_condition = ; 742 // inst->_branch_stack_write = ; 743 // inst->_branch_direction = ; 744 // inst->_address_next = ; 732 inst->_num_reg_rb = 0; //unnecessary 733 inst->_read_rc = 0; 734 inst->_num_reg_rc = 0; //unnecessary 735 inst->_write_rd = 1; 736 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 737 inst->_write_re = 0; 738 inst->_num_reg_re = 0; //unnecessary 739 inst->_exception_use = EXCEPTION_USE_NONE; 740 inst->_exception = EXCEPTION_DECOD_NONE; 741 // inst->_branch_condition = ; 742 // inst->_branch_stack_write = ; 743 // inst->_branch_direction = ; 744 // inst->_address_next = ; // already define : PC+4 745 745 inst->_no_execute = 0; 746 746 inst->_event_type = EVENT_TYPE_NONE; … … 758 758 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 759 759 inst->_read_rb = 0; 760 // inst->_num_reg_rb = ; 761 inst->_read_rc = 0; 762 // inst->_num_reg_rc = ; 763 inst->_write_rd = 1; 764 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 765 inst->_write_re = 0; 766 // inst->_num_reg_re = ; 767 inst->_exception_use = EXCEPTION_USE_NONE; 768 inst->_exception = EXCEPTION_DECOD_NONE; 769 // inst->_branch_condition = ; 770 // inst->_branch_stack_write = ; 771 // inst->_branch_direction = ; 772 // inst->_address_next = ; 760 inst->_num_reg_rb = 0; //unnecessary 761 inst->_read_rc = 0; 762 inst->_num_reg_rc = 0; //unnecessary 763 inst->_write_rd = 1; 764 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 765 inst->_write_re = 0; 766 inst->_num_reg_re = 0; //unnecessary 767 inst->_exception_use = EXCEPTION_USE_NONE; 768 inst->_exception = EXCEPTION_DECOD_NONE; 769 // inst->_branch_condition = ; 770 // inst->_branch_stack_write = ; 771 // inst->_branch_direction = ; 772 // inst->_address_next = ; // already define : PC+4 773 773 inst->_no_execute = 0; 774 774 inst->_event_type = EVENT_TYPE_NONE; … … 782 782 inst->_operation = instruction_information(INSTRUCTION_L_FF1)._operation; //OPERATION_FIND_L_FF1; 783 783 inst->_has_immediat = 0; 784 // inst->_immediat = ; 785 inst->_read_ra = 1; 786 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 787 inst->_read_rb = 0; 788 // inst->_num_reg_rb = ; 789 inst->_read_rc = 0; 790 // inst->_num_reg_rc = ; 791 inst->_write_rd = 1; 792 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 793 inst->_write_re = 0; 794 // inst->_num_reg_re = ; 795 inst->_exception_use = EXCEPTION_USE_NONE; 796 inst->_exception = EXCEPTION_DECOD_NONE; 797 // inst->_branch_condition = ; 798 // inst->_branch_stack_write = ; 799 // inst->_branch_direction = ; 800 // inst->_address_next = ; 784 inst->_immediat = 0; // unnecessary 785 inst->_read_ra = 1; 786 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 787 inst->_read_rb = 0; 788 inst->_num_reg_rb = 0; //unnecessary 789 inst->_read_rc = 0; 790 inst->_num_reg_rc = 0; //unnecessary 791 inst->_write_rd = 1; 792 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 793 inst->_write_re = 0; 794 inst->_num_reg_re = 0; //unnecessary 795 inst->_exception_use = EXCEPTION_USE_NONE; 796 inst->_exception = EXCEPTION_DECOD_NONE; 797 // inst->_branch_condition = ; 798 // inst->_branch_stack_write = ; 799 // inst->_branch_direction = ; 800 // inst->_address_next = ; // already define : PC+4 801 801 inst->_no_execute = 0; 802 802 inst->_event_type = EVENT_TYPE_NONE; … … 810 810 inst->_operation = instruction_information(INSTRUCTION_L_FL1)._operation; //OPERATION_FIND_L_FL1; 811 811 inst->_has_immediat = 0; 812 // inst->_immediat = ; 813 inst->_read_ra = 1; 814 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 815 inst->_read_rb = 0; 816 // inst->_num_reg_rb = ; 817 inst->_read_rc = 0; 818 // inst->_num_reg_rc = ; 819 inst->_write_rd = 1; 820 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 821 inst->_write_re = 0; 822 // inst->_num_reg_re = ; 823 inst->_exception_use = EXCEPTION_USE_NONE; 824 inst->_exception = EXCEPTION_DECOD_NONE; 825 // inst->_branch_condition = ; 826 // inst->_branch_stack_write = ; 827 // inst->_branch_direction = ; 828 // inst->_address_next = ; 812 inst->_immediat = 0; // unnecessary 813 inst->_read_ra = 1; 814 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 815 inst->_read_rb = 0; 816 inst->_num_reg_rb = 0; //unnecessary 817 inst->_read_rc = 0; 818 inst->_num_reg_rc = 0; //unnecessary 819 inst->_write_rd = 1; 820 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 821 inst->_write_re = 0; 822 inst->_num_reg_re = 0; //unnecessary 823 inst->_exception_use = EXCEPTION_USE_NONE; 824 inst->_exception = EXCEPTION_DECOD_NONE; 825 // inst->_branch_condition = ; 826 // inst->_branch_stack_write = ; 827 // inst->_branch_direction = ; 828 // inst->_address_next = ; // already define : PC+4 829 829 inst->_no_execute = 0; 830 830 inst->_event_type = EVENT_TYPE_NONE; … … 838 838 inst->_operation = instruction_information(INSTRUCTION_L_J)._operation; //OPERATION_BRANCH_NONE; 839 839 inst->_has_immediat = 0; 840 // inst->_immediat = ; 840 inst->_immediat = 0; // unnecessary 841 841 inst->_read_ra = 0; 842 // inst->_num_reg_ra = ; 843 inst->_read_rb = 0; 844 // inst->_num_reg_rb = ; 845 inst->_read_rc = 0; 846 // inst->_num_reg_rc = ; 847 inst->_write_rd = 0; 848 // inst->_num_reg_rd = ; 849 inst->_write_re = 0; 850 // inst->_num_reg_re = ; 842 inst->_num_reg_ra = 0; //unnecessary 843 inst->_read_rb = 0; 844 inst->_num_reg_rb = 0; //unnecessary 845 inst->_read_rc = 0; 846 inst->_num_reg_rc = 0; //unnecessary 847 inst->_write_rd = 0; 848 inst->_num_reg_rd = 0; //unnecessary 849 inst->_write_re = 0; 850 inst->_num_reg_re = 0; //unnecessary 851 851 inst->_exception_use = EXCEPTION_USE_NONE; 852 852 inst->_exception = EXCEPTION_DECOD_NONE; … … 869 869 inst->_immediat = inst->_address_next+1; 870 870 inst->_read_ra = 0; 871 // inst->_num_reg_ra = ; 872 inst->_read_rb = 0; 873 // inst->_num_reg_rb = ; 874 inst->_read_rc = 0; 875 // inst->_num_reg_rc = ; 871 inst->_num_reg_ra = 0; //unnecessary 872 inst->_read_rb = 0; 873 inst->_num_reg_rb = 0; //unnecessary 874 inst->_read_rc = 0; 875 inst->_num_reg_rc = 0; //unnecessary 876 876 inst->_write_rd = 1; 877 877 inst->_num_reg_rd = 9; // Link register 878 878 inst->_write_re = 0; 879 // inst->_num_reg_re = ; 879 inst->_num_reg_re = 0; //unnecessary 880 880 inst->_exception_use = EXCEPTION_USE_NONE; 881 881 inst->_exception = EXCEPTION_DECOD_NONE; … … 904 904 inst->_operation = instruction_information(INSTRUCTION_L_JALR)._operation; //OPERATION_BRANCH_L_JALR; 905 905 inst->_has_immediat = 0; 906 // inst->_immediat = ; 906 inst->_immediat = 0; // unnecessary 907 907 inst->_read_ra = 0; 908 // inst->_num_reg_ra = ; 908 inst->_num_reg_ra = 0; //unnecessary 909 909 inst->_read_rb = 1; 910 910 // inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 911 911 inst->_read_rc = 0; 912 // inst->_num_reg_rc = ; 912 inst->_num_reg_rc = 0; //unnecessary 913 913 inst->_write_rd = 1; 914 914 inst->_num_reg_rd = 9; // Link register 915 915 inst->_write_re = 0; 916 // inst->_num_reg_re = ; 916 inst->_num_reg_re = 0; //unnecessary 917 917 inst->_exception_use = EXCEPTION_USE_NONE; 918 918 inst->_exception = EXCEPTION_DECOD_NONE; … … 921 921 // inst->_branch_stack_write = 1; 922 922 inst->_branch_direction = 1; 923 // inst->_address_next = ; 923 // inst->_address_next = ; // already define : PC+4 924 924 inst->_no_execute = 0; 925 925 inst->_event_type = EVENT_TYPE_NONE; … … 934 934 inst->_operation = instruction_information(INSTRUCTION_L_JR)._operation; //OPERATION_BRANCH_L_JALR; 935 935 inst->_has_immediat = 0; 936 // inst->_immediat = ; 936 inst->_immediat = 0; // unnecessary 937 937 inst->_read_ra = 0; 938 // inst->_num_reg_ra = ; 939 inst->_read_rb = 1; 940 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 941 inst->_read_rc = 0; 942 // inst->_num_reg_rc = ; 943 inst->_write_rd = 0; 944 // inst->_num_reg_rd = ; 945 inst->_write_re = 0; 946 // inst->_num_reg_re = ; 938 inst->_num_reg_ra = 0; //unnecessary 939 inst->_read_rb = 1; 940 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 941 inst->_read_rc = 0; 942 inst->_num_reg_rc = 0; //unnecessary 943 inst->_write_rd = 0; 944 inst->_num_reg_rd = 0; //unnecessary 945 inst->_write_re = 0; 946 inst->_num_reg_re = 0; //unnecessary 947 947 inst->_exception_use = EXCEPTION_USE_NONE; 948 948 inst->_exception = EXCEPTION_DECOD_NONE; … … 950 950 // inst->_branch_stack_write = 0; 951 951 inst->_branch_direction = 1; 952 // inst->_address_next = ; 952 // inst->_address_next = ; // already define : PC+4 953 953 inst->_no_execute = 0; 954 954 inst->_event_type = EVENT_TYPE_NONE; … … 966 966 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 967 967 inst->_read_rb = 0; 968 // inst->_num_reg_rb = ; 969 inst->_read_rc = 0; 970 // inst->_num_reg_rc = ; 971 inst->_write_rd = 1; 972 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 973 inst->_write_re = 0; 974 // inst->_num_reg_re = ; 968 inst->_num_reg_rb = 0; //unnecessary 969 inst->_read_rc = 0; 970 inst->_num_reg_rc = 0; //unnecessary 971 inst->_write_rd = 1; 972 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 973 inst->_write_re = 0; 974 inst->_num_reg_re = 0; //unnecessary 975 975 inst->_exception_use = EXCEPTION_USE_MEMORY_WITHOUT_ALIGNMENT; 976 976 inst->_exception = EXCEPTION_DECOD_NONE; … … 978 978 // inst->_branch_stack_write = ; 979 979 // inst->_branch_direction = ; 980 // inst->_address_next = ; 980 // inst->_address_next = ; // already define : PC+4 981 981 inst->_no_execute = 0; 982 982 inst->_event_type = EVENT_TYPE_NONE; … … 994 994 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 995 995 inst->_read_rb = 0; 996 // inst->_num_reg_rb = ; 997 inst->_read_rc = 0; 998 // inst->_num_reg_rc = ; 999 inst->_write_rd = 1; 1000 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 1001 inst->_write_re = 0; 1002 // inst->_num_reg_re = ; 996 inst->_num_reg_rb = 0; //unnecessary 997 inst->_read_rc = 0; 998 inst->_num_reg_rc = 0; //unnecessary 999 inst->_write_rd = 1; 1000 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 1001 inst->_write_re = 0; 1002 inst->_num_reg_re = 0; //unnecessary 1003 1003 inst->_exception_use = EXCEPTION_USE_MEMORY_WITHOUT_ALIGNMENT; 1004 1004 inst->_exception = EXCEPTION_DECOD_NONE; … … 1006 1006 // inst->_branch_stack_write = ; 1007 1007 // inst->_branch_direction = ; 1008 // inst->_address_next = ; 1008 // inst->_address_next = ; // already define : PC+4 1009 1009 inst->_no_execute = 0; 1010 1010 inst->_event_type = EVENT_TYPE_NONE; … … 1022 1022 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1023 1023 inst->_read_rb = 0; 1024 // inst->_num_reg_rb = ; 1025 inst->_read_rc = 0; 1026 // inst->_num_reg_rc = ; 1027 inst->_write_rd = 1; 1028 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 1029 inst->_write_re = 0; 1030 // inst->_num_reg_re = ; 1024 inst->_num_reg_rb = 0; //unnecessary 1025 inst->_read_rc = 0; 1026 inst->_num_reg_rc = 0; //unnecessary 1027 inst->_write_rd = 1; 1028 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 1029 inst->_write_re = 0; 1030 inst->_num_reg_re = 0; //unnecessary 1031 1031 inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT; 1032 1032 inst->_exception = EXCEPTION_DECOD_NONE; … … 1034 1034 // inst->_branch_stack_write = ; 1035 1035 // inst->_branch_direction = ; 1036 // inst->_address_next = ; 1036 // inst->_address_next = ; // already define : PC+4 1037 1037 inst->_no_execute = 0; 1038 1038 inst->_event_type = EVENT_TYPE_NONE; … … 1050 1050 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1051 1051 inst->_read_rb = 0; 1052 // inst->_num_reg_rb = ; 1053 inst->_read_rc = 0; 1054 // inst->_num_reg_rc = ; 1055 inst->_write_rd = 1; 1056 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 1057 inst->_write_re = 0; 1058 // inst->_num_reg_re = ; 1052 inst->_num_reg_rb = 0; //unnecessary 1053 inst->_read_rc = 0; 1054 inst->_num_reg_rc = 0; //unnecessary 1055 inst->_write_rd = 1; 1056 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 1057 inst->_write_re = 0; 1058 inst->_num_reg_re = 0; //unnecessary 1059 1059 inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT; 1060 1060 inst->_exception = EXCEPTION_DECOD_NONE; … … 1062 1062 // inst->_branch_stack_write = ; 1063 1063 // inst->_branch_direction = ; 1064 // inst->_address_next = ; 1064 // inst->_address_next = ; // already define : PC+4 1065 1065 inst->_no_execute = 0; 1066 1066 inst->_event_type = EVENT_TYPE_NONE; … … 1078 1078 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1079 1079 inst->_read_rb = 0; 1080 // inst->_num_reg_rb = ; 1081 inst->_read_rc = 0; 1082 // inst->_num_reg_rc = ; 1083 inst->_write_rd = 1; 1084 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 1085 inst->_write_re = 0; 1086 // inst->_num_reg_re = ; 1080 inst->_num_reg_rb = 0; //unnecessary 1081 inst->_read_rc = 0; 1082 inst->_num_reg_rc = 0; //unnecessary 1083 inst->_write_rd = 1; 1084 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 1085 inst->_write_re = 0; 1086 inst->_num_reg_re = 0; //unnecessary 1087 1087 inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT; 1088 1088 inst->_exception = EXCEPTION_DECOD_NONE; … … 1090 1090 // inst->_branch_stack_write = ; 1091 1091 // inst->_branch_direction = ; 1092 // inst->_address_next = ; 1092 // inst->_address_next = ; // already define : PC+4 1093 1093 inst->_no_execute = 0; 1094 1094 inst->_event_type = EVENT_TYPE_NONE; … … 1106 1106 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1107 1107 inst->_read_rb = 0; 1108 // inst->_num_reg_rb = ; 1109 inst->_read_rc = 0; 1110 // inst->_num_reg_rc = ; 1111 inst->_write_rd = 1; 1112 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 1113 inst->_write_re = 0; 1114 // inst->_num_reg_re = ; 1108 inst->_num_reg_rb = 0; //unnecessary 1109 inst->_read_rc = 0; 1110 inst->_num_reg_rc = 0; //unnecessary 1111 inst->_write_rd = 1; 1112 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 1113 inst->_write_re = 0; 1114 inst->_num_reg_re = 0; //unnecessary 1115 1115 inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT; 1116 1116 inst->_exception = EXCEPTION_DECOD_NONE; … … 1118 1118 // inst->_branch_stack_write = ; 1119 1119 // inst->_branch_direction = ; 1120 // inst->_address_next = ; 1120 // inst->_address_next = ; // already define : PC+4 1121 1121 inst->_no_execute = 0; 1122 1122 inst->_event_type = EVENT_TYPE_NONE; … … 1134 1134 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1135 1135 inst->_read_rb = 0; 1136 // inst->_num_reg_rb = ; 1137 inst->_read_rc = 0; 1138 // inst->_num_reg_rc = ; 1139 inst->_write_rd = 1; 1140 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 1141 inst->_write_re = 0; 1142 // inst->_num_reg_re = ; 1136 inst->_num_reg_rb = 0; //unnecessary 1137 inst->_read_rc = 0; 1138 inst->_num_reg_rc = 0; //unnecessary 1139 inst->_write_rd = 1; 1140 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 1141 inst->_write_re = 0; 1142 inst->_num_reg_re = 0; //unnecessary 1143 1143 inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT; 1144 1144 inst->_exception = EXCEPTION_DECOD_NONE; … … 1146 1146 // inst->_branch_stack_write = ; 1147 1147 // inst->_branch_direction = ; 1148 // inst->_address_next = ; 1148 // inst->_address_next = ; // already define : PC+4 1149 1149 inst->_no_execute = 0; 1150 1150 inst->_event_type = EVENT_TYPE_NONE; … … 1158 1158 inst->_operation = instruction_information(INSTRUCTION_L_MAC)._operation; //OPERATION_SPECIAL_L_MAC; 1159 1159 inst->_has_immediat = 0; 1160 // inst->_immediat = ; 1161 inst->_read_ra = 1; 1162 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1163 inst->_read_rb = 1; 1164 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 1165 inst->_read_rc = 0; 1166 // inst->_num_reg_rc = ; 1167 inst->_write_rd = 0; 1168 // inst->_num_reg_rd = ; 1169 inst->_write_re = 0; 1170 // inst->_num_reg_re = ; 1171 inst->_exception_use = EXCEPTION_USE_NONE; 1172 inst->_exception = EXCEPTION_DECOD_NONE; 1173 // inst->_branch_condition = ; 1174 // inst->_branch_stack_write = ; 1175 // inst->_branch_direction = ; 1176 // inst->_address_next = ; // don't change1160 inst->_immediat = 0; // unnecessary 1161 inst->_read_ra = 1; 1162 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1163 inst->_read_rb = 1; 1164 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 1165 inst->_read_rc = 0; 1166 inst->_num_reg_rc = 0; //unnecessary 1167 inst->_write_rd = 0; 1168 inst->_num_reg_rd = 0; //unnecessary 1169 inst->_write_re = 0; 1170 inst->_num_reg_re = 0; //unnecessary 1171 inst->_exception_use = EXCEPTION_USE_NONE; 1172 inst->_exception = EXCEPTION_DECOD_NONE; 1173 // inst->_branch_condition = ; 1174 // inst->_branch_stack_write = ; 1175 // inst->_branch_direction = ; 1176 // inst->_address_next = ; // already define : PC+4 // don't change 1177 1177 inst->_no_execute = 0; 1178 1178 inst->_event_type = EVENT_TYPE_SPR_ACCESS; … … 1191 1191 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1192 1192 inst->_read_rb = 0; 1193 // inst->_num_reg_rb = ; 1194 inst->_read_rc = 0; 1195 // inst->_num_reg_rc = ; 1196 inst->_write_rd = 0; 1197 // inst->_num_reg_rd = ; 1198 inst->_write_re = 0; 1199 // inst->_num_reg_re = ; 1200 inst->_exception_use = EXCEPTION_USE_NONE; 1201 inst->_exception = EXCEPTION_DECOD_NONE; 1202 // inst->_branch_condition = ; 1203 // inst->_branch_stack_write = ; 1204 // inst->_branch_direction = ; 1205 // inst->_address_next = ; // don't change1193 inst->_num_reg_rb = 0; //unnecessary 1194 inst->_read_rc = 0; 1195 inst->_num_reg_rc = 0; //unnecessary 1196 inst->_write_rd = 0; 1197 inst->_num_reg_rd = 0; //unnecessary 1198 inst->_write_re = 0; 1199 inst->_num_reg_re = 0; //unnecessary 1200 inst->_exception_use = EXCEPTION_USE_NONE; 1201 inst->_exception = EXCEPTION_DECOD_NONE; 1202 // inst->_branch_condition = ; 1203 // inst->_branch_stack_write = ; 1204 // inst->_branch_direction = ; 1205 // inst->_address_next = ; // already define : PC+4 // don't change 1206 1206 inst->_no_execute = 0; 1207 1207 inst->_event_type = EVENT_TYPE_SPR_ACCESS; … … 1221 1221 inst->_operation = instruction_information(INSTRUCTION_L_MACRC)._operation; //OPERATION_SPECIAL_L_MACRC; 1222 1222 inst->_has_immediat = 0; 1223 // inst->_immediat = ; 1223 inst->_immediat = 0; // unnecessary 1224 1224 inst->_read_ra = 0; 1225 // inst->_num_reg_ra = ; 1226 inst->_read_rb = 0; 1227 // inst->_num_reg_rb = ; 1228 inst->_read_rc = 0; 1229 // inst->_num_reg_rc = ; 1230 inst->_write_rd = 1; 1231 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 1232 inst->_write_re = 0; 1233 // inst->_num_reg_re = ; 1234 inst->_exception_use = EXCEPTION_USE_NONE; 1235 inst->_exception = EXCEPTION_DECOD_NONE; 1236 // inst->_branch_condition = ; 1237 // inst->_branch_stack_write = ; 1238 // inst->_branch_direction = ; 1239 // inst->_address_next = ; // don't change1225 inst->_num_reg_ra = 0; //unnecessary 1226 inst->_read_rb = 0; 1227 inst->_num_reg_rb = 0; //unnecessary 1228 inst->_read_rc = 0; 1229 inst->_num_reg_rc = 0; //unnecessary 1230 inst->_write_rd = 1; 1231 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 1232 inst->_write_re = 0; 1233 inst->_num_reg_re = 0; //unnecessary 1234 inst->_exception_use = EXCEPTION_USE_NONE; 1235 inst->_exception = EXCEPTION_DECOD_NONE; 1236 // inst->_branch_condition = ; 1237 // inst->_branch_stack_write = ; 1238 // inst->_branch_direction = ; 1239 // inst->_address_next = ; // already define : PC+4 // don't change 1240 1240 inst->_no_execute = 0; 1241 1241 inst->_event_type = EVENT_TYPE_SPR_ACCESS; … … 1254 1254 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1255 1255 inst->_read_rb = 0; 1256 // inst->_num_reg_rb = ; 1257 inst->_read_rc = 0; 1258 // inst->_num_reg_rc = ; 1259 inst->_write_rd = 1; 1260 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 1261 inst->_write_re = 0; 1262 // inst->_num_reg_re = ; 1263 inst->_exception_use = EXCEPTION_USE_NONE; 1264 inst->_exception = EXCEPTION_DECOD_NONE; 1265 // inst->_branch_condition = ; 1266 // inst->_branch_stack_write = ; 1267 // inst->_branch_direction = ; 1268 // inst->_address_next = ; // don't change1256 inst->_num_reg_rb = 0; //unnecessary 1257 inst->_read_rc = 0; 1258 inst->_num_reg_rc = 0; //unnecessary 1259 inst->_write_rd = 1; 1260 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 1261 inst->_write_re = 0; 1262 inst->_num_reg_re = 0; //unnecessary 1263 inst->_exception_use = EXCEPTION_USE_NONE; 1264 inst->_exception = EXCEPTION_DECOD_NONE; 1265 // inst->_branch_condition = ; 1266 // inst->_branch_stack_write = ; 1267 // inst->_branch_direction = ; 1268 // inst->_address_next = ; // already define : PC+4 // don't change 1269 1269 inst->_no_execute = 0; 1270 1270 inst->_event_type = EVENT_TYPE_SPR_ACCESS; … … 1280 1280 inst->_immediat = EXTENDZ(inst->_instruction,16); 1281 1281 inst->_read_ra = 0; 1282 // inst->_num_reg_ra = ; 1283 inst->_read_rb = 0; 1284 // inst->_num_reg_rb = ; 1285 inst->_read_rc = 0; 1286 // inst->_num_reg_rc = ; 1287 inst->_write_rd = 1; 1288 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 1289 inst->_write_re = 0; 1290 // inst->_num_reg_re = ; 1291 inst->_exception_use = EXCEPTION_USE_NONE; 1292 inst->_exception = EXCEPTION_DECOD_NONE; 1293 // inst->_branch_condition = ; 1294 // inst->_branch_stack_write = ; 1295 // inst->_branch_direction = ; 1296 // inst->_address_next = ; 1282 inst->_num_reg_ra = 0; //unnecessary 1283 inst->_read_rb = 0; 1284 inst->_num_reg_rb = 0; //unnecessary 1285 inst->_read_rc = 0; 1286 inst->_num_reg_rc = 0; //unnecessary 1287 inst->_write_rd = 1; 1288 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 1289 inst->_write_re = 0; 1290 inst->_num_reg_re = 0; //unnecessary 1291 inst->_exception_use = EXCEPTION_USE_NONE; 1292 inst->_exception = EXCEPTION_DECOD_NONE; 1293 // inst->_branch_condition = ; 1294 // inst->_branch_stack_write = ; 1295 // inst->_branch_direction = ; 1296 // inst->_address_next = ; // already define : PC+4 1297 1297 inst->_no_execute = 0; 1298 1298 inst->_event_type = EVENT_TYPE_NONE; … … 1306 1306 inst->_operation = instruction_information(INSTRUCTION_L_MSB)._operation; //OPERATION_SPECIAL_L_MSB; 1307 1307 inst->_has_immediat = 0; 1308 // inst->_immediat = ; 1309 inst->_read_ra = 1; 1310 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1311 inst->_read_rb = 1; 1312 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 1313 inst->_read_rc = 0; 1314 // inst->_num_reg_rc = ; 1315 inst->_write_rd = 0; 1316 // inst->_num_reg_rd = ; 1317 inst->_write_re = 0; 1318 // inst->_num_reg_re = ; 1319 inst->_exception_use = EXCEPTION_USE_NONE; 1320 inst->_exception = EXCEPTION_DECOD_NONE; 1321 // inst->_branch_condition = ; 1322 // inst->_branch_stack_write = ; 1323 // inst->_branch_direction = ; 1324 // inst->_address_next = ; // don't change1308 inst->_immediat = 0; // unnecessary 1309 inst->_read_ra = 1; 1310 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1311 inst->_read_rb = 1; 1312 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 1313 inst->_read_rc = 0; 1314 inst->_num_reg_rc = 0; //unnecessary 1315 inst->_write_rd = 0; 1316 inst->_num_reg_rd = 0; //unnecessary 1317 inst->_write_re = 0; 1318 inst->_num_reg_re = 0; //unnecessary 1319 inst->_exception_use = EXCEPTION_USE_NONE; 1320 inst->_exception = EXCEPTION_DECOD_NONE; 1321 // inst->_branch_condition = ; 1322 // inst->_branch_stack_write = ; 1323 // inst->_branch_direction = ; 1324 // inst->_address_next = ; // already define : PC+4 // don't change 1325 1325 inst->_no_execute = 0; 1326 1326 inst->_event_type = EVENT_TYPE_SPR_ACCESS; … … 1340 1340 inst->_operation = instruction_information(INSTRUCTION_L_MSYNC)._operation; //OPERATION_SPECIAL_L_MSYNC; 1341 1341 inst->_has_immediat = 0; 1342 // inst->_immediat = ; 1342 inst->_immediat = 0; // unnecessary 1343 1343 inst->_read_ra = 0; 1344 // inst->_num_reg_ra = ; 1345 inst->_read_rb = 0; 1346 // inst->_num_reg_rb = ; 1347 inst->_read_rc = 0; 1348 // inst->_num_reg_rc = ; 1349 inst->_write_rd = 0; 1350 // inst->_num_reg_rd = ; 1351 inst->_write_re = 0; 1352 // inst->_num_reg_re = ; 1353 inst->_exception_use = EXCEPTION_USE_NONE; 1354 inst->_exception = EXCEPTION_DECOD_NONE; 1355 // inst->_branch_condition = ; 1356 // inst->_branch_stack_write = ; 1357 // inst->_branch_direction = ; 1358 // inst->_address_next = ; // don't change1344 inst->_num_reg_ra = 0; //unnecessary 1345 inst->_read_rb = 0; 1346 inst->_num_reg_rb = 0; //unnecessary 1347 inst->_read_rc = 0; 1348 inst->_num_reg_rc = 0; //unnecessary 1349 inst->_write_rd = 0; 1350 inst->_num_reg_rd = 0; //unnecessary 1351 inst->_write_re = 0; 1352 inst->_num_reg_re = 0; //unnecessary 1353 inst->_exception_use = EXCEPTION_USE_NONE; 1354 inst->_exception = EXCEPTION_DECOD_NONE; 1355 // inst->_branch_condition = ; 1356 // inst->_branch_stack_write = ; 1357 // inst->_branch_direction = ; 1358 // inst->_address_next = ; // already define : PC+4 // don't change 1359 1359 inst->_no_execute = 0; 1360 1360 inst->_event_type = EVENT_TYPE_MSYNC; … … 1376 1376 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 1377 1377 inst->_read_rc = 0; 1378 // inst->_num_reg_rc = ; 1379 inst->_write_rd = 0; 1380 // inst->_num_reg_rd = ; 1381 inst->_write_re = 0; 1382 // inst->_num_reg_re = ; 1383 inst->_exception_use = EXCEPTION_USE_NONE; 1384 inst->_exception = EXCEPTION_DECOD_NONE; 1385 // inst->_branch_condition = ; 1386 // inst->_branch_stack_write = ; 1387 // inst->_branch_direction = ; 1388 // inst->_address_next = ; // don't change1378 inst->_num_reg_rc = 0; //unnecessary 1379 inst->_write_rd = 0; 1380 inst->_num_reg_rd = 0; //unnecessary 1381 inst->_write_re = 0; 1382 inst->_num_reg_re = 0; //unnecessary 1383 inst->_exception_use = EXCEPTION_USE_NONE; 1384 inst->_exception = EXCEPTION_DECOD_NONE; 1385 // inst->_branch_condition = ; 1386 // inst->_branch_stack_write = ; 1387 // inst->_branch_direction = ; 1388 // inst->_address_next = ; // already define : PC+4 // don't change 1389 1389 inst->_no_execute = 0; 1390 1390 inst->_event_type = EVENT_TYPE_SPR_ACCESS; … … 1398 1398 inst->_operation = instruction_information(INSTRUCTION_L_MUL)._operation; //OPERATION_MUL_L_MUL; 1399 1399 inst->_has_immediat = 0; 1400 // inst->_immediat = ; 1401 inst->_read_ra = 1; 1402 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1403 inst->_read_rb = 1; 1404 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 1405 inst->_read_rc = 0; 1406 // inst->_num_reg_rc = ; 1400 inst->_immediat = 0; // unnecessary 1401 inst->_read_ra = 1; 1402 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1403 inst->_read_rb = 1; 1404 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 1405 inst->_read_rc = 0; 1406 inst->_num_reg_rc = 0; //unnecessary 1407 1407 inst->_write_rd = 1; 1408 1408 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); … … 1414 1414 // inst->_branch_stack_write = ; 1415 1415 // inst->_branch_direction = ; 1416 // inst->_address_next = ; 1416 // inst->_address_next = ; // already define : PC+4 1417 1417 inst->_no_execute = 0; 1418 1418 inst->_event_type = EVENT_TYPE_NONE; … … 1430 1430 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1431 1431 inst->_read_rb = 0; 1432 // inst->_num_reg_rb = ; 1433 inst->_read_rc = 0; 1434 // inst->_num_reg_rc = ; 1432 inst->_num_reg_rb = 0; //unnecessary 1433 inst->_read_rc = 0; 1434 inst->_num_reg_rc = 0; //unnecessary 1435 1435 inst->_write_rd = 1; 1436 1436 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); … … 1442 1442 // inst->_branch_stack_write = ; 1443 1443 // inst->_branch_direction = ; 1444 // inst->_address_next = ; 1444 // inst->_address_next = ; // already define : PC+4 1445 1445 inst->_no_execute = 0; 1446 1446 inst->_event_type = EVENT_TYPE_NONE; … … 1454 1454 inst->_operation = instruction_information(INSTRUCTION_L_MULU)._operation; //OPERATION_MUL_L_MULU; 1455 1455 inst->_has_immediat = 0; 1456 // inst->_immediat = ; 1457 inst->_read_ra = 1; 1458 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1459 inst->_read_rb = 1; 1460 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 1461 inst->_read_rc = 0; 1462 // inst->_num_reg_rc = ; 1456 inst->_immediat = 0; // unnecessary 1457 inst->_read_ra = 1; 1458 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1459 inst->_read_rb = 1; 1460 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 1461 inst->_read_rc = 0; 1462 inst->_num_reg_rc = 0; //unnecessary 1463 1463 inst->_write_rd = 1; 1464 1464 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); … … 1470 1470 // inst->_branch_stack_write = ; 1471 1471 // inst->_branch_direction = ; 1472 // inst->_address_next = ; 1472 // inst->_address_next = ; // already define : PC+4 1473 1473 inst->_no_execute = 0; 1474 1474 inst->_event_type = EVENT_TYPE_NONE; … … 1484 1484 // inst->_immediat = EXTENDZ(inst->_instruction,16); 1485 1485 inst->_has_immediat = 0; 1486 // inst->_immediat = ; 1486 inst->_immediat = 0; // unnecessary 1487 1487 inst->_read_ra = 0; 1488 // inst->_num_reg_ra = ; 1489 inst->_read_rb = 0; 1490 // inst->_num_reg_rb = ; 1491 inst->_read_rc = 0; 1492 // inst->_num_reg_rc = ; 1493 inst->_write_rd = 0; 1494 // inst->_num_reg_rd = ; 1495 inst->_write_re = 0; 1496 // inst->_num_reg_re = ; 1497 inst->_exception_use = EXCEPTION_USE_NONE; 1498 inst->_exception = EXCEPTION_DECOD_NONE; 1499 // inst->_branch_condition = ; 1500 // inst->_branch_stack_write = ; 1501 // inst->_branch_direction = ; 1502 // inst->_address_next = ; 1488 inst->_num_reg_ra = 0; //unnecessary 1489 inst->_read_rb = 0; 1490 inst->_num_reg_rb = 0; //unnecessary 1491 inst->_read_rc = 0; 1492 inst->_num_reg_rc = 0; //unnecessary 1493 inst->_write_rd = 0; 1494 inst->_num_reg_rd = 0; //unnecessary 1495 inst->_write_re = 0; 1496 inst->_num_reg_re = 0; //unnecessary 1497 inst->_exception_use = EXCEPTION_USE_NONE; 1498 inst->_exception = EXCEPTION_DECOD_NONE; 1499 // inst->_branch_condition = ; 1500 // inst->_branch_stack_write = ; 1501 // inst->_branch_direction = ; 1502 // inst->_address_next = ; // already define : PC+4 1503 1503 inst->_no_execute = 1; 1504 1504 inst->_event_type = EVENT_TYPE_NONE; … … 1512 1512 inst->_operation = instruction_information(INSTRUCTION_L_OR)._operation; //OPERATION_ALU_L_OR; 1513 1513 inst->_has_immediat = 0; 1514 // inst->_immediat = ; 1515 inst->_read_ra = 1; 1516 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1517 inst->_read_rb = 1; 1518 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 1519 inst->_read_rc = 0; 1520 // inst->_num_reg_rc = ; 1521 inst->_write_rd = 1; 1522 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 1523 inst->_write_re = 0; 1524 // inst->_num_reg_re = ; 1525 inst->_exception_use = EXCEPTION_USE_NONE; 1526 inst->_exception = EXCEPTION_DECOD_NONE; 1527 // inst->_branch_condition = ; 1528 // inst->_branch_stack_write = ; 1529 // inst->_branch_direction = ; 1530 // inst->_address_next = ; 1514 inst->_immediat = 0; // unnecessary 1515 inst->_read_ra = 1; 1516 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1517 inst->_read_rb = 1; 1518 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 1519 inst->_read_rc = 0; 1520 inst->_num_reg_rc = 0; //unnecessary 1521 inst->_write_rd = 1; 1522 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 1523 inst->_write_re = 0; 1524 inst->_num_reg_re = 0; //unnecessary 1525 inst->_exception_use = EXCEPTION_USE_NONE; 1526 inst->_exception = EXCEPTION_DECOD_NONE; 1527 // inst->_branch_condition = ; 1528 // inst->_branch_stack_write = ; 1529 // inst->_branch_direction = ; 1530 // inst->_address_next = ; // already define : PC+4 1531 1531 inst->_no_execute = 0; 1532 1532 inst->_event_type = EVENT_TYPE_NONE; … … 1544 1544 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1545 1545 inst->_read_rb = 0; 1546 // inst->_num_reg_rb = ; 1547 inst->_read_rc = 0; 1548 // inst->_num_reg_rc = ; 1549 inst->_write_rd = 1; 1550 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 1551 inst->_write_re = 0; 1552 // inst->_num_reg_re = ; 1553 inst->_exception_use = EXCEPTION_USE_NONE; 1554 inst->_exception = EXCEPTION_DECOD_NONE; 1555 // inst->_branch_condition = ; 1556 // inst->_branch_stack_write = ; 1557 // inst->_branch_direction = ; 1558 // inst->_address_next = ; 1546 inst->_num_reg_rb = 0; //unnecessary 1547 inst->_read_rc = 0; 1548 inst->_num_reg_rc = 0; //unnecessary 1549 inst->_write_rd = 1; 1550 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 1551 inst->_write_re = 0; 1552 inst->_num_reg_re = 0; //unnecessary 1553 inst->_exception_use = EXCEPTION_USE_NONE; 1554 inst->_exception = EXCEPTION_DECOD_NONE; 1555 // inst->_branch_condition = ; 1556 // inst->_branch_stack_write = ; 1557 // inst->_branch_direction = ; 1558 // inst->_address_next = ; // already define : PC+4 1559 1559 inst->_no_execute = 0; 1560 1560 inst->_event_type = EVENT_TYPE_NONE; … … 1574 1574 inst->_operation = instruction_information(INSTRUCTION_L_PSYNC)._operation; //OPERATION_SPECIAL_L_PSYNC; 1575 1575 inst->_has_immediat = 0; 1576 // inst->_immediat = ; 1576 inst->_immediat = 0; // unnecessary 1577 1577 inst->_read_ra = 0; 1578 // inst->_num_reg_ra = ; 1579 inst->_read_rb = 0; 1580 // inst->_num_reg_rb = ; 1581 inst->_read_rc = 0; 1582 // inst->_num_reg_rc = ; 1583 inst->_write_rd = 0; 1584 // inst->_num_reg_rd = ; 1585 inst->_write_re = 0; 1586 // inst->_num_reg_re = ; 1587 inst->_exception_use = EXCEPTION_USE_NONE; 1588 inst->_exception = EXCEPTION_DECOD_NONE; 1589 // inst->_branch_condition = ; 1590 // inst->_branch_stack_write = ; 1591 // inst->_branch_direction = ; 1592 // inst->_address_next = ; // don't change1578 inst->_num_reg_ra = 0; //unnecessary 1579 inst->_read_rb = 0; 1580 inst->_num_reg_rb = 0; //unnecessary 1581 inst->_read_rc = 0; 1582 inst->_num_reg_rc = 0; //unnecessary 1583 inst->_write_rd = 0; 1584 inst->_num_reg_rd = 0; //unnecessary 1585 inst->_write_re = 0; 1586 inst->_num_reg_re = 0; //unnecessary 1587 inst->_exception_use = EXCEPTION_USE_NONE; 1588 inst->_exception = EXCEPTION_DECOD_NONE; 1589 // inst->_branch_condition = ; 1590 // inst->_branch_stack_write = ; 1591 // inst->_branch_direction = ; 1592 // inst->_address_next = ; // already define : PC+4 // don't change 1593 1593 inst->_no_execute = 0; 1594 1594 inst->_event_type = EVENT_TYPE_PSYNC; … … 1603 1603 inst->_operation = instruction_information(INSTRUCTION_L_RFE)._operation; //OPERATION_SPECIAL_L_RFE; 1604 1604 inst->_has_immediat = 0; 1605 // inst->_immediat = ; 1605 inst->_immediat = 0; // unnecessary 1606 1606 inst->_read_ra = 0; 1607 // inst->_num_reg_ra = ; 1608 inst->_read_rb = 0; 1609 // inst->_num_reg_rb = ; 1610 inst->_read_rc = 0; 1611 // inst->_num_reg_rc = ; 1612 inst->_write_rd = 0; 1613 // inst->_num_reg_rd = ; 1614 inst->_write_re = 0; 1615 // inst->_num_reg_re = ; 1616 inst->_exception_use = EXCEPTION_USE_NONE; 1617 inst->_exception = EXCEPTION_DECOD_NONE; 1618 // inst->_branch_condition = ; 1619 // inst->_branch_stack_write = ; 1620 // inst->_branch_direction = ; 1621 // inst->_address_next = ; // don't change1607 inst->_num_reg_ra = 0; //unnecessary 1608 inst->_read_rb = 0; 1609 inst->_num_reg_rb = 0; //unnecessary 1610 inst->_read_rc = 0; 1611 inst->_num_reg_rc = 0; //unnecessary 1612 inst->_write_rd = 0; 1613 inst->_num_reg_rd = 0; //unnecessary 1614 inst->_write_re = 0; 1615 inst->_num_reg_re = 0; //unnecessary 1616 inst->_exception_use = EXCEPTION_USE_NONE; 1617 inst->_exception = EXCEPTION_DECOD_NONE; 1618 // inst->_branch_condition = ; 1619 // inst->_branch_stack_write = ; 1620 // inst->_branch_direction = ; 1621 // inst->_address_next = ; // already define : PC+4 // don't change 1622 1622 inst->_no_execute = 1; 1623 1623 inst->_event_type = EVENT_TYPE_NONE; // can't anticip this instruction : must read EPCR in rename stage … … 1631 1631 inst->_operation = instruction_information(INSTRUCTION_L_ROR)._operation; //OPERATION_SHIFT_L_ROR; 1632 1632 inst->_has_immediat = 0; 1633 // inst->_immediat = ; 1634 inst->_read_ra = 1; 1635 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1636 inst->_read_rb = 1; 1637 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 1638 inst->_read_rc = 0; 1639 // inst->_num_reg_rc = ; 1640 inst->_write_rd = 1; 1641 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 1642 inst->_write_re = 0; 1643 // inst->_num_reg_re = ; 1644 inst->_exception_use = EXCEPTION_USE_NONE; 1645 inst->_exception = EXCEPTION_DECOD_NONE; 1646 // inst->_branch_condition = ; 1647 // inst->_branch_stack_write = ; 1648 // inst->_branch_direction = ; 1649 // inst->_address_next = ; 1633 inst->_immediat = 0; // unnecessary 1634 inst->_read_ra = 1; 1635 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1636 inst->_read_rb = 1; 1637 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 1638 inst->_read_rc = 0; 1639 inst->_num_reg_rc = 0; //unnecessary 1640 inst->_write_rd = 1; 1641 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 1642 inst->_write_re = 0; 1643 inst->_num_reg_re = 0; //unnecessary 1644 inst->_exception_use = EXCEPTION_USE_NONE; 1645 inst->_exception = EXCEPTION_DECOD_NONE; 1646 // inst->_branch_condition = ; 1647 // inst->_branch_stack_write = ; 1648 // inst->_branch_direction = ; 1649 // inst->_address_next = ; // already define : PC+4 1650 1650 inst->_no_execute = 0; 1651 1651 inst->_event_type = EVENT_TYPE_NONE; … … 1663 1663 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1664 1664 inst->_read_rb = 0; 1665 // inst->_num_reg_rb = ; 1666 inst->_read_rc = 0; 1667 // inst->_num_reg_rc = ; 1668 inst->_write_rd = 1; 1669 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 1670 inst->_write_re = 0; 1671 // inst->_num_reg_re = ; 1672 inst->_exception_use = EXCEPTION_USE_NONE; 1673 inst->_exception = EXCEPTION_DECOD_NONE; 1674 // inst->_branch_condition = ; 1675 // inst->_branch_stack_write = ; 1676 // inst->_branch_direction = ; 1677 // inst->_address_next = ; 1665 inst->_num_reg_rb = 0; //unnecessary 1666 inst->_read_rc = 0; 1667 inst->_num_reg_rc = 0; //unnecessary 1668 inst->_write_rd = 1; 1669 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 1670 inst->_write_re = 0; 1671 inst->_num_reg_re = 0; //unnecessary 1672 inst->_exception_use = EXCEPTION_USE_NONE; 1673 inst->_exception = EXCEPTION_DECOD_NONE; 1674 // inst->_branch_condition = ; 1675 // inst->_branch_stack_write = ; 1676 // inst->_branch_direction = ; 1677 // inst->_address_next = ; // already define : PC+4 1678 1678 inst->_no_execute = 0; 1679 1679 inst->_event_type = EVENT_TYPE_NONE; … … 1694 1694 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 1695 1695 inst->_read_rc = 0; 1696 // inst->_num_reg_rc = ; 1697 inst->_write_rd = 0; 1698 // inst->_num_reg_rd = ; 1699 inst->_write_re = 0; 1700 // inst->_num_reg_re = ; 1696 inst->_num_reg_rc = 0; //unnecessary 1697 inst->_write_rd = 0; 1698 inst->_num_reg_rd = 0; //unnecessary 1699 inst->_write_re = 0; 1700 inst->_num_reg_re = 0; //unnecessary 1701 1701 inst->_exception_use = EXCEPTION_USE_MEMORY_WITHOUT_ALIGNMENT; 1702 1702 inst->_exception = EXCEPTION_DECOD_NONE; … … 1704 1704 // inst->_branch_stack_write = ; 1705 1705 // inst->_branch_direction = ; 1706 // inst->_address_next = ; 1706 // inst->_address_next = ; // already define : PC+4 1707 1707 inst->_no_execute = 0; 1708 1708 inst->_event_type = EVENT_TYPE_NONE; … … 1723 1723 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 1724 1724 inst->_read_rc = 0; 1725 // inst->_num_reg_rc = ; 1726 inst->_write_rd = 0; 1727 // inst->_num_reg_rd = ; 1728 inst->_write_re = 0; 1729 // inst->_num_reg_re = ; 1725 inst->_num_reg_rc = 0; //unnecessary 1726 inst->_write_rd = 0; 1727 inst->_num_reg_rd = 0; //unnecessary 1728 inst->_write_re = 0; 1729 inst->_num_reg_re = 0; //unnecessary 1730 1730 inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT; 1731 1731 inst->_exception = EXCEPTION_DECOD_NONE; … … 1733 1733 // inst->_branch_stack_write = ; 1734 1734 // inst->_branch_direction = ; 1735 // inst->_address_next = ; 1735 // inst->_address_next = ; // already define : PC+4 1736 1736 inst->_no_execute = 0; 1737 1737 inst->_event_type = EVENT_TYPE_NONE; … … 1745 1745 inst->_operation = instruction_information(INSTRUCTION_L_SFEQ)._operation; //OPERATION_TEST_L_SFEQ; 1746 1746 inst->_has_immediat = 0; 1747 // inst->_immediat = ; 1748 inst->_read_ra = 1; 1749 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1750 inst->_read_rb = 1; 1751 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 1752 inst->_read_rc = 0; 1753 // inst->_num_reg_rc = ; 1754 inst->_write_rd = 0; 1755 // inst->_num_reg_rd = ; 1747 inst->_immediat = 0; // unnecessary 1748 inst->_read_ra = 1; 1749 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1750 inst->_read_rb = 1; 1751 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 1752 inst->_read_rc = 0; 1753 inst->_num_reg_rc = 0; //unnecessary 1754 inst->_write_rd = 0; 1755 inst->_num_reg_rd = 0; //unnecessary 1756 1756 inst->_write_re = 1; 1757 1757 inst->_num_reg_re = SPR_LOGIC_SR_F; … … 1761 1761 // inst->_branch_stack_write = ; 1762 1762 // inst->_branch_direction = ; 1763 // inst->_address_next = ; 1763 // inst->_address_next = ; // already define : PC+4 1764 1764 inst->_no_execute = 0; 1765 1765 inst->_event_type = EVENT_TYPE_NONE; … … 1777 1777 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1778 1778 inst->_read_rb = 0; 1779 // inst->_num_reg_rb = ; 1780 inst->_read_rc = 0; 1781 // inst->_num_reg_rc = ; 1782 inst->_write_rd = 0; 1783 // inst->_num_reg_rd = ; 1779 inst->_num_reg_rb = 0; //unnecessary 1780 inst->_read_rc = 0; 1781 inst->_num_reg_rc = 0; //unnecessary 1782 inst->_write_rd = 0; 1783 inst->_num_reg_rd = 0; //unnecessary 1784 1784 inst->_write_re = 1; 1785 1785 inst->_num_reg_re = SPR_LOGIC_SR_F; … … 1789 1789 // inst->_branch_stack_write = ; 1790 1790 // inst->_branch_direction = ; 1791 // inst->_address_next = ; 1791 // inst->_address_next = ; // already define : PC+4 1792 1792 inst->_no_execute = 0; 1793 1793 inst->_event_type = EVENT_TYPE_NONE; … … 1801 1801 inst->_operation = instruction_information(INSTRUCTION_L_SFGES)._operation; //OPERATION_TEST_L_SFGES; 1802 1802 inst->_has_immediat = 0; 1803 // inst->_immediat = ; 1804 inst->_read_ra = 1; 1805 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1806 inst->_read_rb = 1; 1807 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 1808 inst->_read_rc = 0; 1809 // inst->_num_reg_rc = ; 1810 inst->_write_rd = 0; 1811 // inst->_num_reg_rd = ; 1803 inst->_immediat = 0; // unnecessary 1804 inst->_read_ra = 1; 1805 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1806 inst->_read_rb = 1; 1807 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 1808 inst->_read_rc = 0; 1809 inst->_num_reg_rc = 0; //unnecessary 1810 inst->_write_rd = 0; 1811 inst->_num_reg_rd = 0; //unnecessary 1812 1812 inst->_write_re = 1; 1813 1813 inst->_num_reg_re = SPR_LOGIC_SR_F; … … 1817 1817 // inst->_branch_stack_write = ; 1818 1818 // inst->_branch_direction = ; 1819 // inst->_address_next = ; 1819 // inst->_address_next = ; // already define : PC+4 1820 1820 inst->_no_execute = 0; 1821 1821 inst->_event_type = EVENT_TYPE_NONE; … … 1833 1833 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1834 1834 inst->_read_rb = 0; 1835 // inst->_num_reg_rb = ; 1836 inst->_read_rc = 0; 1837 // inst->_num_reg_rc = ; 1838 inst->_write_rd = 0; 1839 // inst->_num_reg_rd = ; 1835 inst->_num_reg_rb = 0; //unnecessary 1836 inst->_read_rc = 0; 1837 inst->_num_reg_rc = 0; //unnecessary 1838 inst->_write_rd = 0; 1839 inst->_num_reg_rd = 0; //unnecessary 1840 1840 inst->_write_re = 1; 1841 1841 inst->_num_reg_re = SPR_LOGIC_SR_F; … … 1845 1845 // inst->_branch_stack_write = ; 1846 1846 // inst->_branch_direction = ; 1847 // inst->_address_next = ; 1847 // inst->_address_next = ; // already define : PC+4 1848 1848 inst->_no_execute = 0; 1849 1849 inst->_event_type = EVENT_TYPE_NONE; … … 1857 1857 inst->_operation = instruction_information(INSTRUCTION_L_SFGEU)._operation; //OPERATION_TEST_L_SFGEU; 1858 1858 inst->_has_immediat = 0; 1859 // inst->_immediat = ; 1860 inst->_read_ra = 1; 1861 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1862 inst->_read_rb = 1; 1863 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 1864 inst->_read_rc = 0; 1865 // inst->_num_reg_rc = ; 1866 inst->_write_rd = 0; 1867 // inst->_num_reg_rd = ; 1859 inst->_immediat = 0; // unnecessary 1860 inst->_read_ra = 1; 1861 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1862 inst->_read_rb = 1; 1863 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 1864 inst->_read_rc = 0; 1865 inst->_num_reg_rc = 0; //unnecessary 1866 inst->_write_rd = 0; 1867 inst->_num_reg_rd = 0; //unnecessary 1868 1868 inst->_write_re = 1; 1869 1869 inst->_num_reg_re = SPR_LOGIC_SR_F; … … 1873 1873 // inst->_branch_stack_write = ; 1874 1874 // inst->_branch_direction = ; 1875 // inst->_address_next = ; 1875 // inst->_address_next = ; // already define : PC+4 1876 1876 inst->_no_execute = 0; 1877 1877 inst->_event_type = EVENT_TYPE_NONE; … … 1889 1889 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1890 1890 inst->_read_rb = 0; 1891 // inst->_num_reg_rb = ; 1892 inst->_read_rc = 0; 1893 // inst->_num_reg_rc = ; 1894 inst->_write_rd = 0; 1895 // inst->_num_reg_rd = ; 1891 inst->_num_reg_rb = 0; //unnecessary 1892 inst->_read_rc = 0; 1893 inst->_num_reg_rc = 0; //unnecessary 1894 inst->_write_rd = 0; 1895 inst->_num_reg_rd = 0; //unnecessary 1896 1896 inst->_write_re = 1; 1897 1897 inst->_num_reg_re = SPR_LOGIC_SR_F; … … 1901 1901 // inst->_branch_stack_write = ; 1902 1902 // inst->_branch_direction = ; 1903 // inst->_address_next = ; 1903 // inst->_address_next = ; // already define : PC+4 1904 1904 inst->_no_execute = 0; 1905 1905 inst->_event_type = EVENT_TYPE_NONE; … … 1913 1913 inst->_operation = instruction_information(INSTRUCTION_L_SFGTS)._operation; //OPERATION_TEST_L_SFGTS; 1914 1914 inst->_has_immediat = 0; 1915 // inst->_immediat = ; 1916 inst->_read_ra = 1; 1917 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1918 inst->_read_rb = 1; 1919 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 1920 inst->_read_rc = 0; 1921 // inst->_num_reg_rc = ; 1922 inst->_write_rd = 0; 1923 // inst->_num_reg_rd = ; 1915 inst->_immediat = 0; // unnecessary 1916 inst->_read_ra = 1; 1917 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1918 inst->_read_rb = 1; 1919 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 1920 inst->_read_rc = 0; 1921 inst->_num_reg_rc = 0; //unnecessary 1922 inst->_write_rd = 0; 1923 inst->_num_reg_rd = 0; //unnecessary 1924 1924 inst->_write_re = 1; 1925 1925 inst->_num_reg_re = SPR_LOGIC_SR_F; … … 1929 1929 // inst->_branch_stack_write = ; 1930 1930 // inst->_branch_direction = ; 1931 // inst->_address_next = ; 1931 // inst->_address_next = ; // already define : PC+4 1932 1932 inst->_no_execute = 0; 1933 1933 inst->_event_type = EVENT_TYPE_NONE; … … 1945 1945 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1946 1946 inst->_read_rb = 0; 1947 // inst->_num_reg_rb = ; 1948 inst->_read_rc = 0; 1949 // inst->_num_reg_rc = ; 1950 inst->_write_rd = 0; 1951 // inst->_num_reg_rd = ; 1947 inst->_num_reg_rb = 0; //unnecessary 1948 inst->_read_rc = 0; 1949 inst->_num_reg_rc = 0; //unnecessary 1950 inst->_write_rd = 0; 1951 inst->_num_reg_rd = 0; //unnecessary 1952 1952 inst->_write_re = 1; 1953 1953 inst->_num_reg_re = SPR_LOGIC_SR_F; … … 1957 1957 // inst->_branch_stack_write = ; 1958 1958 // inst->_branch_direction = ; 1959 // inst->_address_next = ; 1959 // inst->_address_next = ; // already define : PC+4 1960 1960 inst->_no_execute = 0; 1961 1961 inst->_event_type = EVENT_TYPE_NONE; … … 1969 1969 inst->_operation = instruction_information(INSTRUCTION_L_SFGTU)._operation; //OPERATION_TEST_L_SFGTU; 1970 1970 inst->_has_immediat = 0; 1971 // inst->_immediat = ; 1972 inst->_read_ra = 1; 1973 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1974 inst->_read_rb = 1; 1975 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 1976 inst->_read_rc = 0; 1977 // inst->_num_reg_rc = ; 1978 inst->_write_rd = 0; 1979 // inst->_num_reg_rd = ; 1971 inst->_immediat = 0; // unnecessary 1972 inst->_read_ra = 1; 1973 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1974 inst->_read_rb = 1; 1975 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 1976 inst->_read_rc = 0; 1977 inst->_num_reg_rc = 0; //unnecessary 1978 inst->_write_rd = 0; 1979 inst->_num_reg_rd = 0; //unnecessary 1980 1980 inst->_write_re = 1; 1981 1981 inst->_num_reg_re = SPR_LOGIC_SR_F; … … 1985 1985 // inst->_branch_stack_write = ; 1986 1986 // inst->_branch_direction = ; 1987 // inst->_address_next = ; 1987 // inst->_address_next = ; // already define : PC+4 1988 1988 inst->_no_execute = 0; 1989 1989 inst->_event_type = EVENT_TYPE_NONE; … … 2001 2001 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2002 2002 inst->_read_rb = 0; 2003 // inst->_num_reg_rb = ; 2004 inst->_read_rc = 0; 2005 // inst->_num_reg_rc = ; 2006 inst->_write_rd = 0; 2007 // inst->_num_reg_rd = ; 2003 inst->_num_reg_rb = 0; //unnecessary 2004 inst->_read_rc = 0; 2005 inst->_num_reg_rc = 0; //unnecessary 2006 inst->_write_rd = 0; 2007 inst->_num_reg_rd = 0; //unnecessary 2008 2008 inst->_write_re = 1; 2009 2009 inst->_num_reg_re = SPR_LOGIC_SR_F; … … 2013 2013 // inst->_branch_stack_write = ; 2014 2014 // inst->_branch_direction = ; 2015 // inst->_address_next = ; 2015 // inst->_address_next = ; // already define : PC+4 2016 2016 inst->_no_execute = 0; 2017 2017 inst->_event_type = EVENT_TYPE_NONE; … … 2025 2025 inst->_operation = instruction_information(INSTRUCTION_L_SFLES)._operation; //OPERATION_TEST_L_SFLES; 2026 2026 inst->_has_immediat = 0; 2027 // inst->_immediat = ; 2028 inst->_read_ra = 1; 2029 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2030 inst->_read_rb = 1; 2031 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 2032 inst->_read_rc = 0; 2033 // inst->_num_reg_rc = ; 2034 inst->_write_rd = 0; 2035 // inst->_num_reg_rd = ; 2027 inst->_immediat = 0; // unnecessary 2028 inst->_read_ra = 1; 2029 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2030 inst->_read_rb = 1; 2031 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 2032 inst->_read_rc = 0; 2033 inst->_num_reg_rc = 0; //unnecessary 2034 inst->_write_rd = 0; 2035 inst->_num_reg_rd = 0; //unnecessary 2036 2036 inst->_write_re = 1; 2037 2037 inst->_num_reg_re = SPR_LOGIC_SR_F; … … 2041 2041 // inst->_branch_stack_write = ; 2042 2042 // inst->_branch_direction = ; 2043 // inst->_address_next = ; 2043 // inst->_address_next = ; // already define : PC+4 2044 2044 inst->_no_execute = 0; 2045 2045 inst->_event_type = EVENT_TYPE_NONE; … … 2057 2057 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2058 2058 inst->_read_rb = 0; 2059 // inst->_num_reg_rb = ; 2060 inst->_read_rc = 0; 2061 // inst->_num_reg_rc = ; 2062 inst->_write_rd = 0; 2063 // inst->_num_reg_rd = ; 2059 inst->_num_reg_rb = 0; //unnecessary 2060 inst->_read_rc = 0; 2061 inst->_num_reg_rc = 0; //unnecessary 2062 inst->_write_rd = 0; 2063 inst->_num_reg_rd = 0; //unnecessary 2064 2064 inst->_write_re = 1; 2065 2065 inst->_num_reg_re = SPR_LOGIC_SR_F; … … 2069 2069 // inst->_branch_stack_write = ; 2070 2070 // inst->_branch_direction = ; 2071 // inst->_address_next = ; 2071 // inst->_address_next = ; // already define : PC+4 2072 2072 inst->_no_execute = 0; 2073 2073 inst->_event_type = EVENT_TYPE_NONE; … … 2081 2081 inst->_operation = instruction_information(INSTRUCTION_L_SFLEU)._operation; //OPERATION_TEST_L_SFLEU; 2082 2082 inst->_has_immediat = 0; 2083 // inst->_immediat = ; 2084 inst->_read_ra = 1; 2085 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2086 inst->_read_rb = 1; 2087 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 2088 inst->_read_rc = 0; 2089 // inst->_num_reg_rc = ; 2090 inst->_write_rd = 0; 2091 // inst->_num_reg_rd = ; 2083 inst->_immediat = 0; // unnecessary 2084 inst->_read_ra = 1; 2085 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2086 inst->_read_rb = 1; 2087 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 2088 inst->_read_rc = 0; 2089 inst->_num_reg_rc = 0; //unnecessary 2090 inst->_write_rd = 0; 2091 inst->_num_reg_rd = 0; //unnecessary 2092 2092 inst->_write_re = 1; 2093 2093 inst->_num_reg_re = SPR_LOGIC_SR_F; … … 2097 2097 // inst->_branch_stack_write = ; 2098 2098 // inst->_branch_direction = ; 2099 // inst->_address_next = ; 2099 // inst->_address_next = ; // already define : PC+4 2100 2100 inst->_no_execute = 0; 2101 2101 inst->_event_type = EVENT_TYPE_NONE; … … 2113 2113 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2114 2114 inst->_read_rb = 0; 2115 // inst->_num_reg_rb = ; 2116 inst->_read_rc = 0; 2117 // inst->_num_reg_rc = ; 2118 inst->_write_rd = 0; 2119 // inst->_num_reg_rd = ; 2115 inst->_num_reg_rb = 0; //unnecessary 2116 inst->_read_rc = 0; 2117 inst->_num_reg_rc = 0; //unnecessary 2118 inst->_write_rd = 0; 2119 inst->_num_reg_rd = 0; //unnecessary 2120 2120 inst->_write_re = 1; 2121 2121 inst->_num_reg_re = SPR_LOGIC_SR_F; … … 2125 2125 // inst->_branch_stack_write = ; 2126 2126 // inst->_branch_direction = ; 2127 // inst->_address_next = ; 2127 // inst->_address_next = ; // already define : PC+4 2128 2128 inst->_no_execute = 0; 2129 2129 inst->_event_type = EVENT_TYPE_NONE; … … 2137 2137 inst->_operation = instruction_information(INSTRUCTION_L_SFLTS)._operation; //OPERATION_TEST_L_SFLTS; 2138 2138 inst->_has_immediat = 0; 2139 // inst->_immediat = ; 2140 inst->_read_ra = 1; 2141 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2142 inst->_read_rb = 1; 2143 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 2144 inst->_read_rc = 0; 2145 // inst->_num_reg_rc = ; 2146 inst->_write_rd = 0; 2147 // inst->_num_reg_rd = ; 2139 inst->_immediat = 0; // unnecessary 2140 inst->_read_ra = 1; 2141 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2142 inst->_read_rb = 1; 2143 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 2144 inst->_read_rc = 0; 2145 inst->_num_reg_rc = 0; //unnecessary 2146 inst->_write_rd = 0; 2147 inst->_num_reg_rd = 0; //unnecessary 2148 2148 inst->_write_re = 1; 2149 2149 inst->_num_reg_re = SPR_LOGIC_SR_F; … … 2153 2153 // inst->_branch_stack_write = ; 2154 2154 // inst->_branch_direction = ; 2155 // inst->_address_next = ; 2155 // inst->_address_next = ; // already define : PC+4 2156 2156 inst->_no_execute = 0; 2157 2157 inst->_event_type = EVENT_TYPE_NONE; … … 2169 2169 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2170 2170 inst->_read_rb = 0; 2171 // inst->_num_reg_rb = ; 2172 inst->_read_rc = 0; 2173 // inst->_num_reg_rc = ; 2174 inst->_write_rd = 0; 2175 // inst->_num_reg_rd = ; 2171 inst->_num_reg_rb = 0; //unnecessary 2172 inst->_read_rc = 0; 2173 inst->_num_reg_rc = 0; //unnecessary 2174 inst->_write_rd = 0; 2175 inst->_num_reg_rd = 0; //unnecessary 2176 2176 inst->_write_re = 1; 2177 2177 inst->_num_reg_re = SPR_LOGIC_SR_F; … … 2181 2181 // inst->_branch_stack_write = ; 2182 2182 // inst->_branch_direction = ; 2183 // inst->_address_next = ; 2183 // inst->_address_next = ; // already define : PC+4 2184 2184 inst->_no_execute = 0; 2185 2185 inst->_event_type = EVENT_TYPE_NONE; … … 2193 2193 inst->_operation = instruction_information(INSTRUCTION_L_SFLTU)._operation; //OPERATION_TEST_L_SFLTU; 2194 2194 inst->_has_immediat = 0; 2195 // inst->_immediat = ; 2196 inst->_read_ra = 1; 2197 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2198 inst->_read_rb = 1; 2199 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 2200 inst->_read_rc = 0; 2201 // inst->_num_reg_rc = ; 2202 inst->_write_rd = 0; 2203 // inst->_num_reg_rd = ; 2195 inst->_immediat = 0; // unnecessary 2196 inst->_read_ra = 1; 2197 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2198 inst->_read_rb = 1; 2199 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 2200 inst->_read_rc = 0; 2201 inst->_num_reg_rc = 0; //unnecessary 2202 inst->_write_rd = 0; 2203 inst->_num_reg_rd = 0; //unnecessary 2204 2204 inst->_write_re = 1; 2205 2205 inst->_num_reg_re = SPR_LOGIC_SR_F; … … 2209 2209 // inst->_branch_stack_write = ; 2210 2210 // inst->_branch_direction = ; 2211 // inst->_address_next = ; 2211 // inst->_address_next = ; // already define : PC+4 2212 2212 inst->_no_execute = 0; 2213 2213 inst->_event_type = EVENT_TYPE_NONE; … … 2225 2225 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2226 2226 inst->_read_rb = 0; 2227 // inst->_num_reg_rb = ; 2228 inst->_read_rc = 0; 2229 // inst->_num_reg_rc = ; 2230 inst->_write_rd = 0; 2231 // inst->_num_reg_rd = ; 2227 inst->_num_reg_rb = 0; //unnecessary 2228 inst->_read_rc = 0; 2229 inst->_num_reg_rc = 0; //unnecessary 2230 inst->_write_rd = 0; 2231 inst->_num_reg_rd = 0; //unnecessary 2232 2232 inst->_write_re = 1; 2233 2233 inst->_num_reg_re = SPR_LOGIC_SR_F; … … 2237 2237 // inst->_branch_stack_write = ; 2238 2238 // inst->_branch_direction = ; 2239 // inst->_address_next = ; 2239 // inst->_address_next = ; // already define : PC+4 2240 2240 inst->_no_execute = 0; 2241 2241 inst->_event_type = EVENT_TYPE_NONE; … … 2249 2249 inst->_operation = instruction_information(INSTRUCTION_L_SFNE)._operation; //OPERATION_TEST_L_SFNE; 2250 2250 inst->_has_immediat = 0; 2251 // inst->_immediat = ; 2252 inst->_read_ra = 1; 2253 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2254 inst->_read_rb = 1; 2255 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 2256 inst->_read_rc = 0; 2257 // inst->_num_reg_rc = ; 2258 inst->_write_rd = 0; 2259 // inst->_num_reg_rd = ; 2251 inst->_immediat = 0; // unnecessary 2252 inst->_read_ra = 1; 2253 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2254 inst->_read_rb = 1; 2255 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 2256 inst->_read_rc = 0; 2257 inst->_num_reg_rc = 0; //unnecessary 2258 inst->_write_rd = 0; 2259 inst->_num_reg_rd = 0; //unnecessary 2260 2260 inst->_write_re = 1; 2261 2261 inst->_num_reg_re = SPR_LOGIC_SR_F; … … 2265 2265 // inst->_branch_stack_write = ; 2266 2266 // inst->_branch_direction = ; 2267 // inst->_address_next = ; 2267 // inst->_address_next = ; // already define : PC+4 2268 2268 inst->_no_execute = 0; 2269 2269 inst->_event_type = EVENT_TYPE_NONE; … … 2281 2281 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2282 2282 inst->_read_rb = 0; 2283 // inst->_num_reg_rb = ; 2284 inst->_read_rc = 0; 2285 // inst->_num_reg_rc = ; 2286 inst->_write_rd = 0; 2287 // inst->_num_reg_rd = ; 2283 inst->_num_reg_rb = 0; //unnecessary 2284 inst->_read_rc = 0; 2285 inst->_num_reg_rc = 0; //unnecessary 2286 inst->_write_rd = 0; 2287 inst->_num_reg_rd = 0; //unnecessary 2288 2288 inst->_write_re = 1; 2289 2289 inst->_num_reg_re = SPR_LOGIC_SR_F; … … 2293 2293 // inst->_branch_stack_write = ; 2294 2294 // inst->_branch_direction = ; 2295 // inst->_address_next = ; 2295 // inst->_address_next = ; // already define : PC+4 2296 2296 inst->_no_execute = 0; 2297 2297 inst->_event_type = EVENT_TYPE_NONE; … … 2312 2312 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 2313 2313 inst->_read_rc = 0; 2314 // inst->_num_reg_rc = ; 2315 inst->_write_rd = 0; 2316 // inst->_num_reg_rd = ; 2317 inst->_write_re = 0; 2318 // inst->_num_reg_re = ; 2314 inst->_num_reg_rc = 0; //unnecessary 2315 inst->_write_rd = 0; 2316 inst->_num_reg_rd = 0; //unnecessary 2317 inst->_write_re = 0; 2318 inst->_num_reg_re = 0; //unnecessary 2319 2319 inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT; 2320 2320 inst->_exception = EXCEPTION_DECOD_NONE; … … 2322 2322 // inst->_branch_stack_write = ; 2323 2323 // inst->_branch_direction = ; 2324 // inst->_address_next = ; 2324 // inst->_address_next = ; // already define : PC+4 2325 2325 inst->_no_execute = 0; 2326 2326 inst->_event_type = EVENT_TYPE_NONE; … … 2334 2334 inst->_operation = instruction_information(INSTRUCTION_L_SLL)._operation; //OPERATION_SHIFT_L_SLL; 2335 2335 inst->_has_immediat = 0; 2336 // inst->_immediat = ; 2337 inst->_read_ra = 1; 2338 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2339 inst->_read_rb = 1; 2340 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 2341 inst->_read_rc = 0; 2342 // inst->_num_reg_rc = ; 2343 inst->_write_rd = 1; 2344 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 2345 inst->_write_re = 0; 2346 // inst->_num_reg_re = ; 2347 inst->_exception_use = EXCEPTION_USE_NONE; 2348 inst->_exception = EXCEPTION_DECOD_NONE; 2349 // inst->_branch_condition = ; 2350 // inst->_branch_stack_write = ; 2351 // inst->_branch_direction = ; 2352 // inst->_address_next = ; 2336 inst->_immediat = 0; // unnecessary 2337 inst->_read_ra = 1; 2338 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2339 inst->_read_rb = 1; 2340 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 2341 inst->_read_rc = 0; 2342 inst->_num_reg_rc = 0; //unnecessary 2343 inst->_write_rd = 1; 2344 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 2345 inst->_write_re = 0; 2346 inst->_num_reg_re = 0; //unnecessary 2347 inst->_exception_use = EXCEPTION_USE_NONE; 2348 inst->_exception = EXCEPTION_DECOD_NONE; 2349 // inst->_branch_condition = ; 2350 // inst->_branch_stack_write = ; 2351 // inst->_branch_direction = ; 2352 // inst->_address_next = ; // already define : PC+4 2353 2353 inst->_no_execute = 0; 2354 2354 inst->_event_type = EVENT_TYPE_NONE; … … 2366 2366 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2367 2367 inst->_read_rb = 0; 2368 // inst->_num_reg_rb = ; 2369 inst->_read_rc = 0; 2370 // inst->_num_reg_rc = ; 2371 inst->_write_rd = 1; 2372 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 2373 inst->_write_re = 0; 2374 // inst->_num_reg_re = ; 2375 inst->_exception_use = EXCEPTION_USE_NONE; 2376 inst->_exception = EXCEPTION_DECOD_NONE; 2377 // inst->_branch_condition = ; 2378 // inst->_branch_stack_write = ; 2379 // inst->_branch_direction = ; 2380 // inst->_address_next = ; 2368 inst->_num_reg_rb = 0; //unnecessary 2369 inst->_read_rc = 0; 2370 inst->_num_reg_rc = 0; //unnecessary 2371 inst->_write_rd = 1; 2372 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 2373 inst->_write_re = 0; 2374 inst->_num_reg_re = 0; //unnecessary 2375 inst->_exception_use = EXCEPTION_USE_NONE; 2376 inst->_exception = EXCEPTION_DECOD_NONE; 2377 // inst->_branch_condition = ; 2378 // inst->_branch_stack_write = ; 2379 // inst->_branch_direction = ; 2380 // inst->_address_next = ; // already define : PC+4 2381 2381 inst->_no_execute = 0; 2382 2382 inst->_event_type = EVENT_TYPE_NONE; … … 2390 2390 inst->_operation = instruction_information(INSTRUCTION_L_SRA)._operation; //OPERATION_SHIFT_L_SRA; 2391 2391 inst->_has_immediat = 0; 2392 // inst->_immediat = ; 2393 inst->_read_ra = 1; 2394 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2395 inst->_read_rb = 1; 2396 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 2397 inst->_read_rc = 0; 2398 // inst->_num_reg_rc = ; 2399 inst->_write_rd = 1; 2400 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 2401 inst->_write_re = 0; 2402 // inst->_num_reg_re = ; 2403 inst->_exception_use = EXCEPTION_USE_NONE; 2404 inst->_exception = EXCEPTION_DECOD_NONE; 2405 // inst->_branch_condition = ; 2406 // inst->_branch_stack_write = ; 2407 // inst->_branch_direction = ; 2408 // inst->_address_next = ; 2392 inst->_immediat = 0; // unnecessary 2393 inst->_read_ra = 1; 2394 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2395 inst->_read_rb = 1; 2396 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 2397 inst->_read_rc = 0; 2398 inst->_num_reg_rc = 0; //unnecessary 2399 inst->_write_rd = 1; 2400 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 2401 inst->_write_re = 0; 2402 inst->_num_reg_re = 0; //unnecessary 2403 inst->_exception_use = EXCEPTION_USE_NONE; 2404 inst->_exception = EXCEPTION_DECOD_NONE; 2405 // inst->_branch_condition = ; 2406 // inst->_branch_stack_write = ; 2407 // inst->_branch_direction = ; 2408 // inst->_address_next = ; // already define : PC+4 2409 2409 inst->_no_execute = 0; 2410 2410 inst->_event_type = EVENT_TYPE_NONE; … … 2422 2422 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2423 2423 inst->_read_rb = 0; 2424 // inst->_num_reg_rb = ; 2425 inst->_read_rc = 0; 2426 // inst->_num_reg_rc = ; 2427 inst->_write_rd = 1; 2428 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 2429 inst->_write_re = 0; 2430 // inst->_num_reg_re = ; 2431 inst->_exception_use = EXCEPTION_USE_NONE; 2432 inst->_exception = EXCEPTION_DECOD_NONE; 2433 // inst->_branch_condition = ; 2434 // inst->_branch_stack_write = ; 2435 // inst->_branch_direction = ; 2436 // inst->_address_next = ; 2424 inst->_num_reg_rb = 0; //unnecessary 2425 inst->_read_rc = 0; 2426 inst->_num_reg_rc = 0; //unnecessary 2427 inst->_write_rd = 1; 2428 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 2429 inst->_write_re = 0; 2430 inst->_num_reg_re = 0; //unnecessary 2431 inst->_exception_use = EXCEPTION_USE_NONE; 2432 inst->_exception = EXCEPTION_DECOD_NONE; 2433 // inst->_branch_condition = ; 2434 // inst->_branch_stack_write = ; 2435 // inst->_branch_direction = ; 2436 // inst->_address_next = ; // already define : PC+4 2437 2437 inst->_no_execute = 0; 2438 2438 inst->_event_type = EVENT_TYPE_NONE; … … 2446 2446 inst->_operation = instruction_information(INSTRUCTION_L_SRL)._operation; //OPERATION_SHIFT_L_SRL; 2447 2447 inst->_has_immediat = 0; 2448 // inst->_immediat = ; 2449 inst->_read_ra = 1; 2450 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2451 inst->_read_rb = 1; 2452 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 2453 inst->_read_rc = 0; 2454 // inst->_num_reg_rc = ; 2455 inst->_write_rd = 1; 2456 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 2457 inst->_write_re = 0; 2458 // inst->_num_reg_re = ; 2459 inst->_exception_use = EXCEPTION_USE_NONE; 2460 inst->_exception = EXCEPTION_DECOD_NONE; 2461 // inst->_branch_condition = ; 2462 // inst->_branch_stack_write = ; 2463 // inst->_branch_direction = ; 2464 // inst->_address_next = ; 2448 inst->_immediat = 0; // unnecessary 2449 inst->_read_ra = 1; 2450 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2451 inst->_read_rb = 1; 2452 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 2453 inst->_read_rc = 0; 2454 inst->_num_reg_rc = 0; //unnecessary 2455 inst->_write_rd = 1; 2456 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 2457 inst->_write_re = 0; 2458 inst->_num_reg_re = 0; //unnecessary 2459 inst->_exception_use = EXCEPTION_USE_NONE; 2460 inst->_exception = EXCEPTION_DECOD_NONE; 2461 // inst->_branch_condition = ; 2462 // inst->_branch_stack_write = ; 2463 // inst->_branch_direction = ; 2464 // inst->_address_next = ; // already define : PC+4 2465 2465 inst->_no_execute = 0; 2466 2466 inst->_event_type = EVENT_TYPE_NONE; … … 2478 2478 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2479 2479 inst->_read_rb = 0; 2480 // inst->_num_reg_rb = ; 2481 inst->_read_rc = 0; 2482 // inst->_num_reg_rc = ; 2483 inst->_write_rd = 1; 2484 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 2485 inst->_write_re = 0; 2486 // inst->_num_reg_re = ; 2487 inst->_exception_use = EXCEPTION_USE_NONE; 2488 inst->_exception = EXCEPTION_DECOD_NONE; 2489 // inst->_branch_condition = ; 2490 // inst->_branch_stack_write = ; 2491 // inst->_branch_direction = ; 2492 // inst->_address_next = ; 2480 inst->_num_reg_rb = 0; //unnecessary 2481 inst->_read_rc = 0; 2482 inst->_num_reg_rc = 0; //unnecessary 2483 inst->_write_rd = 1; 2484 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 2485 inst->_write_re = 0; 2486 inst->_num_reg_re = 0; //unnecessary 2487 inst->_exception_use = EXCEPTION_USE_NONE; 2488 inst->_exception = EXCEPTION_DECOD_NONE; 2489 // inst->_branch_condition = ; 2490 // inst->_branch_stack_write = ; 2491 // inst->_branch_direction = ; 2492 // inst->_address_next = ; // already define : PC+4 2493 2493 inst->_no_execute = 0; 2494 2494 inst->_event_type = EVENT_TYPE_NONE; … … 2502 2502 inst->_operation = instruction_information(INSTRUCTION_L_SUB)._operation; //OPERATION_ALU_L_SUB; 2503 2503 inst->_has_immediat = 0; 2504 // inst->_immediat = ; 2505 inst->_read_ra = 1; 2506 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2507 inst->_read_rb = 1; 2508 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 2509 inst->_read_rc = 0; 2510 // inst->_num_reg_rc = ; 2504 inst->_immediat = 0; // unnecessary 2505 inst->_read_ra = 1; 2506 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2507 inst->_read_rb = 1; 2508 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 2509 inst->_read_rc = 0; 2510 inst->_num_reg_rc = 0; //unnecessary 2511 2511 inst->_write_rd = 1; 2512 2512 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); … … 2518 2518 // inst->_branch_stack_write = ; 2519 2519 // inst->_branch_direction = ; 2520 // inst->_address_next = ; 2520 // inst->_address_next = ; // already define : PC+4 2521 2521 inst->_no_execute = 0; 2522 2522 inst->_event_type = EVENT_TYPE_NONE; … … 2537 2537 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 2538 2538 inst->_read_rc = 0; 2539 // inst->_num_reg_rc = ; 2540 inst->_write_rd = 0; 2541 // inst->_num_reg_rd = ; 2542 inst->_write_re = 0; 2543 // inst->_num_reg_re = ; 2539 inst->_num_reg_rc = 0; //unnecessary 2540 inst->_write_rd = 0; 2541 inst->_num_reg_rd = 0; //unnecessary 2542 inst->_write_re = 0; 2543 inst->_num_reg_re = 0; //unnecessary 2544 2544 inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT; 2545 2545 inst->_exception = EXCEPTION_DECOD_NONE; … … 2547 2547 // inst->_branch_stack_write = ; 2548 2548 // inst->_branch_direction = ; 2549 // inst->_address_next = ; 2549 // inst->_address_next = ; // already define : PC+4 2550 2550 inst->_no_execute = 0; 2551 2551 inst->_event_type = EVENT_TYPE_NONE; … … 2567 2567 // inst->_immediat = EXTENDZ(inst->_instruction,16); 2568 2568 inst->_has_immediat = 0; 2569 // inst->_immediat = ; 2569 inst->_immediat = 0; // unnecessary 2570 2570 inst->_read_ra = 0; 2571 // inst->_num_reg_ra = ; 2572 inst->_read_rb = 0; 2573 // inst->_num_reg_rb = ; 2574 inst->_read_rc = 0; 2575 // inst->_num_reg_rc = ; 2576 inst->_write_rd = 0; 2577 // inst->_num_reg_rd = ; 2578 inst->_write_re = 0; 2579 // inst->_num_reg_re = ; 2571 inst->_num_reg_ra = 0; //unnecessary 2572 inst->_read_rb = 0; 2573 inst->_num_reg_rb = 0; //unnecessary 2574 inst->_read_rc = 0; 2575 inst->_num_reg_rc = 0; //unnecessary 2576 inst->_write_rd = 0; 2577 inst->_num_reg_rd = 0; //unnecessary 2578 inst->_write_re = 0; 2579 inst->_num_reg_re = 0; //unnecessary 2580 2580 inst->_exception_use = EXCEPTION_USE_SYSCALL; 2581 2581 inst->_exception = EXCEPTION_SYSCALL; … … 2590 2590 2591 2591 2592 // inst->_address_next = ; // don't change2592 // inst->_address_next = ; // already define : PC+4 // don't change 2593 2593 inst->_no_execute = 1; 2594 2594 inst->_event_type = EVENT_TYPE_EXCEPTION; … … 2611 2611 inst->_immediat = EXTENDZ(inst->_instruction,16); 2612 2612 inst->_read_ra = 0; 2613 // inst->_num_reg_ra = ; 2614 inst->_read_rb = 0; 2615 // inst->_num_reg_rb = ; 2613 inst->_num_reg_ra = 0; //unnecessary 2614 inst->_read_rb = 0; 2615 inst->_num_reg_rb = 0; //unnecessary 2616 2616 inst->_read_rc = 0; // read all SR 2617 // inst->_num_reg_rc = ; 2618 inst->_write_rd = 0; 2619 // inst->_num_reg_rd = ; 2620 inst->_write_re = 0; 2621 // inst->_num_reg_re = ; 2617 inst->_num_reg_rc = 0; //unnecessary 2618 inst->_write_rd = 0; 2619 inst->_num_reg_rd = 0; //unnecessary 2620 inst->_write_re = 0; 2621 inst->_num_reg_re = 0; //unnecessary 2622 2622 inst->_exception_use = EXCEPTION_USE_TRAP; 2623 2623 inst->_exception = EXCEPTION_DECOD_NONE; … … 2625 2625 // inst->_branch_stack_write = ; 2626 2626 // inst->_branch_direction = ; 2627 // inst->_address_next = ; 2627 // inst->_address_next = ; // already define : PC+4 2628 2628 inst->_no_execute = 1; 2629 2629 inst->_event_type = EVENT_TYPE_NONE; … … 2638 2638 inst->_operation = instruction_information(INSTRUCTION_L_XOR)._operation; //OPERATION_ALU_L_XOR; 2639 2639 inst->_has_immediat = 0; 2640 // inst->_immediat = ; 2641 inst->_read_ra = 1; 2642 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2643 inst->_read_rb = 1; 2644 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 2645 inst->_read_rc = 0; 2646 // inst->_num_reg_rc = ; 2647 inst->_write_rd = 1; 2648 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 2649 inst->_write_re = 0; 2650 // inst->_num_reg_re = ; 2651 inst->_exception_use = EXCEPTION_USE_NONE; 2652 inst->_exception = EXCEPTION_DECOD_NONE; 2653 // inst->_branch_condition = ; 2654 // inst->_branch_stack_write = ; 2655 // inst->_branch_direction = ; 2656 // inst->_address_next = ; 2640 inst->_immediat = 0; // unnecessary 2641 inst->_read_ra = 1; 2642 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2643 inst->_read_rb = 1; 2644 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 2645 inst->_read_rc = 0; 2646 inst->_num_reg_rc = 0; //unnecessary 2647 inst->_write_rd = 1; 2648 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 2649 inst->_write_re = 0; 2650 inst->_num_reg_re = 0; //unnecessary 2651 inst->_exception_use = EXCEPTION_USE_NONE; 2652 inst->_exception = EXCEPTION_DECOD_NONE; 2653 // inst->_branch_condition = ; 2654 // inst->_branch_stack_write = ; 2655 // inst->_branch_direction = ; 2656 // inst->_address_next = ; // already define : PC+4 2657 2657 inst->_no_execute = 0; 2658 2658 inst->_event_type = EVENT_TYPE_NONE; … … 2670 2670 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2671 2671 inst->_read_rb = 0; 2672 // inst->_num_reg_rb = ; 2673 inst->_read_rc = 0; 2674 // inst->_num_reg_rc = ; 2675 inst->_write_rd = 1; 2676 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 2677 inst->_write_re = 0; 2678 // inst->_num_reg_re = ; 2679 inst->_exception_use = EXCEPTION_USE_NONE; 2680 inst->_exception = EXCEPTION_DECOD_NONE; 2681 // inst->_branch_condition = ; 2682 // inst->_branch_stack_write = ; 2683 // inst->_branch_direction = ; 2684 // inst->_address_next = ; 2672 inst->_num_reg_rb = 0; //unnecessary 2673 inst->_read_rc = 0; 2674 inst->_num_reg_rc = 0; //unnecessary 2675 inst->_write_rd = 1; 2676 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 2677 inst->_write_re = 0; 2678 inst->_num_reg_re = 0; //unnecessary 2679 inst->_exception_use = EXCEPTION_USE_NONE; 2680 inst->_exception = EXCEPTION_DECOD_NONE; 2681 // inst->_branch_condition = ; 2682 // inst->_branch_stack_write = ; 2683 // inst->_branch_direction = ; 2684 // inst->_address_next = ; // already define : PC+4 2685 2685 inst->_no_execute = 0; 2686 2686 inst->_event_type = EVENT_TYPE_NONE; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/src/test.cpp
r88 r97 75 75 ALLOC1_SC_SIGNAL(out_EVENT_IFETCH_UNIT_ADDRESS_NEXT_VAL ,"out_EVENT_IFETCH_UNIT_ADDRESS_NEXT_VAL ",Tcontrol_t,_param->_nb_context); 76 76 ALLOC1_SC_SIGNAL(out_EVENT_IFETCH_UNIT_IS_DS_TAKE ,"out_EVENT_IFETCH_UNIT_IS_DS_TAKE ",Tcontrol_t,_param->_nb_context); 77 ALLOC1_SC_SIGNAL(out_EVENT_PREDICTION_UNIT_VAL ,"out_EVENT_PREDICTION_UNIT_VAL ",Tcontrol_t,_param->_nb_context); 78 ALLOC1_SC_SIGNAL( in_EVENT_PREDICTION_UNIT_ACK ," in_EVENT_PREDICTION_UNIT_ACK ",Tcontrol_t,_param->_nb_context); 79 ALLOC1_SC_SIGNAL(out_EVENT_PREDICTION_UNIT_TYPE ,"out_EVENT_PREDICTION_UNIT_TYPE ",Tevent_type_t,_param->_nb_context); 80 ALLOC1_SC_SIGNAL(out_EVENT_PREDICTION_UNIT_DEPTH ,"out_EVENT_PREDICTION_UNIT_DEPTH ",Tdepth_t ,_param->_nb_context); 77 81 ALLOC1_SC_SIGNAL( in_EVENT_CONTEXT_STATE_VAL ," in_EVENT_CONTEXT_STATE_VAL ",Tcontrol_t,_param->_nb_context); 78 82 ALLOC1_SC_SIGNAL(out_EVENT_CONTEXT_STATE_ACK ,"out_EVENT_CONTEXT_STATE_ACK ",Tcontrol_t,_param->_nb_context); … … 81 85 ALLOC1_SC_SIGNAL( in_EVENT_CONTEXT_STATE_ADDRESS_NEXT_VAL ," in_EVENT_CONTEXT_STATE_ADDRESS_NEXT_VAL ",Tcontrol_t,_param->_nb_context); 82 86 ALLOC1_SC_SIGNAL( in_EVENT_CONTEXT_STATE_IS_DS_TAKE ," in_EVENT_CONTEXT_STATE_IS_DS_TAKE ",Tcontrol_t,_param->_nb_context); 87 ALLOC1_SC_SIGNAL( in_EVENT_CONTEXT_STATE_TYPE ," in_EVENT_CONTEXT_STATE_TYPE ",Tevent_type_t,_param->_nb_context); 88 ALLOC1_SC_SIGNAL( in_EVENT_CONTEXT_STATE_DEPTH ," in_EVENT_CONTEXT_STATE_DEPTH ",Tdepth_t ,_param->_nb_context); 83 89 84 90 ALLOC1_SC_SIGNAL(out_DEPTH_CURRENT ,"out_DEPTH_CURRENT ",Tdepth_t ,_param->_nb_context); … … 132 138 INSTANCE1_SC_SIGNAL(_Front_end_Glue,out_EVENT_IFETCH_UNIT_ADDRESS_NEXT_VAL ,_param->_nb_context); 133 139 INSTANCE1_SC_SIGNAL(_Front_end_Glue,out_EVENT_IFETCH_UNIT_IS_DS_TAKE ,_param->_nb_context); 140 INSTANCE1_SC_SIGNAL(_Front_end_Glue,out_EVENT_PREDICTION_UNIT_VAL ,_param->_nb_context); 141 INSTANCE1_SC_SIGNAL(_Front_end_Glue, in_EVENT_PREDICTION_UNIT_ACK ,_param->_nb_context); 142 INSTANCE1_SC_SIGNAL(_Front_end_Glue,out_EVENT_PREDICTION_UNIT_TYPE ,_param->_nb_context); 143 if (_param->_have_port_depth) 144 INSTANCE1_SC_SIGNAL(_Front_end_Glue,out_EVENT_PREDICTION_UNIT_DEPTH ,_param->_nb_context); 134 145 INSTANCE1_SC_SIGNAL(_Front_end_Glue, in_EVENT_CONTEXT_STATE_VAL ,_param->_nb_context); 135 146 INSTANCE1_SC_SIGNAL(_Front_end_Glue,out_EVENT_CONTEXT_STATE_ACK ,_param->_nb_context); … … 138 149 INSTANCE1_SC_SIGNAL(_Front_end_Glue, in_EVENT_CONTEXT_STATE_ADDRESS_NEXT_VAL ,_param->_nb_context); 139 150 INSTANCE1_SC_SIGNAL(_Front_end_Glue, in_EVENT_CONTEXT_STATE_IS_DS_TAKE ,_param->_nb_context); 151 INSTANCE1_SC_SIGNAL(_Front_end_Glue, in_EVENT_CONTEXT_STATE_TYPE ,_param->_nb_context); 152 if (_param->_have_port_depth) 153 INSTANCE1_SC_SIGNAL(_Front_end_Glue, in_EVENT_CONTEXT_STATE_DEPTH ,_param->_nb_context); 140 154 141 155 for (uint32_t i=0; i<_param->_nb_context; ++i) … … 230 244 DELETE1_SC_SIGNAL(out_EVENT_IFETCH_UNIT_ADDRESS_NEXT_VAL ,_param->_nb_context); 231 245 DELETE1_SC_SIGNAL(out_EVENT_IFETCH_UNIT_IS_DS_TAKE ,_param->_nb_context); 246 DELETE1_SC_SIGNAL(out_EVENT_PREDICTION_UNIT_VAL ,_param->_nb_context); 247 DELETE1_SC_SIGNAL( in_EVENT_PREDICTION_UNIT_ACK ,_param->_nb_context); 248 DELETE1_SC_SIGNAL(out_EVENT_PREDICTION_UNIT_TYPE ,_param->_nb_context); 249 DELETE1_SC_SIGNAL(out_EVENT_PREDICTION_UNIT_DEPTH ,_param->_nb_context); 232 250 DELETE1_SC_SIGNAL( in_EVENT_CONTEXT_STATE_VAL ,_param->_nb_context); 233 251 DELETE1_SC_SIGNAL(out_EVENT_CONTEXT_STATE_ACK ,_param->_nb_context); … … 236 254 DELETE1_SC_SIGNAL( in_EVENT_CONTEXT_STATE_ADDRESS_NEXT_VAL ,_param->_nb_context); 237 255 DELETE1_SC_SIGNAL( in_EVENT_CONTEXT_STATE_IS_DS_TAKE ,_param->_nb_context); 256 DELETE1_SC_SIGNAL( in_EVENT_CONTEXT_STATE_TYPE ,_param->_nb_context); 257 DELETE1_SC_SIGNAL( in_EVENT_CONTEXT_STATE_DEPTH ,_param->_nb_context); 238 258 239 259 DELETE1_SC_SIGNAL(out_DEPTH_MIN ,_param->_nb_context); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/include/Front_end_Glue.h
r88 r97 97 97 public : SC_OUT(Tcontrol_t ) ** out_EVENT_IFETCH_UNIT_ADDRESS_NEXT_VAL ;//[nb_context] 98 98 public : SC_OUT(Tcontrol_t ) ** out_EVENT_IFETCH_UNIT_IS_DS_TAKE ;//[nb_context] 99 100 public : SC_OUT(Tcontrol_t ) ** out_EVENT_PREDICTION_UNIT_VAL ;//[nb_context] 101 public : SC_IN (Tcontrol_t ) ** in_EVENT_PREDICTION_UNIT_ACK ;//[nb_context] 102 public : SC_OUT(Tevent_type_t ) ** out_EVENT_PREDICTION_UNIT_TYPE ;//[nb_context] 103 public : SC_OUT(Tdepth_t ) ** out_EVENT_PREDICTION_UNIT_DEPTH ;//[nb_context] 99 104 100 105 public : SC_IN (Tcontrol_t ) ** in_EVENT_CONTEXT_STATE_VAL ;//[nb_context] … … 104 109 public : SC_IN (Tcontrol_t ) ** in_EVENT_CONTEXT_STATE_ADDRESS_NEXT_VAL ;//[nb_context] 105 110 public : SC_IN (Tcontrol_t ) ** in_EVENT_CONTEXT_STATE_IS_DS_TAKE ;//[nb_context] 111 public : SC_IN (Tevent_type_t ) ** in_EVENT_CONTEXT_STATE_TYPE ;//[nb_context] 112 public : SC_IN (Tdepth_t ) ** in_EVENT_CONTEXT_STATE_DEPTH ;//[nb_context] 106 113 107 114 // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue.cpp
r88 r97 138 138 // sensitive << (*(in_CLOCK)).neg(); // don't need internal register 139 139 for (uint32_t i=0; i<_param->_nb_context; ++i) 140 sensitive << (*( in_EVENT_ACK [i])) 141 << (*( in_EVENT_IFETCH_UNIT_ACK [i])) 142 << (*( in_EVENT_CONTEXT_STATE_VAL [i])) 143 << (*( in_EVENT_CONTEXT_STATE_ADDRESS [i])) 144 << (*( in_EVENT_CONTEXT_STATE_ADDRESS_NEXT [i])) 145 << (*( in_EVENT_CONTEXT_STATE_ADDRESS_NEXT_VAL [i])) 146 << (*( in_EVENT_CONTEXT_STATE_IS_DS_TAKE [i])); 140 { 141 sensitive << (*( in_EVENT_ACK [i])) 142 << (*( in_EVENT_IFETCH_UNIT_ACK [i])) 143 << (*( in_EVENT_PREDICTION_UNIT_ACK [i])) 144 << (*( in_EVENT_CONTEXT_STATE_VAL [i])) 145 << (*( in_EVENT_CONTEXT_STATE_ADDRESS [i])) 146 << (*( in_EVENT_CONTEXT_STATE_ADDRESS_NEXT [i])) 147 << (*( in_EVENT_CONTEXT_STATE_ADDRESS_NEXT_VAL [i])) 148 << (*( in_EVENT_CONTEXT_STATE_IS_DS_TAKE [i])) 149 << (*( in_EVENT_CONTEXT_STATE_TYPE [i])); 150 if (_param->_have_port_depth) 151 sensitive << (*( in_EVENT_CONTEXT_STATE_DEPTH [i])); 152 } 147 153 148 154 # ifdef SYSTEMCASS_SPECIFIC -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_allocation.cpp
r88 r97 105 105 ALLOC1_SIGNAL_OUT (out_EVENT_IFETCH_UNIT_ADDRESS_NEXT_VAL ,"IFETCH_UNIT_ADDRESS_NEXT_VAL" ,Tcontrol_t ,1); 106 106 ALLOC1_SIGNAL_OUT (out_EVENT_IFETCH_UNIT_IS_DS_TAKE ,"IFETCH_UNIT_IS_DS_TAKE" ,Tcontrol_t ,1); 107 108 ALLOC1_SIGNAL_OUT (out_EVENT_PREDICTION_UNIT_VAL ,"PREDICTION_UNIT_VAL" ,Tcontrol_t ,1); 109 ALLOC1_SIGNAL_IN ( in_EVENT_PREDICTION_UNIT_ACK ,"PREDICTION_UNIT_ACK" ,Tcontrol_t ,1); 110 ALLOC1_SIGNAL_OUT (out_EVENT_PREDICTION_UNIT_TYPE ,"PREDICTION_UNIT_TYPE" ,Tevent_type_t ,_param->_size_event_type); 111 ALLOC1_SIGNAL_OUT (out_EVENT_PREDICTION_UNIT_DEPTH ,"PREDICTION_UNIT_DEPTH" ,Tdepth_t ,_param->_size_depth); 107 112 108 113 ALLOC1_SIGNAL_IN ( in_EVENT_CONTEXT_STATE_VAL ,"CONTEXT_STATE_VAL" ,Tcontrol_t ,1); … … 112 117 ALLOC1_SIGNAL_IN ( in_EVENT_CONTEXT_STATE_ADDRESS_NEXT_VAL ,"CONTEXT_STATE_ADDRESS_NEXT_VAL",Tcontrol_t ,1); 113 118 ALLOC1_SIGNAL_IN ( in_EVENT_CONTEXT_STATE_IS_DS_TAKE ,"CONTEXT_STATE_IS_DS_TAKE" ,Tcontrol_t ,1); 119 ALLOC1_SIGNAL_IN ( in_EVENT_CONTEXT_STATE_TYPE ,"CONTEXT_STATE_TYPE" ,Tevent_type_t ,_param->_size_event_type); 120 ALLOC1_SIGNAL_IN ( in_EVENT_CONTEXT_STATE_DEPTH ,"CONTEXT_STATE_DEPTH" ,Tdepth_t ,_param->_size_depth); 121 114 122 } 115 123 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_deallocation.cpp
r88 r97 55 55 DELETE1_SIGNAL(out_EVENT_IFETCH_UNIT_ADDRESS_NEXT_VAL ,_param->_nb_context,1); 56 56 DELETE1_SIGNAL(out_EVENT_IFETCH_UNIT_IS_DS_TAKE ,_param->_nb_context,1); 57 58 DELETE1_SIGNAL(out_EVENT_PREDICTION_UNIT_VAL ,_param->_nb_context,1); 59 DELETE1_SIGNAL( in_EVENT_PREDICTION_UNIT_ACK ,_param->_nb_context,1); 60 DELETE1_SIGNAL(out_EVENT_PREDICTION_UNIT_TYPE ,_param->_nb_context,_param->_size_event_type); 61 DELETE1_SIGNAL(out_EVENT_PREDICTION_UNIT_DEPTH ,_param->_nb_context,_param->_size_depth); 62 57 63 DELETE1_SIGNAL( in_EVENT_CONTEXT_STATE_VAL ,_param->_nb_context,1); 58 64 DELETE1_SIGNAL(out_EVENT_CONTEXT_STATE_ACK ,_param->_nb_context,1); … … 61 67 DELETE1_SIGNAL( in_EVENT_CONTEXT_STATE_ADDRESS_NEXT_VAL ,_param->_nb_context,1); 62 68 DELETE1_SIGNAL( in_EVENT_CONTEXT_STATE_IS_DS_TAKE ,_param->_nb_context,1); 69 DELETE1_SIGNAL( in_EVENT_CONTEXT_STATE_TYPE ,_param->_nb_context,_param->_size_event_type); 70 DELETE1_SIGNAL( in_EVENT_CONTEXT_STATE_DEPTH ,_param->_nb_context,_param->_size_depth); 63 71 64 72 DELETE1_SIGNAL(out_DEPTH_MIN ,_param->_nb_context,_param->_size_depth ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_genMealy_event.cpp
r88 r97 25 25 for (uint32_t i=0; i<_param->_nb_context; ++i) 26 26 { 27 Taddress_t address = PORT_READ(in_EVENT_CONTEXT_STATE_ADDRESS [i]);27 Taddress_t address = PORT_READ(in_EVENT_CONTEXT_STATE_ADDRESS [i]); 28 28 PORT_WRITE(out_EVENT_ADDRESS [i],address); 29 29 PORT_WRITE(out_EVENT_IFETCH_UNIT_ADDRESS [i],address); 30 30 31 Taddress_t address_next = PORT_READ(in_EVENT_CONTEXT_STATE_ADDRESS_NEXT [i]);31 Taddress_t address_next = PORT_READ(in_EVENT_CONTEXT_STATE_ADDRESS_NEXT [i]); 32 32 PORT_WRITE(out_EVENT_ADDRESS_NEXT [i],address_next); 33 33 PORT_WRITE(out_EVENT_IFETCH_UNIT_ADDRESS_NEXT [i],address_next); 34 34 35 Tcontrol_t address_next_val = PORT_READ(in_EVENT_CONTEXT_STATE_ADDRESS_NEXT_VAL [i]);35 Tcontrol_t address_next_val = PORT_READ(in_EVENT_CONTEXT_STATE_ADDRESS_NEXT_VAL [i]); 36 36 PORT_WRITE(out_EVENT_ADDRESS_NEXT_VAL [i],address_next_val); 37 37 PORT_WRITE(out_EVENT_IFETCH_UNIT_ADDRESS_NEXT_VAL [i],address_next_val); 38 38 39 Tcontrol_t is_ds_take = PORT_READ(in_EVENT_CONTEXT_STATE_IS_DS_TAKE [i]);39 Tcontrol_t is_ds_take = PORT_READ(in_EVENT_CONTEXT_STATE_IS_DS_TAKE [i]); 40 40 PORT_WRITE(out_EVENT_IS_DS_TAKE [i],is_ds_take); 41 41 PORT_WRITE(out_EVENT_IFETCH_UNIT_IS_DS_TAKE [i],is_ds_take); 42 42 43 Tcontrol_t val = PORT_READ(in_EVENT_CONTEXT_STATE_VAL [i]); 44 PORT_WRITE(out_EVENT_VAL [i],val); 45 PORT_WRITE(out_EVENT_IFETCH_UNIT_VAL [i],val); 43 Tevent_type_t event_type = PORT_READ(in_EVENT_CONTEXT_STATE_TYPE [i]); 44 PORT_WRITE(out_EVENT_PREDICTION_UNIT_TYPE [i],event_type); 45 46 if (_param->_have_port_depth) 47 { 48 Tdepth_t depth = PORT_READ(in_EVENT_CONTEXT_STATE_DEPTH [i]); 49 PORT_WRITE(out_EVENT_PREDICTION_UNIT_DEPTH [i],depth); 50 } 51 46 52 47 Tcontrol_t ack = (PORT_READ(in_EVENT_ACK [i]) and 48 PORT_READ(in_EVENT_IFETCH_UNIT_ACK [i])); 49 PORT_WRITE(out_EVENT_CONTEXT_STATE_ACK [i],ack); 53 Tcontrol_t ack = PORT_READ(in_EVENT_ACK [i]); 54 Tcontrol_t ifetch_unit_ack = PORT_READ(in_EVENT_IFETCH_UNIT_ACK [i]); 55 Tcontrol_t prediction_unit_ack = PORT_READ(in_EVENT_PREDICTION_UNIT_ACK [i]); 56 Tcontrol_t context_state_val = PORT_READ(in_EVENT_CONTEXT_STATE_VAL [i]); 57 58 Tcontrol_t val = (//ack and 59 ifetch_unit_ack and 60 prediction_unit_ack and 61 context_state_val 62 ); 63 Tcontrol_t ifetch_unit_val = ( ack and 64 //ifetch_unit_ack and 65 prediction_unit_ack and 66 context_state_val 67 ); 68 Tcontrol_t prediction_unit_val = ( ack and 69 ifetch_unit_ack and 70 //prediction_unit_ack and 71 context_state_val 72 ); 73 Tcontrol_t context_state_ack = ( ack and 74 ifetch_unit_ack and 75 prediction_unit_ack // and 76 //context_state_val 77 ); 78 79 log_printf(TRACE,Front_end_Glue,FUNCTION," * val %d, ack %d",val ,ack ); 80 log_printf(TRACE,Front_end_Glue,FUNCTION," * ifetch_unit_val %d, ifetch_unit_ack %d",ifetch_unit_val ,ifetch_unit_ack ); 81 log_printf(TRACE,Front_end_Glue,FUNCTION," * prediction_unit_val %d, prediction_unit_ack %d",prediction_unit_val,prediction_unit_ack); 82 log_printf(TRACE,Front_end_Glue,FUNCTION," * context_state_val %d, context_state_ack %d",context_state_val ,context_state_ack ); 83 84 85 PORT_WRITE(out_EVENT_VAL [i], val ); 86 PORT_WRITE(out_EVENT_IFETCH_UNIT_VAL [i], ifetch_unit_val ); 87 PORT_WRITE(out_EVENT_PREDICTION_UNIT_VAL [i], prediction_unit_val); 88 PORT_WRITE(out_EVENT_CONTEXT_STATE_ACK [i], context_state_ack ); 50 89 51 90 #ifdef DEBUG -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/SelfTest/src/test.cpp
r95 r97 94 94 ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_ADDRESS_DEST ,"out_BRANCH_EVENT_ADDRESS_DEST ",Taddress_t ,_param->_nb_context); 95 95 96 ALLOC1_SC_SIGNAL( in_EVENT_STATE ," in_EVENT_STATE ",Tevent_state_t ,_param->_nb_context); 97 ALLOC1_SC_SIGNAL( in_EVENT_TYPE ," in_EVENT_TYPE ",Tevent_type_t ,_param->_nb_context); 98 ALLOC1_SC_SIGNAL( in_EVENT_DEPTH ," in_EVENT_DEPTH ",Tdepth_t ,_param->_nb_context); 96 ALLOC1_SC_SIGNAL( in_EVENT_VAL ," in_EVENT_VAL ",Tcontrol_t ,_param->_nb_context); 97 ALLOC1_SC_SIGNAL(out_EVENT_ACK ,"out_EVENT_ACK ",Tcontrol_t ,_param->_nb_context); 98 ALLOC1_SC_SIGNAL( in_EVENT_TYPE ," in_EVENT_TYPE ",Tevent_type_t ,_param->_nb_context); 99 ALLOC1_SC_SIGNAL( in_EVENT_DEPTH ," in_EVENT_DEPTH ",Tdepth_t ,_param->_nb_context); 99 100 100 101 ALLOC1_SC_SIGNAL(out_DEPTH_CURRENT ,"out_DEPTH_CURRENT ",Tdepth_t ,_param->_nb_context); … … 160 161 INSTANCE1_SC_SIGNAL(_Prediction_unit,out_BRANCH_EVENT_ADDRESS_DEST ,_param->_nb_context); 161 162 162 INSTANCE1_SC_SIGNAL(_Prediction_unit, in_EVENT_STATE ,_param->_nb_context); 163 INSTANCE1_SC_SIGNAL(_Prediction_unit, in_EVENT_VAL ,_param->_nb_context); 164 INSTANCE1_SC_SIGNAL(_Prediction_unit,out_EVENT_ACK ,_param->_nb_context); 163 165 INSTANCE1_SC_SIGNAL(_Prediction_unit, in_EVENT_TYPE ,_param->_nb_context); 164 166 if (_param->_have_port_depth) … … 364 366 DELETE1_SC_SIGNAL(out_BRANCH_EVENT_ADDRESS_DEST ,_param->_nb_context); 365 367 366 DELETE1_SC_SIGNAL( in_EVENT_STATE ,_param->_nb_context); 368 DELETE1_SC_SIGNAL( in_EVENT_VAL ,_param->_nb_context); 369 DELETE1_SC_SIGNAL(out_EVENT_ACK ,_param->_nb_context); 367 370 DELETE1_SC_SIGNAL( in_EVENT_TYPE ,_param->_nb_context); 368 371 DELETE1_SC_SIGNAL( in_EVENT_DEPTH ,_param->_nb_context); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/Makefile.deps
r81 r97 21 21 22 22 Update_Prediction_Table_LIBRARY = -lUpdate_Prediction_Table \ 23 $(Behavioural_LIBRARY) 23 $(Behavioural_LIBRARY) 24 24 25 25 Update_Prediction_Table_DIR_LIBRARY = -L$(Update_Prediction_Table_DIR)/lib \ -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/src/test.cpp
r95 r97 42 42 43 43 #ifdef STATISTICS 44 morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5, 50);44 morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,CYCLE_MAX); 45 45 #endif 46 46 … … 137 137 ALLOC1_SC_SIGNAL(out_UPDATE_RAS_PREDICTION_IFETCH ,"out_UPDATE_RAS_PREDICTION_IFETCH ",Tcontrol_t ,_param->_nb_inst_update); 138 138 139 ALLOC1_SC_SIGNAL( in_EVENT_STATE ," in_EVENT_STATE ",Tevent_state_t ,_param->_nb_context); 139 ALLOC1_SC_SIGNAL( in_EVENT_VAL ," in_EVENT_VAL ",Tcontrol_t ,_param->_nb_context); 140 ALLOC1_SC_SIGNAL(out_EVENT_ACK ,"out_EVENT_ACK ",Tcontrol_t ,_param->_nb_context); 140 141 ALLOC1_SC_SIGNAL( in_EVENT_TYPE ," in_EVENT_TYPE ",Tevent_type_t ,_param->_nb_context); 141 142 ALLOC1_SC_SIGNAL( in_EVENT_DEPTH ," in_EVENT_DEPTH ",Tdepth_t ,_param->_nb_context); … … 230 231 INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_INDEX ,_param->_nb_inst_update); 231 232 INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_PREDICTION_IFETCH ,_param->_nb_inst_update); 232 INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_EVENT_STATE ,_param->_nb_context); 233 INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_EVENT_VAL ,_param->_nb_context); 234 INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_EVENT_ACK ,_param->_nb_context); 233 235 INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_EVENT_TYPE ,_param->_nb_context); 234 236 if (_param->_have_port_depth) … … 316 318 in_UPDATE_ACK [i]->write(0); 317 319 for (uint32_t i=0; i<_param->_nb_context; ++i) 318 { 319 in_EVENT_STATE [i]->write(EVENT_STATE_NO_EVENT); 320 in_EVENT_TYPE [i]->write(EVENT_TYPE_NONE ); 321 } 320 in_EVENT_VAL [i]->write(0); 321 322 322 //--------------------------------------------------------------------- 323 323 //--------------------------------------------------------------------- … … 932 932 933 933 SC_START(1); 934 in_EVENT_ STATE [context]->write(EVENT_STATE_END);934 in_EVENT_VAL [context]->write(1); 935 935 in_EVENT_TYPE [context]->write(EVENT_TYPE_MISS_SPECULATION); 936 936 937 937 SC_START(1); 938 in_EVENT_ STATE [context]->write(EVENT_STATE_NO_EVENT);938 in_EVENT_VAL [context]->write(0); 939 939 in_EVENT_TYPE [context]->write(EVENT_TYPE_NONE ); 940 940 } … … 1366 1366 1367 1367 SC_START(1); 1368 in_EVENT_ STATE [context]->write(EVENT_STATE_END);1368 in_EVENT_VAL [context]->write(1); 1369 1369 in_EVENT_TYPE [context]->write(EVENT_TYPE_MISS_SPECULATION); 1370 1370 1371 1371 SC_START(1); 1372 in_EVENT_ STATE [context]->write(EVENT_STATE_NO_EVENT);1372 in_EVENT_VAL [context]->write(0); 1373 1373 in_EVENT_TYPE [context]->write(EVENT_TYPE_NONE ); 1374 1374 } … … 1974 1974 1975 1975 SC_START(1); 1976 in_EVENT_ STATE [context]->write(EVENT_STATE_END);1976 in_EVENT_VAL [context]->write(1); 1977 1977 in_EVENT_TYPE [context]->write(EVENT_TYPE_MISS_SPECULATION); 1978 1978 1979 1979 SC_START(1); 1980 in_EVENT_ STATE [context]->write(EVENT_STATE_NO_EVENT);1980 in_EVENT_VAL [context]->write(0); 1981 1981 in_EVENT_TYPE [context]->write(EVENT_TYPE_NONE ); 1982 1982 } … … 2155 2155 delete [] out_UPDATE_RAS_PREDICTION_IFETCH; 2156 2156 2157 DELETE1_SC_SIGNAL( in_EVENT_STATE ,_param->_nb_context); 2157 DELETE1_SC_SIGNAL( in_EVENT_VAL ,_param->_nb_context); 2158 DELETE1_SC_SIGNAL(out_EVENT_ACK ,_param->_nb_context); 2158 2159 DELETE1_SC_SIGNAL( in_EVENT_TYPE ,_param->_nb_context); 2159 2160 DELETE1_SC_SIGNAL( in_EVENT_DEPTH ,_param->_nb_context); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Update_Prediction_Table.h
r95 r97 52 52 public : Stat * _stat; 53 53 54 private : counter_t ** _stat_nb_branch_hit ; //[nb_context] 55 private : counter_t ** _stat_nb_branch_miss ; //[nb_context] 56 private : counter_t ** _stat_nb_branch_unused ; //[nb_context] 57 private : counter_t ** _stat_queue_nb_cycle_empty; //[nb_context] 58 private : counter_t ** _stat_queue_nb_cycle_full ; //[nb_context] 59 private : counter_t ** _stat_queue_nb_elt ; //[nb_context] 54 private : counter_t *** _stat_nb_branch_hit ; //[nb_context][MAX_BRANCH_CONDITION] 55 private : counter_t *** _stat_nb_branch_miss ; //[nb_context][MAX_BRANCH_CONDITION] 56 private : counter_t ** _stat_nb_branch_unused ; //[nb_context] 57 private : counter_t ** _stat_ufpt_queue_nb_elt ; //[nb_context] 58 private : counter_t ** _stat_upt_queue_nb_elt ; //[nb_context] 60 59 61 60 #endif … … 143 142 144 143 // ~~~~~[ Interface : "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 145 public : SC_IN (Tevent_state_t ) ** in_EVENT_STATE ; //[nb_context] 144 public : SC_IN (Tcontrol_t ) ** in_EVENT_VAL ; //[nb_context] 145 public : SC_OUT(Tcontrol_t ) ** out_EVENT_ACK ; //[nb_context] 146 146 public : SC_IN (Tevent_type_t ) ** in_EVENT_TYPE ; //[nb_context] 147 147 public : SC_IN (Tdepth_t ) ** in_EVENT_DEPTH ; //[nb_context] … … 197 197 private : Tdepth_t * internal_UPDATE_DEPTH ; //[nb_inst_update] 198 198 private : bool * internal_UPDATE_RAS ; //[nb_inst_update] 199 private : Tcontrol_t * internal_EVENT_ACK ; //[nb_context] 199 200 200 201 #endif -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table.cpp
r88 r97 76 76 if (usage_is_set(_usage,USE_SYSTEMC)) 77 77 { 78 78 // Constant 79 79 for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++) 80 80 { … … 82 82 PORT_WRITE(out_BRANCH_COMPLETE_ACK [i], internal_BRANCH_COMPLETE_ACK [i]); 83 83 } 84 for (uint32_t i=0; i<_param->_nb_context; ++i) 85 { 86 internal_EVENT_ACK [i] = 1; 87 PORT_WRITE(out_EVENT_ACK [i], internal_EVENT_ACK [i]); 88 } 84 89 85 90 log_printf(INFO,Update_Prediction_Table,FUNCTION,"Method - transition"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_allocation.cpp
r95 r97 151 151 ALLOC1_INTERFACE("event", IN,SOUTH,"event", _param->_nb_context); 152 152 153 ALLOC1_SIGNAL_IN ( in_EVENT_STATE ,"state",Tevent_state_t,_param->_size_event_state); 153 ALLOC1_VALACK_IN ( in_EVENT_VAL ,VAL); 154 ALLOC1_VALACK_OUT(out_EVENT_ACK ,ACK); 154 155 ALLOC1_SIGNAL_IN ( in_EVENT_TYPE ,"type" ,Tevent_type_t ,_param->_size_event_type ); 155 156 ALLOC1_SIGNAL_IN ( in_EVENT_DEPTH ,"depth",Tdepth_t ,_param->_size_depth ); … … 183 184 ALLOC1(internal_UPDATE_DEPTH ,Tdepth_t ,_param->_nb_inst_update); 184 185 ALLOC1(internal_UPDATE_RAS ,bool ,_param->_nb_inst_update); 186 ALLOC1(internal_EVENT_ACK ,Tcontrol_t,_param->_nb_context); 185 187 186 188 // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_deallocation.cpp
r95 r97 111 111 112 112 // ~~~~~[ Interface : "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 113 DELETE1_SIGNAL( in_EVENT_STATE ,_param->_nb_context,_param->_size_event_state); 113 DELETE1_SIGNAL( in_EVENT_VAL ,_param->_nb_context,1); 114 DELETE1_SIGNAL(out_EVENT_ACK ,_param->_nb_context,1); 114 115 DELETE1_SIGNAL( in_EVENT_TYPE ,_param->_nb_context,_param->_size_event_type ); 115 116 DELETE1_SIGNAL( in_EVENT_DEPTH ,_param->_nb_context,_param->_size_depth ); … … 137 138 DELETE1(internal_UPDATE_DEPTH ,_param->_nb_inst_update); 138 139 DELETE1(internal_UPDATE_RAS ,_param->_nb_inst_update); 140 DELETE1(internal_EVENT_ACK ,_param->_nb_context); 139 141 140 142 // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_genMealy_branch_complete.cpp
r94 r97 67 67 if (take != 1) 68 68 throw ERRORMORPHEO(FUNCTION,toString("Branch_complete[%d] (condition %s) : bad direction.",i,toString(condition).c_str())); 69 if (addr_dest != addr_good)70 throw ERRORMORPHEO(FUNCTION,toString("Branch_complete[%d] (condition %s) : bad destination address.",i,toString(condition).c_str()));69 // if (addr_dest != addr_good) 70 // throw ERRORMORPHEO(FUNCTION,toString("Branch_complete[%d] (condition %s) : bad destination address.",i,toString(condition).c_str())); 71 71 #endif 72 72 … … 85 85 86 86 #ifdef DEBUG_TEST 87 if (addr_dest != addr_good)88 throw ERRORMORPHEO(FUNCTION,toString("Branch_complete[%d] (condition %s) : bad destination address.",i,toString(condition).c_str()));87 // if (addr_dest != addr_good) 88 // throw ERRORMORPHEO(FUNCTION,toString("Branch_complete[%d] (condition %s) : bad destination address.",i,toString(condition).c_str())); 89 89 #endif 90 90 … … 103 103 104 104 #ifdef DEBUG_TEST 105 if (addr_dest != addr_good)106 throw ERRORMORPHEO(FUNCTION,toString("Branch_complete[%d] (condition %s) : bad destination address.",i,toString(condition).c_str()));105 // if (addr_dest != addr_good) 106 // throw ERRORMORPHEO(FUNCTION,toString("Branch_complete[%d] (condition %s) : bad destination address.",i,toString(condition).c_str())); 107 107 #endif 108 108 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_statistics_allocation.cpp
r88 r97 8 8 9 9 #include "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Update_Prediction_Table.h" 10 #include "Behavioural/include/Allocation.h" 11 10 12 11 13 namespace morpheo { … … 28 30 param_statistics); 29 31 30 // _stat_nb_branch_hit = new counter_t * [_param->_nb_context]; 31 // _stat_nb_branch_miss = new counter_t * [_param->_nb_context]; 32 // _stat_nb_branch_unused = new counter_t * [_param->_nb_context]; 33 // _stat_queue_nb_cycle_empty = new counter_t * [_param->_nb_context]; 34 // _stat_queue_nb_cycle_full = new counter_t * [_param->_nb_context]; 35 // _stat_queue_nb_elt = new counter_t * [_param->_nb_context]; 36 37 // for (uint32_t i=0; i<_param->_nb_context; ++i) 38 // { 39 // _stat_nb_branch_hit [i] = _stat->create_counter("nb_branch_hit_" +toString(i),"",toString(_("Branch hit speculation (context %d)"),i)); 40 // _stat_nb_branch_miss [i] = _stat->create_counter("nb_branch_miss_" +toString(i),"",toString(_("Branch miss speculation (context %d)"),i)); 41 // _stat_nb_branch_unused [i] = _stat->create_counter("nb_branch_unused_" +toString(i),"",toString(_("Branch unused, because an previous branch have miss speculation (context %d)"),i)); 42 // _stat_queue_nb_cycle_empty [i] = _stat->create_counter("queue_nb_cycle_empty_"+toString(i),"",toString(_("Cycle number where the Update Prediction Table is empty (context %d)"),i)); 43 // _stat_queue_nb_cycle_full [i] = _stat->create_counter("queue_nb_cycle_full_" +toString(i),"",toString(_("Cycle number where the Update Prediction Table is full (%d elements) (context %d)"),_param->_size_queue[i],i)); 44 // _stat_queue_nb_elt [i] = _stat->create_counter("queue_nb_elt_" +toString(i),"",toString(_("Average branchement by cycle in Update Prediction Table (context %d)"),i)); 45 // } 46 32 { 33 ALLOC2(_stat_nb_branch_hit ,counter_t *,_param->_nb_context,MAX_BRANCH_CONDITION); 34 ALLOC2(_stat_nb_branch_miss ,counter_t *,_param->_nb_context,MAX_BRANCH_CONDITION); 35 ALLOC1(_stat_nb_branch_unused ,counter_t *,_param->_nb_context); 36 37 for (uint32_t i=0; i<_param->_nb_context; ++i) 38 { 39 std::string sum_miss = "0"; 40 std::string sum_branchement = "0"; 41 42 for (uint32_t j=0; j<MAX_BRANCH_CONDITION; ++j) 43 if (is_branch_condition_valid(j)) 44 { 45 std::string nb_miss = "nb_branch_miss_"+toString(i)+"_"+toString(j); 46 std::string nb_branchement = "+ nb_branch_hit_"+toString(i)+"_"+toString(j)+" nb_branch_miss_"+toString(i)+"_"+toString(j); 47 _stat_nb_branch_hit [i][j] = _stat->create_counter("nb_branch_hit_" +toString(i)+"_"+toString(j),"",toString(_("Branch hit speculation, branch condition : %s (context %d)"),toString(static_cast<branch_condition_t>(j)).c_str(),i)); 48 _stat_nb_branch_miss [i][j] = _stat->create_counter(nb_miss,"",toString(_("Branch miss speculation, branch condition : %s (context %d)"),toString(static_cast<branch_condition_t>(j)).c_str(),i)); 49 50 // _stat->create_expr_average("average_miss_"+toString(i)+"_"+toString(j), 51 // "nb_branch_miss_"+toString(i)+"_"+toString(j), 52 // nb_branchement, 53 // "miss/branchement", 54 // toString(_("Average miss by branchement, branch condition : %s (context %d)"),toString(static_cast<branch_condition_t>(j)).c_str(),i)); 55 56 _stat->create_expr_percent("percent_miss_"+toString(i)+"_"+toString(j), 57 nb_miss, 58 nb_branchement, 59 toString(_("Percent miss by branchement, branch condition : %s (context %d)"),toString(static_cast<branch_condition_t>(j)).c_str(),i)); 60 61 sum_miss = "+ "+nb_miss +" "+ sum_miss; 62 sum_branchement = "+ "+nb_branchement+" "+sum_branchement; 63 } 64 65 // _stat->create_expr_average("average_miss_"+toString(i), 66 // sum_miss, 67 // sum_branchement, 68 // "miss/branchement", 69 // toString(_("Average miss by branchement (context %d)"),i)); 70 71 _stat->create_expr_percent("percent_miss_"+toString(i), 72 sum_miss, 73 sum_branchement, 74 toString(_("Percent miss by branchement (context %d)"),i)); 75 76 _stat_nb_branch_unused [i] = _stat->create_counter("nb_branch_unused_" +toString(i),"",toString(_("Branch unused (previous speculation) (context %d)"),i)); 77 } 78 } 79 80 { 81 ALLOC1(_stat_ufpt_queue_nb_elt ,counter_t *,_param->_nb_context); 82 83 for (uint32_t i=0; i<_param->_nb_context; ++i) 84 { 85 _stat_ufpt_queue_nb_elt [i] = _stat->create_counter("ufpt_queue_nb_elt_"+toString(i),"",toString(_("Branchement in Update Fetch Prediction Table (context %d)"),i)); 86 87 _stat->create_expr_average_by_cycle("average_occupation_ufpt_queue_"+toString(i),"ufpt_queue_nb_elt_"+toString(i), "", toString(_("Average instruction by cycle in Update Fetch Prediction Table (context %d)"),i)); 88 _stat->create_expr_percent ("percent_occupation_ufpt_queue_"+toString(i), "average_occupation_ufpt_queue_"+toString(i), toString(_param->_size_ufpt_queue[i]), toString(_("Percent occupation of Update Fetch Prediction Table (context %d)"),i)); 89 } 90 } 91 92 { 93 ALLOC1(_stat_upt_queue_nb_elt ,counter_t *,_param->_nb_context); 94 95 for (uint32_t i=0; i<_param->_nb_context; ++i) 96 { 97 _stat_upt_queue_nb_elt [i] = _stat->create_counter("upt_queue_nb_elt_"+toString(i),"",toString(_("Average branchement by cycle in Update Prediction Table (context %d)"),i)); 98 99 _stat->create_expr_average_by_cycle("average_occupation_upt_queue_"+toString(i),"upt_queue_nb_elt_"+toString(i), "", toString(_("Average instruction by cycle in Update Prediction Table (context %d)"),i)); 100 _stat->create_expr_percent ("percent_occupation_upt_queue_"+toString(i), "average_occupation_upt_queue_"+toString(i), toString(_param->_size_upt_queue[i]), toString(_("Percent occupation of Update Prediction Table (context %d)"),i)); 101 } 102 } 103 47 104 log_printf(FUNC,Update_Prediction_Table,FUNCTION,"End"); 48 105 }; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_statistics_deallocation.cpp
r88 r97 8 8 9 9 #include "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Update_Prediction_Table.h" 10 #include "Behavioural/include/Allocation.h" 10 11 11 12 namespace morpheo { … … 27 28 28 29 delete _stat; 29 // delete [] _stat_nb_branch_hit ; 30 // delete [] _stat_nb_branch_miss;31 // delete [] _stat_nb_branch_unused;32 // delete [] _stat_queue_nb_cycle_empty;33 // delete [] _stat_queue_nb_cycle_full;34 // delete [] _stat_queue_nb_elt;30 31 DELETE2(_stat_nb_branch_hit ,_param->_nb_context,MAX_BRANCH_CONDITION); 32 DELETE2(_stat_nb_branch_miss ,_param->_nb_context,MAX_BRANCH_CONDITION); 33 DELETE1(_stat_nb_branch_unused ,_param->_nb_context); 34 DELETE1(_stat_ufpt_queue_nb_elt ,_param->_nb_context); 35 DELETE1(_stat_upt_queue_nb_elt ,_param->_nb_context); 35 36 36 37 log_printf(FUNC,Update_Prediction_Table,FUNCTION,"End"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_transition.cpp
r95 r97 472 472 // bool have_event = ((reg_UPDATE_PREDICTION_TABLE [context][depth]._state == UPDATE_PREDICTION_STATE_KO) or 473 473 // (reg_UPDATE_PREDICTION_TABLE [context][depth]._state == UPDATE_PREDICTION_STATE_EVENT)); 474 #ifdef STATISTICS 475 Tbranch_condition_t condition = reg_UPDATE_PREDICTION_TABLE [context][depth]._condition; 476 bool ok = (reg_UPDATE_PREDICTION_TABLE [context][depth]._state == UPDATE_PREDICTION_STATE_OK); 477 #endif 474 478 bool ko = (reg_UPDATE_PREDICTION_TABLE [context][depth]._state == UPDATE_PREDICTION_STATE_KO); 475 479 … … 480 484 481 485 reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_END_KO; 486 487 #ifdef STATISTICS 488 if (usage_is_set(_usage,USE_STATISTICS)) 489 (*_stat_nb_branch_miss [context][condition])++; 490 #endif 482 491 } 483 492 else … … 486 495 487 496 reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_END_OK; 497 498 499 #ifdef STATISTICS 500 if (usage_is_set(_usage,USE_STATISTICS)) 501 { 502 if (ok) 503 (*_stat_nb_branch_hit [context][condition]) ++; 504 else 505 (*_stat_nb_branch_unused [context]) ++; 506 } 507 #endif 488 508 } 489 509 … … 548 568 // =================================================================== 549 569 for (uint32_t i=0; i<_param->_nb_context; ++i) 550 { 551 //---------------------------------------------------------------- 552 // Cases 553 //---------------------------------------------------------------- 554 // * EVENT_TYPE_NONE - nothing 555 // * EVENT_TYPE_MISS_SPECULATION 556 // * EVENT_STATE_END - Change state, reset pointer 557 // * EVENT_TYPE_EXCEPTION - 558 // * EVENT_STATE_EVENT - Flush upft and upt 559 // * EVENT_STATE_END - Change state, reset pointer 560 // * EVENT_TYPE_BRANCH_NO_ACCURATE - nothing : manage in decod and update 561 // * EVENT_TYPE_SPR_ACCESS - nothing 562 // * EVENT_TYPE_MSYNC - nothing 563 // * EVENT_TYPE_PSYNC - nothing 564 // * EVENT_TYPE_CSYNC - nothing 565 566 Tevent_state_t event_state = PORT_READ(in_EVENT_STATE [i]); 567 Tevent_type_t event_type = PORT_READ(in_EVENT_TYPE [i]); 568 // Tdepth_t depth = PORT_READ(in_EVENT_DEPTH [i]); 570 if (PORT_READ(in_EVENT_VAL [i]) and internal_EVENT_ACK [i]) 571 { 572 //---------------------------------------------------------------- 573 // Cases 574 //---------------------------------------------------------------- 575 // * EVENT_TYPE_NONE - nothing 576 // * EVENT_TYPE_MISS_SPECULATION - Change state, reset pointer 577 // * EVENT_TYPE_EXCEPTION - Flush upft and upt, Change state, reset pointer 578 // * EVENT_TYPE_BRANCH_NO_ACCURATE - nothing : manage in decod and update 579 // * EVENT_TYPE_SPR_ACCESS - nothing 580 // * EVENT_TYPE_MSYNC - nothing 581 // * EVENT_TYPE_PSYNC - nothing 582 // * EVENT_TYPE_CSYNC - nothing 583 584 Tevent_type_t event_type = PORT_READ(in_EVENT_TYPE [i]); 585 // Tdepth_t depth = PORT_READ(in_EVENT_DEPTH [i]); 569 586 570 // Test if end of miss 571 if ((event_state == EVENT_STATE_END) and 572 (event_type == EVENT_TYPE_MISS_SPECULATION)) 573 { 574 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT"); 575 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * state : EVENT_STATE_END"); 576 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * type : EVENT_TYPE_MISS_SPECULATION"); 577 578 #ifdef DEBUG_TEST 579 if (reg_EVENT_STATE [i] != EVENT_STATE_WAIT_END_EVENT) 580 throw ERRORMORPHEO(FUNCTION,_("Event : invalid event state.")); 581 #endif 582 583 // Change state 584 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_OK (event)",i); 585 586 reg_EVENT_STATE [i] = EVENT_STATE_OK; 587 588 // uint32_t bottom = reg_UPT_BOTTOM [i]; 589 590 // reg_UPT_TOP [i] = bottom; 591 // reg_UPT_UPDATE [i] = bottom; 592 } 593 } 587 // Test if end of miss 588 if (event_type == EVENT_TYPE_MISS_SPECULATION) 589 { 590 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT"); 591 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * type : EVENT_TYPE_MISS_SPECULATION"); 592 593 #ifdef DEBUG_TEST 594 if (reg_EVENT_STATE [i] != EVENT_STATE_WAIT_END_EVENT) 595 throw ERRORMORPHEO(FUNCTION,_("Event : invalid event state.")); 596 #endif 597 598 // Change state 599 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_OK (event)",i); 600 601 reg_EVENT_STATE [i] = EVENT_STATE_OK; 602 } 603 } 594 604 595 605 // =================================================================== … … 634 644 } 635 645 646 #ifdef STATISTICS 647 if (usage_is_set(_usage,USE_STATISTICS)) 648 for (uint32_t i=0; i<_param->_nb_context; i++) 649 { 650 for (uint32_t j=0; j<_param->_size_ufpt_queue[i]; j++) 651 if (reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._state != UPDATE_FETCH_PREDICTION_STATE_EMPTY) 652 (*_stat_ufpt_queue_nb_elt [i]) ++; 653 for (uint32_t j=0; j<_param->_size_upt_queue[i]; j++) 654 if (reg_UPDATE_PREDICTION_TABLE [i][j]._state != UPDATE_PREDICTION_STATE_EMPTY) 655 (*_stat_upt_queue_nb_elt [i]) ++; 656 } 657 #endif 658 636 659 // =================================================================== 637 660 // =====[ PRINT ]===================================================== -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/include/Prediction_unit.h
r95 r97 115 115 116 116 // ~~~~~[ Interface : "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 117 public : SC_IN (Tevent_state_t ) ** in_EVENT_STATE ; //[nb_context] 117 public : SC_IN (Tcontrol_t ) ** in_EVENT_VAL ; //[nb_context] 118 public : SC_OUT(Tcontrol_t ) ** out_EVENT_ACK ; //[nb_context] 118 119 public : SC_IN (Tevent_type_t ) ** in_EVENT_TYPE ; //[nb_context] 119 120 public : SC_IN (Tdepth_t ) ** in_EVENT_DEPTH ; //[nb_context] -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/src/Prediction_unit_allocation.cpp
r95 r97 136 136 ALLOC1_INTERFACE("event", IN,SOUTH,"event", _param->_nb_context); 137 137 138 ALLOC1_SIGNAL_IN ( in_EVENT_STATE ,"state",Tevent_state_t,_param->_size_event_state); 138 ALLOC1_VALACK_IN ( in_EVENT_VAL ,VAL); 139 ALLOC1_VALACK_OUT(out_EVENT_ACK ,ACK); 139 140 ALLOC1_SIGNAL_IN ( in_EVENT_TYPE ,"type" ,Tevent_type_t ,_param->_size_event_type ); 140 141 ALLOC1_SIGNAL_IN ( in_EVENT_DEPTH ,"depth",Tdepth_t ,_param->_size_depth ); … … 711 712 #endif 712 713 713 PORT_MAP(_component,src , "in_EVENT_"+toString(i)+"_STATE",dest, "in_EVENT_"+toString(i)+"_STATE"); 714 PORT_MAP(_component,src , "in_EVENT_"+toString(i)+"_VAL" ,dest, "in_EVENT_"+toString(i)+"_VAL" ); 715 PORT_MAP(_component,src ,"out_EVENT_"+toString(i)+"_ACK" ,dest,"out_EVENT_"+toString(i)+"_ACK" ); 714 716 PORT_MAP(_component,src , "in_EVENT_"+toString(i)+"_TYPE" ,dest, "in_EVENT_"+toString(i)+"_TYPE" ); 715 717 if (_param->_have_port_depth) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/src/Prediction_unit_deallocation.cpp
r95 r97 71 71 DELETE1_SIGNAL(out_BRANCH_EVENT_ADDRESS_DEST ,_param->_nb_context,_param->_size_instruction_address); 72 72 73 DELETE1_SIGNAL( in_EVENT_STATE ,_param->_nb_context,_param->_size_event_state); 73 DELETE1_SIGNAL( in_EVENT_VAL ,_param->_nb_context,1); 74 DELETE1_SIGNAL(out_EVENT_ACK ,_param->_nb_context,1); 74 75 DELETE1_SIGNAL( in_EVENT_TYPE ,_param->_nb_context,_param->_size_event_type ); 75 76 DELETE1_SIGNAL( in_EVENT_DEPTH ,_param->_nb_context,_param->_size_depth ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/src/test.cpp
r88 r97 99 99 ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EPCR ," in_COMMIT_EVENT_ADDRESS_EPCR ",Taddress_t ); 100 100 ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EEAR_VAL ," in_COMMIT_EVENT_ADDRESS_EEAR_VAL ",Tcontrol_t ); 101 ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EEAR ," in_COMMIT_EVENT_ADDRESS_EEAR ",T address_t);101 ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EEAR ," in_COMMIT_EVENT_ADDRESS_EEAR ",Tgeneral_data_t ); 102 102 ALLOC1_SC_SIGNAL(out_EVENT_VAL ,"out_EVENT_VAL ",Tcontrol_t ,_param->_nb_context); 103 103 ALLOC1_SC_SIGNAL( in_EVENT_ACK ," in_EVENT_ACK ",Tcontrol_t ,_param->_nb_context); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Front_end_allocation.cpp
r95 r97 140 140 ALLOC_SIGNAL_IN ( in_COMMIT_EVENT_ADDRESS_EPCR ,"ADDRESS_EPCR" ,Taddress_t ,_param->_size_instruction_address ); 141 141 ALLOC_SIGNAL_IN ( in_COMMIT_EVENT_ADDRESS_EEAR_VAL ,"ADDRESS_EEAR_VAL" ,Tcontrol_t ,1 ); 142 ALLOC_SIGNAL_IN ( in_COMMIT_EVENT_ADDRESS_EEAR ,"ADDRESS_EEAR" ,T address_t ,_param->_size_instruction_address);142 ALLOC_SIGNAL_IN ( in_COMMIT_EVENT_ADDRESS_EEAR ,"ADDRESS_EEAR" ,Tgeneral_data_t ,_param->_size_general_data ); 143 143 } 144 144 … … 580 580 COMPONENT_MAP(_component,src ,"out_BRANCH_EVENT_"+toString(i)+"_ADDRESS_DEST" , 581 581 dest, "in_BRANCH_EVENT_"+toString(i)+"_ADDRESS_DEST" ); 582 } 583 584 // ~~~~~[ Interface : "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 585 for (uint32_t i=0; i<_param->_nb_context; ++i) 586 { 587 dest = _name+"_glue"; 588 #ifdef POSITION 589 _component->interface_map (src ,"event_"+toString(i), 590 dest,"event_"+toString(i)); 591 #endif 592 COMPONENT_MAP(_component,src , "in_EVENT_"+toString(i)+ "_VAL" , 593 dest,"out_EVENT_"+toString(i)+"_PREDICTION_UNIT_VAL" ); 594 COMPONENT_MAP(_component,src ,"out_EVENT_"+toString(i)+ "_ACK" , 595 dest, "in_EVENT_"+toString(i)+"_PREDICTION_UNIT_ACK" ); 596 COMPONENT_MAP(_component,src , "in_EVENT_"+toString(i)+ "_TYPE" , 597 dest,"out_EVENT_"+toString(i)+"_PREDICTION_UNIT_TYPE" ); 598 if (_param->_have_port_depth) 599 COMPONENT_MAP(_component,src , "in_EVENT_"+toString(i)+ "_DEPTH", 600 dest,"out_EVENT_"+toString(i)+"_PREDICTION_UNIT_DEPTH"); 582 601 } 583 602 … … 967 986 COMPONENT_MAP(_component,src ,"out_EVENT_"+toString(i)+ "_IS_DS_TAKE" , 968 987 dest, "in_EVENT_"+toString(i)+"_CONTEXT_STATE_IS_DS_TAKE" ); 988 COMPONENT_MAP(_component,src ,"out_EVENT_"+toString(i)+ "_TYPE" , 989 dest, "in_EVENT_"+toString(i)+"_CONTEXT_STATE_TYPE" ); 990 if (_param->_have_port_depth) 991 COMPONENT_MAP(_component,src ,"out_EVENT_"+toString(i)+ "_DEPTH" , 992 dest, "in_EVENT_"+toString(i)+"_CONTEXT_STATE_DEPTH" ); 969 993 } 970 994 … … 1129 1153 // in_EVENT_IFETCH_UNIT_ACK - component_ifetch_unit 1130 1154 // out_EVENT_IFETCH_UNIT_ADDRESS - component_ifetch_unit 1131 // in_EVENT_IFETCH_UNIT_ADDRESS_NEXT - component_ifetch_unit1155 // out_EVENT_IFETCH_UNIT_ADDRESS_NEXT - component_ifetch_unit 1132 1156 // out_EVENT_IFETCH_UNIT_ADDRESS_NEXT_VAL - component_ifetch_unit 1133 1157 // in_EVENT_IFETCH_UNIT_IS_DS_TAKE - component_ifetch_unit 1158 // out_EVENT_PREDICTION_UNIT_VAL - component_prediction_unit 1159 // in_EVENT_PREDICTION_UNIT_ACK - component_prediction_unit 1160 // out_EVENT_PREDICTION_UNIT_TYPE - component_prediction_unit 1161 // out_EVENT_PREDICTION_UNIT_DEPTH - component_prediction_unit 1134 1162 // in_EVENT_CONTEXT_STATE_VAL - component_context_state 1135 1163 // out_EVENT_CONTEXT_STATE_ACK - component_context_state 1136 1164 // in_EVENT_CONTEXT_STATE_ADDRESS - component_context_state 1137 1165 // in_EVENT_CONTEXT_STATE_ADDRESS_NEXT - component_context_state 1138 // out_EVENT_CONTEXT_STATE_ADDRESS_NEXT_VAL - component_context_state1166 // in_EVENT_CONTEXT_STATE_ADDRESS_NEXT_VAL - component_context_state 1139 1167 // in_EVENT_CONTEXT_STATE_IS_DS_TAKE - component_context_state 1168 // in_EVENT_CONTEXT_STATE_TYPE - component_context_state 1169 // in_EVENT_CONTEXT_STATE_DEPTH - component_context_state 1140 1170 1141 1171 // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/src/test.cpp
r88 r97 68 68 ALLOC2_SC_SIGNAL( in_INSERT_NO_EXECUTE ," in_INSERT_NO_EXECUTE ",Tcontrol_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 69 69 ALLOC2_SC_SIGNAL( in_INSERT_IS_DELAY_SLOT ," in_INSERT_IS_DELAY_SLOT ",Tcontrol_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 70 ALLOC2_SC_SIGNAL( in_INSERT_ADDRESS ," in_INSERT_ADDRESS ",T general_data_t,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);70 ALLOC2_SC_SIGNAL( in_INSERT_ADDRESS ," in_INSERT_ADDRESS ",Taddress_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 71 71 ALLOC2_SC_SIGNAL( in_INSERT_EXCEPTION ," in_INSERT_EXCEPTION ",Texception_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 72 72 ALLOC2_SC_SIGNAL( in_INSERT_EXCEPTION_USE ," in_INSERT_EXCEPTION_USE ",Texception_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); … … 123 123 ALLOC1_SC_SIGNAL( in_COMMIT_EXCEPTION ," in_COMMIT_EXCEPTION ",Texception_t ,_param->_nb_inst_commit); 124 124 ALLOC1_SC_SIGNAL( in_COMMIT_NO_SEQUENCE ," in_COMMIT_NO_SEQUENCE ",Tcontrol_t ,_param->_nb_inst_commit); 125 ALLOC1_SC_SIGNAL( in_COMMIT_ADDRESS ," in_COMMIT_ADDRESS ",T general_data_t,_param->_nb_inst_commit);125 ALLOC1_SC_SIGNAL( in_COMMIT_ADDRESS ," in_COMMIT_ADDRESS ",Taddress_t ,_param->_nb_inst_commit); 126 126 ALLOC1_SC_SIGNAL(out_COMMIT_NUM_REG_RD ,"out_COMMIT_NUM_REG_RD ",Tgeneral_address_t,_param->_nb_inst_commit); 127 127 ALLOC1_SC_SIGNAL(out_REEXECUTE_VAL ,"out_REEXECUTE_VAL ",Tcontrol_t ,_param->_nb_inst_reexecute); … … 151 151 ALLOC_SC_SIGNAL (out_UPDATE_ADDRESS_EPCR ,"out_UPDATE_ADDRESS_EPCR ",Taddress_t ); 152 152 ALLOC_SC_SIGNAL (out_UPDATE_ADDRESS_EEAR_VAL ,"out_UPDATE_ADDRESS_EEAR_VAL ",Tcontrol_t ); 153 ALLOC_SC_SIGNAL (out_UPDATE_ADDRESS_EEAR ,"out_UPDATE_ADDRESS_EEAR ",T address_t);153 ALLOC_SC_SIGNAL (out_UPDATE_ADDRESS_EEAR ,"out_UPDATE_ADDRESS_EEAR ",Tgeneral_data_t ); 154 154 155 155 ALLOC2_SC_SIGNAL( in_EVENT_VAL ," in_EVENT_VAL ",Tcontrol_t,_param->_nb_front_end,_param->_nb_context[it1]); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h
r88 r97 82 82 public : SC_IN (Tcontrol_t ) *** in_INSERT_NO_EXECUTE ;//[nb_rename_unit][nb_inst_insert] 83 83 public : SC_IN (Tcontrol_t ) *** in_INSERT_IS_DELAY_SLOT ;//[nb_rename_unit][nb_inst_insert] 84 public : SC_IN (T general_data_t) *** in_INSERT_ADDRESS ;//[nb_rename_unit][nb_inst_insert]84 public : SC_IN (Taddress_t ) *** in_INSERT_ADDRESS ;//[nb_rename_unit][nb_inst_insert] 85 85 public : SC_IN (Texception_t ) *** in_INSERT_EXCEPTION ;//[nb_rename_unit][nb_inst_insert] 86 86 public : SC_IN (Texception_t ) *** in_INSERT_EXCEPTION_USE ;//[nb_rename_unit][nb_inst_insert] … … 141 141 public : SC_IN (Texception_t ) ** in_COMMIT_EXCEPTION ;//[nb_inst_commit] 142 142 public : SC_IN (Tcontrol_t ) ** in_COMMIT_NO_SEQUENCE ;//[nb_inst_commit] 143 public : SC_IN (T general_data_t) ** in_COMMIT_ADDRESS ;//[nb_inst_commit]143 public : SC_IN (Taddress_t ) ** in_COMMIT_ADDRESS ;//[nb_inst_commit] 144 144 public : SC_OUT(Tgeneral_address_t ) ** out_COMMIT_NUM_REG_RD ;//[nb_inst_commit] 145 145 … … 175 175 public : SC_OUT(Taddress_t ) * out_UPDATE_ADDRESS_EPCR ; 176 176 public : SC_OUT(Tcontrol_t ) * out_UPDATE_ADDRESS_EEAR_VAL ; 177 public : SC_OUT(T address_t) * out_UPDATE_ADDRESS_EEAR ;177 public : SC_OUT(Tgeneral_data_t ) * out_UPDATE_ADDRESS_EEAR ; 178 178 179 179 // ~~~~~[ Interface "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_allocation.cpp
r88 r97 71 71 _ALLOC2_SIGNAL_IN ( in_INSERT_NO_EXECUTE ,"no_execute" ,Tcontrol_t ,1 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 72 72 _ALLOC2_SIGNAL_IN ( in_INSERT_IS_DELAY_SLOT ,"is_delay_slot" ,Tcontrol_t ,1 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 73 _ALLOC2_SIGNAL_IN ( in_INSERT_ADDRESS ,"address" ,T general_data_t,_param->_size_instruction_address ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);73 _ALLOC2_SIGNAL_IN ( in_INSERT_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 74 74 _ALLOC2_SIGNAL_IN ( in_INSERT_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 75 75 _ALLOC2_SIGNAL_IN ( in_INSERT_EXCEPTION_USE ,"exception_use" ,Texception_t ,_param->_size_exception ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); … … 138 138 ALLOC1_SIGNAL_IN ( in_COMMIT_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception ); 139 139 ALLOC1_SIGNAL_IN ( in_COMMIT_NO_SEQUENCE ,"no_sequence",Tcontrol_t ,1 ); 140 ALLOC1_SIGNAL_IN ( in_COMMIT_ADDRESS ,"address" ,T general_data_t,_param->_size_instruction_address);140 ALLOC1_SIGNAL_IN ( in_COMMIT_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address); 141 141 // ALLOC1_SIGNAL_OUT(out_COMMIT_NUM_REG_RD ,"num_reg_rd" ,Tgeneral_address_t,_param->_size_general_register+_param->_size_rename_unit_id); 142 142 ALLOC1_SIGNAL_OUT(out_COMMIT_NUM_REG_RD ,"num_reg_rd" ,Tgeneral_address_t,_param->_size_general_register); … … 185 185 ALLOC_SIGNAL_OUT(out_UPDATE_ADDRESS_EPCR ,"address_epcr" ,Taddress_t ,_param->_size_instruction_address); 186 186 ALLOC_SIGNAL_OUT(out_UPDATE_ADDRESS_EEAR_VAL ,"address_eear_val",Tcontrol_t ,1); 187 ALLOC_SIGNAL_OUT(out_UPDATE_ADDRESS_EEAR ,"address_eear" ,T address_t ,_param->_size_instruction_address);187 ALLOC_SIGNAL_OUT(out_UPDATE_ADDRESS_EEAR ,"address_eear" ,Tgeneral_data_t ,_param->_size_general_data); 188 188 } 189 189 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp
r88 r97 75 75 log_printf(TRACE,Commit_unit,FUNCTION," * front_end_id : %d",front_end_id); 76 76 log_printf(TRACE,Commit_unit,FUNCTION," * context_id : %d",context_id); 77 log_printf(TRACE,Commit_unit,FUNCTION," * type : %s",toString _type(type).c_str());77 log_printf(TRACE,Commit_unit,FUNCTION," * type : %s",toString(type).c_str()); 78 78 log_printf(TRACE,Commit_unit,FUNCTION," * operation : %d",operation ); 79 79 log_printf(TRACE,Commit_unit,FUNCTION," * exception : %d",exception ); … … 478 478 it++) 479 479 { 480 log_printf(TRACE,Commit_unit,FUNCTION," [% d] %.8x (%.8x) %s - ptr :%d",480 log_printf(TRACE,Commit_unit,FUNCTION," [%.4d] %.4d %.4d %.4d %.4d, %.3d %.3d, %.8x %.1d, %.1d %.4d, %.1d %.4d, %s - %d", 481 481 x, 482 (*it)->address, 483 (*it)->address<<2, 484 toString((*it)->state).c_str(), 485 (*it)->ptr); 482 (*it)->front_end_id , 483 (*it)->context_id , 484 (*it)->rename_unit_id , 485 (*it)->depth , 486 (*it)->type , 487 (*it)->operation , 488 (*it)->address , 489 (*it)->is_delay_slot , 490 (*it)->use_store_queue , 491 (*it)->store_queue_ptr_write , 492 (*it)->use_load_queue , 493 (*it)->load_queue_ptr_write , 494 toString((*it)->state).c_str() , 495 (*it)->ptr ); 496 log_printf(TRACE,Commit_unit,FUNCTION," %.1d %.5d %.6d, %.1d %.5d %.6d, %.1d %.5d %.6d, %.1d %.1d %.6d %.6d, %.1d %.1d %.6d %.6d ", 497 (*it)->read_ra , 498 (*it)->num_reg_ra_log , 499 (*it)->num_reg_ra_phy , 500 (*it)->read_rb , 501 (*it)->num_reg_rb_log , 502 (*it)->num_reg_rb_phy , 503 (*it)->read_rc , 504 (*it)->num_reg_rc_log , 505 (*it)->num_reg_rc_phy , 506 (*it)->write_rd , 507 (*it)->num_reg_rd_log , 508 (*it)->num_reg_rd_phy_old , 509 (*it)->num_reg_rd_phy_new , 510 (*it)->write_re , 511 (*it)->num_reg_re_log , 512 (*it)->num_reg_re_phy_old , 513 (*it)->num_reg_re_phy_new ); 514 515 log_printf(TRACE,Commit_unit,FUNCTION," %.2d %.2d %.1d %.1d %.8x %s", 516 (*it)->exception , 517 (*it)->exception_use , 518 (*it)->flags , 519 (*it)->no_sequence , 520 (*it)->data_commit , 521 toString((*it)->event_state).c_str() 522 ); 523 486 524 x++; 487 525 } -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Parameters_msg_error.cpp
r88 r97 78 78 for (uint32_t j=0; j<_nb_type; j++) 79 79 if (not type_present [j]) 80 test.error(toString(_("Rename_unit [%d] can't issue instruction's type \"%s\".\n"),i,toString _type(j).c_str()));80 test.error(toString(_("Rename_unit [%d] can't issue instruction's type \"%s\".\n"),i,toString(j).c_str())); 81 81 } 82 82 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue_allocation.cpp
r88 r97 73 73 ALLOC1_SIGNAL_OUT (out_INSERT_RD_NUM_REG ,"RD_NUM_REG" ,Tgeneral_address_t ,_param->_size_general_register); 74 74 ALLOC1_SIGNAL_OUT (out_INSERT_RE_USE ,"RE_USE" ,Tcontrol_t ,1 ); 75 ALLOC1_SIGNAL_OUT (out_INSERT_RE_NUM_REG ,"RE_NUM_REG" ,Tspecial_address_t ,_param->_size_ general_register);75 ALLOC1_SIGNAL_OUT (out_INSERT_RE_NUM_REG ,"RE_NUM_REG" ,Tspecial_address_t ,_param->_size_special_register); 76 76 } 77 77 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/include/Reexecute_unit.h
r88 r97 80 80 public : SC_IN (Texception_t ) *** in_EXECUTE_LOOP_EXCEPTION ;//[nb_execute_loop][nb_inst_execute] 81 81 public : SC_IN (Tcontrol_t ) *** in_EXECUTE_LOOP_NO_SEQUENCE ;//[nb_execute_loop][nb_inst_execute] 82 public : SC_IN (T general_data_t) *** in_EXECUTE_LOOP_ADDRESS ;//[nb_execute_loop][nb_inst_execute]82 public : SC_IN (Taddress_t ) *** in_EXECUTE_LOOP_ADDRESS ;//[nb_execute_loop][nb_inst_execute] 83 83 public : SC_IN (Tgeneral_data_t ) *** in_EXECUTE_LOOP_DATA ;//[nb_execute_loop][nb_inst_execute] 84 84 … … 95 95 public : SC_OUT(Texception_t ) ** out_COMMIT_EXCEPTION ;//[nb_inst_commit] 96 96 public : SC_OUT(Tcontrol_t ) ** out_COMMIT_NO_SEQUENCE ;//[nb_inst_commit] 97 public : SC_OUT(T general_data_t) ** out_COMMIT_ADDRESS ;//[nb_inst_commit]97 public : SC_OUT(Taddress_t ) ** out_COMMIT_ADDRESS ;//[nb_inst_commit] 98 98 public : SC_IN (Tgeneral_address_t ) ** in_COMMIT_NUM_REG_RD ;//[nb_inst_commit] 99 99 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Parameters.cpp
r88 r97 71 71 if (is_toplevel) 72 72 { 73 _size_instruction_address = size_general_data-2 ; 73 74 _size_context_id = size_context_id ; 74 75 _size_front_end_id = size_front_end_id ; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_allocation.cpp
r88 r97 70 70 _ALLOC2_SIGNAL_IN ( in_EXECUTE_LOOP_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); 71 71 _ALLOC2_SIGNAL_IN ( in_EXECUTE_LOOP_NO_SEQUENCE ,"no_sequence" ,Tcontrol_t ,1 ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); 72 _ALLOC2_SIGNAL_IN ( in_EXECUTE_LOOP_ADDRESS ,"address" ,T general_data_t ,_param->_size_general_data,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]);72 _ALLOC2_SIGNAL_IN ( in_EXECUTE_LOOP_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); 73 73 _ALLOC2_SIGNAL_IN ( in_EXECUTE_LOOP_DATA ,"data" ,Tgeneral_data_t ,_param->_size_general_data,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); 74 74 } … … 89 89 ALLOC1_SIGNAL_OUT(out_COMMIT_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception ); 90 90 ALLOC1_SIGNAL_OUT(out_COMMIT_NO_SEQUENCE ,"no_sequence" ,Tcontrol_t ,1 ); 91 ALLOC1_SIGNAL_OUT(out_COMMIT_ADDRESS ,"address" ,T general_data_t ,_param->_size_general_data);91 ALLOC1_SIGNAL_OUT(out_COMMIT_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address); 92 92 ALLOC1_SIGNAL_IN ( in_COMMIT_NUM_REG_RD ,"num_reg_rd" ,Tgeneral_address_t ,_param->_size_general_register); 93 93 } -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_genMealy_commit.cpp
r88 r97 58 58 // Need spr_acces / reexecute ? 59 59 Texception_t exception = PORT_READ(in_EXECUTE_LOOP_EXCEPTION [x][y]); 60 T general_data_taddress = PORT_READ(in_EXECUTE_LOOP_ADDRESS [x][y]);60 Taddress_t address = PORT_READ(in_EXECUTE_LOOP_ADDRESS [x][y]); 61 61 Tcontrol_t spr_access = ((exception == EXCEPTION_ALU_SPR_ACCESS_MUST_READ ) or 62 62 (exception == EXCEPTION_ALU_SPR_ACCESS_MUST_WRITE)); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/src/Load_Store_pointer_unit_allocation.cpp
r88 r97 80 80 // ALLOC1_SIGNAL_IN ( in_RETIRE_TYPE ,"type" ,Ttype_t ,_param->_size_type ); 81 81 // ALLOC1_SIGNAL_IN ( in_RETIRE_OPERATION ,"operation" ,Toperation_t,_param->_size_operation ); 82 ALLOC1_SIGNAL_IN ( in_RETIRE_USE_STORE_QUEUE ,"use_store_queue" ,Tcontrol_t , _param->_size_operation);83 ALLOC1_SIGNAL_IN ( in_RETIRE_USE_LOAD_QUEUE ,"use_load_queue" ,Tcontrol_t , _param->_size_operation);82 ALLOC1_SIGNAL_IN ( in_RETIRE_USE_STORE_QUEUE ,"use_store_queue" ,Tcontrol_t ,1); 83 ALLOC1_SIGNAL_IN ( in_RETIRE_USE_LOAD_QUEUE ,"use_load_queue" ,Tcontrol_t ,1); 84 84 ALLOC1_SIGNAL_IN ( in_RETIRE_STORE_QUEUE_PTR_WRITE,"store_queue_ptr_write",Tlsq_ptr_t ,_param->_size_store_queue_ptr); 85 85 ALLOC1_SIGNAL_IN ( in_RETIRE_LOAD_QUEUE_PTR_WRITE ,"load_queue_ptr_write" ,Tlsq_ptr_t ,_param->_size_load_queue_ptr ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_genMealy_rename.cpp
r88 r97 27 27 28 28 for (uint32_t i=0; i<_param->_nb_inst_insert; i++) 29 if (PORT_READ(in_RENAME_VAL [i])) // not in sensitive list : it's to have valide value to array access 29 30 { 30 31 Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_RENAME_FRONT_END_ID [i]):0; 31 32 Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_RENAME_CONTEXT_ID [i]):0; 32 33 33 PORT_WRITE(out_RENAME_NUM_REG_RA_PHY [i], rat_gpr[front_end_id][context_id][PORT_READ(in_RENAME_NUM_REG_RA_LOG [i])]); 34 PORT_WRITE(out_RENAME_NUM_REG_RB_PHY [i], rat_gpr[front_end_id][context_id][PORT_READ(in_RENAME_NUM_REG_RB_LOG [i])]); 35 PORT_WRITE(out_RENAME_NUM_REG_RC_PHY [i], rat_spr[front_end_id][context_id][PORT_READ(in_RENAME_NUM_REG_RC_LOG [i])]); 36 PORT_WRITE(out_RENAME_NUM_REG_RD_PHY_OLD [i], rat_gpr[front_end_id][context_id][PORT_READ(in_RENAME_NUM_REG_RD_LOG [i])]); 37 PORT_WRITE(out_RENAME_NUM_REG_RE_PHY_OLD [i], rat_spr[front_end_id][context_id][PORT_READ(in_RENAME_NUM_REG_RE_LOG [i])]); 34 Tgeneral_address_t num_reg_ra_log = PORT_READ(in_RENAME_NUM_REG_RA_LOG [i]); //%_param->_nb_general_register; 35 Tgeneral_address_t num_reg_rb_log = PORT_READ(in_RENAME_NUM_REG_RB_LOG [i]); //%_param->_nb_general_register; 36 Tspecial_address_t num_reg_rc_log = PORT_READ(in_RENAME_NUM_REG_RC_LOG [i]); //%_param->_nb_special_register; 37 Tgeneral_address_t num_reg_rd_log = PORT_READ(in_RENAME_NUM_REG_RD_LOG [i]); //%_param->_nb_general_register; 38 Tspecial_address_t num_reg_re_log = PORT_READ(in_RENAME_NUM_REG_RE_LOG [i]); //%_param->_nb_special_register; 39 40 PORT_WRITE(out_RENAME_NUM_REG_RA_PHY [i], rat_gpr[front_end_id][context_id][num_reg_ra_log]); 41 PORT_WRITE(out_RENAME_NUM_REG_RB_PHY [i], rat_gpr[front_end_id][context_id][num_reg_rb_log]); 42 PORT_WRITE(out_RENAME_NUM_REG_RC_PHY [i], rat_spr[front_end_id][context_id][num_reg_rc_log]); 43 PORT_WRITE(out_RENAME_NUM_REG_RD_PHY_OLD [i], rat_gpr[front_end_id][context_id][num_reg_rd_log]); 44 PORT_WRITE(out_RENAME_NUM_REG_RE_PHY_OLD [i], rat_spr[front_end_id][context_id][num_reg_re_log]); 45 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"yo6"); 38 46 } 39 47 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/SelfTest/src/test.cpp
r88 r97 59 59 ALLOC2_SC_SIGNAL( in_RENAME_IN_NO_EXECUTE ," in_RENAME_IN_NO_EXECUTE ",Tcontrol_t ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); 60 60 ALLOC2_SC_SIGNAL( in_RENAME_IN_IS_DELAY_SLOT ," in_RENAME_IN_IS_DELAY_SLOT ",Tcontrol_t ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); 61 ALLOC2_SC_SIGNAL( in_RENAME_IN_ADDRESS ," in_RENAME_IN_ADDRESS ",T general_data_t,_param->_nb_front_end, _param->_nb_inst_decod[it1]);61 ALLOC2_SC_SIGNAL( in_RENAME_IN_ADDRESS ," in_RENAME_IN_ADDRESS ",Taddress_t ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); 62 62 ALLOC2_SC_SIGNAL( in_RENAME_IN_HAS_IMMEDIAT ," in_RENAME_IN_HAS_IMMEDIAT ",Tcontrol_t ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); 63 63 ALLOC2_SC_SIGNAL( in_RENAME_IN_IMMEDIAT ," in_RENAME_IN_IMMEDIAT ",Tgeneral_data_t ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); … … 84 84 ALLOC1_SC_SIGNAL(out_RENAME_OUT_NO_EXECUTE ,"out_RENAME_OUT_NO_EXECUTE ",Tcontrol_t ,_param->_nb_inst_rename); 85 85 ALLOC1_SC_SIGNAL(out_RENAME_OUT_IS_DELAY_SLOT,"out_RENAME_OUT_IS_DELAY_SLOT",Tcontrol_t ,_param->_nb_inst_rename); 86 ALLOC1_SC_SIGNAL(out_RENAME_OUT_ADDRESS ,"out_RENAME_OUT_ADDRESS ",T general_data_t,_param->_nb_inst_rename);86 ALLOC1_SC_SIGNAL(out_RENAME_OUT_ADDRESS ,"out_RENAME_OUT_ADDRESS ",Taddress_t ,_param->_nb_inst_rename); 87 87 ALLOC1_SC_SIGNAL(out_RENAME_OUT_HAS_IMMEDIAT ,"out_RENAME_OUT_HAS_IMMEDIAT ",Tcontrol_t ,_param->_nb_inst_rename); 88 88 ALLOC1_SC_SIGNAL(out_RENAME_OUT_IMMEDIAT ,"out_RENAME_OUT_IMMEDIAT ",Tgeneral_data_t ,_param->_nb_inst_rename); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/include/Rename_select.h
r88 r97 76 76 public : SC_IN (Tcontrol_t ) *** in_RENAME_IN_NO_EXECUTE ;//[nb_front_end][nb_inst_decod] 77 77 public : SC_IN (Tcontrol_t ) *** in_RENAME_IN_IS_DELAY_SLOT ;//[nb_front_end][nb_inst_decod] 78 public : SC_IN (T general_data_t) *** in_RENAME_IN_ADDRESS ;//[nb_front_end][nb_inst_decod]78 public : SC_IN (Taddress_t ) *** in_RENAME_IN_ADDRESS ;//[nb_front_end][nb_inst_decod] 79 79 public : SC_IN (Tcontrol_t ) *** in_RENAME_IN_HAS_IMMEDIAT ;//[nb_front_end][nb_inst_decod] 80 80 public : SC_IN (Tgeneral_data_t ) *** in_RENAME_IN_IMMEDIAT ;//[nb_front_end][nb_inst_decod] … … 102 102 public : SC_OUT(Tcontrol_t ) ** out_RENAME_OUT_NO_EXECUTE ;//[nb_inst_rename] 103 103 public : SC_OUT(Tcontrol_t ) ** out_RENAME_OUT_IS_DELAY_SLOT;//[nb_inst_rename] 104 public : SC_OUT(T general_data_t) ** out_RENAME_OUT_ADDRESS ;//[nb_inst_rename]104 public : SC_OUT(Taddress_t ) ** out_RENAME_OUT_ADDRESS ;//[nb_inst_rename] 105 105 public : SC_OUT(Tcontrol_t ) ** out_RENAME_OUT_HAS_IMMEDIAT ;//[nb_inst_rename] 106 106 public : SC_OUT(Tgeneral_data_t ) ** out_RENAME_OUT_IMMEDIAT ;//[nb_inst_rename] -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/src/Parameters.cpp
r88 r97 50 50 if (is_toplevel) 51 51 { 52 _size_general_data = size_general_data ; 53 _size_depth = log2(max_branch_speculated); 54 _size_front_end_id = log2(_nb_front_end); 55 _size_context_id = log2(max<uint32_t>(_nb_context,_nb_front_end)); 56 57 _have_port_front_end_id= _size_front_end_id > 0; 58 _have_port_context_id = _size_context_id > 0; 59 _have_port_depth = _size_depth > 0; 52 _size_instruction_address = size_general_data-2; 53 _size_general_data = size_general_data ; 54 _size_depth = log2(max_branch_speculated); 55 _size_front_end_id = log2(_nb_front_end); 56 _size_context_id = log2(max<uint32_t>(_nb_context,_nb_front_end)); 57 58 _have_port_front_end_id = _size_front_end_id > 0; 59 _have_port_context_id = _size_context_id > 0; 60 _have_port_depth = _size_depth > 0; 60 61 61 62 copy(); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/src/Rename_select_allocation.cpp
r88 r97 69 69 _ALLOC2_SIGNAL_IN ( in_RENAME_IN_NO_EXECUTE ,"no_execute" ,Tcontrol_t ,1 , _param->_nb_front_end, _param->_nb_inst_decod[it1]); 70 70 _ALLOC2_SIGNAL_IN ( in_RENAME_IN_IS_DELAY_SLOT ,"is_delay_slot",Tcontrol_t ,1 , _param->_nb_front_end, _param->_nb_inst_decod[it1]); 71 _ALLOC2_SIGNAL_IN ( in_RENAME_IN_ADDRESS ,"address" ,T general_data_t ,_param->_size_general_data, _param->_nb_front_end, _param->_nb_inst_decod[it1]);71 _ALLOC2_SIGNAL_IN ( in_RENAME_IN_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address , _param->_nb_front_end, _param->_nb_inst_decod[it1]); 72 72 _ALLOC2_SIGNAL_IN ( in_RENAME_IN_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t ,1 , _param->_nb_front_end, _param->_nb_inst_decod[it1]); 73 73 _ALLOC2_SIGNAL_IN ( in_RENAME_IN_IMMEDIAT ,"immediat" ,Tgeneral_data_t ,_param->_size_general_data , _param->_nb_front_end, _param->_nb_inst_decod[it1]); … … 82 82 _ALLOC2_SIGNAL_IN ( in_RENAME_IN_WRITE_RE ,"write_re" ,Tcontrol_t ,1 , _param->_nb_front_end, _param->_nb_inst_decod[it1]); 83 83 _ALLOC2_SIGNAL_IN ( in_RENAME_IN_NUM_REG_RE ,"num_reg_re" ,Tspecial_address_t,_param->_size_special_register_logic, _param->_nb_front_end, _param->_nb_inst_decod[it1]); 84 _ALLOC2_SIGNAL_IN ( in_RENAME_IN_EXCEPTION_USE ,"exception_use",Texception_t ,_param->_size_exception 84 _ALLOC2_SIGNAL_IN ( in_RENAME_IN_EXCEPTION_USE ,"exception_use",Texception_t ,_param->_size_exception_use , _param->_nb_front_end, _param->_nb_inst_decod[it1]); 85 85 _ALLOC2_SIGNAL_IN ( in_RENAME_IN_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception , _param->_nb_front_end, _param->_nb_inst_decod[it1]); 86 86 } … … 99 99 ALLOC1_SIGNAL_OUT(out_RENAME_OUT_NO_EXECUTE ,"no_execute" ,Tcontrol_t ,1 ); 100 100 ALLOC1_SIGNAL_OUT(out_RENAME_OUT_IS_DELAY_SLOT ,"is_delay_slot",Tcontrol_t ,1 ); 101 ALLOC1_SIGNAL_OUT(out_RENAME_OUT_ADDRESS ,"address" ,T general_data_t ,_param->_size_general_data);101 ALLOC1_SIGNAL_OUT(out_RENAME_OUT_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address ); 102 102 ALLOC1_SIGNAL_OUT(out_RENAME_OUT_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t ,1 ); 103 103 ALLOC1_SIGNAL_OUT(out_RENAME_OUT_IMMEDIAT ,"immediat" ,Tgeneral_data_t ,_param->_size_general_data ); … … 112 112 ALLOC1_SIGNAL_OUT(out_RENAME_OUT_WRITE_RE ,"write_re" ,Tcontrol_t ,1 ); 113 113 ALLOC1_SIGNAL_OUT(out_RENAME_OUT_NUM_REG_RE ,"num_reg_re" ,Tspecial_address_t,_param->_size_special_register_logic); 114 ALLOC1_SIGNAL_OUT(out_RENAME_OUT_EXCEPTION_USE ,"exception_use",Texception_t ,_param->_size_exception 114 ALLOC1_SIGNAL_OUT(out_RENAME_OUT_EXCEPTION_USE ,"exception_use",Texception_t ,_param->_size_exception_use ); 115 115 ALLOC1_SIGNAL_OUT(out_RENAME_OUT_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception ); 116 116 } -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/include/Rename_unit.h
r88 r97 78 78 public : SC_IN (Tcontrol_t ) *** in_RENAME_IN_NO_EXECUTE ;//[nb_front_end][nb_inst_decod] 79 79 public : SC_IN (Tcontrol_t ) *** in_RENAME_IN_IS_DELAY_SLOT ;//[nb_front_end][nb_inst_decod] 80 public : SC_IN (T general_data_t) *** in_RENAME_IN_ADDRESS ;//[nb_front_end][nb_inst_decod]80 public : SC_IN (Taddress_t ) *** in_RENAME_IN_ADDRESS ;//[nb_front_end][nb_inst_decod] 81 81 public : SC_IN (Tcontrol_t ) *** in_RENAME_IN_HAS_IMMEDIAT ;//[nb_front_end][nb_inst_decod] 82 82 public : SC_IN (Tgeneral_data_t ) *** in_RENAME_IN_IMMEDIAT ;//[nb_front_end][nb_inst_decod] … … 104 104 public : SC_OUT(Tcontrol_t ) ** out_INSERT_NO_EXECUTE ;//[nb_inst_insert] 105 105 public : SC_OUT(Tcontrol_t ) ** out_INSERT_IS_DELAY_SLOT ;//[nb_inst_insert] 106 public : SC_OUT(T general_data_t) ** out_INSERT_ADDRESS ;//[nb_inst_insert]106 public : SC_OUT(Taddress_t ) ** out_INSERT_ADDRESS ;//[nb_inst_insert] 107 107 public : SC_OUT(Tcontrol_t ) ** out_INSERT_HAS_IMMEDIAT ;//[nb_inst_insert] 108 108 public : SC_OUT(Tgeneral_data_t ) ** out_INSERT_IMMEDIAT ;//[nb_inst_insert] -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Parameters.cpp
r88 r97 119 119 if (is_toplevel) 120 120 { 121 _size_instruction_address = size_general_data-2; 121 122 _size_front_end_id = log2(_nb_front_end); 122 123 _size_context_id = log2(max<uint32_t>(_nb_context,_nb_front_end)); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Rename_unit_allocation.cpp
r88 r97 69 69 _ALLOC2_SIGNAL_IN ( in_RENAME_IN_NO_EXECUTE ,"no_execute" ,Tcontrol_t ,1 , _param->_nb_front_end, _param->_nb_inst_decod[it1]); 70 70 _ALLOC2_SIGNAL_IN ( in_RENAME_IN_IS_DELAY_SLOT ,"is_delay_slot",Tcontrol_t ,1 , _param->_nb_front_end, _param->_nb_inst_decod[it1]); 71 _ALLOC2_SIGNAL_IN ( in_RENAME_IN_ADDRESS ,"address" ,T general_data_t ,_param->_size_general_data, _param->_nb_front_end, _param->_nb_inst_decod[it1]);71 _ALLOC2_SIGNAL_IN ( in_RENAME_IN_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address , _param->_nb_front_end, _param->_nb_inst_decod[it1]); 72 72 _ALLOC2_SIGNAL_IN ( in_RENAME_IN_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t ,1 , _param->_nb_front_end, _param->_nb_inst_decod[it1]); 73 73 _ALLOC2_SIGNAL_IN ( in_RENAME_IN_IMMEDIAT ,"immediat" ,Tgeneral_data_t ,_param->_size_general_data , _param->_nb_front_end, _param->_nb_inst_decod[it1]); … … 99 99 ALLOC1_SIGNAL_OUT(out_INSERT_NO_EXECUTE ,"no_execute" ,Tcontrol_t ,1 ); 100 100 ALLOC1_SIGNAL_OUT(out_INSERT_IS_DELAY_SLOT ,"is_delay_slot" ,Tcontrol_t ,1 ); 101 ALLOC1_SIGNAL_OUT(out_INSERT_ADDRESS ,"address" ,T general_data_t ,_param->_size_general_data);101 ALLOC1_SIGNAL_OUT(out_INSERT_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address ); 102 102 ALLOC1_SIGNAL_OUT(out_INSERT_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t ,1 ); 103 103 ALLOC1_SIGNAL_OUT(out_INSERT_IMMEDIAT ,"immediat" ,Tgeneral_data_t ,_param->_size_general_data ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/src/test.cpp
r88 r97 57 57 ALLOC2_SC_SIGNAL( in_RENAME_NO_EXECUTE ," in_RENAME_NO_EXECUTE ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); 58 58 ALLOC2_SC_SIGNAL( in_RENAME_IS_DELAY_SLOT ," in_RENAME_IS_DELAY_SLOT ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); 59 ALLOC2_SC_SIGNAL( in_RENAME_ADDRESS ," in_RENAME_ADDRESS ",T general_data_t,_param->_nb_front_end,_param->_nb_inst_decod[it1]);59 ALLOC2_SC_SIGNAL( in_RENAME_ADDRESS ," in_RENAME_ADDRESS ",Taddress_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); 60 60 ALLOC2_SC_SIGNAL( in_RENAME_HAS_IMMEDIAT ," in_RENAME_HAS_IMMEDIAT ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); 61 61 ALLOC2_SC_SIGNAL( in_RENAME_IMMEDIAT ," in_RENAME_IMMEDIAT ",Tgeneral_data_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); … … 105 105 ALLOC2_SC_SIGNAL( in_EXECUTE_LOOP_EXCEPTION ," in_EXECUTE_LOOP_EXCEPTION ",Texception_t ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); 106 106 ALLOC2_SC_SIGNAL( in_EXECUTE_LOOP_NO_SEQUENCE ," in_EXECUTE_LOOP_NO_SEQUENCE ",Tcontrol_t ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); 107 ALLOC2_SC_SIGNAL( in_EXECUTE_LOOP_ADDRESS ," in_EXECUTE_LOOP_ADDRESS ",T general_data_t,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]);107 ALLOC2_SC_SIGNAL( in_EXECUTE_LOOP_ADDRESS ," in_EXECUTE_LOOP_ADDRESS ",Taddress_t ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); 108 108 ALLOC2_SC_SIGNAL( in_EXECUTE_LOOP_DATA ," in_EXECUTE_LOOP_DATA ",Tgeneral_data_t ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); 109 109 … … 145 145 ALLOC_SC_SIGNAL (out_COMMIT_EVENT_ADDRESS_EPCR ,"out_COMMIT_EVENT_ADDRESS_EPCR ",Taddress_t ); 146 146 ALLOC_SC_SIGNAL (out_COMMIT_EVENT_ADDRESS_EEAR_VAL ,"out_COMMIT_EVENT_ADDRESS_EEAR_VAL ",Tcontrol_t ); 147 ALLOC_SC_SIGNAL (out_COMMIT_EVENT_ADDRESS_EEAR ,"out_COMMIT_EVENT_ADDRESS_EEAR ",T address_t);147 ALLOC_SC_SIGNAL (out_COMMIT_EVENT_ADDRESS_EEAR ,"out_COMMIT_EVENT_ADDRESS_EEAR ",Tgeneral_data_t ); 148 148 149 149 ALLOC2_SC_SIGNAL( in_EVENT_VAL ," in_EVENT_VAL ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_context[it1]); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_transition.cpp
r88 r97 38 38 throw ERRORMORPHEO(FUNCTION,toString(_("Register [%d][%d] is not implemented.\n"),k,l)); 39 39 #endif 40 //log_printf(TRACE,Special_Register_unit,FUNCTION,"Reset SPR [%d][%d][%d][%d]",i,j,k,l);40 log_printf(TRACE,Special_Register_unit,FUNCTION,"Reset SPR [%d][%d][%d][%d]",i,j,k,l); 41 41 _spr [i][j][k][l]->reset(); 42 42 } -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/include/OOO_Engine.h
r88 r97 77 77 public : SC_IN (Tcontrol_t ) *** in_RENAME_NO_EXECUTE ;//[nb_front_end][nb_inst_decod] 78 78 public : SC_IN (Tcontrol_t ) *** in_RENAME_IS_DELAY_SLOT ;//[nb_front_end][nb_inst_decod] 79 public : SC_IN (T general_data_t) *** in_RENAME_ADDRESS ;//[nb_front_end][nb_inst_decod]79 public : SC_IN (Taddress_t ) *** in_RENAME_ADDRESS ;//[nb_front_end][nb_inst_decod] 80 80 public : SC_IN (Tcontrol_t ) *** in_RENAME_HAS_IMMEDIAT ;//[nb_front_end][nb_inst_decod] 81 81 public : SC_IN (Tgeneral_data_t ) *** in_RENAME_IMMEDIAT ;//[nb_front_end][nb_inst_decod] … … 127 127 public : SC_IN (Texception_t ) *** in_EXECUTE_LOOP_EXCEPTION ;//[nb_execute_loop][nb_inst_execute] 128 128 public : SC_IN (Tcontrol_t ) *** in_EXECUTE_LOOP_NO_SEQUENCE ;//[nb_execute_loop][nb_inst_execute] 129 public : SC_IN (T general_data_t) *** in_EXECUTE_LOOP_ADDRESS ;//[nb_execute_loop][nb_inst_execute]129 public : SC_IN (Taddress_t ) *** in_EXECUTE_LOOP_ADDRESS ;//[nb_execute_loop][nb_inst_execute] 130 130 public : SC_IN (Tgeneral_data_t ) *** in_EXECUTE_LOOP_DATA ;//[nb_execute_loop][nb_inst_execute] 131 131 … … 171 171 public : SC_OUT(Taddress_t ) * out_COMMIT_EVENT_ADDRESS_EPCR ; 172 172 public : SC_OUT(Tcontrol_t ) * out_COMMIT_EVENT_ADDRESS_EEAR_VAL ; 173 public : SC_OUT(T address_t) * out_COMMIT_EVENT_ADDRESS_EEAR ;173 public : SC_OUT(Tgeneral_data_t ) * out_COMMIT_EVENT_ADDRESS_EEAR ; 174 174 175 175 // ~~~~~[ Interface "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_allocation.cpp
r88 r97 66 66 _ALLOC2_SIGNAL_IN ( in_RENAME_NO_EXECUTE ,"NO_EXECUTE" ,Tcontrol_t ,1 ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); 67 67 _ALLOC2_SIGNAL_IN ( in_RENAME_IS_DELAY_SLOT ,"IS_DELAY_SLOT" ,Tcontrol_t ,1 ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); 68 _ALLOC2_SIGNAL_IN ( in_RENAME_ADDRESS ,"ADDRESS" ,T general_data_t,_param->_size_instruction_address ,_param->_nb_front_end,_param->_nb_inst_decod[it1]);68 _ALLOC2_SIGNAL_IN ( in_RENAME_ADDRESS ,"ADDRESS" ,Taddress_t ,_param->_size_instruction_address ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); 69 69 _ALLOC2_SIGNAL_IN ( in_RENAME_HAS_IMMEDIAT ,"HAS_IMMEDIAT" ,Tcontrol_t ,1 ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); 70 70 _ALLOC2_SIGNAL_IN ( in_RENAME_IMMEDIAT ,"IMMEDIAT" ,Tgeneral_data_t ,_param->_size_general_data ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); … … 124 124 _ALLOC2_SIGNAL_IN ( in_EXECUTE_LOOP_EXCEPTION ,"EXCEPTION" ,Texception_t ,_param->_size_exception ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); 125 125 _ALLOC2_SIGNAL_IN ( in_EXECUTE_LOOP_NO_SEQUENCE ,"NO_SEQUENCE" ,Tcontrol_t ,1 ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); 126 _ALLOC2_SIGNAL_IN ( in_EXECUTE_LOOP_ADDRESS ,"ADDRESS" ,T general_data_t ,_param->_size_general_data,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]);126 _ALLOC2_SIGNAL_IN ( in_EXECUTE_LOOP_ADDRESS ,"ADDRESS" ,Taddress_t ,_param->_size_instruction_address ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); 127 127 _ALLOC2_SIGNAL_IN ( in_EXECUTE_LOOP_DATA ,"DATA" ,Tgeneral_data_t ,_param->_size_general_data ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); 128 128 } … … 184 184 ALLOC_SIGNAL_OUT (out_COMMIT_EVENT_ADDRESS_EPCR ,"ADDRESS_EPCR" ,Taddress_t ,_param->_size_instruction_address ); 185 185 ALLOC_SIGNAL_OUT (out_COMMIT_EVENT_ADDRESS_EEAR_VAL ,"ADDRESS_EEAR_VAL" ,Tcontrol_t ,1 ); 186 ALLOC_SIGNAL_OUT (out_COMMIT_EVENT_ADDRESS_EEAR ,"ADDRESS_EEAR" ,T address_t,_param->_size_general_data );186 ALLOC_SIGNAL_OUT (out_COMMIT_EVENT_ADDRESS_EEAR ,"ADDRESS_EEAR" ,Tgeneral_data_t ,_param->_size_general_data ); 187 187 } 188 188 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/Parameters_print.cpp
r88 r97 63 63 for (uint32_t i=0; i<_nb_inst_issue ; ++i) 64 64 for (uint32_t j=0; j<_nb_type; ++j) 65 str+= toString(MSG_INFORMATION)+" * table_issue_type ["+toString(i)+"]["+toString _type(j)+"] : "+toString<bool >(_table_issue_type [i][j] )+"\n";//[nb_inst_issue][nb_type]65 str+= toString(MSG_INFORMATION)+" * table_issue_type ["+toString(i)+"]["+toString(j)+"] : "+toString<bool >(_table_issue_type [i][j] )+"\n";//[nb_inst_issue][nb_type] 66 66 str+= toString(MSG_INFORMATION)+" * size_reexecute_queue : "+toString<uint32_t >(_size_reexecute_queue )+"\n"; 67 67 str+= toString(MSG_INFORMATION)+" * reexecute_priority : "+toString<Tpriority_t >(_reexecute_priority )+"\n"; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/SelfTest/config-min.cfg
r88 r97 7 7 2 2 +1 # ras_size_queue [0] [nb_thread] 8 8 1 1 +1 # upt_size_queue [0] [nb_thread] 9 1 1 +1 # ufpt_size_queue [0] [nb_thread] 9 10 1 1 +1 # nb_decod_bloc 10 11 1 1 +1 # size_decod_queue [0] [nb_decod_bloc] -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/SelfTest/config-w1a.cfg
r88 r97 7 7 4 4 +1 # ras_size_queue [0] [nb_thread] 8 8 4 4 +1 # upt_size_queue [0] [nb_thread] 9 2 2 +1 # ufpt_size_queue [0] [nb_thread] 9 10 1 1 +1 # nb_decod_bloc 10 11 4 4 +1 # size_decod_queue [0] [nb_decod_bloc] -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/SelfTest/src/main.cpp
r88 r97 25 25 err (_(" * ras_size_queue [nb_thread] (uint32_t )\n")); 26 26 err (_(" * upt_size_queue [nb_thread] (uint32_t )\n")); 27 err (_(" * ufpt_size_queue [nb_thread] (uint32_t )\n")); 27 28 28 29 err (_(" * nb_decod_bloc (uint32_t )\n")); … … 183 184 uint32_t * _ras_size_queue ;//[nb_thread] 184 185 uint32_t * _upt_size_queue ;//[nb_thread] 186 uint32_t * _ufpt_size_queue ;//[nb_thread] 185 187 186 188 // Decod_bloc … … 335 337 SELFTEST0(_nb_thread ,uint32_t ,argv,x); 336 338 337 if (argc < static_cast<int>(2+NB_PARAMS+ 4*_nb_thread))339 if (argc < static_cast<int>(2+NB_PARAMS+5*_nb_thread)) 338 340 usage (argc, argv); 339 341 … … 346 348 SELFTEST1(_ras_size_queue ,uint32_t ,argv,x,_nb_thread); 347 349 SELFTEST1(_upt_size_queue ,uint32_t ,argv,x,_nb_thread); 350 SELFTEST1(_ufpt_size_queue ,uint32_t ,argv,x,_nb_thread); 348 351 349 352 // Decod bloc … … 351 354 SELFTEST0(_nb_decod_bloc ,uint32_t ,argv,x); 352 355 353 if (argc < static_cast<int>(2+NB_PARAMS+ 4*_nb_thread+5*_nb_decod_bloc))356 if (argc < static_cast<int>(2+NB_PARAMS+5*_nb_thread+5*_nb_decod_bloc)) 354 357 usage (argc, argv); 355 358 … … 364 367 SELFTEST0(_nb_rename_bloc ,uint32_t ,argv,x); 365 368 366 if (argc < static_cast<int>(2+NB_PARAMS+ 4*_nb_thread+5*_nb_decod_bloc+10*_nb_rename_bloc))369 if (argc < static_cast<int>(2+NB_PARAMS+5*_nb_thread+5*_nb_decod_bloc+10*_nb_rename_bloc)) 367 370 usage (argc, argv); 368 371 … … 382 385 SELFTEST0(_nb_read_bloc ,uint32_t ,argv,x); 383 386 384 if (argc < static_cast<int>(2+NB_PARAMS+ 4*_nb_thread+5*_nb_decod_bloc+10*_nb_rename_bloc+3*_nb_read_bloc))387 if (argc < static_cast<int>(2+NB_PARAMS+5*_nb_thread+5*_nb_decod_bloc+10*_nb_rename_bloc+3*_nb_read_bloc)) 385 388 usage (argc, argv); 386 389 … … 393 396 SELFTEST0(_nb_write_bloc ,uint32_t ,argv,x); 394 397 395 if (argc < static_cast<int>(2+NB_PARAMS+ 4*_nb_thread+5*_nb_decod_bloc+10*_nb_rename_bloc+3*_nb_read_bloc+3*_nb_write_bloc))398 if (argc < static_cast<int>(2+NB_PARAMS+5*_nb_thread+5*_nb_decod_bloc+10*_nb_rename_bloc+3*_nb_read_bloc+3*_nb_write_bloc)) 396 399 usage (argc, argv); 397 400 … … 404 407 SELFTEST0(_nb_load_store_unit ,uint32_t ,argv,x); 405 408 406 if (argc < static_cast<int>(2+NB_PARAMS+ 4*_nb_thread+5*_nb_decod_bloc+10*_nb_rename_bloc+3*_nb_read_bloc+3*_nb_write_bloc+8*_nb_load_store_unit))409 if (argc < static_cast<int>(2+NB_PARAMS+5*_nb_thread+5*_nb_decod_bloc+10*_nb_rename_bloc+3*_nb_read_bloc+3*_nb_write_bloc+8*_nb_load_store_unit)) 407 410 usage (argc, argv); 408 411 … … 421 424 SELFTEST0(_nb_functionnal_unit ,uint32_t ,argv,x); 422 425 423 if (argc < static_cast<int>(2+NB_PARAMS+ 4*_nb_thread+5*_nb_decod_bloc+10*_nb_rename_bloc+3*_nb_read_bloc+3*_nb_write_bloc+8*_nb_load_store_unit+1*_nb_functionnal_unit))426 if (argc < static_cast<int>(2+NB_PARAMS+5*_nb_thread+5*_nb_decod_bloc+10*_nb_rename_bloc+3*_nb_read_bloc+3*_nb_write_bloc+8*_nb_load_store_unit+1*_nb_functionnal_unit)) 424 427 usage (argc, argv); 425 428 … … 464 467 SELFTEST0(_nb_front_end ,uint32_t ,argv,x); 465 468 466 if (argc < static_cast<int>(2+NB_PARAMS+ 4*_nb_thread+5*_nb_decod_bloc+10*_nb_rename_bloc+3*_nb_read_bloc+3*_nb_write_bloc+8*_nb_load_store_unit+1*_nb_functionnal_unit+31*_nb_front_end))469 if (argc < static_cast<int>(2+NB_PARAMS+5*_nb_thread+5*_nb_decod_bloc+10*_nb_rename_bloc+3*_nb_read_bloc+3*_nb_write_bloc+8*_nb_load_store_unit+1*_nb_functionnal_unit+31*_nb_front_end)) 467 470 usage (argc, argv); 468 471 … … 491 494 SELFTEST0(_nb_ooo_engine ,uint32_t ,argv,x); 492 495 493 if (argc < static_cast<int>(2+NB_PARAMS+ 4*_nb_thread+5*_nb_decod_bloc+10*_nb_rename_bloc+3*_nb_read_bloc+3*_nb_write_bloc+8*_nb_load_store_unit+1*_nb_functionnal_unit+31*_nb_front_end+18*_nb_ooo_engine))496 if (argc < static_cast<int>(2+NB_PARAMS+5*_nb_thread+5*_nb_decod_bloc+10*_nb_rename_bloc+3*_nb_read_bloc+3*_nb_write_bloc+8*_nb_load_store_unit+1*_nb_functionnal_unit+31*_nb_front_end+18*_nb_ooo_engine)) 494 497 usage (argc, argv); 495 498 … … 518 521 SELFTEST0(_nb_execute_loop ,uint32_t ,argv,x); 519 522 520 if (argc < static_cast<int>(2+NB_PARAMS+ 4*_nb_thread+5*_nb_decod_bloc+10*_nb_rename_bloc+3*_nb_read_bloc+3*_nb_write_bloc+8*_nb_load_store_unit+1*_nb_functionnal_unit+31*_nb_front_end+18*_nb_ooo_engine+11*_nb_execute_loop))523 if (argc < static_cast<int>(2+NB_PARAMS+5*_nb_thread+5*_nb_decod_bloc+10*_nb_rename_bloc+3*_nb_read_bloc+3*_nb_write_bloc+8*_nb_load_store_unit+1*_nb_functionnal_unit+31*_nb_front_end+18*_nb_ooo_engine+11*_nb_execute_loop)) 521 524 usage (argc, argv); 522 525 … … 536 539 printf(" * Link\n"); 537 540 538 if (argc < static_cast<int>(2+NB_PARAMS+ 5*_nb_thread+6*_nb_decod_bloc+11*_nb_rename_bloc+4*_nb_read_bloc+4*_nb_write_bloc+9*_nb_load_store_unit+2*_nb_functionnal_unit+31*_nb_front_end+18*_nb_ooo_engine+11*_nb_execute_loop))541 if (argc < static_cast<int>(2+NB_PARAMS+6*_nb_thread+6*_nb_decod_bloc+11*_nb_rename_bloc+4*_nb_read_bloc+4*_nb_write_bloc+9*_nb_load_store_unit+2*_nb_functionnal_unit+31*_nb_front_end+18*_nb_ooo_engine+11*_nb_execute_loop)) 539 542 usage (argc, argv); 540 543 … … 590 593 _sum_cache_port += _nb_cache_port[i]; 591 594 592 if (argc != static_cast<int>(2+NB_PARAMS+ 5*_nb_thread+6*_nb_decod_bloc+11*_nb_rename_bloc+4*_nb_read_bloc+4*_nb_write_bloc+9*_nb_load_store_unit+2*_nb_functionnal_unit+31*_nb_front_end+18*_nb_ooo_engine+11*_nb_execute_loop+595 if (argc != static_cast<int>(2+NB_PARAMS+6*_nb_thread+6*_nb_decod_bloc+11*_nb_rename_bloc+4*_nb_read_bloc+4*_nb_write_bloc+9*_nb_load_store_unit+2*_nb_functionnal_unit+31*_nb_front_end+18*_nb_ooo_engine+11*_nb_execute_loop+ 593 596 3*_nb_thread+_nb_front_end+_sum_inst_issue*_nb_read_bloc+_nb_load_store_unit*(_nb_read_bloc+_nb_write_bloc+_nb_thread)+_nb_functionnal_unit*(_nb_read_bloc+_nb_write_bloc)+_sum_cache_port)) 594 597 usage (argc, argv); … … 626 629 _ras_size_queue , 627 630 _upt_size_queue , 631 _ufpt_size_queue , 628 632 629 633 _nb_decod_bloc , -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/include/Parameters.h
r88 r97 46 46 public : uint32_t * _ras_size_queue ;//[nb_thread] 47 47 public : uint32_t * _upt_size_queue ;//[nb_thread] 48 public : uint32_t * _ufpt_size_queue ;//[nb_thread] 48 49 49 50 // Decod bloc … … 221 222 public : uint32_t ** _front_end_ras_size_queue ;//[nb_front_end][nb_context] 222 223 public : uint32_t ** _front_end_upt_size_queue ;//[nb_front_end][nb_context] 224 public : uint32_t ** _front_end_ufpt_size_queue ;//[nb_front_end][nb_context] 223 225 224 226 // translate for ooo_engine … … 346 348 uint32_t * ras_size_queue ,//[nb_thread] 347 349 uint32_t * upt_size_queue ,//[nb_thread] 350 uint32_t * ufpt_size_queue ,//[nb_thread] 348 351 349 352 // Decod bloc -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Parameters.cpp
r88 r97 84 84 uint32_t * ras_size_queue ,//[nb_thread] 85 85 uint32_t * upt_size_queue ,//[nb_thread] 86 uint32_t * ufpt_size_queue ,//[nb_thread] 86 87 87 88 // Decod bloc … … 237 238 _ras_size_queue = ras_size_queue ; 238 239 _upt_size_queue = upt_size_queue ; 240 _ufpt_size_queue = ufpt_size_queue ; 239 241 240 242 _nb_decod_bloc = nb_decod_bloc ; … … 441 443 ALLOC2(_front_end_ras_size_queue ,uint32_t ,_nb_front_end,_nb_context[it1]); 442 444 ALLOC2(_front_end_upt_size_queue ,uint32_t ,_nb_front_end,_nb_context[it1]); 445 ALLOC2(_front_end_ufpt_size_queue ,uint32_t ,_nb_front_end,_nb_context[it1]); 443 446 444 447 for (uint32_t i=0; i<_nb_front_end; ++i) … … 451 454 _front_end_ras_size_queue [i][j] = _ras_size_queue [num_thread]; 452 455 _front_end_upt_size_queue [i][j] = _upt_size_queue [num_thread]; 456 _front_end_ufpt_size_queue [i][j] = _ufpt_size_queue [num_thread]; 453 457 454 458 uint32_t num_decod_bloc = _link_decod_bloc_with_thread [num_thread]; … … 1733 1737 _front_end_ras_size_queue [i], 1734 1738 _front_end_upt_size_queue [i], 1739 _front_end_ufpt_size_queue [i], 1735 1740 _size_nb_inst_commit 1736 1741 ); … … 2027 2032 DELETE1(_front_end_nb_inst_branch_complete ,_nb_front_end); 2028 2033 DELETE3(_front_end_instruction_implemeted ,_nb_front_end,_nb_context[it1],NB_INSTRUCTION); 2034 DELETE2(_front_end_ufpt_size_queue ,_nb_front_end,_nb_context[it1]); 2029 2035 DELETE2(_front_end_upt_size_queue ,_nb_front_end,_nb_context[it1]); 2030 2036 DELETE2(_front_end_ras_size_queue ,_nb_front_end,_nb_context[it1]); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Parameters_print.cpp
r88 r97 43 43 str+= toString(MSG_INFORMATION)+" * ras_size_queue : "+toString<uint32_t>(_ras_size_queue [i])+"\n"; 44 44 str+= toString(MSG_INFORMATION)+" * upt_size_queue : "+toString<uint32_t>(_upt_size_queue [i])+"\n"; 45 str+= toString(MSG_INFORMATION)+" * ufpt_size_queue : "+toString<uint32_t>(_ufpt_size_queue [i])+"\n"; 45 46 46 47 for (uint32_t j=0; j<NB_GROUP; ++j) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_vhdl_declaration.cpp
r94 r97 18 18 void RegisterFile_Monolithic::vhdl_declaration (Vhdl * & vhdl) 19 19 { 20 vhdl->set_type ("Tregfile", "array " + std_logic_range(_param->_nb_word,true) + " of " + std_logic(_param->_size_word));20 vhdl->set_type ("Tregfile", "array " + _std_logic_range(_param->_nb_word) + " of " + std_logic(_param->_size_word)); 21 21 22 22 vhdl->set_signal ("reg_DATA", "Tregfile"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/include/test.h
r81 r97 16 16 17 17 #include "Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/include/RegisterFile_Multi_Banked.h" 18 #include "Common/include/Time.h" 18 19 19 20 using namespace std; … … 28 29 morpheo::behavioural::generic::registerfile::registerfile_multi_banked::Parameters * param); 29 30 30 31 class Time32 {33 private : timeval time_begin;34 // private : timeval time_end;35 36 public : Time ()37 {38 gettimeofday(&time_begin ,NULL);39 };40 41 public : ~Time ()42 {43 cout << *this;44 };45 46 public : friend ostream& operator<< (ostream& output_stream,47 const Time & x)48 {49 timeval time_end;50 51 gettimeofday(&time_end ,NULL);52 53 uint32_t nb_cycles = static_cast<uint32_t>(sc_simulation_time());54 55 double average = static_cast<double>(nb_cycles) / static_cast<double>(time_end.tv_sec-x.time_begin.tv_sec);56 57 output_stream << nb_cycles << "\t(" << average << " cycles / seconds )" << endl;58 59 return output_stream;60 }61 }; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/SelfTest/include/test.h
r81 r97 15 15 16 16 #include "Behavioural/Generic/Select/Select_Priority_Fixed/include/Select_Priority_Fixed.h" 17 #include "Common/include/Time.h" 17 18 18 19 using namespace std; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/SelfTest/src/test.cpp
r88 r97 94 94 95 95 cout << "<" << name << "> Start Simulation ............" << endl; 96 Time * _time = new Time(); 96 97 97 98 if (_param->_nb_entity > (8*sizeof (Tentity_t))) … … 148 149 ********************************************************/ 149 150 151 delete _time; 150 152 cout << "<" << name << "> ............ Stop Simulation" << endl; 151 153 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/src/Select_Priority_Fixed.cpp
r88 r97 52 52 53 53 #ifdef VHDL 54 if (usage_is_set(_usage,USE_VHDL) 54 if (usage_is_set(_usage,USE_VHDL)) 55 55 { 56 56 // generate the vhdl -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.Common
r88 r97 27 27 DIR_SRC = src 28 28 DIR_OBJ = obj 29 #DIR_LIB = $(DIR_TMP)/lib30 29 DIR_SCRIPT = $(MORPHEO_SCRIPT) 31 30 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.deps
r81 r97 20 20 #-----[ Library ]------------------------------------------ 21 21 22 Behavioural_LIBRARY = -lBehavioural \ 23 -lCommon 22 Behavioural_LIBRARY = -lBehavioural \ 23 -lCommon 24 24 25 25 26 Behavioural_DIR_LIBRARY = -L$(Behavioural_DIR)/lib \ -
trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Constants.h
r88 r97 16 16 [0][19] - SPR_CID 17 17 */ 18 19 #include "Common/include/ToString.h" 18 20 19 21 namespace morpheo { … … 33 35 34 36 //=========================================================[ Type ]===== 35 # define TYPE_ALU 0x0 // 00000 - unit multiple 36 # define TYPE_SHIFT 0x1 // 00000 - unit multiple 37 # define TYPE_MOVE 0x2 // 00000 - unit multiple 38 # define TYPE_TEST 0x3 // 00000 - unit multiple 39 # define TYPE_MUL 0x4 // 00000 - unit multiple 40 # define TYPE_DIV 0x5 // 00000 - unit multiple, type optionnal 41 # define TYPE_EXTEND 0x6 // 00000 - unit multiple, type optionnal 42 # define TYPE_FIND 0x7 // 00000 - unit multiple, type optionnal 43 # define TYPE_SPECIAL 0x8 // 00000 - unit uniq 44 # define TYPE_CUSTOM 0x9 // 00000 - unit uniq , type optionnal 45 # define TYPE_BRANCH 0xa // 00000 - unit multiple 46 # define TYPE_MEMORY 0xb // 00000 - unit uniq 37 typedef enum 38 { 39 TYPE_ALU = 0x0, // 00000 - unit multiple 40 TYPE_SHIFT = 0x1, // 00000 - unit multiple 41 TYPE_MOVE = 0x2, // 00000 - unit multiple 42 TYPE_TEST = 0x3, // 00000 - unit multiple 43 TYPE_MUL = 0x4, // 00000 - unit multiple 44 TYPE_DIV = 0x5, // 00000 - unit multiple, type optionnal 45 TYPE_EXTEND = 0x6, // 00000 - unit multiple, type optionnal 46 TYPE_FIND = 0x7, // 00000 - unit multiple, type optionnal 47 TYPE_SPECIAL = 0x8, // 00000 - unit uniq 48 TYPE_CUSTOM = 0x9, // 00000 - unit uniq , type optionnal 49 TYPE_BRANCH = 0xa, // 00000 - unit multiple 50 TYPE_MEMORY = 0xb // 00000 - unit uniq 51 } type_t; 47 52 48 53 //#define NB_TYPE 11 … … 610 615 611 616 # define SIZE_BRANCH_CONDITION 4 612 613 # define BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK 0x0 // None condition (jump) 614 # define BRANCH_CONDITION_NONE_WITH_WRITE_STACK 0x8 // None condition (jump) 615 # define BRANCH_CONDITION_FLAG_UNSET 0x2 // Branch if Flag is clear 616 # define BRANCH_CONDITION_FLAG_SET 0x3 // Branch if Flag is set 617 # define BRANCH_CONDITION_READ_REGISTER_WITHOUT_WRITE_STACK 0x4 // Branch if a register is read 618 # define BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK 0xc // Branch if a register is read 619 # define BRANCH_CONDITION_READ_STACK 0xf // Branch with pop in stack pointer 620 617 # define MAX_BRANCH_CONDITION (1<<SIZE_BRANCH_CONDITION) 618 typedef enum 619 { 620 BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK = 0x0, // None condition (jump) 621 BRANCH_CONDITION_NONE_WITH_WRITE_STACK = 0x8, // None condition (jump) 622 BRANCH_CONDITION_FLAG_UNSET = 0x2, // Branch if Flag is clear 623 BRANCH_CONDITION_FLAG_SET = 0x3, // Branch if Flag is set 624 BRANCH_CONDITION_READ_REGISTER_WITHOUT_WRITE_STACK = 0x4, // Branch if a register is read 625 BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK = 0xc, // Branch if a register is read 626 BRANCH_CONDITION_READ_STACK = 0xf // Branch with pop in stack pointer 627 } branch_condition_t; 628 629 # define is_branch_condition_valid(x) \ 630 (( x == BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK ) or \ 631 ( x == BRANCH_CONDITION_NONE_WITH_WRITE_STACK ) or \ 632 ( x == BRANCH_CONDITION_FLAG_UNSET ) or \ 633 ( x == BRANCH_CONDITION_FLAG_SET ) or \ 634 ( x == BRANCH_CONDITION_READ_REGISTER_WITHOUT_WRITE_STACK) or \ 635 ( x == BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK ) or \ 636 ( x == BRANCH_CONDITION_READ_STACK )) 637 638 639 /* 640 enum 641 { 642 BRANCH_TYPE_SEQUENTIAL, 643 BRANCH_TYPE_JUMP, 644 BRANCH_TYPE_CONDITIONNAL, 645 BRANCH_TYPE_REGISTER, 646 BRANCH_TYPE_CALL, 647 BRANCH_TYPE_RETURN, 648 NB_BRANCH_TYPE 649 }; 650 651 # define branch_condition_to_type(x) \ 652 (x == BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK )?BRANCH_TYPE_JUMP: \ 653 ((x == BRANCH_CONDITION_NONE_WITH_WRITE_STACK )?BRANCH_TYPE_CALL: \ 654 ((x == BRANCH_CONDITION_FLAG_UNSET )?BRANCH_TYPE_CONDITIONNAL: \ 655 ((x == BRANCH_CONDITION_FLAG_SET )?BRANCH_TYPE_CONDITIONNAL: \ 656 ((x == BRANCH_CONDITION_READ_REGISTER_WITHOUT_WRITE_STACK)?BRANCH_TYPE_REGISTER: \ 657 ((x == BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK )?BRANCH_TYPE_CALL: \ 658 ((x == BRANCH_CONDITION_READ_STACK )?BRANCH_TYPE_RETURN:BRANCH_TYPE_SEQUENTIAL)))))); 659 */ 660 621 661 //--------------------------------------------------[ instruction ]----- 622 662 # define NB_INSTRUCTION 213 // 92 ORBIS, 30 ORFPX (15 simple, 15 double), 91 ORVDX (38 on byte, 41 on half, 12 independant format) … … 991 1031 992 1032 }; // end namespace behavioural 1033 1034 template<> inline std::string toString<morpheo::behavioural::type_t>(const morpheo::behavioural::type_t& x) 1035 { 1036 switch (x) 1037 { 1038 case morpheo::behavioural::TYPE_ALU : return "ALU" ; 1039 case morpheo::behavioural::TYPE_SHIFT : return "SHIFT" ; 1040 case morpheo::behavioural::TYPE_MOVE : return "MOVE" ; 1041 case morpheo::behavioural::TYPE_TEST : return "TEST" ; 1042 case morpheo::behavioural::TYPE_MUL : return "MUL" ; 1043 case morpheo::behavioural::TYPE_DIV : return "DIV" ; 1044 case morpheo::behavioural::TYPE_EXTEND : return "EXTEND" ; 1045 case morpheo::behavioural::TYPE_FIND : return "FIND" ; 1046 case morpheo::behavioural::TYPE_SPECIAL : return "SPECIAL" ; 1047 case morpheo::behavioural::TYPE_CUSTOM : return "CUSTOM" ; 1048 case morpheo::behavioural::TYPE_BRANCH : return "BRANCH" ; 1049 case morpheo::behavioural::TYPE_MEMORY : return "MEMORY" ; 1050 default : return ""; 1051 } 1052 }; 1053 1054 template<> inline std::string toString<morpheo::behavioural::branch_condition_t>(const morpheo::behavioural::branch_condition_t& x) 1055 { 1056 switch (x) 1057 { 1058 case morpheo::behavioural::BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK : return "none_without_write_stack" ; 1059 case morpheo::behavioural::BRANCH_CONDITION_NONE_WITH_WRITE_STACK : return "none_with_write_stack" ; 1060 case morpheo::behavioural::BRANCH_CONDITION_FLAG_UNSET : return "flag_unset" ; 1061 case morpheo::behavioural::BRANCH_CONDITION_FLAG_SET : return "flag_set" ; 1062 case morpheo::behavioural::BRANCH_CONDITION_READ_REGISTER_WITHOUT_WRITE_STACK : return "read_register_without_write_stack"; 1063 case morpheo::behavioural::BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK : return "read_register_with_write_stack" ; 1064 case morpheo::behavioural::BRANCH_CONDITION_READ_STACK : return "read_stack" ; 1065 default : return ""; 1066 } 1067 }; 1068 993 1069 }; // end namespace morpheo 994 1070 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Types.h
r88 r97 152 152 153 153 }; // end namespace behavioural 154 155 inline std::string toString_type(const morpheo::behavioural::Ttype_t& x)156 {157 switch (x)158 {159 case TYPE_ALU : return "ALU" ; break;160 case TYPE_SHIFT : return "SHIFT" ; break;161 case TYPE_MOVE : return "MOVE" ; break;162 case TYPE_TEST : return "TEST" ; break;163 case TYPE_MUL : return "MUL" ; break;164 case TYPE_DIV : return "DIV" ; break;165 case TYPE_EXTEND : return "EXTEND" ; break;166 case TYPE_FIND : return "FIND" ; break;167 case TYPE_SPECIAL : return "SPECIAL" ; break;168 case TYPE_CUSTOM : return "CUSTOM" ; break;169 case TYPE_BRANCH : return "BRANCH" ; break;170 case TYPE_MEMORY : return "MEMORY" ; break;171 default : return "Unknow type"; break;172 }173 };174 154 175 155 template<> inline std::string toString<morpheo::behavioural::Tpriority_t>(const morpheo::behavioural::Tpriority_t& x) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Version.h
r96 r97 10 10 #define MORPHEO_MAJOR_VERSION 0 11 11 #define MORPHEO_MINOR_VERSION 2 12 #define MORPHEO_REVISION "9 6"12 #define MORPHEO_REVISION "97" 13 13 #define MORPHEO_CODENAME "Castor" 14 14 15 #define MORPHEO_DATE_DAY "1 6"15 #define MORPHEO_DATE_DAY "19" 16 16 #define MORPHEO_DATE_MONTH "12" 17 17 #define MORPHEO_DATE_YEAR "2008" -
trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Vhdl.h
r95 r97 23 23 namespace behavioural { 24 24 25 std::string std_logic (uint32_t size); 26 std::string std_logic_conv (uint32_t size, std::string value); 27 std::string std_logic_conv (uint32_t size, uint32_t value); 28 std::string std_logic_cst (uint32_t size, uint32_t value); 29 std::string std_logic_range (uint32_t size, uint32_t max , uint32_t min , bool force=false); 30 std::string std_logic_range ( uint32_t max , uint32_t min , bool force=false); 31 std::string std_logic_range (uint32_t size, bool force=false); 32 std::string std_logic_others (uint32_t size, bool cst); 25 std::string std_logic (uint32_t size); 26 std::string std_logic_conv (uint32_t size, std::string value); 27 std::string std_logic_conv (uint32_t size, uint32_t value); 28 std::string std_logic_cst (uint32_t size, uint32_t value); 29 std::string std_logic_range (uint32_t size, uint32_t max , uint32_t min ); 30 std::string std_logic_range ( uint32_t max , uint32_t min ); 31 std::string std_logic_range (uint32_t size ); 32 std::string _std_logic_range (uint32_t size, uint32_t max , uint32_t min ); 33 std::string _std_logic_range ( uint32_t max , uint32_t min ); 34 std::string _std_logic_range (uint32_t size ); 35 std::string std_logic_others (uint32_t size, bool cst); 33 36 34 37 class Vhdl -
trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Component_test_map.cpp
r94 r97 48 48 i != _list_component->end(); 49 49 ++i) 50 { 51 test_ok &= (*i)->_entity->test_map(depth+1,false,is_behavioural); 52 if (recursive) 53 try 54 { 55 test_ok &= (*i)->_component->test_map(depth+1,recursive); 56 } 57 catch (morpheo::ErrorMorpheo & error) 58 { 59 // no error propagation, only top level 60 } 61 } 50 if (((*i)->_instance & INSTANCE_COMPONENT) != 0) 51 { 52 test_ok &= (*i)->_entity->test_map(depth+1,false,is_behavioural); 53 if (recursive) 54 try 55 { 56 test_ok &= (*i)->_component->test_map(depth+1,recursive); 57 } 58 catch (morpheo::ErrorMorpheo & error) 59 { 60 // no error propagation, only top level 61 } 62 } 62 63 63 64 log_printf(FUNC,Behavioural,FUNCTION,"End"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/src/SPR_access_mode_exist.cpp
r88 r97 1 1 #include "Behavioural/include/SPR_access_mode.h" 2 // #include "Common/include/Debug.h" 2 3 3 4 namespace morpheo { … … 15 16 16 17 spr_access_mode_t mode = _spr_generic [num_group][num_reg]; 18 // log_printf(TRACE,true,"exist"," * exist"); 19 // log_printf(TRACE,true,"exist"," * num_group : %d",num_group); 20 // log_printf(TRACE,true,"exist"," * num_register : %d",num_reg); 21 // log_printf(TRACE,true,"exist"," * supervisor_access_mode : %d",mode._supervisor_access_mode); 22 // log_printf(TRACE,true,"exist"," * user_access_mode : %d",mode._user_access_mode ); 17 23 18 24 return ((mode._supervisor_access_mode != SPR_ACCESS_MODE_NONE) or -
trunk/IPs/systemC/processor/Morpheo/Behavioural/src/SPR_access_mode_implement_group.cpp
r88 r97 33 33 _spr_generic [GROUP_SYSTEM_AND_CONTROL ][ 20]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE; 34 34 35 const uint32_t nb_shadow = 1; 35 const uint32_t nb_shadow = 1; // max 16 36 36 37 for (uint32_t i=32; i< =32+nb_shadow; i++)38 _spr_generic [GROUP_SYSTEM_AND_CONTROL ][ i]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE; 39 for (uint32_t i=48; i< =48+nb_shadow; i++)40 _spr_generic [GROUP_SYSTEM_AND_CONTROL ][ i]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE; 41 for (uint32_t i=64; i< =64+nb_shadow; i++)42 _spr_generic [GROUP_SYSTEM_AND_CONTROL ][ i]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE; 43 for (uint32_t i=1024; i<=1024+32*nb_shadow; i++)44 _spr_generic [GROUP_SYSTEM_AND_CONTROL ][ i]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE;37 for (uint32_t i=32; i<32+nb_shadow; i++) 38 _spr_generic [GROUP_SYSTEM_AND_CONTROL ][ i]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE; 39 for (uint32_t i=48; i<48+nb_shadow; i++) 40 _spr_generic [GROUP_SYSTEM_AND_CONTROL ][ i]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE; 41 for (uint32_t i=64; i<64+nb_shadow; i++) 42 _spr_generic [GROUP_SYSTEM_AND_CONTROL ][ i]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE; 43 // for (uint32_t i=1024; i<1024+32*nb_shadow; i++) 44 // _spr_generic [GROUP_SYSTEM_AND_CONTROL ][ i]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE; 45 45 46 46 break; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_set_body_component_port_map.cpp
r81 r97 18 18 #define FUNCTION "Vhdl::set_body_component_port_map" 19 19 void Vhdl::set_body_component_port_map (std::list<std::string> & list_port_map , 20 std::string name_port ,21 uint32_t size_port ,22 std::string name_signal ,23 uint32_t size_signal )20 std::string name_port , 21 uint32_t size_port , 22 std::string name_signal , 23 uint32_t size_signal ) 24 24 { 25 25 log_printf(FUNC,Behavioural,FUNCTION,"Begin"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_std_logic.cpp
r95 r97 80 80 #undef FUNCTION 81 81 #define FUNCTION "Vhdl::std_logic_range" 82 std::string std_logic_range (uint32_t size, uint32_t max, uint32_t min , bool force)82 std::string std_logic_range (uint32_t size, uint32_t max, uint32_t min) 83 83 { 84 84 log_printf(FUNC,Behavioural,FUNCTION,"Begin"); 85 85 std::string type; 86 86 87 if (force)88 87 { 89 type = "("+toString(max)+" downto "+toString(min)+")"; 90 } 91 else 92 { 93 if (max == min) 94 { 95 type = "("+toString(max)+")"; 96 } 88 if (size < 2) 89 type = ""; 97 90 else 98 91 { 99 if (size < 2) 100 type = ""; 92 if (max == min) 93 { 94 type = "("+toString(max)+")"; 95 } 101 96 else 102 type = "("+toString(max)+" downto "+toString(min)+")"; 97 { 98 type = "("+toString(max)+" downto "+toString(min)+")"; 99 } 103 100 } 104 101 } … … 109 106 }; 110 107 111 std::string std_logic_range (uint32_t max, uint32_t min , bool force)108 std::string std_logic_range (uint32_t max, uint32_t min) 112 109 { 113 110 log_printf(FUNC,Behavioural,FUNCTION,"Begin"); 114 111 std::string type; 115 112 116 if (force)117 {118 type = "("+toString(max)+" downto "+toString(min)+")";119 }120 else121 113 { 122 114 if (max == min) … … 138 130 }; 139 131 140 std::string std_logic_range (uint32_t size , bool force)132 std::string std_logic_range (uint32_t size) 141 133 { 142 134 log_printf(FUNC,Behavioural,FUNCTION,"Begin"); 143 std::string _return = std_logic_range(size-1,0,force); 135 std::string _return = std_logic_range(size,size-1,0); 136 log_printf(FUNC,Behavioural,FUNCTION,"End"); 137 138 return _return; 139 } 140 141 #undef FUNCTION 142 #define FUNCTION "Vhdl::_std_logic_range" 143 std::string _std_logic_range (uint32_t size, uint32_t max, uint32_t min) 144 { 145 log_printf(FUNC,Behavioural,FUNCTION,"Begin"); 146 std::string type=_std_logic_range(max,min); 147 log_printf(FUNC,Behavioural,FUNCTION,"End"); 148 149 return type; 150 }; 151 152 std::string _std_logic_range (uint32_t max, uint32_t min) 153 { 154 log_printf(FUNC,Behavioural,FUNCTION,"Begin"); 155 std::string type = "("+toString(max)+" downto "+toString(min)+")"; 156 log_printf(FUNC,Behavioural,FUNCTION,"End"); 157 158 return type; 159 }; 160 161 std::string _std_logic_range (uint32_t size) 162 { 163 log_printf(FUNC,Behavioural,FUNCTION,"Begin"); 164 std::string _return = _std_logic_range(size,size-1,0); 144 165 log_printf(FUNC,Behavioural,FUNCTION,"End"); 145 166 -
trunk/IPs/systemC/processor/Morpheo/Common/include/Debug.h
r88 r97 9 9 * function to help the debugging : 10 10 * 11 * - debug_tab12 11 * - log_printf 13 12 * - log_begin … … 26 25 27 26 #include "Common/include/Message.h" 27 #include "Common/include/FromString.h" 28 #include "Common/include/ChangeCase.h" 28 29 #include "Behavioural/include/Debug_component.h" 29 30 #include <systemc.h> … … 36 37 namespace morpheo { 37 38 38 enum _debug_verbosity39 typedef enum 39 40 { 40 41 DEBUG_NONE , … … 43 44 DEBUG_FUNC , 44 45 DEBUG_ALL 45 } ;46 47 std::string debug_tab (void);48 void debug_tab_inc (void); 49 void debug_ tab_dec(void);50 46 } debug_verbosity_t; 47 48 extern debug_verbosity_t debug; 49 50 void debug_init (void); 51 void debug_init (debug_verbosity_t level); 51 52 #ifdef DEBUG 53 52 54 # define log_printf(level, component, func, str... ) \ 53 55 do \ 54 56 { \ 55 if ((DEBUG == DEBUG_ALL ) or \ 57 debug_init(); \ 58 \ 59 if ((debug == DEBUG_ALL ) or \ 56 60 (DEBUG_ ## level == DEBUG_NONE) or \ 57 (( DEBUG_ ## level <= DEBUG) and \61 (( DEBUG_ ## level <= debug) and \ 58 62 ( DEBUG_ ## component == true )) ) \ 59 63 { \ … … 67 71 } \ 68 72 \ 69 if (DEBUG >= DEBUG_FUNC) \ 70 { \ 71 msg("%s",debug_tab().c_str()); \ 72 } \ 73 if (DEBUG >= DEBUG_ALL ) \ 73 if (debug >= DEBUG_ALL ) \ 74 74 { \ 75 75 switch (DEBUG_ ## level) \ … … 83 83 } \ 84 84 } \ 85 if ( DEBUG>= DEBUG_FUNC) \85 if (debug >= DEBUG_FUNC) \ 86 86 { \ 87 87 msg( "<%s> " ,func); \ … … 98 98 do \ 99 99 { \ 100 debug_tab_inc (); \101 100 log_printf(FUNC,component,func,_("Begin")); \ 102 101 } while(0) … … 106 105 { \ 107 106 log_printf(FUNC,component,func,_("End")); \ 108 debug_tab_dec (); \109 107 } while(0) 110 108 … … 172 170 #endif 173 171 172 173 template<> inline debug_verbosity_t fromString<debug_verbosity_t> (const std::string& x) 174 { 175 std::string y=x; 176 LowerCase(y); 177 178 if ( (y.compare("0") == 0) or 179 (y.compare("none") == 0)) 180 return DEBUG_NONE ; 181 if ( (y.compare("1") == 0) or 182 (y.compare("info") == 0)) 183 return DEBUG_INFO ; 184 if ( (y.compare("2") == 0) or 185 (y.compare("trace") == 0)) 186 return DEBUG_TRACE; 187 if ( (y.compare("3") == 0) or 188 (y.compare("func") == 0)) 189 return DEBUG_FUNC ; 190 if ( (y.compare("4") == 0) or 191 (y.compare("all") == 0)) 192 return DEBUG_ALL ; 193 194 #ifdef DEBUG 195 return DEBUG; 196 #else 197 return DEBUG_NONE ; 198 #endif 199 } 200 174 201 }; // end namespace morpheo 175 202 #endif // !DEBUG_H -
trunk/IPs/systemC/processor/Morpheo/Common/include/Message.h
r88 r97 41 41 #endif 42 42 43 #ifdef LOG_FILE44 43 extern FILE * log_stream; 45 void log_init (void); 44 FILE * log (FILE * stream); 45 void log_init (bool have_file, 46 std::string directory, 47 std::string file=""); 46 48 47 49 #define fmsg(stream,arg...) \ 48 50 do \ 49 51 { \ 50 log_init();\51 fprintf( log_stream,arg); \52 fflush( log_stream);\52 FILE * _stream = log(stream); \ 53 fprintf(_stream,arg); \ 54 fflush(_stream); \ 53 55 } while (0) 54 55 #else56 57 #define fmsg(stream,arg...) \58 do \59 { \60 fprintf(stream,arg); \61 fflush(stream); \62 } while (0)63 64 #endif65 56 66 57 #define fmsgDebug(stream,arg...) \ -
trunk/IPs/systemC/processor/Morpheo/Common/include/Time.h
r88 r97 15 15 { 16 16 #ifdef SYSTEMC 17 private : double nb_cycles_begin; 17 private : const bool systemc; 18 private : double nb_cycles_begin; 18 19 #endif 19 private : timeval time_begin;20 private : timeval time_begin; 20 21 // private : timeval time_end; 21 22 22 public : Time () 23 public : Time (bool systemc=true) 24 #ifdef SYSTEMC 25 : 26 systemc (systemc) 27 #endif 23 28 { 24 29 #ifdef SYSTEMC … … 41 46 42 47 #ifdef SYSTEMC 43 double nb_cycles_end = sc_simulation_time();44 double average = static_cast<double>(nb_cycles_end-x.nb_cycles_begin+1) / static_cast<double>(time_end.tv_sec-x.time_begin.tv_sec+1);45 46 output << "Timing : " << nb_cycles_end << " cycles \t(" << average << " cycles/s)" << std::endl;47 #else 48 double average = static_cast<double>(time_end.tv_sec-x.time_begin.tv_sec+1);49 50 output << "Timing : " average << " s" << std::endl;48 if (x.systemc) 49 { 50 double nb_cycles_end = sc_simulation_time(); 51 double average = static_cast<double>(nb_cycles_end-x.nb_cycles_begin+1) / static_cast<double>(time_end.tv_sec-x.time_begin.tv_sec+1); 52 53 output << "Timing : " << nb_cycles_end << " cycles \t(" << average << " cycles/s)" << std::endl; 54 } 55 else 51 56 #endif 52 57 { 58 double average = static_cast<double>(time_end.tv_sec-x.time_begin.tv_sec+1); 59 60 output << "Timing : " << average << " s" << std::endl; 61 } 62 53 63 return output; 54 64 } -
trunk/IPs/systemC/processor/Morpheo/Common/src/Debug.cpp
r88 r97 11 11 namespace morpheo { 12 12 13 static uint32_t _debug_depth = 0; 13 #ifdef DEBUG 14 static bool debug_initialized; 15 #endif 16 debug_verbosity_t debug; 14 17 15 18 #undef FUNCTION 16 #define FUNCTION "debug_ tab"17 std::string debug_tab(void)19 #define FUNCTION "debug_init" 20 void debug_init (void) 18 21 { 19 return std::string(_debug_depth,'\t'); 22 #ifdef DEBUG 23 if (not debug_initialized) 24 { 25 debug = DEBUG; 26 27 // debug_initialized = true; 28 } 29 #endif 20 30 } 21 31 22 32 #undef FUNCTION 23 #define FUNCTION "debug_ tab_inc"24 void debug_ tab_inc (void)33 #define FUNCTION "debug_init" 34 void debug_init (debug_verbosity_t level) 25 35 { 26 // _debug_depth ++; 27 } 28 29 #undef FUNCTION 30 #define FUNCTION "debug_tab_dec" 31 void debug_tab_dec (void) 32 { 33 // _debug_depth --; 36 #ifdef DEBUG 37 if (not debug_initialized) 38 { 39 // Take min 40 debug = (level < DEBUG)?level:DEBUG; 41 42 debug_initialized = true; 43 } 44 #endif 34 45 } 35 46 -
trunk/IPs/systemC/processor/Morpheo/Common/src/Environment.cpp
r88 r97 9 9 #include "Common/include/ErrorMorpheo.h" 10 10 #include "Common/include/Debug.h" 11 #include "Common/include/Message.h" 11 12 #include <sys/stat.h> 12 13 -
trunk/IPs/systemC/processor/Morpheo/Common/src/Message.cpp
r88 r97 1 #ifdef LOG_FILE2 1 /* 3 2 * $Id$ … … 16 15 namespace morpheo { 17 16 18 static bool log_initialized; 19 FILE * log_stream; 20 17 static bool log_initialized; 18 FILE * log_stream; 19 20 #undef FUNCTION 21 #define FUNCTION "log" 22 FILE * log (FILE * stream) 23 { 24 // if log stream is initialized, take this, else return the default stream. 25 return (log_initialized and (log_stream!=NULL))?log_stream:stream; 26 }; 27 21 28 #undef FUNCTION 22 29 #define FUNCTION "log_init" 23 void log_init (void) 24 { 25 if (not log_initialized) 26 { 27 log_initialized = true; 28 29 directory(); 30 31 std::string filename = MORPHEO_LOG+"/Morpheo_"+toString<pid_t>(getpid())+".log"; 32 33 log_stream = fopen (filename.c_str(), "w"); 34 35 if (log_stream==NULL) 36 { 37 fprintf(stderr,_("%s Error create log file \"%s\", take the standard output.\n"),MSG_ERROR,filename.c_str()); 38 log_stream = stdout; 39 } 40 else 41 { 42 fprintf(stdout,_("%s Create log file \"%s\".\n"),MSG_INFORMATION,filename.c_str()); 43 } 44 } 45 } 46 30 void log_init (bool have_file, 31 std::string directory, 32 std::string file) 33 { 34 if (not log_initialized) 35 { 36 log_initialized = true; 37 38 if (have_file) 39 { 40 // if the file is not define, take pid. 41 std::string filename = directory+"/Morpheo_"+((file!="")?file:toString<pid_t>(getpid()))+".log"; 42 43 log_stream = fopen (filename.c_str(), "w"); 44 45 if (log_stream==NULL) 46 { 47 fprintf(stderr,_("%s Error create log file \"%s\", take the standard output.\n"),MSG_ERROR,filename.c_str()); 48 log_stream = stdout; 49 } 50 else 51 { 52 fprintf(stdout,_("%s Create log file \"%s\".\n"),MSG_INFORMATION,filename.c_str()); 53 } 54 } 55 else 56 { 57 log_stream = NULL; 58 } 59 } 60 } 61 47 62 }; // end namespace morpheo 48 #endif -
trunk/IPs/systemC/processor/Morpheo/Files/Morpheo.gen
r88 r97 20 20 <parameter name="ras_size_queue" min="2" max="8" step="* 2" default="2" level="..." description="..." /> 21 21 <parameter name="upt_size_queue" min="1" max="8" step="* 2" default="2" level="..." description="..." /> 22 <parameter name="ufpt_size_queue" min="1" max="8" step="* 2" default="2" level="..." description="..." /> 22 23 23 24 <parameter name="nb_decod_bloc" min="1" max="8" step="* 2" default="1" level="..." description="..." /> -
trunk/IPs/systemC/processor/Morpheo/Files/Morpheo.sim
r95 r97 10 10 <parameter name="use_statistics" value="0" /> 11 11 <parameter name="use_information" value="0" /> 12 <parameter name="use_header" value=" 0" />12 <parameter name="use_header" value="1" /> 13 13 14 14 <parameter name="nb_cycle_before_begin" value="0" /> … … 18 18 <parameter name="simulation_nb_instruction" value="0" /> 19 19 20 <parameter name="directory_statistics" value=" /tmp/Morpheo/" />21 <parameter name="directory_vhdl" value=" /tmp/Morpheo/" />22 <parameter name="directory_position" value=" /tmp/Morpheo/" />23 <parameter name="directory_log" value=" /tmp/Morpheo/" />20 <parameter name="directory_statistics" value="." /> 21 <parameter name="directory_vhdl" value="." /> 22 <parameter name="directory_position" value="." /> 23 <parameter name="directory_log" value="." /> 24 24 25 <parameter name="debug" value="0" /> 25 <parameter name="debug_level" value="trace" /> 26 <parameter name="debug_have_log_file" value="0" /> 26 27 27 28 </parameters> -
trunk/IPs/systemC/processor/Morpheo/TopLevel/include/Morpheo.h
r88 r97 150 150 public : ~Morpheo (void); 151 151 152 private : std::string header (void);153 154 152 private : void configuration (std::string filename_simulator, 155 153 std::string filename_generator, -
trunk/IPs/systemC/processor/Morpheo/TopLevel/src/Morpheo.cpp
r88 r97 37 37 filename_instance, 38 38 get_custom_information); 39 40 if (usage_is_set(_usage,USE_HEADER))41 std::cout << header();42 39 43 40 log_printf(INFO,Morpheo,FUNCTION,_("<%s> : Allocation"),_name.c_str()); -
trunk/IPs/systemC/processor/Morpheo/TopLevel/src/Morpheo_configuration.cpp
r88 r97 52 52 param->_ras_size_queue , 53 53 param->_upt_size_queue , 54 param->_ufpt_size_queue , 54 55 55 56 param->_nb_decod_bloc , -
trunk/Makefile.flags
r88 r97 23 23 24 24 # -DPRINT_COLOR \ 25 # -DLOG_FILE \26 25 # -DPOSITION \ 27 26 # -DREGISTER_INIT \ … … 29 28 # Flags : 30 29 # DEBUG={level} - Print Debug Message 31 # LOG_FILE - Print Message in a log file32 30 # SYSTEMC - To generate a systemc's model 33 31 # VHDL - To generate a vhdl's models -
trunk/Platforms/Test/Makefile
r88 r97 58 58 OBJECTS = $(patsubst $(DIR_SRC)/%.cpp,$(DIR_OBJ)/%.o,$(wildcard $(DIR_SRC)/*.cpp)) 59 59 LOGS = $(patsubst $(DIR_DATA)/%.cfg,$(DIR_LOG)/%.log,$(wildcard $(DIR_DATA)/*.cfg)) 60 DEBUG_CFG = $(DIR_DATA)/debug.cfg 61 DEBUG_LOG = $(DIR_LOG)/debug.log 60 62 61 63 EXEC = $(DIR_BIN)/soft.x … … 106 108 run : $(DIR_LOG) all 107 109 @\ 108 $(MAKE) $(LOGS); \ 110 declare logs; \ 111 if $(TEST) -f "$(DEBUG_CFG)"; then \ 112 logs="$(DEBUG_LOG)"; \ 113 else \ 114 logs="$(LOGS)"; \ 115 fi; \ 116 $(MAKE) $$logs; \ 109 117 declare -i have_test_ko=0; \ 110 for log in $ (LOGS); do \118 for log in $$logs; do \ 111 119 $(GREP) -q "Test OK" $$log; \ 112 120 declare -i test_ok=$$?; \
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