Ignore:
Timestamp:
May 21, 2014, 11:36:19 AM (10 years ago)
Author:
rolagamo
Message:

Ceci est la version 16 bits de la plateforme ainsi que la version hierarchique du NoCNoC

Location:
PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.0
Files:
1 edited
15 copied

Legend:

Unmodified
Added
Removed

  • PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.0/Test_Timer/Test_Timer.gise

    r137 r139  
    1616  <!--                                                          -->
    1717
    18   <!-- Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved. -->
     18  <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
    1919
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    … …  
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    … …  
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    … …  
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     175    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="test_tree_8x8_pad.csv" xil_pn:subbranch="Par"/>
     176    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="test_tree_8x8_pad.txt" xil_pn:subbranch="Par"/>
     177    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="test_tree_8x8_par.xrpt"/>
     178    <file xil_pn:fileType="FILE_HTML" xil_pn:name="test_tree_8x8_summary.html"/>
     179    <file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="test_tree_8x8_summary.xml"/>
     180    <file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="test_tree_8x8_usage.xml"/>
     181    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="test_tree_8x8_xst.xrpt"/>
     182    <file xil_pn:fileType="FILE_HTML" xil_pn:name="usage_statistics_webtalk.html"/>
     183    <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_MODELSIM_LOG" xil_pn:name="vsim.wlf"/>
     184    <file xil_pn:fileType="FILE_LOG" xil_pn:name="webtalk.log"/>
    83185    <file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
     186    <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="work"/>
    84187    <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xlnx_auto_0_xdb"/>
    85188    <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/>
    … …  
    87190
    88191  <transforms xmlns="http://www.xilinx.com/XMLSchema">
    89     <transform xil_pn:end_ts="1397065166" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1397065166">
    90       <status xil_pn:value="SuccessfullyRun"/>
    91     </transform>
    92     <transform xil_pn:end_ts="1397065166" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="8802460352089655353" xil_pn:start_ts="1397065166">
    93       <status xil_pn:value="SuccessfullyRun"/>
    94       <status xil_pn:value="ReadyToRun"/>
    95     </transform>
    96     <transform xil_pn:end_ts="1397065167" xil_pn:in_ck="-4721685615919775683" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="491076837086602063" xil_pn:start_ts="1397065166">
     192    <transform xil_pn:end_ts="1397211097" xil_pn:name="TRANEXT_compLibraries2_virtex5" xil_pn:prop_ck="6769433014420063265" xil_pn:start_ts="1397209614">
     193      <status xil_pn:value="SuccessfullyRun"/>
     194      <status xil_pn:value="ReadyToRun"/>
     195      <outfile xil_pn:name="compxlib.log"/>
     196    </transform>
     197    <transform xil_pn:end_ts="1397209568" xil_pn:name="TRAN_copyInitialToAbstractSimulation" xil_pn:start_ts="1397209567">
     198      <status xil_pn:value="SuccessfullyRun"/>
     199      <status xil_pn:value="ReadyToRun"/>
     200    </transform>
     201    <transform xil_pn:end_ts="1400574571" xil_pn:in_ck="8755842774537234124" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1400574571">
     202      <status xil_pn:value="SuccessfullyRun"/>
     203      <status xil_pn:value="ReadyToRun"/>
     204      <status xil_pn:value="OutOfDateForInputs"/>
     205      <status xil_pn:value="OutOfDateForOutputs"/>
     206      <status xil_pn:value="InputChanged"/>
     207      <status xil_pn:value="OutputChanged"/>
     208      <outfile xil_pn:name="../CORE_MPI/CORE_MPI.vhd"/>
     209      <outfile xil_pn:name="../CORE_MPI/DEMUX1.vhd"/>
     210      <outfile xil_pn:name="../CORE_MPI/DMA_ARBITER.vhd"/>
     211      <outfile xil_pn:name="../CORE_MPI/EX1_FSM.vhd"/>
     212      <outfile xil_pn:name="../CORE_MPI/EX2_FSM.vhd"/>
     213      <outfile xil_pn:name="../CORE_MPI/EX3_FSM.vhd"/>
     214      <outfile xil_pn:name="../CORE_MPI/EX4_FSM.vhd"/>
     215      <outfile xil_pn:name="../CORE_MPI/Ex0_Fsm.vhd"/>
     216      <outfile xil_pn:name="../CORE_MPI/Ex5_FSM.vhd"/>
     217      <outfile xil_pn:name="../CORE_MPI/FIFO_64_FWFT.vhd"/>
     218      <outfile xil_pn:name="../CORE_MPI/FIfo_mem.vhd"/>
     219      <outfile xil_pn:name="../CORE_MPI/FIfo_proc.vhd"/>
     220      <outfile xil_pn:name="../CORE_MPI/MPICORETEST.vhd"/>
     221      <outfile xil_pn:name="../CORE_MPI/MPI_CORE_SCHEDULER.vhd"/>
     222      <outfile xil_pn:name="../CORE_MPI/MPI_NOC.vhd"/>
     223      <outfile xil_pn:name="../CORE_MPI/MPI_PKG.vhd"/>
     224      <outfile xil_pn:name="../CORE_MPI/MPI_RMA.vhd"/>
     225      <outfile xil_pn:name="../CORE_MPI/MUX1.vhd"/>
     226      <outfile xil_pn:name="../CORE_MPI/MUX8.vhd"/>
     227      <outfile xil_pn:name="../CORE_MPI/MultiMPITest.vhd"/>
     228      <outfile xil_pn:name="../CORE_MPI/Packet_type.vhd"/>
     229      <outfile xil_pn:name="../CORE_MPI/RAM_32_32.vhd"/>
     230      <outfile xil_pn:name="../CORE_MPI/RAM_64.vhd"/>
     231      <outfile xil_pn:name="../CORE_MPI/RAM_MUX.vhd"/>
     232      <outfile xil_pn:name="../CORE_MPI/SetBit.vhd"/>
     233      <outfile xil_pn:name="../CORE_MPI/image_pkg.vhd"/>
     234      <outfile xil_pn:name="../CORE_MPI/load_instr.vhd"/>
     235      <outfile xil_pn:name="../CORE_MPI/round_robbin_machine.vhd"/>
     236      <outfile xil_pn:name="../CORE_MPI/test_DMA.vhd"/>
     237      <outfile xil_pn:name="../HCL_Arch_conf.vhd"/>
     238      <outfile xil_pn:name="../HT_process.vhd"/>
     239      <outfile xil_pn:name="../Hold_FSM.vhd"/>
     240      <outfile xil_pn:name="../IP_Timer.vhd"/>
     241      <outfile xil_pn:name="../NOC/Arbiter.vhd"/>
     242      <outfile xil_pn:name="../NOC/CoreTypes.vhd"/>
     243      <outfile xil_pn:name="../NOC/Crossbar.vhd"/>
     244      <outfile xil_pn:name="../NOC/Crossbit.vhd"/>
     245      <outfile xil_pn:name="../NOC/Def_Request.vhd"/>
     246      <outfile xil_pn:name="../NOC/FIFO_256_FWFT.vhd"/>
     247      <outfile xil_pn:name="../NOC/FIFO_DP.vhd"/>
     248      <outfile xil_pn:name="../NOC/INPUT_PORT_MODULE.vhd"/>
     249      <outfile xil_pn:name="../NOC/NOC_tree.vhd"/>
     250      <outfile xil_pn:name="../NOC/OUTPUT_PORT_MODULE.vhd"/>
     251      <outfile xil_pn:name="../NOC/PortRam.vhd"/>
     252      <outfile xil_pn:name="../NOC/Proto_receiv.vhd"/>
     253      <outfile xil_pn:name="../NOC/RAM_256.vhd"/>
     254      <outfile xil_pn:name="../NOC/SCHEDULER10_10.VHD"/>
     255      <outfile xil_pn:name="../NOC/SCHEDULER11_11.VHD"/>
     256      <outfile xil_pn:name="../NOC/SCHEDULER12_12.VHD"/>
     257      <outfile xil_pn:name="../NOC/SCHEDULER13_13.VHD"/>
     258      <outfile xil_pn:name="../NOC/SCHEDULER14_14.VHD"/>
     259      <outfile xil_pn:name="../NOC/SCHEDULER15_15.VHD"/>
     260      <outfile xil_pn:name="../NOC/SCHEDULER16_16.VHD"/>
     261      <outfile xil_pn:name="../NOC/SCHEDULER2_2.VHD"/>
     262      <outfile xil_pn:name="../NOC/SCHEDULER3_3.VHD"/>
     263      <outfile xil_pn:name="../NOC/SCHEDULER4_4.VHD"/>
     264      <outfile xil_pn:name="../NOC/SCHEDULER5_5.VHD"/>
     265      <outfile xil_pn:name="../NOC/SCHEDULER6_6.VHD"/>
     266      <outfile xil_pn:name="../NOC/SCHEDULER7_7.VHD"/>
     267      <outfile xil_pn:name="../NOC/SCHEDULER8_8.VHD"/>
     268      <outfile xil_pn:name="../NOC/SCHEDULER9_9.VHD"/>
     269      <outfile xil_pn:name="../NOC/SWITCH_GEN.vhd"/>
     270      <outfile xil_pn:name="../NOC/SWITCH_GENERIQUE.vhd"/>
     271      <outfile xil_pn:name="../NOC/Scheduler.vhd"/>
     272      <outfile xil_pn:name="../NOC/conv.vhd"/>
     273      <outfile xil_pn:name="../NOC/proto_send.vhd"/>
     274      <outfile xil_pn:name="../NOC/stimuli1.vhd"/>
     275      <outfile xil_pn:name="../NOC/test_noc_tree.vhd"/>
     276      <outfile xil_pn:name="../NOC/test_xbar_8x8.vhd"/>
     277      <outfile xil_pn:name="../PE.vhd"/>
     278      <outfile xil_pn:name="../mpi_test.vhd"/>
     279      <outfile xil_pn:name="simu_tree.vhd"/>
     280    </transform>
     281    <transform xil_pn:end_ts="1399017011" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-2831012963420336669" xil_pn:start_ts="1399017011">
     282      <status xil_pn:value="SuccessfullyRun"/>
     283      <status xil_pn:value="ReadyToRun"/>
     284    </transform>
     285    <transform xil_pn:end_ts="1399017011" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-6993736891428108223" xil_pn:start_ts="1399017011">
     286      <status xil_pn:value="SuccessfullyRun"/>
     287      <status xil_pn:value="ReadyToRun"/>
     288    </transform>
     289    <transform xil_pn:end_ts="1398960571" xil_pn:in_ck="-4721685615919775683" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-83444157416746671" xil_pn:start_ts="1398960570">
    97290      <status xil_pn:value="SuccessfullyRun"/>
    98291      <status xil_pn:value="ReadyToRun"/>
    … …  
    100293      <outfile xil_pn:name="ipcore_dir/mem8k8.vhd"/>
    101294    </transform>
    102     <transform xil_pn:name="TRAN_SubProjectAbstractToPreProxy">
    103       <status xil_pn:value="SuccessfullyRun"/>
    104       <status xil_pn:value="ReadyToRun"/>
    105     </transform>
    106     <transform xil_pn:end_ts="1397065167" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-8804766714685316537" xil_pn:start_ts="1397065167">
    107       <status xil_pn:value="SuccessfullyRun"/>
    108       <status xil_pn:value="ReadyToRun"/>
    109     </transform>
    110     <transform xil_pn:end_ts="1397065167" xil_pn:in_ck="-1335772100541163525" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-7782322491054780976" xil_pn:start_ts="1397065167">
    111       <status xil_pn:value="SuccessfullyRun"/>
    112       <status xil_pn:value="ReadyToRun"/>
    113     </transform>
    114     <transform xil_pn:end_ts="1397065167" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-4953193664677071463" xil_pn:start_ts="1397065167">
    115       <status xil_pn:value="SuccessfullyRun"/>
    116       <status xil_pn:value="ReadyToRun"/>
    117     </transform>
    118     <transform xil_pn:end_ts="1397065387" xil_pn:in_ck="1277596895833658219" xil_pn:name="TRANEXT_xstsynthesize_virtex6" xil_pn:prop_ck="4264687095207808167" xil_pn:start_ts="1397065167">
     295    <transform xil_pn:end_ts="1400574571" xil_pn:in_ck="-1562866336050216827" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1400574571">
     296      <status xil_pn:value="SuccessfullyRun"/>
     297      <status xil_pn:value="ReadyToRun"/>
     298      <status xil_pn:value="OutOfDateForInputs"/>
     299      <status xil_pn:value="OutOfDateForPredecessor"/>
     300      <status xil_pn:value="OutOfDateForOutputs"/>
     301      <status xil_pn:value="InputChanged"/>
     302      <status xil_pn:value="OutputChanged"/>
     303      <outfile xil_pn:name="../CORE_MPI/CORE_MPI.vhd"/>
     304      <outfile xil_pn:name="../CORE_MPI/DEMUX1.vhd"/>
     305      <outfile xil_pn:name="../CORE_MPI/DMA_ARBITER.vhd"/>
     306      <outfile xil_pn:name="../CORE_MPI/EX1_FSM.vhd"/>
     307      <outfile xil_pn:name="../CORE_MPI/EX2_FSM.vhd"/>
     308      <outfile xil_pn:name="../CORE_MPI/EX3_FSM.vhd"/>
     309      <outfile xil_pn:name="../CORE_MPI/EX4_FSM.vhd"/>
     310      <outfile xil_pn:name="../CORE_MPI/Ex0_Fsm.vhd"/>
     311      <outfile xil_pn:name="../CORE_MPI/Ex5_FSM.vhd"/>
     312      <outfile xil_pn:name="../CORE_MPI/FIFO_64_FWFT.vhd"/>
     313      <outfile xil_pn:name="../CORE_MPI/FIfo_mem.vhd"/>
     314      <outfile xil_pn:name="../CORE_MPI/FIfo_proc.vhd"/>
     315      <outfile xil_pn:name="../CORE_MPI/MPICORETEST.vhd"/>
     316      <outfile xil_pn:name="../CORE_MPI/MPI_CORE_SCHEDULER.vhd"/>
     317      <outfile xil_pn:name="../CORE_MPI/MPI_NOC.vhd"/>
     318      <outfile xil_pn:name="../CORE_MPI/MPI_PKG.vhd"/>
     319      <outfile xil_pn:name="../CORE_MPI/MPI_RMA.vhd"/>
     320      <outfile xil_pn:name="../CORE_MPI/MUX1.vhd"/>
     321      <outfile xil_pn:name="../CORE_MPI/MUX8.vhd"/>
     322      <outfile xil_pn:name="../CORE_MPI/MultiMPITest.vhd"/>
     323      <outfile xil_pn:name="../CORE_MPI/Packet_type.vhd"/>
     324      <outfile xil_pn:name="../CORE_MPI/RAM_32_32.vhd"/>
     325      <outfile xil_pn:name="../CORE_MPI/RAM_64.vhd"/>
     326      <outfile xil_pn:name="../CORE_MPI/RAM_MUX.vhd"/>
     327      <outfile xil_pn:name="../CORE_MPI/SetBit.vhd"/>
     328      <outfile xil_pn:name="../CORE_MPI/image_pkg.vhd"/>
     329      <outfile xil_pn:name="../CORE_MPI/load_instr.vhd"/>
     330      <outfile xil_pn:name="../CORE_MPI/round_robbin_machine.vhd"/>
     331      <outfile xil_pn:name="../CORE_MPI/test_DMA.vhd"/>
     332      <outfile xil_pn:name="../HCL_Arch_conf.vhd"/>
     333      <outfile xil_pn:name="../HT_process.vhd"/>
     334      <outfile xil_pn:name="../Hold_FSM.vhd"/>
     335      <outfile xil_pn:name="../IP_Timer.vhd"/>
     336      <outfile xil_pn:name="../NOC/Arbiter.vhd"/>
     337      <outfile xil_pn:name="../NOC/CoreTypes.vhd"/>
     338      <outfile xil_pn:name="../NOC/Crossbar.vhd"/>
     339      <outfile xil_pn:name="../NOC/Crossbit.vhd"/>
     340      <outfile xil_pn:name="../NOC/Def_Request.vhd"/>
     341      <outfile xil_pn:name="../NOC/FIFO_256_FWFT.vhd"/>
     342      <outfile xil_pn:name="../NOC/FIFO_DP.vhd"/>
     343      <outfile xil_pn:name="../NOC/INPUT_PORT_MODULE.vhd"/>
     344      <outfile xil_pn:name="../NOC/NOC_tree.vhd"/>
     345      <outfile xil_pn:name="../NOC/OUTPUT_PORT_MODULE.vhd"/>
     346      <outfile xil_pn:name="../NOC/PortRam.vhd"/>
     347      <outfile xil_pn:name="../NOC/Proto_receiv.vhd"/>
     348      <outfile xil_pn:name="../NOC/RAM_256.vhd"/>
     349      <outfile xil_pn:name="../NOC/SCHEDULER10_10.VHD"/>
     350      <outfile xil_pn:name="../NOC/SCHEDULER11_11.VHD"/>
     351      <outfile xil_pn:name="../NOC/SCHEDULER12_12.VHD"/>
     352      <outfile xil_pn:name="../NOC/SCHEDULER13_13.VHD"/>
     353      <outfile xil_pn:name="../NOC/SCHEDULER14_14.VHD"/>
     354      <outfile xil_pn:name="../NOC/SCHEDULER15_15.VHD"/>
     355      <outfile xil_pn:name="../NOC/SCHEDULER16_16.VHD"/>
     356      <outfile xil_pn:name="../NOC/SCHEDULER2_2.VHD"/>
     357      <outfile xil_pn:name="../NOC/SCHEDULER3_3.VHD"/>
     358      <outfile xil_pn:name="../NOC/SCHEDULER4_4.VHD"/>
     359      <outfile xil_pn:name="../NOC/SCHEDULER5_5.VHD"/>
     360      <outfile xil_pn:name="../NOC/SCHEDULER6_6.VHD"/>
     361      <outfile xil_pn:name="../NOC/SCHEDULER7_7.VHD"/>
     362      <outfile xil_pn:name="../NOC/SCHEDULER8_8.VHD"/>
     363      <outfile xil_pn:name="../NOC/SCHEDULER9_9.VHD"/>
     364      <outfile xil_pn:name="../NOC/SWITCH_GEN.vhd"/>
     365      <outfile xil_pn:name="../NOC/SWITCH_GENERIQUE.vhd"/>
     366      <outfile xil_pn:name="../NOC/Scheduler.vhd"/>
     367      <outfile xil_pn:name="../NOC/conv.vhd"/>
     368      <outfile xil_pn:name="../NOC/proto_send.vhd"/>
     369      <outfile xil_pn:name="../NOC/stimuli1.vhd"/>
     370      <outfile xil_pn:name="../NOC/test_noc_tree.vhd"/>
     371      <outfile xil_pn:name="../NOC/test_xbar_8x8.vhd"/>
     372      <outfile xil_pn:name="../PE.vhd"/>
     373      <outfile xil_pn:name="../mpi_test.vhd"/>
     374      <outfile xil_pn:name="ipcore_dir/mem8k8.vhd"/>
     375      <outfile xil_pn:name="simu_tree.vhd"/>
     376    </transform>
     377    <transform xil_pn:end_ts="1400574588" xil_pn:in_ck="-1562866336050216827" xil_pn:name="TRAN_MSimulateBehavioralModel" xil_pn:prop_ck="1609861126049403543" xil_pn:start_ts="1400574571">
     378      <status xil_pn:value="SuccessfullyRun"/>
     379      <status xil_pn:value="ReadyToRun"/>
     380      <status xil_pn:value="OutOfDateForInputs"/>
     381      <status xil_pn:value="OutOfDateForPredecessor"/>
     382      <status xil_pn:value="OutOfDateForOutputs"/>
     383      <status xil_pn:value="InputChanged"/>
     384      <status xil_pn:value="OutputChanged"/>
     385      <outfile xil_pn:name="simu_tree.fdo"/>
     386      <outfile xil_pn:name="vsim.wlf"/>
     387      <outfile xil_pn:name="work"/>
     388    </transform>
     389    <transform xil_pn:end_ts="1397218827" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1397218827">
     390      <status xil_pn:value="SuccessfullyRun"/>
     391      <status xil_pn:value="ReadyToRun"/>
     392    </transform>
     393    <transform xil_pn:end_ts="1399046270" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="8468098917384163338" xil_pn:start_ts="1399046270">
     394      <status xil_pn:value="SuccessfullyRun"/>
     395      <status xil_pn:value="ReadyToRun"/>
     396    </transform>
     397    <transform xil_pn:end_ts="1399046272" xil_pn:in_ck="-4721685615919775683" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-83444157416746671" xil_pn:start_ts="1399046270">
     398      <status xil_pn:value="SuccessfullyRun"/>
     399      <status xil_pn:value="ReadyToRun"/>
     400    </transform>
     401    <transform xil_pn:end_ts="1399046272" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1399046272">
     402      <status xil_pn:value="SuccessfullyRun"/>
     403      <status xil_pn:value="ReadyToRun"/>
     404    </transform>
     405    <transform xil_pn:end_ts="1399046272" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-6814437710028855700" xil_pn:start_ts="1399046272">
     406      <status xil_pn:value="SuccessfullyRun"/>
     407      <status xil_pn:value="ReadyToRun"/>
     408    </transform>
     409    <transform xil_pn:end_ts="1399046272" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="3206529612922900429" xil_pn:start_ts="1399046272">
     410      <status xil_pn:value="SuccessfullyRun"/>
     411      <status xil_pn:value="ReadyToRun"/>
     412    </transform>
     413    <transform xil_pn:end_ts="1399046272" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="3604293158989973787" xil_pn:start_ts="1399046272">
     414      <status xil_pn:value="SuccessfullyRun"/>
     415      <status xil_pn:value="ReadyToRun"/>
     416    </transform>
     417    <transform xil_pn:end_ts="1400569081" xil_pn:in_ck="-3921163766406526424" xil_pn:name="TRANEXT_xstsynthesize_virtex6" xil_pn:prop_ck="-384648266013009569" xil_pn:start_ts="1400568915">
    119418      <status xil_pn:value="SuccessfullyRun"/>
    120419      <status xil_pn:value="WarningsGenerated"/>
    121420      <status xil_pn:value="ReadyToRun"/>
    122       <status xil_pn:value="OutOfDateForOutputs"/>
    123       <status xil_pn:value="OutputChanged"/>
    124       <outfile xil_pn:name="MultiMPITest.lso"/>
    125       <outfile xil_pn:name="MultiMPITest.ngc"/>
    126       <outfile xil_pn:name="MultiMPITest.ngr"/>
    127       <outfile xil_pn:name="MultiMPITest.prj"/>
    128       <outfile xil_pn:name="MultiMPITest.stx"/>
    129       <outfile xil_pn:name="MultiMPITest.syr"/>
    130       <outfile xil_pn:name="MultiMPITest.xst"/>
    131       <outfile xil_pn:name="MultiMPITest_xst.xrpt"/>
     421      <status xil_pn:value="OutOfDateForInputs"/>
     422      <status xil_pn:value="InputChanged"/>
     423      <outfile xil_pn:name="INPUT_PORT_MODULE.ngr"/>
     424      <outfile xil_pn:name="NOC_tree.ngr"/>
    132425      <outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
     426      <outfile xil_pn:name="test_tree_8x8.lso"/>
     427      <outfile xil_pn:name="test_tree_8x8.ngc"/>
     428      <outfile xil_pn:name="test_tree_8x8.ngr"/>
     429      <outfile xil_pn:name="test_tree_8x8.prj"/>
     430      <outfile xil_pn:name="test_tree_8x8.stx"/>
     431      <outfile xil_pn:name="test_tree_8x8.syr"/>
     432      <outfile xil_pn:name="test_tree_8x8.xst"/>
     433      <outfile xil_pn:name="test_tree_8x8_xst.xrpt"/>
    133434      <outfile xil_pn:name="webtalk_pn.xml"/>
    134435      <outfile xil_pn:name="xst"/>
    135436    </transform>
    136     <transform xil_pn:end_ts="1397065387" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-4542759591300251492" xil_pn:start_ts="1397065387">
    137       <status xil_pn:value="SuccessfullyRun"/>
    138       <status xil_pn:value="ReadyToRun"/>
    139     </transform>
    140     <transform xil_pn:end_ts="1397065428" xil_pn:in_ck="-8086002020225495248" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="6806536488953865956" xil_pn:start_ts="1397065387">
    141       <status xil_pn:value="SuccessfullyRun"/>
    142       <status xil_pn:value="ReadyToRun"/>
    143       <outfile xil_pn:name="MultiMPITest.bld"/>
    144       <outfile xil_pn:name="MultiMPITest.ngd"/>
    145       <outfile xil_pn:name="MultiMPITest_ngdbuild.xrpt"/>
     437    <transform xil_pn:end_ts="1398966148" xil_pn:in_ck="2859792709664363507" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="1272206509727528225" xil_pn:start_ts="1398966148">
     438      <status xil_pn:value="SuccessfullyRun"/>
     439      <status xil_pn:value="ReadyToRun"/>
     440    </transform>
     441    <transform xil_pn:end_ts="1399046810" xil_pn:in_ck="421470291212023124" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="4605975241377538732" xil_pn:start_ts="1399046777">
     442      <status xil_pn:value="SuccessfullyRun"/>
     443      <status xil_pn:value="ReadyToRun"/>
     444      <status xil_pn:value="OutOfDateForInputs"/>
     445      <status xil_pn:value="OutOfDateForPredecessor"/>
     446      <status xil_pn:value="InputChanged"/>
    146447      <outfile xil_pn:name="_ngo"/>
    147448      <outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
    148     </transform>
    149     <transform xil_pn:end_ts="1397065815" xil_pn:in_ck="2034496922163271928" xil_pn:name="TRANEXT_map_virtex7" xil_pn:prop_ck="-9088675071633060577" xil_pn:start_ts="1397065428">
     449      <outfile xil_pn:name="test_tree_8x8.bld"/>
     450      <outfile xil_pn:name="test_tree_8x8.ngd"/>
     451      <outfile xil_pn:name="test_tree_8x8_ngdbuild.xrpt"/>
     452    </transform>
     453    <transform xil_pn:end_ts="1399046952" xil_pn:in_ck="6627695165874816958" xil_pn:name="TRANEXT_map_virtex7" xil_pn:prop_ck="-2080211183630724906" xil_pn:start_ts="1399046810">
    150454      <status xil_pn:value="SuccessfullyRun"/>
    151455      <status xil_pn:value="WarningsGenerated"/>
    152456      <status xil_pn:value="ReadyToRun"/>
    153       <outfile xil_pn:name="MultiMPITest.pcf"/>
    154       <outfile xil_pn:name="MultiMPITest_map.map"/>
    155       <outfile xil_pn:name="MultiMPITest_map.mrp"/>
    156       <outfile xil_pn:name="MultiMPITest_map.ncd"/>
    157       <outfile xil_pn:name="MultiMPITest_map.ngm"/>
    158       <outfile xil_pn:name="MultiMPITest_map.xrpt"/>
    159       <outfile xil_pn:name="MultiMPITest_summary.xml"/>
    160       <outfile xil_pn:name="MultiMPITest_usage.xml"/>
     457      <status xil_pn:value="OutOfDateForPredecessor"/>
    161458      <outfile xil_pn:name="_xmsgs/map.xmsgs"/>
    162     </transform>
    163     <transform xil_pn:end_ts="1397066096" xil_pn:in_ck="-7713434038111607791" xil_pn:name="TRANEXT_par_virtex5" xil_pn:prop_ck="-4101483914851371285" xil_pn:start_ts="1397065815">
     459      <outfile xil_pn:name="test_tree_8x8.pcf"/>
     460      <outfile xil_pn:name="test_tree_8x8_map.map"/>
     461      <outfile xil_pn:name="test_tree_8x8_map.mrp"/>
     462      <outfile xil_pn:name="test_tree_8x8_map.ncd"/>
     463      <outfile xil_pn:name="test_tree_8x8_map.ngm"/>
     464      <outfile xil_pn:name="test_tree_8x8_map.xrpt"/>
     465      <outfile xil_pn:name="test_tree_8x8_summary.xml"/>
     466      <outfile xil_pn:name="test_tree_8x8_usage.xml"/>
     467    </transform>
     468    <transform xil_pn:end_ts="1399047097" xil_pn:in_ck="-615742213859023607" xil_pn:name="TRANEXT_par_virtex5" xil_pn:prop_ck="-2224445544780208925" xil_pn:start_ts="1399046952">
    164469      <status xil_pn:value="SuccessfullyRun"/>
    165470      <status xil_pn:value="WarningsGenerated"/>
    166471      <status xil_pn:value="ReadyToRun"/>
    167       <outfile xil_pn:name="MultiMPITest.ncd"/>
    168       <outfile xil_pn:name="MultiMPITest.pad"/>
    169       <outfile xil_pn:name="MultiMPITest.par"/>
    170       <outfile xil_pn:name="MultiMPITest.ptwx"/>
    171       <outfile xil_pn:name="MultiMPITest.unroutes"/>
    172       <outfile xil_pn:name="MultiMPITest.xpi"/>
    173       <outfile xil_pn:name="MultiMPITest_pad.csv"/>
    174       <outfile xil_pn:name="MultiMPITest_pad.txt"/>
    175       <outfile xil_pn:name="MultiMPITest_par.xrpt"/>
     472      <status xil_pn:value="OutOfDateForPredecessor"/>
    176473      <outfile xil_pn:name="_xmsgs/par.xmsgs"/>
    177     </transform>
    178     <transform xil_pn:end_ts="1397066096" xil_pn:in_ck="2034496922163271796" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1397066041">
    179       <status xil_pn:value="SuccessfullyRun"/>
    180       <status xil_pn:value="ReadyToRun"/>
    181       <status xil_pn:value="OutOfDateForOutputs"/>
    182       <status xil_pn:value="OutputChanged"/>
    183       <outfile xil_pn:name="MultiMPITest.twr"/>
    184       <outfile xil_pn:name="MultiMPITest.twx"/>
     474      <outfile xil_pn:name="test_tree_8x8.ncd"/>
     475      <outfile xil_pn:name="test_tree_8x8.pad"/>
     476      <outfile xil_pn:name="test_tree_8x8.par"/>
     477      <outfile xil_pn:name="test_tree_8x8.ptwx"/>
     478      <outfile xil_pn:name="test_tree_8x8.unroutes"/>
     479      <outfile xil_pn:name="test_tree_8x8.xpi"/>
     480      <outfile xil_pn:name="test_tree_8x8_pad.csv"/>
     481      <outfile xil_pn:name="test_tree_8x8_pad.txt"/>
     482      <outfile xil_pn:name="test_tree_8x8_par.xrpt"/>
     483    </transform>
     484    <transform xil_pn:end_ts="1399047059" xil_pn:in_ck="-3872251990810369121" xil_pn:name="TRAN_clkRegionRpt" xil_pn:start_ts="1399047027">
     485      <status xil_pn:value="SuccessfullyRun"/>
     486      <status xil_pn:value="ReadyToRun"/>
     487      <status xil_pn:value="OutOfDateForPredecessor"/>
     488      <outfile xil_pn:name="test_tree_8x8.clk_rgn"/>
     489    </transform>
     490    <transform xil_pn:end_ts="1399047097" xil_pn:in_ck="1726028384799355954" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1399047059">
     491      <status xil_pn:value="SuccessfullyRun"/>
     492      <status xil_pn:value="ReadyToRun"/>
     493      <status xil_pn:value="OutOfDateForPredecessor"/>
    185494      <outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
    186     </transform>
    187     <transform xil_pn:end_ts="1397066405" xil_pn:in_ck="-7713434038111607791" xil_pn:name="TRAN_preRouteTrce" xil_pn:prop_ck="722859607460791352" xil_pn:start_ts="1397066336">
    188       <status xil_pn:value="SuccessfullyRun"/>
    189       <status xil_pn:value="ReadyToRun"/>
    190       <outfile xil_pn:name="MultiMPITest_preroute.twr"/>
    191       <outfile xil_pn:name="MultiMPITest_preroute.twx"/>
    192       <outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
     495      <outfile xil_pn:name="test_tree_8x8.twr"/>
     496      <outfile xil_pn:name="test_tree_8x8.twx"/>
    193497    </transform>
    194498  </transforms>

  • PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.0/Test_Timer/Test_Timer.xise

    r137 r139  
    1010    <!-- implement in ISE Project Navigator.                               -->
    1111    <!--                                                                   -->
    12     <!-- Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved. -->
     12    <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
    1313  </header>
    1414
    15   <version xil_pn:ise_version="13.3" xil_pn:schema_version="2"/>
     15  <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
    1616
    1717  <files>
    18     <file xil_pn:name="../NoC/Arbiter.vhd" xil_pn:type="FILE_VHDL">
     18    <file xil_pn:name="../NOC/Arbiter.vhd" xil_pn:type="FILE_VHDL">
    1919      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
    2020      <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
    2121      <library xil_pn:name="NoCLib"/>
    2222    </file>
    23     <file xil_pn:name="../NoC/conv.vhd" xil_pn:type="FILE_VHDL">
    24       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
    25       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    26       <library xil_pn:name="NoCLib"/>
    27     </file>
    28     <file xil_pn:name="../NoC/CoreTypes.vhd" xil_pn:type="FILE_VHDL">
     23    <file xil_pn:name="../NOC/conv.vhd" xil_pn:type="FILE_VHDL">
     24      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
     25      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     26      <library xil_pn:name="NoCLib"/>
     27    </file>
     28    <file xil_pn:name="../NOC/CoreTypes.vhd" xil_pn:type="FILE_VHDL">
    2929      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
    3030      <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
    3131      <library xil_pn:name="NoCLib"/>
    3232    </file>
    33     <file xil_pn:name="../NoC/Crossbar.vhd" xil_pn:type="FILE_VHDL">
    34       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="32"/>
    35       <association xil_pn:name="Implementation" xil_pn:seqID="32"/>
    36       <library xil_pn:name="NoCLib"/>
    37     </file>
    38     <file xil_pn:name="../NoC/Crossbit.vhd" xil_pn:type="FILE_VHDL">
     33    <file xil_pn:name="../NOC/Crossbar.vhd" xil_pn:type="FILE_VHDL">
     34      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/>
     35      <association xil_pn:name="Implementation" xil_pn:seqID="24"/>
     36      <library xil_pn:name="NoCLib"/>
     37    </file>
     38    <file xil_pn:name="../NOC/Crossbit.vhd" xil_pn:type="FILE_VHDL">
     39      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
     40      <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
     41      <library xil_pn:name="NoCLib"/>
     42    </file>
     43    <file xil_pn:name="../NOC/FIFO_256_FWFT.vhd" xil_pn:type="FILE_VHDL">
     44      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
     45      <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
     46      <library xil_pn:name="NoCLib"/>
     47    </file>
     48    <file xil_pn:name="../NOC/FIFO_DP.vhd" xil_pn:type="FILE_VHDL">
     49      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
     50      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     51      <library xil_pn:name="NoCLib"/>
     52    </file>
     53    <file xil_pn:name="../NOC/INPUT_PORT_MODULE.vhd" xil_pn:type="FILE_VHDL">
     54      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/>
     55      <association xil_pn:name="Implementation" xil_pn:seqID="23"/>
     56      <library xil_pn:name="NoCLib"/>
     57    </file>
     58    <file xil_pn:name="../NOC/OUTPUT_PORT_MODULE.vhd" xil_pn:type="FILE_VHDL">
    3959      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/>
    4060      <association xil_pn:name="Implementation" xil_pn:seqID="22"/>
    4161      <library xil_pn:name="NoCLib"/>
    4262    </file>
    43     <file xil_pn:name="../NoC/FIFO_256_FWFT.vhd" xil_pn:type="FILE_VHDL">
     63    <file xil_pn:name="../NOC/PortRam.vhd" xil_pn:type="FILE_VHDL">
     64      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
     65      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     66      <library xil_pn:name="NoCLib"/>
     67    </file>
     68    <file xil_pn:name="../NOC/Proto_receiv.vhd" xil_pn:type="FILE_VHDL">
     69      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
     70      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     71      <library xil_pn:name="NoCLib"/>
     72    </file>
     73    <file xil_pn:name="../NOC/proto_send.vhd" xil_pn:type="FILE_VHDL">
     74      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
     75      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     76      <library xil_pn:name="NoCLib"/>
     77    </file>
     78    <file xil_pn:name="../NOC/RAM_256.vhd" xil_pn:type="FILE_VHDL">
     79      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
     80      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     81      <library xil_pn:name="NoCLib"/>
     82    </file>
     83    <file xil_pn:name="../NOC/Scheduler.vhd" xil_pn:type="FILE_VHDL">
    4484      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/>
    4585      <association xil_pn:name="Implementation" xil_pn:seqID="21"/>
    4686      <library xil_pn:name="NoCLib"/>
    4787    </file>
    48     <file xil_pn:name="../NoC/FIFO_DP.vhd" xil_pn:type="FILE_VHDL">
    49       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
    50       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    51       <library xil_pn:name="NoCLib"/>
    52     </file>
    53     <file xil_pn:name="../NoC/INPUT_PORT_MODULE.vhd" xil_pn:type="FILE_VHDL">
    54       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="31"/>
    55       <association xil_pn:name="Implementation" xil_pn:seqID="31"/>
    56       <library xil_pn:name="NoCLib"/>
    57     </file>
    58     <file xil_pn:name="../NoC/OUTPUT_PORT_MODULE.vhd" xil_pn:type="FILE_VHDL">
    59       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="30"/>
    60       <association xil_pn:name="Implementation" xil_pn:seqID="30"/>
    61       <library xil_pn:name="NoCLib"/>
    62     </file>
    63     <file xil_pn:name="../NoC/PortRam.vhd" xil_pn:type="FILE_VHDL">
    64       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
    65       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    66       <library xil_pn:name="NoCLib"/>
    67     </file>
    68     <file xil_pn:name="../NoC/Proto_receiv.vhd" xil_pn:type="FILE_VHDL">
    69       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
    70       <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
    71       <library xil_pn:name="NoCLib"/>
    72     </file>
    73     <file xil_pn:name="../NoC/proto_send.vhd" xil_pn:type="FILE_VHDL">
    74       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
    75       <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
    76       <library xil_pn:name="NoCLib"/>
    77     </file>
    78     <file xil_pn:name="../NoC/RAM_256.vhd" xil_pn:type="FILE_VHDL">
    79       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
    80       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    81       <library xil_pn:name="NoCLib"/>
    82     </file>
    83     <file xil_pn:name="../NoC/Scheduler.vhd" xil_pn:type="FILE_VHDL">
    84       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="29"/>
    85       <association xil_pn:name="Implementation" xil_pn:seqID="29"/>
    86       <library xil_pn:name="NoCLib"/>
    87     </file>
    88     <file xil_pn:name="../NoC/SCHEDULER10_10.VHD" xil_pn:type="FILE_VHDL">
     88    <file xil_pn:name="../NOC/SCHEDULER10_10.VHD" xil_pn:type="FILE_VHDL">
    8989      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
    9090      <association xil_pn:name="Implementation" xil_pn:seqID="18"/>
    9191      <library xil_pn:name="NoCLib"/>
    9292    </file>
    93     <file xil_pn:name="../NoC/SCHEDULER11_11.VHD" xil_pn:type="FILE_VHDL">
     93    <file xil_pn:name="../NOC/SCHEDULER11_11.VHD" xil_pn:type="FILE_VHDL">
    9494      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
    9595      <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
    9696      <library xil_pn:name="NoCLib"/>
    9797    </file>
    98     <file xil_pn:name="../NoC/SCHEDULER12_12.VHD" xil_pn:type="FILE_VHDL">
     98    <file xil_pn:name="../NOC/SCHEDULER12_12.VHD" xil_pn:type="FILE_VHDL">
    9999      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
    100100      <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
    101101      <library xil_pn:name="NoCLib"/>
    102102    </file>
    103     <file xil_pn:name="../NoC/SCHEDULER13_13.VHD" xil_pn:type="FILE_VHDL">
     103    <file xil_pn:name="../NOC/SCHEDULER13_13.VHD" xil_pn:type="FILE_VHDL">
    104104      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
    105105      <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
    106106      <library xil_pn:name="NoCLib"/>
    107107    </file>
    108     <file xil_pn:name="../NoC/SCHEDULER14_14.VHD" xil_pn:type="FILE_VHDL">
     108    <file xil_pn:name="../NOC/SCHEDULER14_14.VHD" xil_pn:type="FILE_VHDL">
    109109      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
    110110      <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
    111111      <library xil_pn:name="NoCLib"/>
    112112    </file>
    113     <file xil_pn:name="../NoC/SCHEDULER15_15.VHD" xil_pn:type="FILE_VHDL">
     113    <file xil_pn:name="../NOC/SCHEDULER15_15.VHD" xil_pn:type="FILE_VHDL">
    114114      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
    115115      <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
    116116      <library xil_pn:name="NoCLib"/>
    117117    </file>
    118     <file xil_pn:name="../NoC/SCHEDULER16_16.VHD" xil_pn:type="FILE_VHDL">
     118    <file xil_pn:name="../NOC/SCHEDULER16_16.VHD" xil_pn:type="FILE_VHDL">
    119119      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
    120120      <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
    121121      <library xil_pn:name="NoCLib"/>
    122122    </file>
    123     <file xil_pn:name="../NoC/SCHEDULER2_2.VHD" xil_pn:type="FILE_VHDL">
     123    <file xil_pn:name="../NOC/SCHEDULER2_2.VHD" xil_pn:type="FILE_VHDL">
    124124      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
    125125      <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
    126126      <library xil_pn:name="NoCLib"/>
    127127    </file>
    128     <file xil_pn:name="../NoC/SCHEDULER3_3.VHD" xil_pn:type="FILE_VHDL">
     128    <file xil_pn:name="../NOC/SCHEDULER3_3.VHD" xil_pn:type="FILE_VHDL">
    129129      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
    130130      <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
    131131      <library xil_pn:name="NoCLib"/>
    132132    </file>
    133     <file xil_pn:name="../NoC/SCHEDULER4_4.VHD" xil_pn:type="FILE_VHDL">
     133    <file xil_pn:name="../NOC/SCHEDULER4_4.VHD" xil_pn:type="FILE_VHDL">
    134134      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
    135135      <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
    136136      <library xil_pn:name="NoCLib"/>
    137137    </file>
    138     <file xil_pn:name="../NoC/SCHEDULER5_5.VHD" xil_pn:type="FILE_VHDL">
     138    <file xil_pn:name="../NOC/SCHEDULER5_5.VHD" xil_pn:type="FILE_VHDL">
    139139      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
    140140      <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
    141141      <library xil_pn:name="NoCLib"/>
    142142    </file>
    143     <file xil_pn:name="../NoC/SCHEDULER6_6.VHD" xil_pn:type="FILE_VHDL">
     143    <file xil_pn:name="../NOC/SCHEDULER6_6.VHD" xil_pn:type="FILE_VHDL">
    144144      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
    145145      <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
    146146      <library xil_pn:name="NoCLib"/>
    147147    </file>
    148     <file xil_pn:name="../NoC/SCHEDULER7_7.VHD" xil_pn:type="FILE_VHDL">
     148    <file xil_pn:name="../NOC/SCHEDULER7_7.VHD" xil_pn:type="FILE_VHDL">
    149149      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
    150150      <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
    151151      <library xil_pn:name="NoCLib"/>
    152152    </file>
    153     <file xil_pn:name="../NoC/SCHEDULER8_8.VHD" xil_pn:type="FILE_VHDL">
     153    <file xil_pn:name="../NOC/SCHEDULER8_8.VHD" xil_pn:type="FILE_VHDL">
    154154      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
    155155      <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
    156156      <library xil_pn:name="NoCLib"/>
    157157    </file>
    158     <file xil_pn:name="../NoC/SCHEDULER9_9.VHD" xil_pn:type="FILE_VHDL">
     158    <file xil_pn:name="../NOC/SCHEDULER9_9.VHD" xil_pn:type="FILE_VHDL">
    159159      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
    160160      <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
    161161      <library xil_pn:name="NoCLib"/>
    162162    </file>
    163     <file xil_pn:name="../NoC/stimuli1.vhd" xil_pn:type="FILE_VHDL">
    164       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
    165       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    166       <library xil_pn:name="NoCLib"/>
    167     </file>
    168     <file xil_pn:name="../NoC/SWITCH_GEN.vhd" xil_pn:type="FILE_VHDL">
    169       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="45"/>
    170       <association xil_pn:name="Implementation" xil_pn:seqID="45"/>
    171       <library xil_pn:name="NoCLib"/>
    172     </file>
    173     <file xil_pn:name="../NoC/SWITCH_GENERIQUE.vhd" xil_pn:type="FILE_VHDL">
    174       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
    175       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    176       <library xil_pn:name="NoCLib"/>
    177     </file>
    178     <file xil_pn:name="../NoC/test_xbar_8x8.vhd" xil_pn:type="FILE_VHDL">
    179       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
    180       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    181       <library xil_pn:name="NoCLib"/>
    182     </file>
    183     <file xil_pn:name="../Core_MPI/CORE_MPI.vhd" xil_pn:type="FILE_VHDL">
    184       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="48"/>
    185       <association xil_pn:name="Implementation" xil_pn:seqID="48"/>
    186       <library xil_pn:name="MPI_HCL"/>
    187     </file>
    188     <file xil_pn:name="../Core_MPI/DEMUX1.vhd" xil_pn:type="FILE_VHDL">
    189       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="28"/>
    190       <association xil_pn:name="Implementation" xil_pn:seqID="28"/>
    191       <library xil_pn:name="MPI_HCL"/>
    192     </file>
    193     <file xil_pn:name="../Core_MPI/DMA_ARBITER.vhd" xil_pn:type="FILE_VHDL">
    194       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="43"/>
    195       <association xil_pn:name="Implementation" xil_pn:seqID="43"/>
    196       <library xil_pn:name="MPI_HCL"/>
    197     </file>
    198     <file xil_pn:name="../Core_MPI/Ex0_Fsm.vhd" xil_pn:type="FILE_VHDL">
    199       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="42"/>
    200       <association xil_pn:name="Implementation" xil_pn:seqID="42"/>
    201       <library xil_pn:name="MPI_HCL"/>
    202     </file>
    203     <file xil_pn:name="../Core_MPI/EX1_FSM.vhd" xil_pn:type="FILE_VHDL">
    204       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="41"/>
    205       <association xil_pn:name="Implementation" xil_pn:seqID="41"/>
    206       <library xil_pn:name="MPI_HCL"/>
    207     </file>
    208     <file xil_pn:name="../Core_MPI/EX2_FSM.vhd" xil_pn:type="FILE_VHDL">
    209       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="40"/>
    210       <association xil_pn:name="Implementation" xil_pn:seqID="40"/>
    211       <library xil_pn:name="MPI_HCL"/>
    212     </file>
    213     <file xil_pn:name="../Core_MPI/EX3_FSM.vhd" xil_pn:type="FILE_VHDL">
    214       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="39"/>
    215       <association xil_pn:name="Implementation" xil_pn:seqID="39"/>
    216       <library xil_pn:name="MPI_HCL"/>
    217     </file>
    218     <file xil_pn:name="../Core_MPI/EX4_FSM.vhd" xil_pn:type="FILE_VHDL">
    219       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="38"/>
    220       <association xil_pn:name="Implementation" xil_pn:seqID="38"/>
    221       <library xil_pn:name="MPI_HCL"/>
    222     </file>
    223     <file xil_pn:name="../Core_MPI/Ex5_FSM.vhd" xil_pn:type="FILE_VHDL">
    224       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
    225       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    226       <library xil_pn:name="MPI_HCL"/>
    227     </file>
    228     <file xil_pn:name="../Core_MPI/FIFO_64_FWFT.vhd" xil_pn:type="FILE_VHDL">
    229       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="37"/>
    230       <association xil_pn:name="Implementation" xil_pn:seqID="37"/>
    231       <library xil_pn:name="MPI_HCL"/>
    232     </file>
    233     <file xil_pn:name="../Core_MPI/FIfo_mem.vhd" xil_pn:type="FILE_VHDL">
    234       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
    235       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    236       <library xil_pn:name="MPI_HCL"/>
    237     </file>
    238     <file xil_pn:name="../Core_MPI/FIfo_proc.vhd" xil_pn:type="FILE_VHDL">
    239       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
    240       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    241       <library xil_pn:name="MPI_HCL"/>
    242     </file>
    243     <file xil_pn:name="../Core_MPI/image_pkg.vhd" xil_pn:type="FILE_VHDL">
    244       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
    245       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    246       <library xil_pn:name="MPI_HCL"/>
    247     </file>
    248     <file xil_pn:name="../Core_MPI/load_instr.vhd" xil_pn:type="FILE_VHDL">
    249       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="36"/>
    250       <association xil_pn:name="Implementation" xil_pn:seqID="36"/>
    251       <library xil_pn:name="MPI_HCL"/>
    252     </file>
    253     <file xil_pn:name="../Core_MPI/MPICORETEST.vhd" xil_pn:type="FILE_VHDL">
    254       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
    255       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    256       <library xil_pn:name="MPI_HCL"/>
    257     </file>
    258     <file xil_pn:name="../Core_MPI/MPI_CORE_SCHEDULER.vhd" xil_pn:type="FILE_VHDL">
    259       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="35"/>
    260       <association xil_pn:name="Implementation" xil_pn:seqID="35"/>
    261       <library xil_pn:name="MPI_HCL"/>
    262     </file>
    263     <file xil_pn:name="../Core_MPI/MPI_NOC.vhd" xil_pn:type="FILE_VHDL">
    264       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="51"/>
    265       <association xil_pn:name="Implementation" xil_pn:seqID="51"/>
    266       <library xil_pn:name="MPI_HCL"/>
    267     </file>
    268     <file xil_pn:name="../Core_MPI/MPI_PKG.vhd" xil_pn:type="FILE_VHDL">
    269       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
    270       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    271       <library xil_pn:name="MPI_HCL"/>
    272     </file>
    273     <file xil_pn:name="../Core_MPI/MPI_RMA.vhd" xil_pn:type="FILE_VHDL">
    274       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="34"/>
    275       <association xil_pn:name="Implementation" xil_pn:seqID="34"/>
    276       <library xil_pn:name="MPI_HCL"/>
    277     </file>
    278     <file xil_pn:name="../Core_MPI/MultiMPITest.vhd" xil_pn:type="FILE_VHDL">
    279       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="52"/>
    280       <association xil_pn:name="Implementation" xil_pn:seqID="52"/>
    281     </file>
    282     <file xil_pn:name="../Core_MPI/MUX1.vhd" xil_pn:type="FILE_VHDL">
    283       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/>
    284       <association xil_pn:name="Implementation" xil_pn:seqID="27"/>
    285       <library xil_pn:name="MPI_HCL"/>
    286     </file>
    287     <file xil_pn:name="../Core_MPI/MUX8.vhd" xil_pn:type="FILE_VHDL">
    288       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/>
    289       <association xil_pn:name="Implementation" xil_pn:seqID="26"/>
    290       <library xil_pn:name="MPI_HCL"/>
    291     </file>
    292     <file xil_pn:name="../Core_MPI/Packet_type.vhd" xil_pn:type="FILE_VHDL">
     163    <file xil_pn:name="../NOC/stimuli1.vhd" xil_pn:type="FILE_VHDL">
     164      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
     165      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     166      <library xil_pn:name="NoCLib"/>
     167    </file>
     168    <file xil_pn:name="../NOC/SWITCH_GEN.vhd" xil_pn:type="FILE_VHDL">
    293169      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="25"/>
    294170      <association xil_pn:name="Implementation" xil_pn:seqID="25"/>
    295       <library xil_pn:name="MPI_HCL"/>
    296     </file>
    297     <file xil_pn:name="../Core_MPI/RAM_32_32.vhd" xil_pn:type="FILE_VHDL">
    298       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
    299       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    300       <library xil_pn:name="MPI_HCL"/>
    301     </file>
    302     <file xil_pn:name="../Core_MPI/RAM_64.vhd" xil_pn:type="FILE_VHDL">
    303       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
    304       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    305       <library xil_pn:name="MPI_HCL"/>
    306     </file>
    307     <file xil_pn:name="../Core_MPI/RAM_MUX.vhd" xil_pn:type="FILE_VHDL">
    308       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
    309       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    310       <library xil_pn:name="MPI_HCL"/>
    311     </file>
    312     <file xil_pn:name="../Core_MPI/round_robbin_machine.vhd" xil_pn:type="FILE_VHDL">
    313       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/>
    314       <association xil_pn:name="Implementation" xil_pn:seqID="24"/>
    315       <library xil_pn:name="MPI_HCL"/>
    316     </file>
    317     <file xil_pn:name="../Core_MPI/SetBit.vhd" xil_pn:type="FILE_VHDL">
    318       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/>
    319       <association xil_pn:name="Implementation" xil_pn:seqID="23"/>
    320       <library xil_pn:name="MPI_HCL"/>
    321     </file>
    322     <file xil_pn:name="../Core_MPI/test_DMA.vhd" xil_pn:type="FILE_VHDL">
     171      <library xil_pn:name="NoCLib"/>
     172    </file>
     173    <file xil_pn:name="../NOC/SWITCH_GENERIQUE.vhd" xil_pn:type="FILE_VHDL">
     174      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
     175      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     176      <library xil_pn:name="NoCLib"/>
     177    </file>
     178    <file xil_pn:name="../NOC/test_xbar_8x8.vhd" xil_pn:type="FILE_VHDL">
     179      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
     180      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     181      <library xil_pn:name="NoCLib"/>
     182    </file>
     183    <file xil_pn:name="../CORE_MPI/CORE_MPI.vhd" xil_pn:type="FILE_VHDL">
     184      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
     185      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     186      <library xil_pn:name="MPI_HCL"/>
     187    </file>
     188    <file xil_pn:name="../CORE_MPI/DEMUX1.vhd" xil_pn:type="FILE_VHDL">
     189      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
     190      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     191      <library xil_pn:name="MPI_HCL"/>
     192    </file>
     193    <file xil_pn:name="../CORE_MPI/DMA_ARBITER.vhd" xil_pn:type="FILE_VHDL">
     194      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
     195      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     196      <library xil_pn:name="MPI_HCL"/>
     197    </file>
     198    <file xil_pn:name="../CORE_MPI/Ex0_Fsm.vhd" xil_pn:type="FILE_VHDL">
     199      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
     200      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     201      <library xil_pn:name="MPI_HCL"/>
     202    </file>
     203    <file xil_pn:name="../CORE_MPI/EX1_FSM.vhd" xil_pn:type="FILE_VHDL">
     204      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
     205      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     206      <library xil_pn:name="MPI_HCL"/>
     207    </file>
     208    <file xil_pn:name="../CORE_MPI/EX2_FSM.vhd" xil_pn:type="FILE_VHDL">
     209      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
     210      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     211      <library xil_pn:name="MPI_HCL"/>
     212    </file>
     213    <file xil_pn:name="../CORE_MPI/EX3_FSM.vhd" xil_pn:type="FILE_VHDL">
     214      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
     215      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     216      <library xil_pn:name="MPI_HCL"/>
     217    </file>
     218    <file xil_pn:name="../CORE_MPI/EX4_FSM.vhd" xil_pn:type="FILE_VHDL">
     219      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
     220      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     221      <library xil_pn:name="MPI_HCL"/>
     222    </file>
     223    <file xil_pn:name="../CORE_MPI/Ex5_FSM.vhd" xil_pn:type="FILE_VHDL">
     224      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
     225      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     226      <library xil_pn:name="MPI_HCL"/>
     227    </file>
     228    <file xil_pn:name="../CORE_MPI/FIFO_64_FWFT.vhd" xil_pn:type="FILE_VHDL">
     229      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
     230      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     231      <library xil_pn:name="MPI_HCL"/>
     232    </file>
     233    <file xil_pn:name="../CORE_MPI/FIfo_mem.vhd" xil_pn:type="FILE_VHDL">
     234      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
     235      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     236      <library xil_pn:name="MPI_HCL"/>
     237    </file>
     238    <file xil_pn:name="../CORE_MPI/FIfo_proc.vhd" xil_pn:type="FILE_VHDL">
     239      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
     240      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     241      <library xil_pn:name="MPI_HCL"/>
     242    </file>
     243    <file xil_pn:name="../CORE_MPI/image_pkg.vhd" xil_pn:type="FILE_VHDL">
     244      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
     245      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     246      <library xil_pn:name="MPI_HCL"/>
     247    </file>
     248    <file xil_pn:name="../CORE_MPI/load_instr.vhd" xil_pn:type="FILE_VHDL">
     249      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
     250      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     251      <library xil_pn:name="MPI_HCL"/>
     252    </file>
     253    <file xil_pn:name="../CORE_MPI/MPICORETEST.vhd" xil_pn:type="FILE_VHDL">
     254      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
     255      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     256      <library xil_pn:name="MPI_HCL"/>
     257    </file>
     258    <file xil_pn:name="../CORE_MPI/MPI_CORE_SCHEDULER.vhd" xil_pn:type="FILE_VHDL">
     259      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
     260      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     261      <library xil_pn:name="MPI_HCL"/>
     262    </file>
     263    <file xil_pn:name="../CORE_MPI/MPI_NOC.vhd" xil_pn:type="FILE_VHDL">
     264      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
     265      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     266      <library xil_pn:name="MPI_HCL"/>
     267    </file>
     268    <file xil_pn:name="../CORE_MPI/MPI_PKG.vhd" xil_pn:type="FILE_VHDL">
     269      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
     270      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     271      <library xil_pn:name="MPI_HCL"/>
     272    </file>
     273    <file xil_pn:name="../CORE_MPI/MPI_RMA.vhd" xil_pn:type="FILE_VHDL">
     274      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
     275      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     276      <library xil_pn:name="MPI_HCL"/>
     277    </file>
     278    <file xil_pn:name="../CORE_MPI/MultiMPITest.vhd" xil_pn:type="FILE_VHDL">
     279      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
     280      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     281    </file>
     282    <file xil_pn:name="../CORE_MPI/MUX1.vhd" xil_pn:type="FILE_VHDL">
     283      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
     284      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     285      <library xil_pn:name="MPI_HCL"/>
     286    </file>
     287    <file xil_pn:name="../CORE_MPI/MUX8.vhd" xil_pn:type="FILE_VHDL">
     288      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
     289      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     290      <library xil_pn:name="MPI_HCL"/>
     291    </file>
     292    <file xil_pn:name="../CORE_MPI/Packet_type.vhd" xil_pn:type="FILE_VHDL">
     293      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
     294      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     295      <library xil_pn:name="MPI_HCL"/>
     296    </file>
     297    <file xil_pn:name="../CORE_MPI/RAM_32_32.vhd" xil_pn:type="FILE_VHDL">
     298      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
     299      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     300      <library xil_pn:name="MPI_HCL"/>
     301    </file>
     302    <file xil_pn:name="../CORE_MPI/RAM_64.vhd" xil_pn:type="FILE_VHDL">
     303      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
     304      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     305      <library xil_pn:name="MPI_HCL"/>
     306    </file>
     307    <file xil_pn:name="../CORE_MPI/RAM_MUX.vhd" xil_pn:type="FILE_VHDL">
     308      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
     309      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     310      <library xil_pn:name="MPI_HCL"/>
     311    </file>
     312    <file xil_pn:name="../CORE_MPI/round_robbin_machine.vhd" xil_pn:type="FILE_VHDL">
     313      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
     314      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     315      <library xil_pn:name="MPI_HCL"/>
     316    </file>
     317    <file xil_pn:name="../CORE_MPI/SetBit.vhd" xil_pn:type="FILE_VHDL">
     318      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
     319      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     320      <library xil_pn:name="MPI_HCL"/>
     321    </file>
     322    <file xil_pn:name="../CORE_MPI/test_DMA.vhd" xil_pn:type="FILE_VHDL">
    323323      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
    324324      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    … …  
    326326    </file>
    327327    <file xil_pn:name="../HCL_Arch_conf.vhd" xil_pn:type="FILE_VHDL">
    328       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="50"/>
    329       <association xil_pn:name="Implementation" xil_pn:seqID="50"/>
     328      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
     329      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    330330    </file>
    331331    <file xil_pn:name="../Hold_FSM.vhd" xil_pn:type="FILE_VHDL">
    332       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="47"/>
    333       <association xil_pn:name="Implementation" xil_pn:seqID="47"/>
     332      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
     333      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    334334    </file>
    335335    <file xil_pn:name="../HT_process.vhd" xil_pn:type="FILE_VHDL">
    336       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="46"/>
    337       <association xil_pn:name="Implementation" xil_pn:seqID="46"/>
     336      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
     337      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    338338    </file>
    339339    <file xil_pn:name="../IP_Timer.vhd" xil_pn:type="FILE_VHDL">
    340       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="33"/>
    341       <association xil_pn:name="Implementation" xil_pn:seqID="33"/>
     340      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
     341      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    342342    </file>
    343343    <file xil_pn:name="../PE.vhd" xil_pn:type="FILE_VHDL">
    344       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="49"/>
    345       <association xil_pn:name="Implementation" xil_pn:seqID="49"/>
     344      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
     345      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    346346    </file>
    347347    <file xil_pn:name="../mpi_test.vhd" xil_pn:type="FILE_VHDL">
    348       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="53"/>
     348      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
    349349      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    350350    </file>
    … …  
    354354    </file>
    355355    <file xil_pn:name="ipcore_dir/mem8k8.xco" xil_pn:type="FILE_COREGEN">
    356       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="44"/>
    357       <association xil_pn:name="Implementation" xil_pn:seqID="44"/>
     356      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
     357      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    358358    </file>
    359359    <file xil_pn:name="../NOC/Def_Request.vhd" xil_pn:type="FILE_VHDL">
    … …  
    362362      <library xil_pn:name="NoCLib"/>
    363363    </file>
    364     <file xil_pn:name="ipcore_dir/mem_4k8.xise" xil_pn:type="FILE_COREGENISE">
    365       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    366     </file>
    367     <file xil_pn:name="ipcore_dir/mem8k8.xise" xil_pn:type="FILE_COREGENISE">
    368       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     364    <file xil_pn:name="Nexys4_Master.ucf" xil_pn:type="FILE_UCF">
     365      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     366    </file>
     367    <file xil_pn:name="../NOC/NOC_tree.vhd" xil_pn:type="FILE_VHDL">
     368      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/>
     369      <association xil_pn:name="Implementation" xil_pn:seqID="26"/>
     370      <library xil_pn:name="NoCLib"/>
     371    </file>
     372    <file xil_pn:name="../NOC/test_noc_tree.vhd" xil_pn:type="FILE_VHDL">
     373      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/>
     374      <association xil_pn:name="Implementation" xil_pn:seqID="27"/>
     375    </file>
     376    <file xil_pn:name="pinloc.ucf" xil_pn:type="FILE_UCF">
     377      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     378    </file>
     379    <file xil_pn:name="simu_tree.vhd" xil_pn:type="FILE_VHDL">
     380      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="28"/>
     381      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="238"/>
     382      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="238"/>
     383      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="238"/>
    369384    </file>
    370385  </files>
    … …  
    429444    <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
    430445    <property xil_pn:name="Delay Values To Be Read from SDF ModelSim" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
    431     <property xil_pn:name="Device" xil_pn:value="xc7vx485t" xil_pn:valueState="non-default"/>
    432     <property xil_pn:name="Device Family" xil_pn:value="Virtex7" xil_pn:valueState="non-default"/>
     446    <property xil_pn:name="Device" xil_pn:value="xc7a100t" xil_pn:valueState="default"/>
     447    <property xil_pn:name="Device Family" xil_pn:value="Artix7" xil_pn:valueState="non-default"/>
    433448    <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-2" xil_pn:valueState="default"/>
    434449    <property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
    … …  
    467482    <property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
    468483    <property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
    469     <property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
     484    <property xil_pn:name="Generate Clock Region Report" xil_pn:value="true" xil_pn:valueState="non-default"/>
    470485    <property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
    471486    <property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
    … …  
    491506    <property xil_pn:name="HMAC Key (Hex String)" xil_pn:value="" xil_pn:valueState="default"/>
    492507    <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
    493     <property xil_pn:name="ICAP Select" xil_pn:value="Top" xil_pn:valueState="default"/>
     508    <property xil_pn:name="ICAP Select" xil_pn:value="Top" xil_pn:valueState="non-default"/>
    494509    <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
    495510    <property xil_pn:name="Ignore Pre-Compiled Library Warning Check" xil_pn:value="false" xil_pn:valueState="default"/>
    496511    <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
    497512    <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
    498     <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|MultiMPITest|behavior" xil_pn:valueState="non-default"/>
    499     <property xil_pn:name="Implementation Top File" xil_pn:value="../Core_MPI/MultiMPITest.vhd" xil_pn:valueState="non-default"/>
    500     <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/mpi_test/uut" xil_pn:valueState="non-default"/>
     513    <property xil_pn:name="Ignore Version Check" xil_pn:value="false" xil_pn:valueState="default"/>
     514    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|test_tree_8x8|behavior" xil_pn:valueState="non-default"/>
     515    <property xil_pn:name="Implementation Top File" xil_pn:value="../NOC/test_noc_tree.vhd" xil_pn:valueState="non-default"/>
     516    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/test_tree_8x8" xil_pn:valueState="non-default"/>
    501517    <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
    502518    <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
    … …  
    538554    <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
    539555    <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
     556    <property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile virtex7" xil_pn:value="Enable" xil_pn:valueState="default"/>
    540557    <property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
    541558    <property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
    … …  
    568585    <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
    569586    <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
    570     <property xil_pn:name="Output File Name" xil_pn:value="MultiMPITest" xil_pn:valueState="default"/>
     587    <property xil_pn:name="Output File Name" xil_pn:value="test_tree_8x8" xil_pn:valueState="default"/>
    571588    <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
    572589    <property xil_pn:name="Overwrite Existing Symbol" xil_pn:value="false" xil_pn:valueState="default"/>
    573590    <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
    574591    <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
    575     <property xil_pn:name="Package" xil_pn:value="ffg1761" xil_pn:valueState="non-default"/>
     592    <property xil_pn:name="Package" xil_pn:value="csg324" xil_pn:valueState="default"/>
    576593    <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
    577594    <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
    … …  
    579596    <property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
    580597    <property xil_pn:name="Place And Route Mode" xil_pn:value="Route Only" xil_pn:valueState="default"/>
     598    <property xil_pn:name="Place MultiBoot Settings into Bitstream virtex7" xil_pn:value="false" xil_pn:valueState="default"/>
    581599    <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
    582600    <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
    583601    <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
    584     <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="MultiMPITest_map.vhd" xil_pn:valueState="default"/>
    585     <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="MultiMPITest_timesim.vhd" xil_pn:valueState="default"/>
    586     <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="MultiMPITest_synthesis.vhd" xil_pn:valueState="default"/>
    587     <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="MultiMPITest_translate.vhd" xil_pn:valueState="default"/>
     602    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="test_tree_8x8_map.vhd" xil_pn:valueState="default"/>
     603    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="test_tree_8x8_timesim.vhd" xil_pn:valueState="default"/>
     604    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="test_tree_8x8_synthesis.vhd" xil_pn:valueState="default"/>
     605    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="test_tree_8x8_translate.vhd" xil_pn:valueState="default"/>
    588606    <property xil_pn:name="Power Down Device if Over Safe Temperature" xil_pn:value="false" xil_pn:valueState="default"/>
    589607    <property xil_pn:name="Power Reduction Map virtex6" xil_pn:value="Off" xil_pn:valueState="default"/>
    … …  
    609627    <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
    610628    <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
    611     <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="MultiMPITest" xil_pn:valueState="default"/>
     629    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="test_tree_8x8" xil_pn:valueState="default"/>
    612630    <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
    613631    <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
    … …  
    632650    <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
    633651    <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
    634     <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/mpi_test" xil_pn:valueState="non-default"/>
    635     <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.mpi_test" xil_pn:valueState="non-default"/>
     652    <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/simu_tree" xil_pn:valueState="non-default"/>
     653    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.simu_tree" xil_pn:valueState="non-default"/>
    636654    <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
    637655    <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
    … …  
    655673    <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
    656674    <property xil_pn:name="Specify Top Level Instance Names" xil_pn:value="" xil_pn:valueState="default"/>
    657     <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.mpi_test" xil_pn:valueState="default"/>
     675    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.simu_tree" xil_pn:valueState="default"/>
    658676    <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
    659677    <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
    … …  
    665683    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
    666684    <property xil_pn:name="Target Simulator" xil_pn:value="Modelsim-SE VHDL" xil_pn:valueState="default"/>
     685    <property xil_pn:name="Target UCF File Name" xil_pn:value="pinloc.ucf" xil_pn:valueState="non-default"/>
    667686    <property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
    668687    <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
    … …  
    698717    <property xil_pn:name="Use SPI Falling Edge" xil_pn:value="No" xil_pn:valueState="default"/>
    699718    <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
    700     <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
    701     <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
     719    <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="non-default"/>
     720    <property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="non-default"/>
    702721    <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
    703722    <property xil_pn:name="User Access Register Value" xil_pn:value="None" xil_pn:valueState="default"/>
    … …  
    720739    <!-- The following properties are for internal use only. These should not be modified.-->
    721740    <!--                                                                                  -->
    722     <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|mpi_test|behavior" xil_pn:valueState="non-default"/>
     741    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|simu_tree|behavior" xil_pn:valueState="non-default"/>
    723742    <property xil_pn:name="PROP_DesignName" xil_pn:value="Test_Timer" xil_pn:valueState="non-default"/>
    724     <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="virtex7" xil_pn:valueState="default"/>
     743    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="artix7" xil_pn:valueState="default"/>
    725744    <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
    726745    <property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
    … …  
    736755  </properties>
    737756
    738   <bindings/>
     757  <bindings>
     758    <binding xil_pn:location="/MultiMPITest" xil_pn:name="Nexys4_Master.ucf"/>
     759    <binding xil_pn:location="/test_tree_8x8" xil_pn:name="pinloc.ucf"/>
     760  </bindings>
    739761
    740762  <libraries>

  • PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.0/Test_Timer/wave.do

    r112 r139  
    11onerror {resume}
    22quietly WaveActivateNextPane {} 0
    3 add wave -noupdate /mpi_test/clk
    4 add wave -noupdate /mpi_test/reset
    5 add wave -noupdate /mpi_test/result
    6 add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/setbit1/Ram_data_in
    7 add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/setbit1/Ram_data_out
    8 add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/sb_ram_rd
    9 add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/sb_ram_wr
    10 add wave -noupdate -radix hexadecimal /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/ram_address
    11 add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/Ram_data_in
    12 add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/Ram_data_out
    13 add wave -noupdate /mpi_test/clk
    14 add wave -noupdate /mpi_test/reset
    15 add wave -noupdate /mpi_test/result
    16 add wave -noupdate /mpi_test/clk
    17 add wave -noupdate /mpi_test/reset
    18 add wave -noupdate /mpi_test/result
    19 add wave -noupdate /mpi_test/clk
    20 add wave -noupdate /mpi_test/reset
    21 add wave -noupdate -radix hexadecimal /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX1_FSM/src_address
    22 add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX1_FSM/switch_port_in_data
    23 add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX1_FSM/switch_port_in_wr_en
    24 add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX1_FSM/dma_rd_grant
    25 add wave -noupdate /mpi_test/result
    26 add wave -noupdate /mpi_test/clk
    27 add wave -noupdate /mpi_test/reset
    28 add wave -noupdate /mpi_test/result
    29 add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/sb_ram_rd
    30 add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/sb_ram_wr
    31 add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/sb_whole
    32 add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/sb_done
    33 add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/sb_BitMask
    34 add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/sb_BitVal
    35 add wave -noupdate -radix hexadecimal /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/ram_address
    36 add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/Ram_data_in
    37 add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/Ram_data_out
    38 add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/ram_rd
    39 add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/ram_wr
    40 add wave -noupdate /mpi_test/uut/PE_s(1)/S/HT_task/RunState
    41 add wave -noupdate /mpi_test/uut/PE_s(1)/S/HT_task/ct_state
    42 add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX1_FSM/ex1_state
    43 add wave -noupdate -radix hexadecimal /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX1_FSM/switch_port_in_data
    44 add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX1_FSM/fifo_src
    45 add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/ex2_state
    46 add wave -noupdate -radix hexadecimal /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/switch_port_out_data
    47 add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX1_FSM/Snd_Start
    48 add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX4_FSM/Snd_Start
    49 add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX4_FSM/stInit2
    50 add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX4_FSM/etcmd
    51 add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX4_FSM/etrec
    52 add wave -noupdate -radix hexadecimal /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX4_FSM/port_out_data
    53 add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX4_FSM/port_out_data_available
    54 add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX4_FSM/snd_start_i
    55 add wave -noupdate -radix hexadecimal /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX1_FSM/switch_port_in_data
    56 add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX1_FSM/n
    57 add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX1_FSM/switch_port_in_wr_en
    58 add wave -noupdate -radix hexadecimal /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX1_FSM/fifo_data_out
    59 add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX1_FSM/p_len
    60 add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX1_FSM/fifo_rd_en
    61 add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX1_FSM/fifo_empty
    62 add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/ex2_state
    63 add wave -noupdate -radix unsigned /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/P_len
    64 add wave -noupdate -radix hexadecimal /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/switch_port_out_data
    65 add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/switch_data_available
    66 add wave -noupdate -radix hexadecimal /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX1_FSM/dest_address
    67 add wave -noupdate -radix hexadecimal /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/P_len
    68 add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/n
    69 add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/ex2_state
    70 add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/setbit1/State
    71 add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/setbit1/Ram_data_in
    72 add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/setbit1/Ram_data_out
    73 add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/n
    74 add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/n_i
    75 add wave -noupdate -radix hexadecimal /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/P_len
    76 add wave -noupdate -radix hexadecimal /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/P_len_i
    77 add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/dma_wr_request
    78 add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/dma_wr_grant
    79 add wave -noupdate /mpi_test/result
    80 add wave -noupdate -expand -subitemconfig {/mpi_test/uut/PE_s(1)/S/HT_task/sram.O {-height 18 -childformat {{/mpi_test/uut/PE_s(1)/S/HT_task/sram.O.addr_wr -radix hexadecimal} {/mpi_test/uut/PE_s(1)/S/HT_task/sram.O.addr_rd -radix hexadecimal} {/mpi_test/uut/PE_s(1)/S/HT_task/sram.O.data_in -radix hexadecimal}} -expand} /mpi_test/uut/PE_s(1)/S/HT_task/sram.O.addr_wr {-height 18 -radix hexadecimal} /mpi_test/uut/PE_s(1)/S/HT_task/sram.O.addr_rd {-height 18 -radix hexadecimal} /mpi_test/uut/PE_s(1)/S/HT_task/sram.O.data_in {-height 18 -radix hexadecimal} /mpi_test/uut/PE_s(1)/S/HT_task/sram.I -expand} /mpi_test/uut/PE_s(1)/S/HT_task/sram
    81 add wave -noupdate /mpi_test/uut/PE_s(1)/S/HT_task/Libr
    82 add wave -noupdate /mpi_test/uut/PE_s(1)/S/HT_task/RunState
    83 add wave -noupdate /mpi_test/uut/PE_s(1)/S/HT_task/ct_state
    84 add wave -noupdate /mpi_test/uut/PE_s(2)/S/HT_task/RunState
    85 add wave -noupdate /mpi_test/uut/PE_s(2)/S/HT_task/ct_state
    86 add wave -noupdate -radix hexadecimal /mpi_test/uut/PE_s(2)/S/HT_task/sram.O.addr_rd
    87 add wave -noupdate /mpi_test/uut/PE_s(2)/S/HT_task/sram.I.data_out
    88 add wave -noupdate -radix hexadecimal /mpi_test/uut/PE_s(2)/S/Ram8k8/addra
    89 add wave -noupdate -radix hexadecimal /mpi_test/uut/PE_s(2)/S/Ram8k8/addrb
    90 add wave -noupdate /mpi_test/uut/PE_s(2)/S/Ram8k8/doutb
    91 add wave -noupdate /mpi_test/uut/PE_s(2)/S/Ram8k8/dina
    92 add wave -noupdate /mpi_test/uut/PE_s(2)/S/Ram8k8/wea(0)
    93 add wave -noupdate /mpi_test/uut/dyn_HT/PE_D(3)/D/HT_task/RunState
    94 add wave -noupdate /mpi_test/uut/dyn_HT/PE_D(4)/D/HT_task/RunState
    95 add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/ex2_state
    96 add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/GPost
    97 add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/Rec_WPost
    98 add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/Received_get
    99 add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/GPost_Set
    100 add wave -noupdate -radix hexadecimal /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/Waited_Get(0)
    101 add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/GComp
    102 add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/ex2_state
    103 add wave -noupdate -radix hexadecimal /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/switch_port_out_data
    104 add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/n
    105 add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX1_FSM/ex1_state
    106 add wave -noupdate -radix hexadecimal /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX1_FSM/fifo_data_out
    107 add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX1_FSM/n
    108 add wave -noupdate -radix hexadecimal /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/ram_address
    109 add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/dma_rd_grant
    110 add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/dma_wr_grant
    111 add wave -noupdate -radix hexadecimal /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/dest_address
    112 add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/WBUSY
    113 add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/Rec_WPost
    114 add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/Received_get
    115 add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/Set_Wbusy
    116 add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/Waited_Get(0)
    117 add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/GPost
    118 add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/GComp
    119 add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/GPost_Set
    120 add wave -noupdate -radix hexadecimal /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/switch_port_out_data
    121 add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/switch_data_available
    122 add wave -noupdate /mpi_test/clk
    123 add wave -noupdate /mpi_test/uut/PE_s(2)/S/Ram8k8/enb
    124 add wave -noupdate /mpi_test/uut/PE_s(2)/S/Ram8k8/wea(0)
    125 add wave -noupdate -radix binary /mpi_test/uut/PE_s(2)/S/Ram8k8/doutb
    126 add wave -noupdate -radix binary /mpi_test/uut/PE_s(2)/S/Ram8k8/dina
    127 add wave -noupdate -radix hexadecimal /mpi_test/uut/PE_s(2)/S/Ram8k8/addrb
    128 add wave -noupdate -radix hexadecimal /mpi_test/uut/PE_s(2)/S/Ram8k8/addra
     3add wave -noupdate /simu_tree/reset
     4add wave -noupdate /simu_tree/uut/x1/NoC_tree1(2)/Noc_elt/port_out_switch5x5/PORT2_OUTPUT_PORT_MODULE/fifo_wr
     5add wave -noupdate /simu_tree/uut/x1/NoC_tree1(2)/Noc_elt/port_out_switch5x5/PORT2_OUTPUT_PORT_MODULE/wr_en
     6add wave -noupdate /simu_tree/uut/x1/NoC_tree1(2)/Noc_elt/port_out_switch5x5/PORT2_OUTPUT_PORT_MODULE/nib
     7add wave -noupdate /simu_tree/sw
     8add wave -noupdate /simu_tree/led
     9add wave -noupdate /simu_tree/uut/etsnd3
     10add wave -noupdate -radix hexadecimal /simu_tree/uut/PortIn(3)
     11add wave -noupdate -radix hexadecimal /simu_tree/uut/PortIn(6)
     12add wave -noupdate /simu_tree/uut/etsnd2
     13add wave -noupdate -radix hexadecimal /simu_tree/uut/PortIn(2)
     14add wave -noupdate /simu_tree/uut/etsnd1
     15add wave -noupdate -radix hexadecimal -childformat {{/simu_tree/uut/PortIn(1)(15) -radix hexadecimal} {/simu_tree/uut/PortIn(1)(14) -radix hexadecimal} {/simu_tree/uut/PortIn(1)(13) -radix hexadecimal} {/simu_tree/uut/PortIn(1)(12) -radix hexadecimal} {/simu_tree/uut/PortIn(1)(11) -radix hexadecimal} {/simu_tree/uut/PortIn(1)(10) -radix hexadecimal} {/simu_tree/uut/PortIn(1)(9) -radix hexadecimal} {/simu_tree/uut/PortIn(1)(8) -radix hexadecimal} {/simu_tree/uut/PortIn(1)(7) -radix hexadecimal} {/simu_tree/uut/PortIn(1)(6) -radix hexadecimal} {/simu_tree/uut/PortIn(1)(5) -radix hexadecimal} {/simu_tree/uut/PortIn(1)(4) -radix hexadecimal} {/simu_tree/uut/PortIn(1)(3) -radix hexadecimal} {/simu_tree/uut/PortIn(1)(2) -radix hexadecimal} {/simu_tree/uut/PortIn(1)(1) -radix hexadecimal} {/simu_tree/uut/PortIn(1)(0) -radix hexadecimal}} -subitemconfig {/simu_tree/uut/PortIn(1)(15) {-height 18 -radix hexadecimal} /simu_tree/uut/PortIn(1)(14) {-height 18 -radix hexadecimal} /simu_tree/uut/PortIn(1)(13) {-height 18 -radix hexadecimal} /simu_tree/uut/PortIn(1)(12) {-height 18 -radix hexadecimal} /simu_tree/uut/PortIn(1)(11) {-height 18 -radix hexadecimal} /simu_tree/uut/PortIn(1)(10) {-height 18 -radix hexadecimal} /simu_tree/uut/PortIn(1)(9) {-height 18 -radix hexadecimal} /simu_tree/uut/PortIn(1)(8) {-height 18 -radix hexadecimal} /simu_tree/uut/PortIn(1)(7) {-height 18 -radix hexadecimal} /simu_tree/uut/PortIn(1)(6) {-height 18 -radix hexadecimal} /simu_tree/uut/PortIn(1)(5) {-height 18 -radix hexadecimal} /simu_tree/uut/PortIn(1)(4) {-height 18 -radix hexadecimal} /simu_tree/uut/PortIn(1)(3) {-height 18 -radix hexadecimal} /simu_tree/uut/PortIn(1)(2) {-height 18 -radix hexadecimal} /simu_tree/uut/PortIn(1)(1) {-height 18 -radix hexadecimal} /simu_tree/uut/PortIn(1)(0) {-height 18 -radix hexadecimal}} /simu_tree/uut/PortIn(1)
     16add wave -noupdate /simu_tree/uut/etrec
     17add wave -noupdate /simu_tree/uut/x1/NoC_tree1(1)/Noc_elt/port_out_switch5x5/PORT3_OUTPUT_PORT_MODULE/Et_store
     18add wave -noupdate /simu_tree/uut/x1/NoC_tree1(1)/Noc_elt/port_out_switch5x5/PORT3_OUTPUT_PORT_MODULE/wr_en
     19add wave -noupdate -radix hexadecimal /simu_tree/uut/x1/NoC_tree1(1)/Noc_elt/port_out_switch5x5/PORT3_OUTPUT_PORT_MODULE/data_in
     20add wave -noupdate -radix hexadecimal /simu_tree/uut/x1/NoC_tree1(1)/Noc_elt/port_out_switch5x5/PORT3_OUTPUT_PORT_MODULE/data_out
     21add wave -noupdate /simu_tree/uut/x1/NoC_tree1(1)/Noc_elt/port_out_switch5x5/PORT3_OUTPUT_PORT_MODULE/nib
     22add wave -noupdate -radix hexadecimal /simu_tree/uut/x1/NoC_tree1(1)/Noc_elt/port_out_switch5x5/PORT3_OUTPUT_PORT_MODULE/fifo_in
     23add wave -noupdate /simu_tree/uut/x1/NoC_tree1(1)/Noc_elt/port_out_switch5x5/PORT3_OUTPUT_PORT_MODULE/fifo_wr
     24add wave -noupdate /simu_tree/uut/etcmd
     25add wave -noupdate -radix hexadecimal -childformat {{/simu_tree/uut/portOut(1) -radix hexadecimal} {/simu_tree/uut/portOut(2) -radix hexadecimal} {/simu_tree/uut/portOut(3) -radix hexadecimal} {/simu_tree/uut/portOut(4) -radix hexadecimal} {/simu_tree/uut/portOut(5) -radix hexadecimal} {/simu_tree/uut/portOut(6) -radix hexadecimal} {/simu_tree/uut/portOut(7) -radix hexadecimal} {/simu_tree/uut/portOut(8) -radix hexadecimal}} -expand -subitemconfig {/simu_tree/uut/portOut(1) {-height 18 -radix hexadecimal} /simu_tree/uut/portOut(2) {-height 18 -radix hexadecimal} /simu_tree/uut/portOut(3) {-height 18 -radix hexadecimal} /simu_tree/uut/portOut(4) {-height 18 -radix hexadecimal} /simu_tree/uut/portOut(5) {-height 18 -radix hexadecimal} /simu_tree/uut/portOut(6) {-height 18 -radix hexadecimal} /simu_tree/uut/portOut(7) {-height 18 -radix hexadecimal} /simu_tree/uut/portOut(8) {-height 18 -radix hexadecimal}} /simu_tree/uut/portOut
     26add wave -noupdate /simu_tree/uut/data_available
     27add wave -noupdate /simu_tree/uut/x1/NoC_tree1(2)/Noc_elt/switch4x4_7x7/switch_4x4_7x7(2)/PORTx4_INPUT_PORT_MODULE/pop_state
     28add wave -noupdate /simu_tree/uut/x1/NoC_tree1(2)/Noc_elt/switch4x4_7x7/switch_4x4_7x7(2)/PORTx4_INPUT_PORT_MODULE/nib
     29add wave -noupdate /simu_tree/uut/x1/NoC_tree1(2)/Noc_elt/switch4x4_7x7/switch_4x4_7x7(2)/PORTx4_INPUT_PORT_MODULE/fifo_read_signal
     30add wave -noupdate -radix hexadecimal /simu_tree/uut/x1/NoC_tree1(2)/Noc_elt/switch4x4_7x7/switch_4x4_7x7(2)/PORTx4_INPUT_PORT_MODULE/fifo_out_signal
     31add wave -noupdate -radix hexadecimal /simu_tree/uut/x1/NoC_tree1(2)/Noc_elt/switch4x4_7x7/switch_4x4_7x7(2)/PORTx4_INPUT_PORT_MODULE/fifo_out2
     32add wave -noupdate -radix hexadecimal /simu_tree/uut/x1/NoC_tree1(2)/Noc_elt/switch4x4_7x7/switch_4x4_7x7(2)/PORTx4_INPUT_PORT_MODULE/push_dout
     33add wave -noupdate -radix hexadecimal /simu_tree/uut/x1/NoC_tree1(2)/Noc_elt/switch4x4_7x7/switch_4x4_7x7(2)/PORTx4_INPUT_PORT_MODULE/data_out
     34add wave -noupdate -radix hexadecimal /simu_tree/uut/x1/NoC_tree1(2)/Noc_elt/switch4x4_7x7/switch_4x4_7x7(2)/PORTx4_INPUT_PORT_MODULE/pipeline_latch
     35add wave -noupdate /simu_tree/uut/x1/NoC_tree1(2)/Noc_elt/switch4x4_7x7/switch_4x4_7x7(2)/PORTx4_INPUT_PORT_MODULE/pipeline_latch_en
     36add wave -noupdate /simu_tree/uut/x1/NoC_tree1(2)/Noc_elt/switch4x4_7x7/switch_4x4_7x7(2)/PORTx4_INPUT_PORT_MODULE/data_out_pulse
     37add wave -noupdate /simu_tree/uut/x1/NoC_tree1(1)/Noc_elt/switch4x4_7x7/switch_4x4_7x7(1)/PORTx4_INPUT_PORT_MODULE/cmdstate
     38add wave -noupdate /simu_tree/uut/x1/NoC_tree1(1)/Noc_elt/switch4x4_7x7/switch_4x4_7x7(2)/PORTx4_INPUT_PORT_MODULE/pop_state
     39add wave -noupdate /simu_tree/clkm
     40add wave -noupdate -radix hexadecimal /simu_tree/uut/x1/NoC_tree1(1)/Noc_elt/switch4x4_7x7/switch_4x4_7x7(2)/PORTx4_INPUT_PORT_MODULE/fifo_out_signal
     41add wave -noupdate -radix hexadecimal /simu_tree/uut/x1/NoC_tree1(1)/Noc_elt/switch4x4_7x7/switch_4x4_7x7(2)/PORTx4_INPUT_PORT_MODULE/fifo_out2
     42add wave -noupdate -radix hexadecimal /simu_tree/uut/x1/NoC_tree1(1)/Noc_elt/switch4x4_7x7/switch_4x4_7x7(2)/PORTx4_INPUT_PORT_MODULE/push_dout
     43add wave -noupdate /simu_tree/uut/x1/NoC_tree1(1)/Noc_elt/switch4x4_7x7/switch_4x4_7x7(2)/PORTx4_INPUT_PORT_MODULE/wrok
     44add wave -noupdate -radix hexadecimal /simu_tree/uut/x1/NoC_tree1(1)/Noc_elt/switch4x4_7x7/switch_4x4_7x7(2)/PORTx4_INPUT_PORT_MODULE/pipeline_latch
     45add wave -noupdate /simu_tree/uut/x1/NoC_tree1(1)/Noc_elt/switch4x4_7x7/switch_4x4_7x7(2)/PORTx4_INPUT_PORT_MODULE/pipeline_latch_en
     46add wave -noupdate -radix hexadecimal /simu_tree/uut/x1/NoC_tree1(1)/Noc_elt/switch4x4_7x7/switch_4x4_7x7(1)/PORTx4_INPUT_PORT_MODULE/cmd_data_signal
     47add wave -noupdate -radix hexadecimal /simu_tree/uut/x1/NoC_tree1(1)/Noc_elt/switch4x4_7x7/switch_4x4_7x7(1)/PORTx4_INPUT_PORT_MODULE/data_out
     48add wave -noupdate /simu_tree/uut/etcmd
     49add wave -noupdate /simu_tree/uut/x1/NoC_tree1(1)/Noc_elt/switch4x4_7x7/switch_4x4_7x7(3)/PORTx4_INPUT_PORT_MODULE/request_latch
     50add wave -noupdate /simu_tree/uut/x1/NoC_tree1(1)/Noc_elt/switch4x4_7x7/switch_4x4_7x7(3)/PORTx4_INPUT_PORT_MODULE/PORT_ID
     51add wave -noupdate -radix hexadecimal /simu_tree/uut/PortIn(1)
     52add wave -noupdate -radix hexadecimal /simu_tree/uut/portOut(1)
     53add wave -noupdate /simu_tree/uut/cmd_in_en
     54add wave -noupdate /simu_tree/uut/sorigport
     55add wave -noupdate /simu_tree/uut/data_available
     56add wave -noupdate -radix hexadecimal -childformat {{/simu_tree/uut/PortIn(1) -radix hexadecimal} {/simu_tree/uut/PortIn(2) -radix hexadecimal} {/simu_tree/uut/PortIn(3) -radix hexadecimal} {/simu_tree/uut/PortIn(4) -radix hexadecimal} {/simu_tree/uut/PortIn(5) -radix hexadecimal} {/simu_tree/uut/PortIn(6) -radix hexadecimal} {/simu_tree/uut/PortIn(7) -radix hexadecimal} {/simu_tree/uut/PortIn(8) -radix hexadecimal}} -expand -subitemconfig {/simu_tree/uut/PortIn(1) {-height 18 -radix hexadecimal} /simu_tree/uut/PortIn(2) {-height 18 -radix hexadecimal} /simu_tree/uut/PortIn(3) {-height 18 -radix hexadecimal} /simu_tree/uut/PortIn(4) {-height 18 -radix hexadecimal} /simu_tree/uut/PortIn(5) {-height 18 -radix hexadecimal} /simu_tree/uut/PortIn(6) {-height 18 -radix hexadecimal} /simu_tree/uut/PortIn(7) {-height 18 -radix hexadecimal} /simu_tree/uut/PortIn(8) {-height 18 -radix hexadecimal}} /simu_tree/uut/PortIn
     57add wave -noupdate /simu_tree/uut/x1/NoC_tree1(1)/Noc_elt/switch4x4_7x7/switch_4x4_7x7(3)/PORTx4_INPUT_PORT_MODULE/cmdstate
     58add wave -noupdate -radix hexadecimal /simu_tree/uut/x1/NoC_tree1(1)/Noc_elt/switch4x4_7x7/switch_4x4_7x7(3)/PORTx4_INPUT_PORT_MODULE/cmd_data_signal
     59add wave -noupdate /simu_tree/uut/x1/NoC_tree1(1)/Noc_elt/switch4x4_7x7/switch_4x4_7x7(3)/PORTx4_INPUT_PORT_MODULE/cmd_data_out_pulse
     60add wave -noupdate /simu_tree/uut/x1/NoC_tree1(1)/Noc_elt/port_out_switch5x5/PORT2_OUTPUT_PORT_MODULE/Et_store
     61add wave -noupdate /simu_tree/uut/x1/NoC_tree1(1)/Noc_elt/port_out_switch5x5/PORT2_OUTPUT_PORT_MODULE/wr_en
     62add wave -noupdate -radix hexadecimal /simu_tree/uut/x1/NoC_tree1(1)/Noc_elt/port_out_switch5x5/PORT2_OUTPUT_PORT_MODULE/data_in
     63add wave -noupdate -radix hexadecimal /simu_tree/uut/x1/NoC_tree1(1)/Noc_elt/port_out_switch5x5/PORT2_OUTPUT_PORT_MODULE/fifo_in
     64add wave -noupdate -radix hexadecimal /simu_tree/uut/x1/NoC_tree1(1)/Noc_elt/port_out_switch5x5/PORT2_OUTPUT_PORT_MODULE/fifo_wr
     65add wave -noupdate -radix hexadecimal /simu_tree/uut/x1/NoC_tree1(1)/Noc_elt/port_out_switch5x5/PORT2_OUTPUT_PORT_MODULE/data_avalaible
     66add wave -noupdate -radix hexadecimal /simu_tree/uut/x1/NoC_tree1(1)/Noc_elt/port_out_switch5x5/PORT2_OUTPUT_PORT_MODULE/data_out
     67add wave -noupdate /simu_tree/uut/x1/NoC_tree1(1)/Noc_elt/switch4x4_7x7/switch_4x4_7x7(2)/PORTx4_INPUT_PORT_MODULE/pop_state
     68add wave -noupdate /simu_tree/uut/x1/NoC_tree1(1)/Noc_elt/switch4x4_7x7/switch_4x4_7x7(2)/PORTx4_INPUT_PORT_MODULE/fifo_out_signal
     69add wave -noupdate /simu_tree/uut/x1/NoC_tree1(1)/Noc_elt/switch4x4_7x7/switch_4x4_7x7(2)/PORTx4_INPUT_PORT_MODULE/request_latch_en
     70add wave -noupdate /simu_tree/uut/x1/NoC_tree1(1)/Noc_elt/switch4x4_7x7/switch_4x4_7x7(2)/PORTx4_INPUT_PORT_MODULE/request_latch
     71add wave -noupdate /simu_tree/uut/x1/NoC_tree1(1)/Noc_elt/switch4x4_7x7/switch_4x4_7x7(4)/PORTx4_INPUT_PORT_MODULE/pop_state
     72add wave -noupdate -radix hexadecimal /simu_tree/uut/x1/NoC_tree1(1)/Noc_elt/switch4x4_7x7/switch_4x4_7x7(4)/PORTx4_INPUT_PORT_MODULE/fifo_out_signal
     73add wave -noupdate /simu_tree/uut/x1/NoC_tree1(1)/Noc_elt/switch4x4_7x7/switch_4x4_7x7(4)/PORTx4_INPUT_PORT_MODULE/request_latch_en
     74add wave -noupdate /simu_tree/uut/x1/NoC_tree1(1)/Noc_elt/switch4x4_7x7/switch_4x4_7x7(4)/PORTx4_INPUT_PORT_MODULE/data_out_pulse
     75add wave -noupdate -radix hexadecimal /simu_tree/uut/x1/NoC_tree1(1)/Noc_elt/switch4x4_7x7/switch_4x4_7x7(4)/PORTx4_INPUT_PORT_MODULE/data_out
     76add wave -noupdate /simu_tree/uut/x1/NoC_tree1(1)/Noc_elt/switch4x4_7x7/switch_4x4_7x7(4)/PORTx4_INPUT_PORT_MODULE/request
     77add wave -noupdate /simu_tree/uut/x1/NoC_tree1(1)/Noc_elt/switch4x4_7x7/switch_4x4_7x7(4)/PORTx4_INPUT_PORT_MODULE/request_latch
     78add wave -noupdate /simu_tree/uut/x1/noc_data_out_en(10)
     79add wave -noupdate /simu_tree/uut/x1/noc_data_out_en
     80add wave -noupdate /simu_tree/uut/x1/noc_data_out_en(5)
     81add wave -noupdate /simu_tree/uut/x1/noc_fifo_in_full(5)
     82add wave -noupdate /simu_tree/uut/x1/noc_fifo_in_full(10)
     83add wave -noupdate /simu_tree/uut/x1/tree_data_available(1)
     84add wave -noupdate /simu_tree/uut/x1/tree_fifo_in_full(1)
     85add wave -noupdate /simu_tree/uut/x1/noc_data_available(5)
     86add wave -noupdate /simu_tree/uut/x1/noc_data_in_en
    12987TreeUpdate [SetDefaultTree]
    130 WaveRestoreCursors {{Cursor 1} {13042 ps} 0} {{Cursor 2} {31415000 ps} 0} {{Cursor 3} {100265000 ps} 0}
     88WaveRestoreCursors {{Cursor 3} {6075000 ps} 0}
    13189quietly wave cursor active 1
    13290configure wave -namecolwidth 165
    … …  
    144102configure wave -timelineunits ns
    145103update
    146 WaveRestoreZoom {0 ps} {74096 ps}
     104WaveRestoreZoom {6873500 ps} {6927711 ps}
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