Ignore:
Timestamp:
Mar 3, 2014, 4:09:09 PM (11 years ago)
Author:
lambert
Message:

Adding generation simulation support for verilog

Location:
PROJECT_SMART_EEG/trunk/hw/sync_sys
Files:
7 edited

Legend:

Unmodified
Added
Removed

  • PROJECT_SMART_EEG/trunk/hw/sync_sys/audio_codec/audio_codec_hw.tcl

    r84 r87  
    11# TCL File Generated by Component Editor 13.1
    2 # Fri Feb 28 16:58:45 CET 2014
     2# Mon Mar 03 15:31:24 CET 2014
    33# DO NOT MODIFY
    44
    … …  
    66#
    77# audio_codec "audio_codec" v1.0
    8 #  2014.02.28.16:58:45
     8#  2014.03.03.15:31:24
    99#
    1010#
    … …  
    4141set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
    4242add_fileset_file audio_codec.v VERILOG PATH audio_codec.v TOP_LEVEL_FILE
     43
     44add_fileset SIM_VERILOG SIM_VERILOG "" ""
     45set_fileset_property SIM_VERILOG TOP_LEVEL audio_codec
     46set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false
     47add_fileset_file audio_codec.v VERILOG PATH audio_codec.v
    4348
    4449

  • PROJECT_SMART_EEG/trunk/hw/sync_sys/exg_codec/exg_codec_hw.tcl

    r84 r87  
    11# TCL File Generated by Component Editor 13.1
    2 # Fri Feb 28 17:02:33 CET 2014
     2# Mon Mar 03 15:32:05 CET 2014
    33# DO NOT MODIFY
    44
    … …  
    66#
    77# exg_codec "exg_codec" v1.0
    8 #  2014.02.28.17:02:33
     8#  2014.03.03.15:32:05
    99#
    1010#
    … …  
    4141set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
    4242add_fileset_file exg_codec.v VERILOG PATH exg_codec.v TOP_LEVEL_FILE
     43
     44add_fileset SIM_VERILOG SIM_VERILOG "" ""
     45set_fileset_property SIM_VERILOG TOP_LEVEL exg_codec
     46set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false
     47add_fileset_file exg_codec.v VERILOG PATH exg_codec.v
    4348
    4449

  • PROJECT_SMART_EEG/trunk/hw/sync_sys/frame_grabber/frame_grabber_hw.tcl

    r84 r87  
    11# TCL File Generated by Component Editor 13.1
    2 # Fri Feb 28 17:27:39 CET 2014
     2# Mon Mar 03 15:33:08 CET 2014
    33# DO NOT MODIFY
    44
    … …  
    66#
    77# frame_grabber "frame_grabber" v1.0
    8 #  2014.02.28.17:27:39
     8#  2014.03.03.15:33:08
    99#
    1010#
    … …  
    4141set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
    4242add_fileset_file frame_grabber.v VERILOG PATH frame_grabber.v TOP_LEVEL_FILE
     43
     44add_fileset SIM_VERILOG SIM_VERILOG "" ""
     45set_fileset_property SIM_VERILOG TOP_LEVEL frame_grabber
     46set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false
     47add_fileset_file frame_grabber.v VERILOG PATH frame_grabber.v
    4348
    4449

  • PROJECT_SMART_EEG/trunk/hw/sync_sys/signal_grabber/signal_grabber_hw.tcl

    r84 r87  
    11# TCL File Generated by Component Editor 13.1
    2 # Fri Feb 28 17:57:56 CET 2014
     2# Mon Mar 03 15:33:43 CET 2014
    33# DO NOT MODIFY
    44
    … …  
    66#
    77# signal_grabber "signal_grabber" v1.0
    8 #  2014.02.28.17:57:56
     8#  2014.03.03.15:33:43
    99#
    1010#
    … …  
    4141set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
    4242add_fileset_file signal_grabber.v VERILOG PATH signal_grabber.v TOP_LEVEL_FILE
     43
     44add_fileset SIM_VERILOG SIM_VERILOG "" ""
     45set_fileset_property SIM_VERILOG TOP_LEVEL signal_grabber
     46set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false
     47add_fileset_file signal_grabber.v VERILOG PATH signal_grabber.v
    4348
    4449

  • PROJECT_SMART_EEG/trunk/hw/sync_sys/stream_merger/stream_merger_hw.tcl

    r84 r87  
    11# TCL File Generated by Component Editor 13.1
    2 # Fri Feb 28 18:03:07 CET 2014
     2# Mon Mar 03 15:30:43 CET 2014
    33# DO NOT MODIFY
    44
    … …  
    66#
    77# stream_merger "stream_merger" v1.0
    8 #  2014.02.28.18:03:07
     8#  2014.03.03.15:30:43
    99#
    1010#
    … …  
    4141set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
    4242add_fileset_file stream_merger.v VERILOG PATH stream_merger.v TOP_LEVEL_FILE
     43
     44add_fileset SIM_VERILOG SIM_VERILOG "" ""
     45set_fileset_property SIM_VERILOG TOP_LEVEL stream_merger
     46set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false
     47add_fileset_file stream_merger.v VERILOG PATH stream_merger.v
    4348
    4449
    … …  
    107112set_interface_property ctrl SVD_ADDRESS_GROUP ""
    108113
    109 add_interface_port ctrl avs_s0_address address Input 8
    110 add_interface_port ctrl avs_s0_read read Input 1
    111 add_interface_port ctrl avs_s0_readdata readdata Output 32
    112 add_interface_port ctrl avs_s0_write write Input 1
    113 add_interface_port ctrl avs_s0_writedata writedata Input 32
    114 add_interface_port ctrl avs_s0_waitrequest waitrequest Output 1
     114add_interface_port ctrl avs_ctrl_address address Input 8
     115add_interface_port ctrl avs_ctrl_read read Input 1
     116add_interface_port ctrl avs_ctrl_readdata readdata Output 32
     117add_interface_port ctrl avs_ctrl_write write Input 1
     118add_interface_port ctrl avs_ctrl_writedata writedata Input 32
     119add_interface_port ctrl avs_ctrl_waitrequest waitrequest Output 1
    115120set_interface_assignment ctrl embeddedsw.configuration.isFlash 0
    116121set_interface_assignment ctrl embeddedsw.configuration.isMemoryDevice 0

  • PROJECT_SMART_EEG/trunk/hw/sync_sys/synchro/synchro_hw.tcl

    r84 r87  
    11# TCL File Generated by Component Editor 13.1
    2 # Fri Feb 28 17:08:14 CET 2014
     2# Mon Mar 03 15:34:33 CET 2014
    33# DO NOT MODIFY
    44
    … …  
    66#
    77# synchro "synchro" v1.0
    8 #  2014.02.28.17:08:14
     8#  2014.03.03.15:34:33
    99#
    1010#
    … …  
    4141set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
    4242add_fileset_file synchro.v VERILOG PATH synchro.v TOP_LEVEL_FILE
     43
     44add_fileset SIM_VERILOG SIM_VERILOG "" ""
     45set_fileset_property SIM_VERILOG TOP_LEVEL synchro
     46set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false
     47add_fileset_file synchro.v VERILOG PATH synchro.v
    4348
    4449

  • PROJECT_SMART_EEG/trunk/hw/sync_sys/video_codec/video_codec_hw.tcl

    r84 r87  
    11# TCL File Generated by Component Editor 13.1
    2 # Fri Feb 28 17:11:09 CET 2014
     2# Mon Mar 03 15:34:59 CET 2014
    33# DO NOT MODIFY
    44
    … …  
    66#
    77# video_codec "video_codec" v1.0
    8 #  2014.02.28.17:11:09
     8#  2014.03.03.15:34:59
    99#
    1010#
    … …  
    4141set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
    4242add_fileset_file video_codec.v VERILOG PATH video_codec.v TOP_LEVEL_FILE
     43
     44add_fileset SIM_VERILOG SIM_VERILOG "" ""
     45set_fileset_property SIM_VERILOG TOP_LEVEL video_codec
     46set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false
     47add_fileset_file video_codec.v VERILOG PATH video_codec.v
    4348
    4449
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