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@453
|
11 years |
devigne |
Rename dspin_dhccp_param into dspin_odccp_param
|
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@452
|
11 years |
devigne |
Introduction of ODCCP branch
New components :
-dspin_odccp_param …
|
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|
@448
|
11 years |
cfuguet |
Modification in branches/v5/platforms/tsar_generic_xbar:
- Adding a …
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|
@447
|
11 years |
cfuguet |
Adding tsar_generic_xbar platform in branches/v5/platforms:
- This …
|
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@446
|
11 years |
cfuguet |
Modifications in vci_cc_vcache_wrapper:
- Merging the states …
|
|
|
@445
|
11 years |
cfuguet |
Bugfix in vci_mem_cache:
- Adding missing "strings" for …
|
|
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@444
|
11 years |
cfuguet |
Modifications in branches/v5/modules/vci_cc_vcache_wrapper:
- …
|
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|
@443
|
11 years |
cfuguet |
Merging branch/v5/vci_cc_vcache_wrapper with trunk modifications
to …
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|
@442
|
11 years |
cfuguet |
Modifications in branches/v5/communication/dspin_dhccp_param:
- …
|
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|
@441
|
11 years |
cfuguet |
Modifications in branches/v5/vci_mem_cache:
- Changing name of CC …
|
|
|
@440
|
11 years |
cfuguet |
Merging branch/v5/vci_mem_cache with trunk modifications to
start the …
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@420
|
11 years |
porquet |
various modifications to the platform
- make simulation parameters a …
|
|
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@419
|
11 years |
porquet |
modifications in Makefile
- I can't stand this banner anymore
- rule …
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@418
|
11 years |
porquet |
just for me
|
|
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@414
|
11 years |
porquet |
oups in segmentation.h
|
|
|
@410
|
11 years |
porquet |
add a new platform tsarv4
- mono mipsel32
- xicu, blockdevice, tty
…
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|
@407
|
12 years |
porquet |
add missing header (for ::read, ::write, etc.)
|
|
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@380
|
12 years |
simerabe |
Another bugfix
|
|
|
@371
|
12 years |
joannou |
Create TsarV4 branch from trunk as of now
|
|
|
@370
|
12 years |
joannou |
In tsarv5_generic_mmu :
* top.cpp : go look for hard_config.h in …
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|
|
@369
|
12 years |
joannou |
Bugfix in vci_cc_vcache_wrapper v5 :
forgot to copy the nline when …
|
|
|
@367
|
12 years |
cfuguet |
Modification in v5/vci_mem_cache
Aligning to left the SRCID into the …
|
|
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@366
|
12 years |
joannou |
In vci_cc_vcache_wrapper v5,
* now using the new generic_cache_tsar …
|
|
|
@364
|
12 years |
haoliu |
Bug fix in dcache fsm, in dcache_xtn_dc_inval_go state,
set the slot …
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|
|
@363
|
12 years |
joannou |
In tsarv5_generic_mmu platform, in tsar cluster, added l_width to …
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|
|
@362
|
12 years |
cfuguet |
Bugfix in vci_mem_cache:
In function "copy()" of the xram_transaction …
|
|
|
@360
|
12 years |
joannou |
In tsarv5_generic_mmu platform (tsarcluster):
* connected vci to dspin …
|
|
|
@359
|
12 years |
joannou |
bugfix : correctly updating the r_preempt register
|
|
|
@358
|
12 years |
simerabe |
bugfix : preempt in case of broadcast, palloc in case of single flit
|
|
|
@357
|
12 years |
simerabe |
fixbug : test on eop in case of single_flit coherence request
|
|
|
@356
|
12 years |
cfuguet |
Modifying comments in the dspin_dhccp_param to comply the type …
|
|
|
@355
|
12 years |
joannou |
In vci_cc_vcache_wrapper v5
- added check for p_dspin_in.write in …
|
|
|
@354
|
12 years |
cfuguet |
Bugfix in branches/v5/vci_mem_cache
Adding missing condition in …
|
|
|
@353
|
12 years |
cfuguet |
Bugfix in branches/v5/vci_mem_cache
Adding missing fifo get in case of …
|
|
|
@351
|
12 years |
joannou |
Got rid of intermediate v5 version. _dspin_coherence versions changed …
|
|
|
@350
|
12 years |
alain |
Introducing Platform tsarv5_dspin_array,
that can be used for TSAR …
|
|
|
@346
|
12 years |
alain |
New contructors for vci_mem_cache & vci_cc_vcache,
as we don't need …
|
|
|
@345
|
12 years |
alain |
Introducing the cluster component in tsarv5_generic_mmu platform.
|
|
|
@344
|
12 years |
alain |
Introducing the tsarv5_generic_mmu platform.
|
|
|
@343
|
12 years |
cfuguet |
Using the Xicu SOFT IRQs (IPIs). Adding them on the Xicu
constructor
|
|
|
@342
|
12 years |
joannou |
Introducing tsar_generic_mmu_dspin_coherence platform (ring dspin for …
|
|
|
@341
|
12 years |
joannou |
In vci_cc_vcache_wrapper_dspin_coherence, DCACHE_TLB_PTE1_MISS and …
|
|
|
@339
|
12 years |
cfuguet |
Erasing always false condition in the if statement of the …
|
|
|
@338
|
12 years |
joannou |
* In vci_cc_vcache_wrapper_dspin_coherence, modified both states
…
|
|
|
@336
|
12 years |
cfuguet |
Bug fix in the vci_cc_vcache_wrapper and vci_mem_cache components
(and …
|
|
|
@335
|
12 years |
joannou |
Added llsc table initialization in both vci_mem_cache and …
|
|
|
@333
|
12 years |
joannou |
- In vci_cc_vcache_wrapper_dspin_coherence : initializing …
|
|
|
@332
|
12 years |
joannou |
Updated top.cpp in tsar_mono_mmu_dspin_coherence to respect new file …
|
|
|
@331
|
12 years |
joannou |
Renaming all files form vci_cc_vcache_wrapper_dspin_coherence and …
|
|
|
@330
|
12 years |
joannou |
* Commented debug in dspin_local_ring_fast_c
* Added test on plen …
|
|
|
@329
|
12 years |
joannou |
Added test on INST/DATA for the CLACK in the …
|
|
|
@328
|
12 years |
cfuguet |
Including TYPE_CLEANUP_ACK_INST and TYPE_CLEANUP_ACK_DATA in the …
|
|
|
@327
|
12 years |
simerabe |
introducing topcell examples using dspin ring interconnect
|
|
|
@326
|
12 years |
simerabe |
introducing 2 new components : simple and local ring interconnect …
|
|
|
@325
|
12 years |
joannou |
bugfix in vci_cc_vcache_wrapper_dspin_coherence :
- consume fifo in …
|
|
|
@323
|
12 years |
joannou |
removed unusefull flipflop r_*cache_cc_fifo_done + syntax correction …
|
|
|
@321
|
12 years |
joannou |
bugfix in vci_cc_vcache_wrapper_dspin_coherence in coherence type checking
|
|
|
@320
|
12 years |
cfuguet |
vci_mem_cache_dspin_coherence:
- Fixing typo error in …
|
|
|
@319
|
12 years |
cfuguet |
Fix bug in vci_mem_cache_dspin_coherence. The write signal
in the …
|
|
|
@318
|
12 years |
joannou |
vci_cc_vcache_wrapper_dspin_coherence now use DspinDhccpParam::* types …
|
|
|
@317
|
12 years |
cfuguet |
Introducing missing debug strings in the vci_mem_cache cpp file
|
|
|
@316
|
12 years |
joannou |
Introducing new tsar_mono_mmu_dspin_coherence platform
Same as …
|
|
|
@315
|
12 years |
joannou |
Introducing new dspin interface for …
|
|
|
@313
|
12 years |
cfuguet |
Erasing useless template parameters for the …
|
|
|
@312
|
12 years |
cfuguet |
Updating width of the way index in DSPIN coherence flits.
Using 2 bits …
|
|
|
@311
|
12 years |
cfuguet |
Including GET and SET methods for the FROM_L1_BC and
FROM_MC_BC bit in …
|
|
|
@310
|
12 years |
cfuguet |
Introducing FROM_L1_BC and FROM_MC_BC in dspin param class to
access …
|
|
|
@309
|
12 years |
joannou |
Bugfix : typo in component name (was 'dhcpp', is now 'dhccp')
|
|
|
@308
|
12 years |
cfuguet |
Fixing parameter name error in metadata of vci_mem_cache
|
|
|
@307
|
12 years |
cfuguet |
Including vci_mem_cache v5 using dspin interface for
the coherence …
|
|
|
@306
|
12 years |
joannou |
Added tsar_mono_mmu and tsar_generic_mmu platforms
|
|
|
@305
|
12 years |
joannou |
In vci_mem_cache component:
Adding an assert for cleanup commands …
|
|
|
@304
|
12 years |
joannou |
Bug fixing in vci_cc_vcache_wrapper component :
- In TGT_RSP_DCACHE, …
|
|
|
@300
|
12 years |
joannou |
Moved tsar modules vci_cc_vcache_wrapper and vci_mem_cache under the …
|
|
|
@299
|
12 years |
alain |
bug fixing: coherence interrupt must be taken in the MISS_DIR_UPDT states.
|
|
|
@296
|
12 years |
alain |
introducing major modifications in vci_cc_vcache_wrappers
- remove …
|
|
|
@295
|
12 years |
cfuguet |
Introducing branches/v5/ components directory. This branch
will be …
|
|
|
@294
|
12 years |
cfuguet |
Creating branch repertory for the TSAR svn repository.
Copying the …
|