- Timestamp:
- Feb 19, 2009, 5:31:47 PM (16 years ago)
- Location:
- trunk
- Files:
-
- 143 added
- 2 deleted
- 114 edited
- 3 moved
Legend:
- Unmodified
- Added
- Removed
-
trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Configuration.cpp
r109 r110 43 43 fromString<double> (_simulator->getParam("debug_cycle_start")), 44 44 fromString<double> (_simulator->getParam("debug_cycle_stop")), 45 fromString<double> (_simulator->getParam("debug_cycle_idle"))); 45 fromString<double> (_simulator->getParam("debug_idle_cycle")), 46 fromString<uint32_t> (_simulator->getParam("debug_idle_time"))); 46 47 47 48 log_init(fromString<bool>(_simulator->getParam("debug_have_log_file")), … … 124 125 delete _generator; 125 126 delete _instance; 127 // simulation_destroy(); 126 128 delete _param_statistics; 127 129 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Simulator_fromFile.cpp
r108 r110 74 74 } 75 75 //-------------------------------------------- 76 // Child : Simulation76 // Child : Component 77 77 //-------------------------------------------- 78 78 else 79 79 { 80 testNodeName (xml," simulation");80 testNodeName (xml,"component"); 81 81 testSingleton (xml,true); 82 82 } -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h
r97 r110 67 67 private : counter_t * _stat_percent_use_load_queue; 68 68 private : counter_t * _stat_percent_use_speculative_access_queue; 69 70 private : counter_t * _stat_nb_inst_load; 71 private : counter_t * _stat_nb_inst_load_commit_speculative; 72 private : counter_t * _stat_nb_inst_load_commit_miss; 69 73 70 74 // private : counter_t * _stat_nb_load_miss_speculation; … … 226 230 227 231 #ifdef STATISTICS 228 public : void statistics_declaration (morpheo::behavioural::Parameters_Statistics * param_statistics); 232 public : void statistics_allocation (morpheo::behavioural::Parameters_Statistics * param_statistics); 233 public : void statistics_deallocation (void); 229 234 #endif 230 235 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit.cpp
r88 r110 56 56 log_printf(INFO,Load_store_unit,FUNCTION,"Allocation of statistics"); 57 57 58 statistics_ declaration(param_statistics);58 statistics_allocation(param_statistics); 59 59 } 60 60 #endif … … 181 181 #ifdef STATISTICS 182 182 if (usage_is_set(_usage,USE_STATISTICS)) 183 { 184 log_printf(INFO,Load_store_unit,FUNCTION,"Generate Statistics file"); 185 186 delete _stat; 187 } 183 statistics_deallocation (); 188 184 #endif 189 185 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_transition.cpp
r106 r110 602 602 _load_queue[index_load]._exception = EXCEPTION_MEMORY_MISS_SPECULATION; 603 603 _load_queue[index_load]._write_rd = 1; // write the good result 604 605 #ifdef STATISTICS 606 if (usage_is_set(_usage,USE_STATISTICS)) 607 (*_stat_nb_inst_load_commit_miss) ++; 608 #endif 604 609 } 605 610 … … 696 701 #ifdef DEBUG_TEST 697 702 if (is_operation_memory_store_head(operation) == true) 698 throw E rrorMorpheo(_("Transaction in memory_in's interface, actual state of store_queue is \"STORE_QUEUE_NO_VALID_NO_SPECULATIVE\", also a previous store_head have been receiveid. But this operation is a store_head."));703 throw ERRORMORPHEO(FUNCTION,_("Transaction in memory_in's interface, actual state of store_queue is \"STORE_QUEUE_NO_VALID_NO_SPECULATIVE\", also a previous store_head have been receiveid. But this operation is a store_head.")); 699 704 #endif 700 705 // Test if have a new exception (priority : miss_speculation) … … 714 719 #ifdef DEBUG_TEST 715 720 if (is_operation_memory_store_head(operation) == false) 716 throw E rrorMorpheo(_("Transaction in memory_in's interface, actual state of store_queue is \"STORE_QUEUE_VALID_SPECULATIVE\", also a previous access with register and address have been receiveid. But this operation is a not store_head."));721 throw ERRORMORPHEO(FUNCTION,_("Transaction in memory_in's interface, actual state of store_queue is \"STORE_QUEUE_VALID_SPECULATIVE\", also a previous access with register and address have been receiveid. But this operation is a not store_head.")); 717 722 #endif 718 723 if (operation == OPERATION_MEMORY_STORE_HEAD_KO) … … 729 734 case STORE_QUEUE_COMMIT : 730 735 { 731 throw E rrorMorpheo("<Load_store_unit::function_speculative_load_commit_transition> Invalid state and operation");736 throw ERRORMORPHEO(FUNCTION,"<Load_store_unit::function_speculative_load_commit_transition> Invalid state and operation"); 732 737 } 733 738 } … … 847 852 // if the speculation is a miss, write_rd is re set at 1. 848 853 _load_queue [internal_MEMORY_OUT_PTR]._write_rd = 0; 854 855 #ifdef STATISTICS 856 if (usage_is_set(_usage,USE_STATISTICS)) 857 (*_stat_nb_inst_load_commit_speculative) ++; 858 #endif 859 849 860 break; 850 861 } … … 889 900 case SELECT_LOAD_QUEUE : 890 901 { 891 throw E rrorMorpheo(_("Invalid selection"));902 throw ERRORMORPHEO(FUNCTION,_("Invalid selection")); 892 903 break; 893 904 } … … 964 975 965 976 _speculative_access_queue_control->pop(); 966 } 977 978 #ifdef STATISTICS 979 if (usage_is_set(_usage,USE_STATISTICS)) 980 (*_stat_nb_inst_load) ++; 981 #endif 982 } 967 983 968 984 //================================================================ … … 993 1009 #ifdef DEBUG_TEST 994 1010 if (not have_dcache_rsp(_load_queue [packet_id]._operation)) 995 throw E rrorMorpheo(_("Receive of respons, but the corresponding operation don't wait a respons."));1011 throw ERRORMORPHEO(FUNCTION,_("Receive of respons, but the corresponding operation don't wait a respons.")); 996 1012 #endif 997 1013 … … 1032 1048 case LOAD_QUEUE_WAIT_CHECK : _load_queue [packet_id]._state = LOAD_QUEUE_COMMIT_CHECK; break; 1033 1049 case LOAD_QUEUE_WAIT : _load_queue [packet_id]._state = LOAD_QUEUE_COMMIT ; break; 1034 default : throw E rrorMorpheo(_("Illegal state (dcache_rsp).")); break;1050 default : throw ERRORMORPHEO(FUNCTION,_("Illegal state (dcache_rsp).")); break; 1035 1051 } 1036 1052 } -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_statistics_allocation.cpp
r108 r110 20 20 21 21 #undef FUNCTION 22 #define FUNCTION "Load_store_unit::statistics_ declaration"23 void Load_store_unit::statistics_ declaration (morpheo::behavioural::Parameters_Statistics * param_statistics)22 #define FUNCTION "Load_store_unit::statistics_allocation" 23 void Load_store_unit::statistics_allocation (morpheo::behavioural::Parameters_Statistics * param_statistics) 24 24 { 25 25 log_printf(FUNC,Load_store_unit,FUNCTION,"Begin"); … … 49 49 _stat->create_expr("percent_use_speculative_access_queue" , "/ * average_use_speculative_access_queue 100 " + toString(_param->_size_speculative_access_queue), false); 50 50 51 52 _stat_nb_inst_load = _stat->create_variable("nb_inst_load" ); 53 _stat_nb_inst_load_commit_speculative = _stat->create_variable("nb_inst_load_commit_speculative"); 54 _stat_nb_inst_load_commit_miss = _stat->create_variable("nb_inst_load_commit_miss" ); 55 56 _stat->create_expr_percent("percent_nb_inst_load_commit_speculative","nb_inst_load_commit_speculative", "nb_inst_load" , "Percent of load instruction with a speculative commit "); 57 _stat->create_expr_percent("percent_nb_inst_load_commit_miss" ,"nb_inst_load_commit_miss" , "nb_inst_load_commit_speculative", "Percent of load instruction with a miss speculative commit"); 58 59 51 60 log_printf(FUNC,Load_store_unit,FUNCTION,"End"); 52 61 }; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/src/Reservation_station_genMoore.cpp
r88 r110 4 4 * $Id$ 5 5 * 6 * [ 6 * [ Description ] 7 7 * 8 8 */ … … 27 27 log_function(Reservation_station,FUNCTION,_name.c_str()); 28 28 29 // ~~~~~[ 29 // ~~~~~[ Interface "insert" ]~~~~~~~~~~~~~~~~~~~~~~~~ 30 30 31 31 // accept a new instructions when reservation_station is not full … … 38 38 PORT_WRITE(out_INSERT_ACK, internal_INSERT_ACK); 39 39 40 // ~~~~~[ 40 // ~~~~~[ Interface "retire" ]~~~~~~~~~~~~~~~~~~~~~~~ 41 41 42 42 uint32_t index_queue=0; … … 46 46 { 47 47 bool val = false; 48 uint32_t index_find = 0;; 48 uint32_t index_find = 0; 49 50 log_printf(TRACE,Reservation_station,FUNCTION," * RETIRE [%d]",i); 49 51 50 52 for (; ( … … 67 69 ( 68 70 #ifdef SYSTEMC_VHDL_COMPATIBILITY 69 _queue_valid [index_queue]and71 _queue_valid [index_queue] and 70 72 #endif 71 73 _queue[index_find]._data_ra_val and … … 74 76 ); 75 77 76 // cout << "========== Moore : " << endl 77 // << " * i : " << i << endl 78 // << " * val : " << val << endl 79 // << " * index_queue : " << index_queue << endl 80 // << " * index_find : " << index_find << endl; 78 log_printf( 79 #ifdef SYSTEMC_VHDL_COMPATIBILITY 80 TRACE,Reservation_station,FUNCTION," [%d] valid : %d, data ra %d, rb %d, rc %d - %d", 81 index_find, 82 _queue_valid [index_queue], 83 #else 84 TRACE,Reservation_station,FUNCTION," [%d] data ra %d, rb %d, rc %d - %d", 85 index_find, 86 #endif 87 _queue[index_find]._data_ra_val, 88 _queue[index_find]._data_rb_val, 89 _queue[index_find]._data_rc_val, 90 val); 81 91 } 82 92 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/src/test.cpp
r108 r110 100 100 ALLOC1_SC_SIGNAL(out_PREDICT_ADDRESS_SRC ,"out_PREDICT_ADDRESS_SRC ",Tgeneral_data_t ,_param->_nb_inst_decod); 101 101 ALLOC1_SC_SIGNAL(out_PREDICT_ADDRESS_DEST ,"out_PREDICT_ADDRESS_DEST ",Tgeneral_data_t ,_param->_nb_inst_decod); 102 //ALLOC1_SC_SIGNAL( in_PREDICT_CAN_CONTINUE ," in_PREDICT_CAN_CONTINUE ",Tcontrol_t ,_param->_nb_inst_decod);102 ALLOC1_SC_SIGNAL( in_PREDICT_CAN_CONTINUE ," in_PREDICT_CAN_CONTINUE ",Tcontrol_t ,_param->_nb_inst_decod); 103 103 ALLOC1_SC_SIGNAL( in_CONTEXT_DECOD_ENABLE ," in_CONTEXT_DECOD_ENABLE ",Tcontrol_t ,_param->_nb_context); 104 104 ALLOC1_SC_SIGNAL( in_CONTEXT_DEPTH_VAL ," in_CONTEXT_DEPTH_VAL ",Tcontrol_t ,_param->_nb_context); … … 183 183 INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_ADDRESS_SRC ,_param->_nb_inst_decod); 184 184 INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_ADDRESS_DEST ,_param->_nb_inst_decod); 185 //INSTANCE1_SC_SIGNAL(_Decod, in_PREDICT_CAN_CONTINUE ,_param->_nb_inst_decod);185 INSTANCE1_SC_SIGNAL(_Decod, in_PREDICT_CAN_CONTINUE ,_param->_nb_inst_decod); 186 186 INSTANCE1_SC_SIGNAL(_Decod, in_CONTEXT_DECOD_ENABLE ,_param->_nb_context); 187 187 INSTANCE1_SC_SIGNAL(_Decod, in_CONTEXT_DEPTH_VAL ,_param->_nb_context); … … 306 306 307 307 in_PREDICT_ACK [i]->write((rand()%100)<percent_transaction_predict); 308 //in_PREDICT_CAN_CONTINUE [i]->write(0);308 in_PREDICT_CAN_CONTINUE [i]->write(0); 309 309 } 310 310 } … … 486 486 delete [] out_PREDICT_ADDRESS_SRC ; 487 487 delete [] out_PREDICT_ADDRESS_DEST ; 488 //delete [] in_PREDICT_CAN_CONTINUE ;488 delete [] in_PREDICT_CAN_CONTINUE ; 489 489 490 490 delete [] in_CONTEXT_DECOD_ENABLE ; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/include/Decod.h
r108 r110 119 119 public : SC_OUT(Tgeneral_data_t ) ** out_PREDICT_ADDRESS_SRC ;//[nb_inst_decod] 120 120 public : SC_OUT(Tgeneral_data_t ) ** out_PREDICT_ADDRESS_DEST ;//[nb_inst_decod] 121 //public : SC_IN (Tcontrol_t ) ** in_PREDICT_CAN_CONTINUE ;//[nb_inst_decod]121 public : SC_IN (Tcontrol_t ) ** in_PREDICT_CAN_CONTINUE ;//[nb_inst_decod] 122 122 123 123 // ~~~~~[ Interface : "context" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_allocation.cpp
r108 r110 124 124 ALLOC1_SIGNAL_OUT(out_PREDICT_ADDRESS_SRC ,"address_src" ,Tgeneral_data_t ,_param->_size_instruction_address ); 125 125 ALLOC1_SIGNAL_OUT(out_PREDICT_ADDRESS_DEST ,"address_dest" ,Tgeneral_data_t ,_param->_size_instruction_address ); 126 //ALLOC1_SIGNAL_IN ( in_PREDICT_CAN_CONTINUE ,"can_continue" ,Tcontrol_t ,1 );126 ALLOC1_SIGNAL_IN ( in_PREDICT_CAN_CONTINUE ,"can_continue" ,Tcontrol_t ,1 ); 127 127 } 128 128 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_deallocation.cpp
r108 r110 79 79 DELETE1_SIGNAL(out_PREDICT_ADDRESS_SRC ,_param->_nb_inst_decod,_param->_size_instruction_address ); 80 80 DELETE1_SIGNAL(out_PREDICT_ADDRESS_DEST ,_param->_nb_inst_decod,_param->_size_instruction_address ); 81 //DELETE1_SIGNAL( in_PREDICT_CAN_CONTINUE ,_param->_nb_inst_decod,1 );81 DELETE1_SIGNAL( in_PREDICT_CAN_CONTINUE ,_param->_nb_inst_decod,1 ); 82 82 83 83 DELETE1_SIGNAL(in_CONTEXT_DECOD_ENABLE, _param->_nb_context,1); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_genMealy.cpp
r108 r110 43 43 44 44 Tcontrol_t can_continue [_param->_nb_context]; 45 // Tcontrol_t can_continue_next [_param->_nb_context]; 46 // Tcontrol_t have_decod_branch [_param->_nb_context]; 45 Tcontrol_t have_decod_branch [_param->_nb_context]; 47 46 48 47 for (uint32_t i=0; i<_param->_nb_context; i++) … … 53 52 54 53 can_continue [i] = PORT_READ(in_CONTEXT_DECOD_ENABLE [i]); 55 // can_continue_next [i] = PORT_READ(in_CONTEXT_DECOD_ENABLE [i]); 56 // have_decod_branch [i] = false; 54 have_decod_branch [i] = false; 57 55 } 58 56 … … 80 78 log_printf(TRACE,Decod,FUNCTION," * IFETCH [%d][%d]",x,y); 81 79 log_printf(TRACE,Decod,FUNCTION," * decod_ack [%d] : %d",i,PORT_READ(in_DECOD_ACK [i])); 82 83 // can_continue [x] = can_continue_next [x];84 80 85 81 decod_val [i] = true; // fetch_val and decod_enable … … 131 127 132 128 Ttype_t type = _decod_instruction->_type; 133 Tdepth_t depth = (_param->_have_port_depth)?PORT_READ(in_CONTEXT_DEPTH [x]):0; // DEPTH_CURRENT 134 129 // Depth current. If have decod a branch and i can continue : depth = depth_next 130 Tdepth_t depth = (_param->_have_port_depth)?PORT_READ(in_CONTEXT_DEPTH [x]):0; 131 132 if ((_param->_nb_branch_speculated[x] > 0) and have_decod_branch [x]) 133 depth = (depth+1)%_param->_nb_branch_speculated[x]; 134 135 135 if (_param->_have_port_context_id) 136 136 PORT_WRITE(out_DECOD_CONTEXT_ID [i], x); … … 179 179 log_printf(TRACE,Decod,FUNCTION," * address dest : %.8x (%.8x)",_decod_instruction->_address_next,_decod_instruction->_address_next<<2); 180 180 181 predict_val [i] = ifetch_ack [x][y] // and decod_val [i] 181 // test if have already decod an branch : one branch per context 182 predict_val [i] = not have_decod_branch [x] and ifetch_ack [x][y] // and decod_val [i] 182 183 ; 183 decod_val [i] &= PORT_READ(in_PREDICT_ACK [i]);// predict_ack and fetch_val and decod_enable184 ifetch_ack [x][y] &= PORT_READ(in_PREDICT_ACK [i]);// predict_ack and fetch_val and decod_enable and decod_ack184 decod_val [i] &= not have_decod_branch [x] and PORT_READ(in_PREDICT_ACK [i]);// predict_ack and fetch_val and decod_enable 185 ifetch_ack [x][y] &= not have_decod_branch [x] and PORT_READ(in_PREDICT_ACK [i]);// predict_ack and fetch_val and decod_enable and decod_ack 185 186 186 187 if (_param->_have_port_context_id) … … 196 197 PORT_WRITE(out_PREDICT_ADDRESS_DEST [i],_decod_instruction->_address_next ); 197 198 198 //can_continue_next [x] = PORT_READ(in_PREDICT_CAN_CONTINUE [i]); // can continue is set if direction is "not take" (also, continue is sequential order) 199 can_continue [x] = false; // one branch per context, the DS don't execute 200 // can_continue_next [x] = false; // one branch per context, the DS don't execute 201 // have_decod_branch [x] = true; 199 // can continue is set if direction is "not take" (also, continue is sequential order) 200 201 // can_continue [x] = false; // one branch per context, the DS don't execute 202 can_continue [x]&= PORT_READ(in_PREDICT_CAN_CONTINUE [i]); // one branch per context, the DS don't execute 203 have_decod_branch [x] = true; 202 204 } 203 205 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_statistics_allocation.cpp
r88 r110 33 33 _stat->create_expr_average_by_cycle ("average_nb_inst_decod","sum_inst_decod","","Average of decod instruction by cycle"); 34 34 _stat->create_expr_percent ("percent_nb_inst_decod","average_nb_inst_decod", toString(_param->_nb_inst_decod), "Percent of decod instruction by cycle"); 35 36 37 35 38 36 log_printf(FUNC,Decod,FUNCTION,"End"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/include/Decod_queue.h
r108 r110 55 55 private : counter_t ** _stat_nb_inst; 56 56 private : counter_t * _stat_use_queue; 57 58 private : counter_t * _stat_sum_inst_enable; 59 private : counter_t * _stat_sum_transaction_decod_in; 60 private : counter_t * _stat_average_occupation_bundle; 57 61 #endif 58 62 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_statistics_allocation.cpp
r88 r110 29 29 param_statistics); 30 30 31 _stat_sum_transaction_decod_in = _stat->create_variable("sum_transaction_decod_in"); 32 _stat_sum_inst_enable = _stat->create_variable("sum_inst_enable"); 33 _stat_average_occupation_bundle= _stat->create_counter ("average_occupation_bundle", "", "Occupation average of instruction's bundle."); 34 35 _stat->create_expr ("average_occupation_bundle" ,"/ sum_inst_enable sum_transaction_decod_in"); 36 _stat->create_expr_percent ("percent_occupation_bundle" ,"average_occupation_bundle", toString(_param->_nb_inst_decod),"Percent of instruction's bundle occupation."); 37 31 38 _stat_use_queue = _stat->create_variable ("use_queue"); 32 39 _stat_nb_inst = new counter_t * [_param->_nb_context]; … … 39 46 40 47 _stat->create_expr_average_by_cycle("average_inst_"+toString(i), "nb_inst_"+toString(i), "", toString(_("Average instruction number in decod_queue by cycle (context %d)"),i)); 41 _stat->create_expr_percent ("percent_use_inst_"+toString(i) , "average_inst_"+toString(i), toString(_param->_ size_queue), toString(_("Percent decod_queue's occupation (context %d)"),i));48 _stat->create_expr_percent ("percent_use_inst_"+toString(i) , "average_inst_"+toString(i), toString(_param->_nb_instruction_in_queue), toString(_("Percent decod_queue's occupation (context %d)"),i)); 42 49 43 50 if (i == 0) … … 48 55 49 56 _stat->create_expr_average_by_cycle("average_inst", expr_average_inst, "", _("Average instruction number in decod_queue by cycle (all context)")); 50 _stat->create_expr_percent ("percent_use_inst" , "average_inst", toString(_param->_ size_queue), _("Percent decod_queue's occupation (all context)"));57 _stat->create_expr_percent ("percent_use_inst" , "average_inst", toString(_param->_nb_instruction_in_queue), _("Percent decod_queue's occupation (all context)")); 51 58 52 59 _stat->create_expr_average_by_cycle("average_use_queue", "use_queue", "", _("Average slot decod_queue occupation by cycle.")); 53 _stat->create_expr_percent ("percent_use_queue", "average_use_queue", toString(_param->_ size_queue), _("Percent slot decod_queue occupation."));60 _stat->create_expr_percent ("percent_use_queue", "average_use_queue", toString(_param->_nb_instruction_in_queue), _("Percent slot decod_queue occupation.")); 54 61 55 62 log_end(Decod_queue,FUNCTION); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_transition.cpp
r109 r110 51 51 entry = new decod_queue_entry_t (_param->_nb_inst_decod); 52 52 reg_QUEUE->push_back(entry); 53 54 #ifdef STATISTICS 55 if (usage_is_set(_usage,USE_STATISTICS)) 56 (*_stat_sum_transaction_decod_in) ++; 57 #endif 53 58 } 59 60 #ifdef STATISTICS 61 if (usage_is_set(_usage,USE_STATISTICS)) 62 (*_stat_sum_inst_enable) ++; 63 #endif 54 64 55 65 Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_DECOD_IN_CONTEXT_ID [i]):0; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/SelfTest/src/test.cpp
r108 r110 103 103 ALLOC1_SC_SIGNAL(out_PREDICT_ADDRESS_SRC ,"out_PREDICT_ADDRESS_SRC ",Tgeneral_data_t ,_param->_nb_inst_decod); 104 104 ALLOC1_SC_SIGNAL(out_PREDICT_ADDRESS_DEST ,"out_PREDICT_ADDRESS_DEST ",Tgeneral_data_t ,_param->_nb_inst_decod); 105 //ALLOC1_SC_SIGNAL( in_PREDICT_CAN_CONTINUE ," in_PREDICT_CAN_CONTINUE ",Tcontrol_t ,_param->_nb_inst_decod);105 ALLOC1_SC_SIGNAL( in_PREDICT_CAN_CONTINUE ," in_PREDICT_CAN_CONTINUE ",Tcontrol_t ,_param->_nb_inst_decod); 106 106 107 107 ALLOC1_SC_SIGNAL( in_DEPTH_MIN ," in_DEPTH_MIN ",Tdepth_t ,_param->_nb_context); … … 194 194 INSTANCE1_SC_SIGNAL(_Decod_unit,out_PREDICT_ADDRESS_SRC ,_param->_nb_inst_decod); 195 195 INSTANCE1_SC_SIGNAL(_Decod_unit,out_PREDICT_ADDRESS_DEST ,_param->_nb_inst_decod); 196 //INSTANCE1_SC_SIGNAL(_Decod_unit, in_PREDICT_CAN_CONTINUE ,_param->_nb_inst_decod);196 INSTANCE1_SC_SIGNAL(_Decod_unit, in_PREDICT_CAN_CONTINUE ,_param->_nb_inst_decod); 197 197 198 198 if (_param->_have_port_depth) … … 332 332 333 333 in_PREDICT_ACK [i]->write((rand()%100)<percent_transaction_predict); 334 //in_PREDICT_CAN_CONTINUE [i]->write(0);334 in_PREDICT_CAN_CONTINUE [i]->write(0); 335 335 } 336 336 } … … 526 526 DELETE1_SC_SIGNAL(out_PREDICT_ADDRESS_SRC ,_param->_nb_inst_decod); 527 527 DELETE1_SC_SIGNAL(out_PREDICT_ADDRESS_DEST ,_param->_nb_inst_decod); 528 //DELETE1_SC_SIGNAL( in_PREDICT_CAN_CONTINUE ,_param->_nb_inst_decod);528 DELETE1_SC_SIGNAL( in_PREDICT_CAN_CONTINUE ,_param->_nb_inst_decod); 529 529 530 530 DELETE1_SC_SIGNAL( in_DEPTH_MIN ,_param->_nb_context); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/include/Decod_unit.h
r108 r110 118 118 public : SC_OUT(Tgeneral_data_t ) ** out_PREDICT_ADDRESS_SRC ;//[nb_inst_decod] 119 119 public : SC_OUT(Tgeneral_data_t ) ** out_PREDICT_ADDRESS_DEST ;//[nb_inst_decod] 120 //public : SC_IN (Tcontrol_t ) ** in_PREDICT_CAN_CONTINUE ;//[nb_inst_decod]120 public : SC_IN (Tcontrol_t ) ** in_PREDICT_CAN_CONTINUE ;//[nb_inst_decod] 121 121 122 122 // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/src/Decod_unit_allocation.cpp
r108 r110 124 124 ALLOC1_SIGNAL_OUT(out_PREDICT_ADDRESS_SRC ,"address_src" ,Tgeneral_data_t ,_param->_size_instruction_address ); 125 125 ALLOC1_SIGNAL_OUT(out_PREDICT_ADDRESS_DEST ,"address_dest" ,Tgeneral_data_t ,_param->_size_instruction_address ); 126 //ALLOC1_SIGNAL_IN ( in_PREDICT_CAN_CONTINUE ,"can_continue" ,Tcontrol_t ,1 );126 ALLOC1_SIGNAL_IN ( in_PREDICT_CAN_CONTINUE ,"can_continue" ,Tcontrol_t ,1 ); 127 127 } 128 128 … … 365 365 PORT_MAP(_component,src ,"out_PREDICT_"+toString(i)+"_ADDRESS_DEST" , 366 366 dest,"out_PREDICT_"+toString(i)+"_ADDRESS_DEST" ); 367 //PORT_MAP(_component,src , "in_PREDICT_"+toString(i)+"_CAN_CONTINUE" ,368 //dest, "in_PREDICT_"+toString(i)+"_CAN_CONTINUE" );367 PORT_MAP(_component,src , "in_PREDICT_"+toString(i)+"_CAN_CONTINUE" , 368 dest, "in_PREDICT_"+toString(i)+"_CAN_CONTINUE" ); 369 369 } 370 370 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/src/Decod_unit_deallocation.cpp
r108 r110 78 78 DELETE1_SIGNAL(out_PREDICT_ADDRESS_SRC ,_param->_nb_inst_decod,_param->_size_instruction_address); 79 79 DELETE1_SIGNAL(out_PREDICT_ADDRESS_DEST ,_param->_nb_inst_decod,_param->_size_instruction_address); 80 //DELETE1_SIGNAL( in_PREDICT_CAN_CONTINUE ,_param->_nb_inst_decod,1 );80 DELETE1_SIGNAL( in_PREDICT_CAN_CONTINUE ,_param->_nb_inst_decod,1 ); 81 81 82 82 DELETE1_SIGNAL( in_DEPTH_MIN ,_param->_nb_context,_param->_size_depth); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_statistics_allocation.cpp
r81 r110 42 42 _stat->create_expr ("sum_use_queue" ,"+ + sum_use_queue_wait_rsp sum_use_queue_have_rsp sum_use_queue_error_wait_rsp"); 43 43 _stat->create_expr_average_by_cycle("average_use_queue" ,"sum_use_queue" ,"","Average occupation of ifetch queue"); 44 _stat->create_expr_percent ("percent_use_queue" ,"average_use_queue" ,toString(_param->_ size_queue),"Percent of occupation of ifetch queue");44 _stat->create_expr_percent ("percent_use_queue" ,"average_use_queue" ,toString(_param->_nb_instruction_in_queue),"Percent of occupation of ifetch queue"); 45 45 _stat->create_expr_percent ("percent_use_queue_wait_rsp" ,"sum_use_queue_wait_rsp" ,"sum_use_queue","Part of ifetch queue that wait the respons icache"); 46 46 _stat->create_expr_percent ("percent_use_queue_have_rsp" ,"sum_use_queue_have_rsp" ,"sum_use_queue","Part of ifetch queue that wait the decod"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Makefile.deps
r81 r110 16 16 include $(DIR_MORPHEO)/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Direction_Glue/Makefile.deps 17 17 endif 18 #ifndef Meta_Predictor19 #include $(DIR_MORPHEO)/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Makefile.deps20 #endif18 ifndef Meta_Predictor 19 include $(DIR_MORPHEO)/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Makefile.deps 20 endif 21 21 22 22 #-----[ Directory ]---------------------------------------- … … 28 28 Direction_LIBRARY = -lDirection \ 29 29 $(Behavioural_LIBRARY) \ 30 $(Direction_Glue_LIBRARY) 31 #$(Meta_Predictor_LIBRARY)30 $(Direction_Glue_LIBRARY) \ 31 $(Meta_Predictor_LIBRARY) 32 32 33 33 Direction_DIR_LIBRARY = -L$(Direction_DIR)/lib \ 34 34 $(Behavioural_DIR_LIBRARY) \ 35 $(Direction_Glue_DIR_LIBRARY) 36 #$(Meta_Predictor_DIR_LIBRARY)35 $(Direction_Glue_DIR_LIBRARY) \ 36 $(Meta_Predictor_DIR_LIBRARY) 37 37 38 38 #-----[ Rules ]-------------------------------------------- … … 43 43 $(MAKE) Direction_Glue_library; \ 44 44 $(MAKE) --directory=$(Direction_DIR) --makefile=Makefile; 45 #$(MAKE) Meta_Predictor_library; \45 $(MAKE) Meta_Predictor_library; \ 46 46 47 47 Direction_library_clean : … … 50 50 $(MAKE) Direction_Glue_library_clean; \ 51 51 $(MAKE) --directory=$(Direction_DIR) --makefile=Makefile clean; 52 #$(MAKE) Meta_Predictor_library_clean; \52 $(MAKE) Meta_Predictor_library_clean; \ -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/SelfTest/src/test.cpp
r100 r110 115 115 ALLOC2_SC_SIGNAL( in_DECOD_ADDRESS_SRC ," in_DECOD_ADDRESS_SRC ",Taddress_t ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); 116 116 ALLOC2_SC_SIGNAL( in_DECOD_ADDRESS_DEST ," in_DECOD_ADDRESS_DEST ",Taddress_t ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); 117 ALLOC2_SC_SIGNAL(out_DECOD_CAN_CONTINUE ,"out_DECOD_CAN_CONTINUE ",Tcontrol_t ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); 117 118 ALLOC1_SC_SIGNAL(out_DECOD_BTB_VAL ,"out_DECOD_BTB_VAL ",Tcontrol_t ,_param->_nb_inst_branch_decod); 118 119 ALLOC1_SC_SIGNAL( in_DECOD_BTB_ACK ," in_DECOD_BTB_ACK ",Tcontrol_t ,_param->_nb_inst_branch_decod); … … 146 147 ALLOC1_SC_SIGNAL(out_DECOD_UPT_UPDATE_PREDICTION_ID ,"out_DECOD_UPT_UPDATE_PREDICTION_ID ",Tprediction_ptr_t ,_param->_nb_inst_branch_decod); 147 148 ALLOC1_SC_SIGNAL(out_DECOD_UPT_IS_ACCURATE ,"out_DECOD_UPT_IS_ACCURATE ",Tcontrol_t ,_param->_nb_inst_branch_decod); 149 ALLOC1_SC_SIGNAL( in_DECOD_UPT_CAN_CONTINUE ," in_DECOD_UPT_CAN_CONTINUE ",Tcontrol_t ,_param->_nb_inst_branch_decod); 148 150 149 151 ALLOC1_SC_SIGNAL(out_UPDATE_BTB_VAL ,"out_UPDATE_BTB_VAL ",Tcontrol_t ,_param->_nb_inst_branch_update); … … 268 270 INSTANCE2_SC_SIGNAL(_Prediction_unit_Glue, in_DECOD_ADDRESS_SRC ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); 269 271 INSTANCE2_SC_SIGNAL(_Prediction_unit_Glue, in_DECOD_ADDRESS_DEST ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); 272 INSTANCE2_SC_SIGNAL(_Prediction_unit_Glue,out_DECOD_CAN_CONTINUE ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); 270 273 INSTANCE1_SC_SIGNAL(_Prediction_unit_Glue,out_DECOD_BTB_VAL ,_param->_nb_inst_branch_decod); 271 274 INSTANCE1_SC_SIGNAL(_Prediction_unit_Glue, in_DECOD_BTB_ACK ,_param->_nb_inst_branch_decod); … … 303 306 INSTANCE1_SC_SIGNAL(_Prediction_unit_Glue,out_DECOD_UPT_UPDATE_PREDICTION_ID ,_param->_nb_inst_branch_decod); 304 307 INSTANCE1_SC_SIGNAL(_Prediction_unit_Glue,out_DECOD_UPT_IS_ACCURATE ,_param->_nb_inst_branch_decod); 308 INSTANCE1_SC_SIGNAL(_Prediction_unit_Glue, in_DECOD_UPT_CAN_CONTINUE ,_param->_nb_inst_branch_decod); 305 309 306 310 INSTANCE1_SC_SIGNAL(_Prediction_unit_Glue,out_UPDATE_BTB_VAL ,_param->_nb_inst_branch_update); … … 799 803 DELETE2_SC_SIGNAL( in_DECOD_ADDRESS_SRC ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); 800 804 DELETE2_SC_SIGNAL( in_DECOD_ADDRESS_DEST ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); 805 DELETE2_SC_SIGNAL(out_DECOD_CAN_CONTINUE ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); 801 806 DELETE1_SC_SIGNAL(out_DECOD_BTB_VAL ,_param->_nb_inst_branch_decod); 802 807 DELETE1_SC_SIGNAL( in_DECOD_BTB_ACK ,_param->_nb_inst_branch_decod); … … 830 835 DELETE1_SC_SIGNAL(out_DECOD_UPT_UPDATE_PREDICTION_ID ,_param->_nb_inst_branch_decod); 831 836 DELETE1_SC_SIGNAL(out_DECOD_UPT_IS_ACCURATE ,_param->_nb_inst_branch_decod); 837 DELETE1_SC_SIGNAL( in_DECOD_UPT_CAN_CONTINUE ,_param->_nb_inst_branch_decod); 832 838 833 839 DELETE1_SC_SIGNAL(out_UPDATE_BTB_VAL ,_param->_nb_inst_branch_update); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/include/Prediction_unit_Glue.h
r88 r110 128 128 public : SC_IN (Taddress_t ) *** in_DECOD_ADDRESS_SRC ; //[nb_decod_unit][nb_inst_decod] 129 129 public : SC_IN (Taddress_t ) *** in_DECOD_ADDRESS_DEST ; //[nb_decod_unit][nb_inst_decod] 130 public : SC_OUT(Tcontrol_t ) *** out_DECOD_CAN_CONTINUE ; //[nb_decod_unit][nb_inst_decod] 130 131 131 132 public : SC_OUT(Tcontrol_t ) ** out_DECOD_BTB_VAL ; //[nb_inst_branch_decod] … … 162 163 public : SC_OUT(Tprediction_ptr_t ) ** out_DECOD_UPT_UPDATE_PREDICTION_ID ; //[nb_inst_branch_decod] 163 164 public : SC_OUT(Tcontrol_t ) ** out_DECOD_UPT_IS_ACCURATE ; //[nb_inst_branch_decod] 165 public : SC_IN (Tcontrol_t ) ** in_DECOD_UPT_CAN_CONTINUE ; //[nb_inst_branch_decod] 164 166 165 167 // ~~~~~[ Interface : "update" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/src/Prediction_unit_Glue.cpp
r88 r110 1058 1058 << (*(in_DECOD_RAS_ADDRESS_POP [i] )) 1059 1059 // << (*(in_DECOD_RAS_INDEX [i] )) 1060 << (*(in_DECOD_UPT_ACK [i] )) ; 1060 << (*(in_DECOD_UPT_ACK [i] )) 1061 << (*(in_DECOD_UPT_CAN_CONTINUE [i] )) ; 1061 1062 } 1062 1063 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/src/Prediction_unit_Glue_allocation.cpp
r98 r110 149 149 _ALLOC2_SIGNAL_IN ( in_DECOD_ADDRESS_SRC ,"address_src" ,Taddress_t ,_param->_size_instruction_address ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); 150 150 _ALLOC2_SIGNAL_IN ( in_DECOD_ADDRESS_DEST ,"address_dest" ,Taddress_t ,_param->_size_instruction_address ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); 151 _ALLOC2_SIGNAL_OUT(out_DECOD_CAN_CONTINUE ,"can_continue" ,Tcontrol_t ,1 ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); 151 152 } 152 153 … … 195 196 ALLOC1_SIGNAL_OUT(out_DECOD_UPT_UPDATE_PREDICTION_ID,"update_prediction_id",Tprediction_ptr_t ,_param->_size_depth ); 196 197 ALLOC1_SIGNAL_OUT(out_DECOD_UPT_IS_ACCURATE ,"is_accurate" ,Tcontrol_t ,1); 198 ALLOC1_SIGNAL_IN ( in_DECOD_UPT_CAN_CONTINUE ,"can_continue" ,Tcontrol_t ,1); 197 199 } 198 200 } -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/src/Prediction_unit_Glue_deallocation.cpp
r88 r110 91 91 DELETE2_SIGNAL( in_DECOD_ADDRESS_SRC ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1],_param->_size_instruction_address ); 92 92 DELETE2_SIGNAL( in_DECOD_ADDRESS_DEST ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1],_param->_size_instruction_address ); 93 DELETE2_SIGNAL(out_DECOD_CAN_CONTINUE ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1],1); 94 93 95 DELETE1_SIGNAL(out_DECOD_BTB_VAL ,_param->_nb_inst_branch_decod,1); 94 96 DELETE1_SIGNAL( in_DECOD_BTB_ACK ,_param->_nb_inst_branch_decod,1); … … 124 126 DELETE1_SIGNAL(out_DECOD_UPT_UPDATE_PREDICTION_ID,_param->_nb_inst_branch_decod,_param->_size_depth); 125 127 DELETE1_SIGNAL(out_DECOD_UPT_IS_ACCURATE ,_param->_nb_inst_branch_decod,1); 128 DELETE1_SIGNAL( in_DECOD_UPT_CAN_CONTINUE ,_param->_nb_inst_branch_decod,1); 126 129 127 130 // ~~~~~[ Interface : "update" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/src/Prediction_unit_Glue_genMealy_decod.cpp
r107 r110 78 78 // * branch was not detected 79 79 Tcontrol_t miss_decod = (branch_state == BRANCH_STATE_NONE); 80 Tcontrol_t can_continue = false; 80 81 81 82 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * DECOD [%d][%d] : valid",decod_unit,i); … … 90 91 { 91 92 Tbranch_condition_t condition = PORT_READ(in_DECOD_BRANCH_CONDITION [decod_unit][i]); 92 Tcontrol_t direction = PORT_READ(in_DECOD_BRANCH_DIRECTION [decod_unit][i]);93 Tcontrol_t take; 93 94 Taddress_t address_src = PORT_READ(in_DECOD_ADDRESS_SRC [decod_unit][i]); 94 95 Taddress_t address_dest = PORT_READ(in_DECOD_ADDRESS_DEST [decod_unit][i]); … … 105 106 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * BRANCH_CONDITION_NONE_WITH_WRITE_STACK"); 106 107 108 take = true ; 107 109 is_accurate = true ;//PORT_READ(in_DECOD_RAS_HIT [port]); 108 110 use_ras = true ; … … 119 121 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK"); 120 122 123 take = true ; 121 124 is_accurate = false; // address unknow : in a register 122 125 use_ras = true; … … 132 135 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * BRANCH_CONDITION_READ_STACK"); 133 136 137 take = true ; 134 138 is_accurate = PORT_READ(in_DECOD_RAS_HIT [port]); 135 139 use_ras = true; … … 146 150 147 151 // * READ_REGISTER_WITHOUT_WRITE_STACK : Take but destination is unknow - don't continue 152 take = true ; 148 153 is_accurate = false; // address unknow : in a register 149 154 … … 158 163 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * BRANCH_CONDITION_FLAG"); 159 164 165 take = PORT_READ(in_DECOD_BRANCH_DIRECTION [decod_unit][i]); 160 166 is_accurate = true; // address dest is know 161 167 … … 168 174 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK"); 169 175 176 take = true; 170 177 is_accurate = true; 171 178 … … 173 180 } 174 181 } 182 183 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * take : %d",take); 175 184 176 185 if (use_btb) … … 181 190 PORT_WRITE(out_DECOD_BTB_ADDRESS_DEST [port],address_dest); 182 191 PORT_WRITE(out_DECOD_BTB_CONDITION [port],condition); 183 PORT_WRITE(out_DECOD_BTB_LAST_TAKE [port], direction);192 PORT_WRITE(out_DECOD_BTB_LAST_TAKE [port],take); 184 193 PORT_WRITE(out_DECOD_BTB_MISS_PREDICTION [port],1); 185 194 PORT_WRITE(out_DECOD_BTB_IS_ACCURATE [port],is_accurate); … … 198 207 PORT_WRITE(out_DECOD_UPT_BTB_ADDRESS_DEST[port],address_dest); 199 208 PORT_WRITE(out_DECOD_UPT_BTB_CONDITION [port],condition); 200 PORT_WRITE(out_DECOD_UPT_BTB_LAST_TAKE [port], direction);209 PORT_WRITE(out_DECOD_UPT_BTB_LAST_TAKE [port],take); 201 210 PORT_WRITE(out_DECOD_UPT_RAS_ADDRESS [port],PORT_READ(in_DECOD_RAS_ADDRESS_POP [port])); 202 211 PORT_WRITE(out_DECOD_UPT_IS_ACCURATE [port],is_accurate); 203 212 } 213 214 can_continue = false; // need update upt 204 215 } 205 // else 206 // { 207 // log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * hit"); 216 else 217 { 218 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * hit"); 219 220 if (branch_state == BRANCH_STATE_SPEC_NTAKE) 221 can_continue = PORT_READ(in_DECOD_UPT_CAN_CONTINUE [port]); 222 else 223 // BRANCH_STATE_NONE -> miss 224 // BRANCH_STATE_NSPEC_TAKE -> take 225 // BRANCH_STATE_SPEC_TAKE -> take 226 can_continue = false; 208 227 209 228 // miss_decod = false; 210 229 // // Hit speculation 211 //}230 } 212 231 213 214 232 // in all case 215 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * use_btb : %d",use_btb); 216 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * use_ras : %d",use_ras); 217 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * use_upt : %d",use_upt); 233 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * can_continue : %d",can_continue); 234 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * use_btb : %d",use_btb); 235 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * use_ras : %d",use_ras); 236 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * use_upt : %d",use_upt); 218 237 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * btb_ack [%d] : %d",port,PORT_READ(in_DECOD_BTB_ACK [port])); 219 238 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * ras_ack [%d] : %d",port,PORT_READ(in_DECOD_RAS_ACK [port])); … … 250 269 if (_param->_have_port_depth) 251 270 PORT_WRITE(out_DECOD_UPT_UPDATE_PREDICTION_ID [port],depth); 252 271 PORT_WRITE(out_DECOD_CAN_CONTINUE [decod_unit][i], can_continue); 272 253 273 port ++; // have find port 254 274 } -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/SelfTest/src/test.cpp
r101 r110 73 73 ALLOC2_SC_SIGNAL( in_DECOD_ADDRESS_SRC ," in_DECOD_ADDRESS_SRC ",Taddress_t ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); 74 74 ALLOC2_SC_SIGNAL( in_DECOD_ADDRESS_DEST ," in_DECOD_ADDRESS_DEST ",Taddress_t ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); 75 ALLOC2_SC_SIGNAL(out_DECOD_CAN_CONTINUE ," in_DECOD_CAN_CONTINUE ",Tcontrol_t ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); 75 76 76 77 ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_VAL ," in_BRANCH_COMPLETE_VAL ",Tcontrol_t ,_param->_nb_inst_branch_complete); … … 139 140 INSTANCE2_SC_SIGNAL(_Prediction_unit, in_DECOD_ADDRESS_SRC ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); 140 141 INSTANCE2_SC_SIGNAL(_Prediction_unit, in_DECOD_ADDRESS_DEST ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); 142 INSTANCE2_SC_SIGNAL(_Prediction_unit,out_DECOD_CAN_CONTINUE ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); 141 143 142 144 INSTANCE1_SC_SIGNAL(_Prediction_unit, in_BRANCH_COMPLETE_VAL ,_param->_nb_inst_branch_complete); … … 350 352 DELETE2_SC_SIGNAL( in_DECOD_ADDRESS_SRC ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); 351 353 DELETE2_SC_SIGNAL( in_DECOD_ADDRESS_DEST ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); 354 DELETE2_SC_SIGNAL(out_DECOD_CAN_CONTINUE ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); 352 355 353 356 DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_VAL ,_param->_nb_inst_branch_complete); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/src/test.cpp
r107 r110 99 99 //ALLOC1_SC_SIGNAL(out_DECOD_DEPTH ,"out_DECOD_DEPTH ",Tdepth_t ,_param->_nb_inst_decod); 100 100 ALLOC1_SC_SIGNAL( in_DECOD_IS_ACCURATE ," in_DECOD_IS_ACCURATE ",Tcontrol_t ,_param->_nb_inst_decod); 101 ALLOC1_SC_SIGNAL(out_DECOD_CAN_CONTINUE ,"out_DECOD_CAN_CONTINUE ",Tcontrol_t ,_param->_nb_inst_decod); 101 102 102 103 ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_VAL ," in_BRANCH_COMPLETE_VAL ",Tcontrol_t ,_param->_nb_inst_branch_complete); … … 190 191 //INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_DECOD_DEPTH ,_param->_nb_inst_decod); 191 192 INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_IS_ACCURATE ,_param->_nb_inst_decod); 193 INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_DECOD_CAN_CONTINUE ,_param->_nb_inst_decod); 194 192 195 INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_COMPLETE_VAL ,_param->_nb_inst_branch_complete); 193 196 INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_COMPLETE_ACK ,_param->_nb_inst_branch_complete); … … 2833 2836 delete [] in_DECOD_RAS_ADDRESS ; 2834 2837 delete [] in_DECOD_RAS_INDEX ; 2835 delete [] in_DECOD_MISS_IFETCH ;2836 2838 delete [] in_DECOD_MISS_DECOD ; 2837 2839 delete [] in_DECOD_UPDATE_PREDICTION_ID ; 2838 2840 //delete [] out_DECOD_DEPTH ; 2839 2841 delete [] in_DECOD_IS_ACCURATE ; 2840 2842 delete [] out_DECOD_CAN_CONTINUE ; 2843 2841 2844 // ~~~~~[ Interface : "branch_complete" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2842 2845 delete [] in_BRANCH_COMPLETE_VAL ; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Update_Prediction_Table.h
r109 r110 99 99 //public : SC_OUT(Tdepth_t ) ** out_DECOD_DEPTH ; //[nb_inst_decod] 100 100 public : SC_IN (Tcontrol_t ) ** in_DECOD_IS_ACCURATE ; //[nb_inst_decod] 101 public : SC_OUT(Tcontrol_t ) ** out_DECOD_CAN_CONTINUE ; //[nb_inst_decod] 101 102 102 103 // ~~~~~[ Interface : "branch_complete" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_allocation.cpp
r109 r110 92 92 // ALLOC1_SIGNAL_OUT(out_DECOD_DEPTH ,"depth" ,Tdepth_t ,_param->_size_depth); 93 93 ALLOC1_SIGNAL_IN ( in_DECOD_IS_ACCURATE ,"is_accurate" ,Tcontrol_t ,1); 94 ALLOC1_SIGNAL_OUT(out_DECOD_CAN_CONTINUE ,"can_continue" ,Tcontrol_t ,1); 94 95 } 95 96 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_deallocation.cpp
r109 r110 64 64 // delete [] out_DECOD_DEPTH ; 65 65 delete [] in_DECOD_IS_ACCURATE ; 66 delete [] out_DECOD_CAN_CONTINUE ; 66 67 67 68 // ~~~~~[ Interface : "branch_complete" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_genMealy_decod.cpp
r105 r110 36 36 event_state_t event_state = reg_EVENT_STATE [context]; 37 37 uint32_t ptr_write = reg_UPT_TOP [context]; 38 // can continue if next slot is empty 39 Tcontrol_t can_continue= ((reg_UPDATE_PREDICTION_TABLE [context][(reg_UPT_TOP [context]+1)%_param->_size_upt_queue[context]]._state == UPDATE_PREDICTION_STATE_EMPTY) and 40 (reg_EVENT_STATE [context] == EVENT_STATE_OK)); 38 41 39 42 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context ); … … 42 45 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * ptr_write : %d",ptr_write ); 43 46 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * upt_state : %s",toString(reg_UPDATE_PREDICTION_TABLE [context][ptr_write]._state).c_str()); 47 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * can_continue: %d",can_continue); 44 48 45 49 // ack : … … 58 62 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * ack : %d",internal_DECOD_ACK [i]); 59 63 60 PORT_WRITE(out_DECOD_ACK [i], internal_DECOD_ACK [i]); 64 PORT_WRITE(out_DECOD_ACK [i], internal_DECOD_ACK [i]); 65 PORT_WRITE(out_DECOD_CAN_CONTINUE [i], can_continue); 61 66 } 62 67 } -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/include/Prediction_unit.h
r101 r110 91 91 public : SC_IN (Taddress_t ) *** in_DECOD_ADDRESS_SRC ; //[nb_decod_unit][nb_inst_decod] 92 92 public : SC_IN (Taddress_t ) *** in_DECOD_ADDRESS_DEST ; //[nb_decod_unit][nb_inst_decod] 93 public : SC_OUT(Tcontrol_t ) *** out_DECOD_CAN_CONTINUE ; //[nb_decod_unit][nb_inst_decod] 93 94 94 95 // ~~~~~[ Interface : "branch_complete" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ … … 115 116 116 117 // ~~~~~[ Interface : "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 117 public : SC_IN (Tcontrol_t ) ** in_EVENT_VAL ; //[nb_context]118 public : SC_OUT(Tcontrol_t ) ** out_EVENT_ACK ; //[nb_context]119 public : SC_IN (Tevent_type_t ) ** in_EVENT_TYPE ; //[nb_context]120 public : SC_IN (Tdepth_t ) ** in_EVENT_DEPTH ; //[nb_context]118 public : SC_IN (Tcontrol_t ) ** in_EVENT_VAL ; //[nb_context] 119 public : SC_OUT(Tcontrol_t ) ** out_EVENT_ACK ; //[nb_context] 120 public : SC_IN (Tevent_type_t ) ** in_EVENT_TYPE ; //[nb_context] 121 public : SC_IN (Tdepth_t ) ** in_EVENT_DEPTH ; //[nb_context] 121 122 122 123 // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/src/Prediction_unit_allocation.cpp
r101 r110 90 90 _ALLOC2_SIGNAL_IN ( in_DECOD_ADDRESS_SRC ,"address_src" ,Taddress_t ,_param->_size_address ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); 91 91 _ALLOC2_SIGNAL_IN ( in_DECOD_ADDRESS_DEST ,"address_dest" ,Taddress_t ,_param->_size_address ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); 92 _ALLOC2_SIGNAL_OUT(out_DECOD_CAN_CONTINUE ,"can_continue" ,Tcontrol_t ,1 ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); 92 93 } 93 94 } … … 617 618 COMPONENT_MAP(_component,src , "in_DECOD_" +toString(i)+"_IS_ACCURATE" , 618 619 dest,"out_DECOD_UPT_"+toString(i)+"_IS_ACCURATE" ); 620 COMPONENT_MAP(_component,src ,"out_DECOD_" +toString(i)+"_CAN_CONTINUE" , 621 dest, "in_DECOD_UPT_"+toString(i)+"_CAN_CONTINUE" ); 619 622 620 623 //out_DECOD_UPT_RAS_INDEX - component_map return_address_stack … … 857 860 PORT_MAP(_component,src , "in_DECOD_"+toString(i)+"_"+toString(j)+"_ADDRESS_DEST" , 858 861 dest, "in_DECOD_"+toString(i)+"_"+toString(j)+"_ADDRESS_DEST" ); 862 PORT_MAP(_component,src ,"out_DECOD_"+toString(i)+"_"+toString(j)+"_CAN_CONTINUE" , 863 dest,"out_DECOD_"+toString(i)+"_"+toString(j)+"_CAN_CONTINUE" ); 859 864 } 860 865 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/src/Prediction_unit_deallocation.cpp
r101 r110 50 50 DELETE2_SIGNAL( in_DECOD_ADDRESS_SRC ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1],_param->_size_instruction_address ); 51 51 DELETE2_SIGNAL( in_DECOD_ADDRESS_DEST ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1],_param->_size_instruction_address ); 52 DELETE2_SIGNAL(out_DECOD_CAN_CONTINUE ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1],1); 52 53 53 54 DELETE1_SIGNAL( in_BRANCH_COMPLETE_VAL ,_param->_nb_inst_branch_complete,1); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Front_end_allocation.cpp
r108 r110 784 784 COMPONENT_MAP(_component,src ,"out_PREDICT_"+toString(j)+ "_ADDRESS_DEST" , 785 785 dest, "in_DECOD_" +toString(i)+"_"+toString(j)+"_ADDRESS_DEST" ); 786 //COMPONENT_MAP(_component,src , "in_PREDICT_"+toString(j)+ "_CAN_CONTINUE" ,787 //dest,"out_DECOD_" +toString(i)+"_"+toString(j)+"_CAN_CONTINUE" );786 COMPONENT_MAP(_component,src , "in_PREDICT_"+toString(j)+ "_CAN_CONTINUE" , 787 dest,"out_DECOD_" +toString(i)+"_"+toString(j)+"_CAN_CONTINUE" ); 788 788 789 789 } -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/src/main.cpp
r108 r110 7 7 8 8 #include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/include/test.h" 9 #include "Behavioural/include/Allocation.h" 9 10 10 11 #define NB_PARAMS 16 … … 99 100 uint32_t _nb_rename_unit_select = fromString<uint32_t >(argv[x++]); 100 101 102 uint32_t _nb_thread ; 103 uint32_t ** _translate_num_context_to_num_thread; //[nb_front_end][nb_context] 104 105 ALLOC2(_translate_num_context_to_num_thread,uint32_t,_nb_front_end,_nb_context[it1]); 106 107 _nb_thread = 0; 108 for (uint32_t i=0; i<_nb_front_end; i++) 109 for (uint32_t j=0; j<_nb_context [i]; j++) 110 _translate_num_context_to_num_thread [i][j] = _nb_thread ++; 111 101 112 int _return = EXIT_SUCCESS; 102 113 try … … 123 134 _load_balancing , 124 135 _nb_rename_unit_select , 136 _nb_thread , 137 _translate_num_context_to_num_thread, 125 138 true // is_toplevel 126 139 ); … … 149 162 } 150 163 164 DELETE2(_translate_num_context_to_num_thread,_nb_front_end,_nb_context[it1]); 165 151 166 delete [] _nb_context ; 152 167 delete [] _nb_inst_insert; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/src/test.cpp
r108 r110 9 9 #include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/include/test.h" 10 10 #include "Behavioural/include/Allocation.h" 11 #include "Behavioural/include/Simulation.h" 11 12 #include "Common/include/Max.h" 12 13 … … 27 28 morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,CYCLE_MAX); 28 29 #endif 30 31 simulation_init(0,0); 32 33 debug_idle_cycle = CYCLE_MAX; 29 34 30 35 Tusage_t _usage = USE_ALL; … … 744 749 745 750 delete _Commit_unit; 751 746 752 #ifdef STATISTICS 747 753 delete _parameters_statistics; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h
r109 r110 54 54 #ifdef STATISTICS 55 55 public : Stat * _stat; 56 public : counter_t ** _stat_nb_inst_insert; 57 public : counter_t * _stat_nb_inst_commit; 56 public : counter_t ** _stat_nb_inst_insert ;//[nb_rename_unit] 57 public : counter_t ** _stat_nb_inst_retire ;//[nb_rename_unit] 58 public : counter_t * _stat_nb_inst_commit ; 58 59 public : counter_t * _stat_nb_inst_commit_conflit_access; 59 public : counter_t ** _stat_nb_inst_retire_ok; 60 public : counter_t ** _stat_nb_inst_retire_ko; 61 public : counter_t ** _stat_bank_nb_inst;// [nb_bank] 60 public : counter_t ** _stat_nb_inst_retire_ok ;//[nb_thread] 61 public : counter_t ** _stat_nb_inst_retire_ko ;//[nb_thread] 62 public : counter_t ** _stat_nb_inst_type ;//[nb_type] 63 public : counter_t ** _stat_bank_nb_inst ;//[nb_bank] 62 64 #endif 63 65 … … 254 256 private : entry_t * ** internal_BANK_COMMIT_ENTRY ;//[nb_bank][nb_bank_access_commit] 255 257 258 private : uint32_t internal_BANK_RETIRE_HEAD ; 256 259 private : Tcontrol_t * internal_BANK_RETIRE_VAL ;//[nb_bank] 257 260 private : uint32_t * internal_BANK_RETIRE_NUM_RENAME_UNIT ;//[nb_bank] -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Parameters.h
r108 r110 24 24 { 25 25 //-----[ fields ]------------------------------------------------------------ 26 public : uint32_t _nb_front_end ; 27 public : uint32_t * _nb_context ;//[nb_front_end] 28 public : uint32_t _nb_rename_unit ; 29 public : uint32_t _size_queue ; 30 public : uint32_t _nb_bank ; 31 public : uint32_t * _nb_inst_insert ;//[nb_rename_unit] 32 public : uint32_t * _nb_inst_retire ;//[nb_rename_unit] 33 public : uint32_t _nb_inst_commit ; 34 public : uint32_t _nb_inst_reexecute ; 35 public : uint32_t _nb_inst_branch_complete ; 36 public : uint32_t ** _nb_branch_speculated ;//[nb_front_end][nb_context] 37 //public : uint32_t _size_general_data ; 38 //public : uint32_t _size_store_queue_ptr ; 39 //public : uint32_t _size_load_queue_ptr ; 40 //public : uint32_t _size_general_register ; 41 //public : uint32_t _size_special_register ; 42 public : Tpriority_t _priority ; 43 public : Tload_balancing_t _load_balancing ; 44 public : uint32_t _nb_rename_unit_select ; 45 public : const uint32_t _nb_bank_access_commit ; 46 public : const retire_ooo_t _retire_ooo ; 26 public : uint32_t _nb_front_end ; 27 public : uint32_t * _nb_context ;//[nb_front_end] 28 public : uint32_t _nb_rename_unit ; 29 public : uint32_t _size_queue ; 30 public : uint32_t _nb_bank ; 31 public : uint32_t * _nb_inst_insert ;//[nb_rename_unit] 32 public : uint32_t * _nb_inst_retire ;//[nb_rename_unit] 33 public : uint32_t _nb_inst_commit ; 34 public : uint32_t _nb_inst_reexecute ; 35 public : uint32_t _nb_inst_branch_complete ; 36 public : uint32_t ** _nb_branch_speculated ;//[nb_front_end][nb_context] 37 //public : uint32_t _size_general_data ; 38 //public : uint32_t _size_store_queue_ptr ; 39 //public : uint32_t _size_load_queue_ptr ; 40 //public : uint32_t _size_general_register ; 41 //public : uint32_t _size_special_register ; 42 public : Tpriority_t _priority ; 43 public : Tload_balancing_t _load_balancing ; 44 public : uint32_t _nb_rename_unit_select ; 45 public : uint32_t _nb_thread ; 46 public : uint32_t ** _translate_num_context_to_num_thread; //[nb_front_end][nb_context] 47 public : const uint32_t _nb_bank_access_commit ; 48 public : const retire_ooo_t _retire_ooo ; 47 49 48 50 public : uint32_t _max_nb_context ; … … 69 71 //public : bool ** _have_port_depth ;//[nb_front_end][nb_context] 70 72 73 public : bool * _have_thread ;//[nb_thread] 74 71 75 //-----[ methods ]----------------------------------------------------------- 72 public : Parameters (uint32_t nb_front_end , 73 uint32_t * nb_context , 74 uint32_t nb_rename_unit , 75 uint32_t size_queue , 76 uint32_t nb_bank , 77 uint32_t * nb_inst_insert , 78 uint32_t * nb_inst_retire , 79 uint32_t nb_inst_commit , 80 uint32_t nb_inst_reexecute , 81 uint32_t nb_inst_branch_complete , 82 uint32_t ** nb_branch_speculated , 83 uint32_t size_nb_inst_decod , 84 uint32_t size_general_data , 85 uint32_t size_store_queue_ptr , 86 uint32_t size_load_queue_ptr , 87 uint32_t size_general_register , 88 uint32_t size_special_register , 89 Tpriority_t priority , 90 Tload_balancing_t load_balancing , 91 uint32_t nb_rename_unit_select , 76 public : Parameters (uint32_t nb_front_end , 77 uint32_t * nb_context ,//[nb_front_end] 78 uint32_t nb_rename_unit , 79 uint32_t size_queue , 80 uint32_t nb_bank , 81 uint32_t * nb_inst_insert ,//[nb_rename_unit] 82 uint32_t * nb_inst_retire ,//[nb_rename_unit] 83 uint32_t nb_inst_commit , 84 uint32_t nb_inst_reexecute , 85 uint32_t nb_inst_branch_complete , 86 uint32_t ** nb_branch_speculated ,//[nb_front_end][nb_context] 87 uint32_t size_nb_inst_decod , 88 uint32_t size_general_data , 89 uint32_t size_store_queue_ptr , 90 uint32_t size_load_queue_ptr , 91 uint32_t size_general_register , 92 uint32_t size_special_register , 93 Tpriority_t priority , 94 Tload_balancing_t load_balancing , 95 uint32_t nb_rename_unit_select , 96 uint32_t nb_thread , 97 uint32_t ** translate_num_context_to_num_thread, //[nb_front_end][nb_context] 92 98 bool is_toplevel=false 93 99 ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit.cpp
r104 r110 7 7 8 8 #include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h" 9 #include "Behavioural/include/Simulation.h" 9 10 10 11 namespace morpheo { … … 260 261 261 262 #endif 263 264 // Init stop condition 265 while (_simulation_nb_instruction_commited.size() < _param->_nb_thread) 266 _simulation_nb_instruction_commited.push_back(0); 262 267 } 263 268 log_end(Commit_unit,FUNCTION); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_retire.cpp
r105 r110 57 57 } 58 58 // Scan Top of each bank 59 internal_BANK_RETIRE_HEAD = reg_NUM_BANK_HEAD; 59 60 for (uint32_t i=0; i<_param->_nb_bank; i++) 60 61 { 61 uint32_t num_bank = ( reg_NUM_BANK_HEAD+i)%_param->_nb_bank;62 uint32_t num_bank = (internal_BANK_RETIRE_HEAD+i)%_param->_nb_bank; 62 63 63 64 if (not _rob[num_bank].empty()) … … 167 168 PORT_WRITE(out_RETIRE_NUM_REG_RE_PHY_OLD [x][y], entry->num_reg_re_phy_old ); 168 169 PORT_WRITE(out_RETIRE_NUM_REG_RE_PHY_NEW [x][y], entry->num_reg_re_phy_new ); 170 171 // Event -> rob must be manage this event 172 if ((state == ROB_END_BRANCH_MISS) or 173 (state == ROB_END_LOAD_MISS)) 174 can_retire [x] = false; 169 175 } 170 176 } -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_statistics_allocation.cpp
r109 r110 28 28 29 29 _stat_nb_inst_insert = new counter_t * [_param->_nb_rename_unit]; 30 _stat_nb_inst_retire_ok = new counter_t * [_param->_nb_rename_unit]; 31 _stat_nb_inst_retire_ko = new counter_t * [_param->_nb_rename_unit]; 30 _stat_nb_inst_retire = new counter_t * [_param->_nb_rename_unit]; 31 _stat_nb_inst_retire_ok = new counter_t * [_param->_nb_thread]; 32 _stat_nb_inst_retire_ko = new counter_t * [_param->_nb_thread]; 33 _stat_nb_inst_type = new counter_t * [_param->_nb_type]; 32 34 _stat_bank_nb_inst = new counter_t * [_param->_nb_bank]; 33 35 34 36 { 35 37 std::string sum_nb_inst_insert = "0"; 36 std::string sum_nb_inst_retire_ok = "0"; 37 std::string sum_nb_inst_retire_ko = "0"; 38 std::string sum_nb_inst_retire = "0"; 38 39 39 40 for (uint32_t i=0; i<_param->_nb_rename_unit; i++) 40 41 { 41 42 _stat_nb_inst_insert [i] = _stat->create_variable("nb_inst_insert_" +toString(i)); 42 _stat_nb_inst_retire_ok [i] = _stat->create_variable("nb_inst_retire_ok_"+toString(i)); 43 _stat_nb_inst_retire_ko [i] = _stat->create_variable("nb_inst_retire_ko_"+toString(i)); 43 _stat_nb_inst_retire [i] = _stat->create_variable("nb_inst_retire_" +toString(i)); 44 44 45 45 _stat->create_expr_average_by_cycle("average_use_interface_insert_"+toString(i), "nb_inst_insert_"+toString(i), "", toString(_("Average instruction by cycle on insert interface (rename_unit %d)"),i)); 46 _stat->create_expr_average_by_cycle("average_use_interface_retire_"+toString(i), " + nb_inst_retire_ok_"+toString(i)+" nb_inst_retire_ko_"+toString(i), "", toString(_("Average instruction by cycle on retire interface (rename_unit %d)"),i));46 _stat->create_expr_average_by_cycle("average_use_interface_retire_"+toString(i), "nb_inst_retire_"+toString(i), "", toString(_("Average instruction by cycle on retire interface (rename_unit %d)"),i)); 47 47 _stat->create_expr_percent ("percent_use_interface_insert_"+toString(i) , "average_use_interface_insert_"+toString(i), toString(_param->_nb_inst_insert [i]), toString(_("Percent usage of insert interface (rename_unit %d)"),i)); 48 48 _stat->create_expr_percent ("percent_use_interface_retire_"+toString(i) , "average_use_interface_retire_"+toString(i), toString(_param->_nb_inst_retire [i]), toString(_("Percent usage of retire interface (rename_unit %d)"),i)); 49 49 50 50 sum_nb_inst_insert = "+ nb_inst_insert_"+ toString(i) + " " +sum_nb_inst_insert; 51 sum_nb_inst_retire_ok = "+ nb_inst_retire_ok_"+toString(i) + " " +sum_nb_inst_retire_ok; 52 sum_nb_inst_retire_ko = "+ nb_inst_retire_ko_"+toString(i) + " " +sum_nb_inst_retire_ko; 53 } 51 sum_nb_inst_retire = "+ nb_inst_retire_"+ toString(i) + " " +sum_nb_inst_retire; 52 } 54 53 55 54 _stat->create_expr_average_by_cycle("average_inst_insert" , sum_nb_inst_insert , "", _("Average instruction insert by cycle")); 56 _stat->create_expr_average_by_cycle("average_inst_retire_ok", sum_nb_inst_retire_ok, "", _("Average instruction retire ok by cycle (IPC)")); 57 _stat->create_expr_average_by_cycle("average_inst_retire_ko", sum_nb_inst_retire_ko, "", _("Average instruction retire ko (event, miss) by cycle")); 58 _stat->create_expr_average_by_cycle("average_inst_retire" , "+ "+sum_nb_inst_retire_ok+" "+sum_nb_inst_retire_ko, "", _("Average instruction retire by cycle")); 55 _stat->create_expr_average_by_cycle("average_inst_retire" , sum_nb_inst_retire , "", _("Average instruction retire by cycle")); 56 } 59 57 60 _stat->create_expr ("IPC_ok" , "average_inst_retire_ok", TYPE_COUNTER, "inst/cycle", "Instruction Per Cycle (Instruction Ok)"); 58 { 59 std::string sum_nb_inst_retire_ok = "0"; 60 std::string sum_nb_inst_retire_ko = "0"; 61 62 for (uint32_t i=0; i<_param->_nb_thread; i++) 63 if (_param->_have_thread [i]) 64 { 65 _stat_nb_inst_retire_ok [i] = _stat->create_variable("nb_inst_retire_ok_"+toString(i)); 66 _stat_nb_inst_retire_ko [i] = _stat->create_variable("nb_inst_retire_ko_"+toString(i)); 67 68 sum_nb_inst_retire_ok = "+ nb_inst_retire_ok_"+toString(i) + " " +sum_nb_inst_retire_ok; 69 sum_nb_inst_retire_ko = "+ nb_inst_retire_ko_"+toString(i) + " " +sum_nb_inst_retire_ko; 70 71 _stat->create_expr_average_by_cycle("average_inst_retire_ok_"+toString(i), sum_nb_inst_retire_ok, "", toString(_("Average instruction retire ok by cycle (IPC) (thread %d)"),i)); 72 _stat->create_expr_average_by_cycle("average_inst_retire_ko_"+toString(i), sum_nb_inst_retire_ko, "", toString(_("Average instruction retire ko (event, miss) by cycle (thread %d)"),i)); 73 74 _stat->create_expr ("IPC_ok_"+toString(i) , "average_inst_retire_ok_"+toString(i), TYPE_COUNTER, "inst/cycle", toString("Instruction Per Cycle (Instruction Ok) (thread %d)",i)); 75 _stat->create_expr ("CPI_ok_"+toString(i) , "/ 1 IPC_ok_"+toString(i) , TYPE_COUNTER, "cycle/inst", toString("Cycle Per Instruction (Instruction Ok) (thread %d)",i)); 76 77 _stat->create_expr ("IPC_ko_"+toString(i) , "average_inst_retire_ko_"+toString(i), TYPE_COUNTER, "inst/cycle", toString("Instruction Per Cycle (Instruction Ko) (thread %d)",i)); 78 _stat->create_expr ("CPI_ko_"+toString(i) , "/ 1 IPC_ko_"+toString(i) , TYPE_COUNTER, "cycle/inst", toString("Cycle Per Instruction (Instruction Ko) (thread %d)",i)); 79 80 _stat->create_expr ("IPC_all_"+toString(i), "+ IPC_ok_"+toString(i)+" IPC_ko_"+toString(i), TYPE_COUNTER, "inst/cycle", toString("Instruction Per Cycle (Instruction Ok and Ko) (thread %d)",i)); 81 _stat->create_expr ("CPI_all_"+toString(i), "/ 1 IPC_all_"+toString(i) , TYPE_COUNTER, "cycle/inst", toString("Cycle Per Instruction (Instruction Ok and Ko) (thread %d)",i)); 82 } 83 84 _stat->create_expr ("IPC_ok" , "/ "+sum_nb_inst_retire_ok+" cycle", TYPE_COUNTER, "inst/cycle", "Instruction Per Cycle (Instruction Ok)"); 61 85 _stat->create_expr ("CPI_ok" , "/ 1 IPC_ok" , TYPE_COUNTER, "cycle/inst", "Cycle Per Instruction (Instruction Ok)"); 62 86 63 _stat->create_expr ("IPC_ko" , " average_inst_retire_ko", TYPE_COUNTER, "inst/cycle", "Instruction Per Cycle (Instruction Ko)");87 _stat->create_expr ("IPC_ko" , "/ "+sum_nb_inst_retire_ko+" cycle", TYPE_COUNTER, "inst/cycle", "Instruction Per Cycle (Instruction Ko)"); 64 88 _stat->create_expr ("CPI_ko" , "/ 1 IPC_ko" , TYPE_COUNTER, "cycle/inst", "Cycle Per Instruction (Instruction Ko)"); 65 89 66 _stat->create_expr ("IPC_all", " average_inst_retire", TYPE_COUNTER, "inst/cycle", "Instruction Per Cycle (Instruction Ok and Ko)");90 _stat->create_expr ("IPC_all", "+ IPC_ok IPC_ko" , TYPE_COUNTER, "inst/cycle", "Instruction Per Cycle (Instruction Ok and Ko)"); 67 91 _stat->create_expr ("CPI_all", "/ 1 IPC_all" , TYPE_COUNTER, "cycle/inst", "Cycle Per Instruction (Instruction Ok and Ko)"); 68 92 } 93 94 { 95 std::string sum_nb_inst_type = "0"; 96 97 for (uint32_t i=0; i<_param->_nb_type; i++) 98 if (is_type_valid(i)) 99 { 100 _stat_nb_inst_type [i] = _stat->create_variable("nb_inst_type_"+toString(i)); 101 102 sum_nb_inst_type = "+ nb_inst_type_"+toString(i) + " " +sum_nb_inst_type; 103 } 104 105 for (uint32_t i=0; i<_param->_nb_type; i++) 106 if (is_type_valid(i)) 107 { 108 std::string name = toString(static_cast<type_t>(i)).c_str(); 109 // _stat->create_expr_average_by_cycle("average_inst_type_"+toString(name), "nb_inst_type_"+toString(i), "", toString(_("Average instruction retire ok by cycle (type %s)"),name.c_str())); 110 _stat->create_expr_percent ("percent_inst_type_"+toString(name), "nb_inst_type_"+toString(i), sum_nb_inst_type, toString(_("Percent instruction retire ok by cycle (type %s)"),name.c_str())); 111 } 112 } 113 69 114 70 115 _stat_nb_inst_commit = _stat->create_variable("nb_inst_commit"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_statistics_deallocation.cpp
r98 r110 28 28 29 29 delete [] _stat_nb_inst_insert; 30 delete [] _stat_nb_inst_retire; 30 31 delete [] _stat_nb_inst_retire_ok; 31 32 delete [] _stat_nb_inst_retire_ko; 33 delete [] _stat_nb_inst_type; 32 34 delete [] _stat_bank_nb_inst; 33 35 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp
r109 r110 8 8 9 9 #include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h" 10 #include "Behavioural/include/Simulation.h" 10 11 11 12 namespace morpheo { … … 114 115 { 115 116 log_printf(TRACE,Commit_unit,FUNCTION," * INSERT [%d][%d]",x,y); 116 117 #ifdef STATISTICS118 if (usage_is_set(_usage,USE_STATISTICS))119 (*_stat_nb_inst_insert [x]) ++;120 #endif121 117 122 118 // get information … … 219 215 } 220 216 } 217 218 #ifdef STATISTICS 219 if (usage_is_set(_usage,USE_STATISTICS)) 220 (*_stat_nb_inst_insert [x]) ++; 221 #endif 221 222 222 223 // Push in rob … … 346 347 // =================================================================== 347 348 for (uint32_t i=0; i<_param->_nb_bank; i++) 348 if (internal_BANK_RETIRE_VAL [i]) 349 { 350 uint32_t x = internal_BANK_RETIRE_NUM_RENAME_UNIT [i]; 351 uint32_t y = internal_BANK_RETIRE_NUM_INST [i]; 352 353 log_printf(TRACE,Commit_unit,FUNCTION," * RETIRE [%d][%d]",x,y); 354 349 { 350 uint32_t num_bank = (internal_BANK_RETIRE_HEAD+i)%_param->_nb_bank; 351 352 if (internal_BANK_RETIRE_VAL [num_bank]) 353 { 354 uint32_t x = internal_BANK_RETIRE_NUM_RENAME_UNIT [num_bank]; 355 uint32_t y = internal_BANK_RETIRE_NUM_INST [num_bank]; 356 357 log_printf(TRACE,Commit_unit,FUNCTION," * RETIRE [%d][%d]",x,y); 358 355 359 #ifdef DEBUG_TEST 356 if (not PORT_READ(in_RETIRE_ACK [x][y])) 357 throw ERRORMORPHEO(FUNCTION,_("Retire : retire_ack must be set.\n")); 358 #endif 359 360 entry_t * entry = _rob [i].front(); 361 rob_state_t state = entry->state; 362 363 #ifdef STATISTICS 364 if (usage_is_set(_usage,USE_STATISTICS)) 365 { 366 if (state == ROB_END_OK) 367 (*_stat_nb_inst_retire_ok [x]) ++; 368 else 369 (*_stat_nb_inst_retire_ko [x]) ++; 370 } 371 #endif 372 373 Tcontext_t front_end_id = entry->front_end_id; 374 Tcontext_t context_id = entry->context_id ; 375 Ttype_t type = entry->type ; 376 377 if ((state == ROB_END_OK ) or 378 // (state == ROB_END_KO ) or 379 (state == ROB_END_BRANCH_MISS) or 380 (state == ROB_END_LOAD_MISS )// or 381 // (state == ROB_END_MISS ) or 382 // (state == ROB_END_EXCEPTION ) 383 ) 384 { 385 // reg_PC_PREVIOUS [front_end_id][context_id] = reg_PC_CURRENT [front_end_id][context_id]; 386 reg_PC_CURRENT [front_end_id][context_id] = reg_PC_NEXT [front_end_id][context_id]; 387 reg_PC_CURRENT_IS_DS [front_end_id][context_id] = entry->type == TYPE_BRANCH; 388 reg_PC_CURRENT_IS_DS_TAKE [front_end_id][context_id] = entry->no_sequence; 389 reg_PC_NEXT [front_end_id][context_id] = (entry->no_sequence)?(entry->address_next):(reg_PC_CURRENT [front_end_id][context_id]+1); 360 if (not PORT_READ(in_RETIRE_ACK [x][y])) 361 throw ERRORMORPHEO(FUNCTION,_("Retire : retire_ack must be set.\n")); 362 #endif 363 364 entry_t * entry = _rob [num_bank].front(); 365 rob_state_t state = entry->state; 366 367 Tcontext_t front_end_id = entry->front_end_id; 368 Tcontext_t context_id = entry->context_id ; 369 uint32_t num_thread = _param->_translate_num_context_to_num_thread [front_end_id][context_id]; 370 Ttype_t type = entry->type ; 371 bool retire_ok = false; 372 373 log_printf(TRACE,Commit_unit,FUNCTION," * front_end_id : %d",front_end_id ); 374 log_printf(TRACE,Commit_unit,FUNCTION," * context_id : %d",context_id ); 375 log_printf(TRACE,Commit_unit,FUNCTION," * num_thread : %d",num_thread ); 376 log_printf(TRACE,Commit_unit,FUNCTION," * type : %s",toString(type).c_str()); 377 log_printf(TRACE,Commit_unit,FUNCTION," * state : %s",toString(state).c_str()); 378 379 if ((state == ROB_END_OK ) or 380 // (state == ROB_END_KO ) or 381 (state == ROB_END_BRANCH_MISS) or 382 (state == ROB_END_LOAD_MISS )// or 383 // (state == ROB_END_MISS ) or 384 // (state == ROB_END_EXCEPTION ) 385 ) 386 { 387 log_printf(TRACE,Commit_unit,FUNCTION," * retire_ok"); 388 389 retire_ok = true; 390 391 // reg_PC_PREVIOUS [front_end_id][context_id] = reg_PC_CURRENT [front_end_id][context_id]; 392 reg_PC_CURRENT [front_end_id][context_id] = reg_PC_NEXT [front_end_id][context_id]; 393 reg_PC_CURRENT_IS_DS [front_end_id][context_id] = entry->type == TYPE_BRANCH; 394 reg_PC_CURRENT_IS_DS_TAKE [front_end_id][context_id] = entry->no_sequence; 395 reg_PC_NEXT [front_end_id][context_id] = (entry->no_sequence)?(entry->address_next):(reg_PC_CURRENT [front_end_id][context_id]+1); 390 396 391 397 // if (entry->address_next != reg_PC_NEXT [front_end_id][context_id]) 392 398 // throw ERRORMORPHEO(FUNCTION,toString(_("Retire : Instruction's address_next (%.8x) is different of commit_unit's address_next (%.8x)"),entry->address_next,reg_PC_NEXT [front_end_id][context_id])); 393 } 394 395 if ((state == ROB_END_BRANCH_MISS) or 396 (state == ROB_END_LOAD_MISS)) 397 { 398 reg_EVENT_STATE [front_end_id][context_id] = EVENT_STATE_EVENT; 399 reg_EVENT_FLUSH [front_end_id][context_id] = true; 400 } 401 402 // Update nb_inst 403 reg_NB_INST_COMMIT_ALL [front_end_id][context_id] --; 404 if (type == TYPE_MEMORY) 405 reg_NB_INST_COMMIT_MEM [front_end_id][context_id] --; 406 407 reg_NUM_BANK_HEAD = (reg_NUM_BANK_HEAD+1)%_param->_nb_bank; 408 409 _rob [i].pop_front(); 410 delete entry; 411 412 // Transaction on retire interface : reset watch dog timer. 413 _nb_cycle_idle [front_end_id][context_id] = 0; 414 } 399 } 400 401 if ((state == ROB_END_BRANCH_MISS) or 402 (state == ROB_END_LOAD_MISS)) 403 { 404 reg_EVENT_STATE [front_end_id][context_id] = EVENT_STATE_EVENT; 405 reg_EVENT_FLUSH [front_end_id][context_id] = true; 406 } 407 408 // Update nb_inst 409 reg_NB_INST_COMMIT_ALL [front_end_id][context_id] --; 410 if (type == TYPE_MEMORY) 411 reg_NB_INST_COMMIT_MEM [front_end_id][context_id] --; 412 413 reg_NUM_BANK_HEAD = (reg_NUM_BANK_HEAD+1)%_param->_nb_bank; 414 415 _rob [num_bank].pop_front(); 416 delete entry; 417 418 // Transaction on retire interface : reset watch dog timer. 419 _nb_cycle_idle [front_end_id][context_id] = 0; 420 421 // Increase stop condition 422 if (retire_ok) 423 _simulation_nb_instruction_commited [num_thread] ++; 424 425 #ifdef STATISTICS 426 if (usage_is_set(_usage,USE_STATISTICS)) 427 { 428 (*_stat_nb_inst_retire [x]) ++; 429 430 if (retire_ok) 431 { 432 (*_stat_nb_inst_retire_ok [num_thread]) ++; 433 (*_stat_nb_inst_type [type] ) ++; 434 } 435 else 436 (*_stat_nb_inst_retire_ko [num_thread]) ++; 437 } 438 #endif 439 } 440 } 415 441 416 442 // =================================================================== … … 652 678 for (uint32_t j=0; j<_param->_nb_context [i]; j++) 653 679 { 654 log_printf(TRACE,Commit_unit,FUNCTION," * [%d][%d] ",i,j);680 log_printf(TRACE,Commit_unit,FUNCTION," * [%d][%d] - %d",i,j,_param->_translate_num_context_to_num_thread [i][j]); 655 681 log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_STATE : %s",toString(reg_EVENT_STATE [i][j]).c_str()); 656 682 log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_FLUSH : %d",reg_EVENT_FLUSH [i][j]); … … 667 693 log_printf(TRACE,Commit_unit,FUNCTION," * Bank [%d] size : %d, ptr : %d",num_bank,(int)_rob[num_bank].size(), reg_BANK_PTR [i]); 668 694 669 uint32_t x=0;670 695 for (std::list<entry_t*>::iterator it=_rob[num_bank].begin(); 671 696 it!=_rob[num_bank].end(); 672 697 it++) 673 698 { 674 log_printf(TRACE,Commit_unit,FUNCTION," [%.4d] %.4d %.4d %.4d %.4d, %.3d %.3d, %.1d, %.1d %.4d, %.1d %.4d, %s - %d", 675 x, 699 log_printf(TRACE,Commit_unit,FUNCTION," [%.4d][%.4d] (%.4d) %.4d %.4d %.4d %.4d, %.3d %.3d, %.1d, %.1d %.4d, %.1d %.4d, %s", 700 num_bank , 701 (*it)->ptr , 702 ((num_bank << _param->_shift_num_bank) | (*it)->ptr), 676 703 (*it)->front_end_id , 677 704 (*it)->context_id , … … 685 712 (*it)->use_load_queue , 686 713 (*it)->load_queue_ptr_write , 687 toString((*it)->state).c_str() , 688 (*it)->ptr ); 689 log_printf(TRACE,Commit_unit,FUNCTION," %.1d %.2d %.6d, %.1d %.2d %.6d, %.1d %.1d %.6d, %.1d %.2d %.6d %.6d, %.1d %.1d %.6d %.6d ", 714 toString((*it)->state).c_str() ); 715 log_printf(TRACE,Commit_unit,FUNCTION," %.1d %.2d %.6d, %.1d %.2d %.6d, %.1d %.1d %.6d, %.1d %.2d %.6d %.6d, %.1d %.1d %.6d %.6d ", 690 716 (*it)->read_ra , 691 717 (*it)->num_reg_ra_log , … … 706 732 (*it)->num_reg_re_phy_new ); 707 733 708 log_printf(TRACE,Commit_unit,FUNCTION," %.2d %.2d %.1d %.1d %.1d - %.8x (%.8x) %.8x (%.8x)",734 log_printf(TRACE,Commit_unit,FUNCTION," %.2d %.2d %.1d %.1d %.1d - %.8x (%.8x) %.8x (%.8x)", 709 735 (*it)->exception_use , 710 736 (*it)->exception , … … 717 743 (*it)->address_next<<2 718 744 ); 719 720 x++;721 745 } 722 746 } … … 772 796 for (uint32_t i=0; i<_param->_nb_front_end; i++) 773 797 for (uint32_t j=0; j<_param->_nb_context [i]; j++) 774 if (_nb_cycle_idle [i][j] >= debug_ cycle_idle)775 throw ERRORMORPHEO(FUNCTION,toString(_(" Context [%d][%d] is idle since %.0f cycles.\n"),i,j,_nb_cycle_idle [i][j]));798 if (_nb_cycle_idle [i][j] >= debug_idle_cycle) 799 throw ERRORMORPHEO(FUNCTION,toString(_("Thread [%d] is idle since %.0f cycles.\n"),_param->_translate_num_context_to_num_thread[i][j],_nb_cycle_idle [i][j])); 776 800 777 801 log_end(Commit_unit,FUNCTION); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Parameters.cpp
r108 r110 7 7 8 8 #include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Parameters.h" 9 #include "Behavioural/include/Allocation.h" 9 10 #include "Common/include/Max.h" 10 11 #include "Common/include/BitManipulation.h" … … 20 21 #undef FUNCTION 21 22 #define FUNCTION "Commit_unit::Parameters" 22 Parameters::Parameters (uint32_t nb_front_end , 23 uint32_t * nb_context , 24 uint32_t nb_rename_unit , 25 uint32_t size_queue , 26 uint32_t nb_bank , 27 uint32_t * nb_inst_insert , 28 uint32_t * nb_inst_retire , 29 uint32_t nb_inst_commit , 30 uint32_t nb_inst_reexecute , 31 uint32_t nb_inst_branch_complete , 32 uint32_t ** nb_branch_speculated , 33 uint32_t size_nb_inst_decod , 34 uint32_t size_general_data , 35 uint32_t size_store_queue_ptr , 36 uint32_t size_load_queue_ptr , 37 uint32_t size_general_register , 38 uint32_t size_special_register , 39 Tpriority_t priority , 40 Tload_balancing_t load_balancing , 41 uint32_t nb_rename_unit_select , 23 Parameters::Parameters (uint32_t nb_front_end , 24 uint32_t * nb_context , 25 uint32_t nb_rename_unit , 26 uint32_t size_queue , 27 uint32_t nb_bank , 28 uint32_t * nb_inst_insert , 29 uint32_t * nb_inst_retire , 30 uint32_t nb_inst_commit , 31 uint32_t nb_inst_reexecute , 32 uint32_t nb_inst_branch_complete , 33 uint32_t ** nb_branch_speculated , 34 uint32_t size_nb_inst_decod , 35 uint32_t size_general_data , 36 uint32_t size_store_queue_ptr , 37 uint32_t size_load_queue_ptr , 38 uint32_t size_general_register , 39 uint32_t size_special_register , 40 Tpriority_t priority , 41 Tload_balancing_t load_balancing , 42 uint32_t nb_rename_unit_select , 43 uint32_t nb_thread , 44 uint32_t ** translate_num_context_to_num_thread, 42 45 bool is_toplevel): 43 46 _nb_bank_access_commit (1 ), … … 46 49 log_begin(Commit_unit,FUNCTION); 47 50 48 _nb_front_end = nb_front_end ; 49 _nb_context = nb_context ; 50 _nb_rename_unit = nb_rename_unit ; 51 _size_queue = size_queue ; 52 _nb_bank = nb_bank ; 53 _nb_inst_insert = nb_inst_insert ; 54 _nb_inst_retire = nb_inst_retire ; 55 _nb_inst_commit = nb_inst_commit ; 56 _nb_inst_reexecute = nb_inst_reexecute ; 57 _nb_inst_branch_complete = nb_inst_branch_complete; 58 _nb_branch_speculated = nb_branch_speculated ; 59 _priority = priority ; 60 _load_balancing = load_balancing ; 61 _nb_rename_unit_select = nb_rename_unit_select ; 51 _nb_front_end = nb_front_end ; 52 _nb_context = nb_context ; 53 _nb_rename_unit = nb_rename_unit ; 54 _size_queue = size_queue ; 55 _nb_bank = nb_bank ; 56 _nb_inst_insert = nb_inst_insert ; 57 _nb_inst_retire = nb_inst_retire ; 58 _nb_inst_commit = nb_inst_commit ; 59 _nb_inst_reexecute = nb_inst_reexecute ; 60 _nb_inst_branch_complete = nb_inst_branch_complete ; 61 _nb_branch_speculated = nb_branch_speculated ; 62 _priority = priority ; 63 _load_balancing = load_balancing ; 64 _nb_rename_unit_select = nb_rename_unit_select ; 65 _nb_thread = nb_thread ; 66 _translate_num_context_to_num_thread = translate_num_context_to_num_thread; 62 67 63 68 _size_rename_unit_id = log2(_nb_rename_unit); … … 71 76 _have_port_rename_unit_id = _size_rename_unit_id > 0; 72 77 73 _array_size_depth = new uint32_t * [_nb_front_end];78 ALLOC2(_array_size_depth,uint32_t,_nb_front_end,_nb_context [it1]); 74 79 for (uint32_t i=0; i<_nb_front_end; i++) 75 { 76 _array_size_depth [i] = new uint32_t [_nb_context [i]]; 77 for (uint32_t j=0; j<_nb_context [i]; j++) 78 _array_size_depth [i][j] = (_nb_branch_speculated [i][j] == 0)?0:log2(_nb_branch_speculated [i][j]); 79 } 80 for (uint32_t j=0; j<_nb_context [i]; j++) 81 _array_size_depth [i][j] = (_nb_branch_speculated [i][j] == 0)?0:log2(_nb_branch_speculated [i][j]); 80 82 81 83 test(); 84 85 ALLOC1(_have_thread,bool,_nb_thread); 86 for (uint32_t i=0; i<_nb_thread; i++) 87 _have_thread[i] = false; 88 for (uint32_t i=0; i<_nb_front_end; i++) 89 for (uint32_t j=0; j<_nb_context [i]; j++) 90 _have_thread[_translate_num_context_to_num_thread [i][j]] = true; 82 91 83 92 if (is_toplevel) … … 123 132 log_begin(Commit_unit,FUNCTION); 124 133 125 for (uint32_t i=0; i<_nb_front_end; i++) 126 { 127 delete [] _array_size_depth [i]; 128 } 129 delete [] _array_size_depth; 134 DELETE1(_have_thread ,_nb_thread); 135 DELETE2(_array_size_depth,_nb_front_end,_nb_context [it1]); 130 136 131 137 log_end(Commit_unit,FUNCTION); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Parameters_msg_error.cpp
r88 r110 35 35 36 36 if (_nb_rename_unit_select > _nb_rename_unit) 37 test.error( "nb_rename_unit must be >= nb_rename_unit_select.\n");37 test.error(_("nb_rename_unit must be >= nb_rename_unit_select.\n")); 38 38 39 39 if (not is_multiple(_size_queue, _nb_bank)) 40 test.error( "nb_bank must be a multiple of size_queue.\n");40 test.error(_("nb_bank must be a multiple of size_queue.\n")); 41 41 42 42 if (_nb_inst_reexecute != 1) 43 test.error("nb_inst_reexecute must be set at 1. Anothers value is unsupported.\n"); 43 test.error(_("nb_inst_reexecute must be set at 1. Anothers value is unsupported.\n")); 44 45 for (uint32_t i=0; i<_nb_front_end; ++i) 46 for (uint32_t j=0; j<_nb_context[i]; ++j) 47 if (_translate_num_context_to_num_thread [i][j] >= _nb_thread) 48 test.error(toString(_("num_thread [%d][%d] (%d) is >= at nb_thread (%d).\n"),i,j,_translate_num_context_to_num_thread [i][j],_nb_thread)); 49 50 for (uint32_t i=0; i<_nb_front_end; ++i) 51 for (uint32_t j=0; j<_nb_context[i]-1; ++j) 52 for (uint32_t x=i; x<_nb_front_end; ++x) 53 for (uint32_t y=j+1; y<_nb_context[i]; ++y) 54 if (_translate_num_context_to_num_thread [i][j] == _translate_num_context_to_num_thread [x][y]) 55 test.error(toString(_("To context [%d][%d] and [%d][%d], num_thread is the same (%d).\n"),i,j,x,y,_translate_num_context_to_num_thread [i][j])); 56 44 57 45 58 if (_size_queue == 1) 46 test.information ( "Instructions are issued In-Order.\n");59 test.information (_("Instructions are issued In-Order.\n")); 47 60 else 48 test.information ( "Instructions are issued Out-Of-Order.\n");61 test.information (_("Instructions are issued Out-Of-Order.\n")); 49 62 50 63 log_end(Commit_unit,FUNCTION); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/SelfTest/src/test.cpp
r88 r110 333 333 } 334 334 335 bool test_size = issue_queue.size() <= _param->_size_queue;335 bool test_size = issue_queue.size() <= (_param->_size_queue+_param->_size_reexecute_queue); 336 336 TEST(bool,test_size,true); 337 337 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/include/Issue_queue.h
r88 r110 144 144 // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 145 145 private : std::list<entry_t*> * _issue_queue; 146 private : std::list<entry_t*> _reexecute_queue; 146 147 147 148 // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 148 149 private : Tcontrol_t * internal_BANK_IN_ACK ;//[nb_bank] 149 private : bool * internal_BANK_IN_IS_REEXECUTE ;//[nb_bank]150 150 private : uint32_t * internal_BANK_IN_NUM_RENAME_UNIT ;//[nb_bank] 151 151 private : uint32_t * internal_BANK_IN_NUM_INST ;//[nb_bank] 152 152 153 private : Tcontrol_t * internal_BANK_OUT_VAL ;//[nb_bank] 154 private : uint32_t * internal_BANK_OUT_NUM_INST ;//[nb_bank] 153 private : Tcontrol_t * internal_ISSUE_OUT_VAL ;//[nb_inst_issue] 154 private : Tcontrol_t * internal_ISSUE_OUT_FROM_REEXECUTE ;//[nb_inst_issue] 155 private : uint32_t * internal_ISSUE_OUT_NUM_BANK ;//[nb_inst_issue] 156 private : entry_t * * internal_ISSUE_OUT_ENTRY ;//[nb_inst_issue] 157 158 private : Tcontrol_t * internal_REEXECUTE_ACK ;//[nb_inst_reexecute] 155 159 #endif 156 160 … … 187 191 public : void transition (void); 188 192 public : void genMoore (void); 189 public : void genMealy (void);190 193 #endif 191 194 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/include/Parameters.h
r88 r110 45 45 public : bool ** _table_routing ;//[nb_rename_unit][nb_inst_issue] 46 46 public : bool ** _table_issue_type ;//[nb_inst_issue][nb_type] 47 public : uint32_t _size_reexecute_queue ; 47 48 48 49 //public : uint32_t _nb_bank_select_out ; 49 50 public : uint32_t _max_nb_inst_rename ; 50 51 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue.cpp
r88 r110 95 95 # endif 96 96 97 log_printf(INFO,Issue_queue,FUNCTION,_("<%s> : Method - genMealy"),_name.c_str());98 99 SC_METHOD (genMealy);100 dont_initialize ();101 sensitive << (*(in_CLOCK)).neg(); // need internal register102 for (uint32_t i=0; i<_param->_nb_inst_reexecute; i++)103 sensitive << (*(in_REEXECUTE_VAL [i]))104 << (*(in_REEXECUTE_TYPE [i]));105 for (uint32_t i=0; i<_param->_nb_rename_unit; i++)106 for (uint32_t j=0; j<_param->_nb_inst_rename[i]; j++)107 sensitive // << (*(in_ISSUE_IN_VAL [i][j]))108 << (*(in_ISSUE_IN_TYPE [i][j]));109 110 # ifdef SYSTEMCASS_SPECIFIC111 // List dependency information112 for (uint32_t i=0; i<_param->_nb_inst_reexecute; i++)113 for (uint32_t x=0; x<_param->_nb_inst_reexecute; x++)114 {115 (*(out_REEXECUTE_ACK [i])) (*(in_REEXECUTE_VAL [x]));116 (*(out_REEXECUTE_ACK [i])) (*(in_REEXECUTE_TYPE [x]));117 }118 119 for (uint32_t i=0; i<_param->_nb_rename_unit; i++)120 for (uint32_t j=0; j<_param->_nb_inst_rename[i]; j++)121 {122 for (uint32_t x=0; x<_param->_nb_inst_reexecute; x++)123 {124 (*(out_ISSUE_IN_ACK [i][j])) (*(in_REEXECUTE_VAL [x]));125 (*(out_ISSUE_IN_ACK [i][j])) (*(in_REEXECUTE_TYPE [x]));126 }127 128 for (uint32_t x=0; x<_param->_nb_rename_unit; x++)129 for (uint32_t y=0; y<_param->_nb_inst_rename[x]; y++)130 {131 (*(out_ISSUE_IN_ACK [i][j])) (*(in_ISSUE_IN_VAL [x][y]));132 (*(out_ISSUE_IN_ACK [i][j])) (*(in_ISSUE_IN_TYPE [x][y]));133 }134 }135 # endif136 137 97 #endif 138 98 } -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_allocation.cpp
r88 r110 141 141 { 142 142 // ~~~~~[ Registers ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 143 _issue_queue = new std::list<entry_t*> [_param->_nb_bank];143 _issue_queue = new std::list<entry_t*> [_param->_nb_bank]; 144 144 145 145 // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 146 internal_BANK_IN_ACK = new Tcontrol_t [_param->_nb_bank]; 147 internal_BANK_IN_IS_REEXECUTE = new bool [_param->_nb_bank]; 148 internal_BANK_IN_NUM_RENAME_UNIT = new uint32_t [_param->_nb_bank]; 149 internal_BANK_IN_NUM_INST = new uint32_t [_param->_nb_bank]; 150 151 internal_BANK_OUT_VAL = new Tcontrol_t [_param->_nb_bank]; 152 internal_BANK_OUT_NUM_INST = new uint32_t [_param->_nb_bank]; 146 ALLOC1(internal_BANK_IN_ACK ,Tcontrol_t,_param->_nb_bank); 147 ALLOC1(internal_BANK_IN_NUM_RENAME_UNIT ,uint32_t ,_param->_nb_bank); 148 ALLOC1(internal_BANK_IN_NUM_INST ,uint32_t ,_param->_nb_bank); 149 150 ALLOC1(internal_ISSUE_OUT_VAL ,Tcontrol_t,_param->_nb_inst_issue); 151 ALLOC1(internal_ISSUE_OUT_FROM_REEXECUTE,Tcontrol_t,_param->_nb_inst_issue); 152 ALLOC1(internal_ISSUE_OUT_NUM_BANK ,uint32_t ,_param->_nb_inst_issue); 153 ALLOC1(internal_ISSUE_OUT_ENTRY ,entry_t * ,_param->_nb_inst_issue); 154 155 ALLOC1(internal_REEXECUTE_ACK ,Tcontrol_t,_param->_nb_inst_reexecute); 153 156 } 154 157 … … 164 167 _priority_out = new generic::priority::Priority (_name+"_priority_out" , 165 168 _param->_priority , 166 _param->_nb_bank _select_out,167 _param->_nb_bank _select_out);169 _param->_nb_bank, 170 _param->_nb_bank); 168 171 169 _priority_reg = new generic::priority::Priority (_name+"_priority_reg" ,170 PRIORITY_ROUND_ROBIN,172 _priority_reg = new generic::priority::Priority (_name+"_priority_reg" , 173 _param->_priority , 171 174 _param->_nb_bank, 172 175 _param->_nb_bank); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_deallocation.cpp
r88 r110 98 98 99 99 // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 100 delete [] internal_BANK_IN_ACK ; 101 delete [] internal_BANK_IN_IS_REEXECUTE ; 102 delete [] internal_BANK_IN_NUM_RENAME_UNIT; 103 delete [] internal_BANK_IN_NUM_INST ; 104 105 delete [] internal_BANK_OUT_VAL ; 106 delete [] internal_BANK_OUT_NUM_INST ; 100 DELETE1(internal_BANK_IN_ACK ,_param->_nb_bank); 101 DELETE1(internal_BANK_IN_NUM_RENAME_UNIT ,_param->_nb_bank); 102 DELETE1(internal_BANK_IN_NUM_INST ,_param->_nb_bank); 103 104 DELETE1(internal_ISSUE_OUT_VAL ,_param->_nb_inst_issue); 105 DELETE1(internal_ISSUE_OUT_FROM_REEXECUTE,_param->_nb_inst_issue); 106 DELETE1(internal_ISSUE_OUT_NUM_BANK ,_param->_nb_inst_issue); 107 DELETE1(internal_ISSUE_OUT_ENTRY ,_param->_nb_inst_issue); 108 109 DELETE1(internal_REEXECUTE_ACK ,_param->_nb_inst_reexecute); 107 110 } 108 111 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_genMoore.cpp
r88 r110 24 24 log_function(Issue_queue,FUNCTION,_name.c_str()); 25 25 26 for (uint32_t i=0; i<_param->_nb_bank; i++) 27 internal_BANK_OUT_VAL [i] = false; 28 29 std::list<generic::priority::select_t> * select = _priority_out->select(); // same select for all issue 30 31 uint32_t num_bank_offset = 0; 32 for (uint32_t i=0; i<_param->_nb_inst_issue; i++) 26 // =================================================================== 27 // =====[ REEXECUTE_UNIT ]============================================ 28 // =================================================================== 29 30 for (uint32_t i=0; i<_param->_nb_inst_reexecute; ++i) 33 31 { 34 // log_printf(TRACE,Issue_queue,FUNCTION," * ISSUE_OUT [%d]",i); 35 Tcontrol_t val = false; 36 uint32_t num_bank = 0; 37 38 // find a non empty bank 39 for (std::list<generic::priority::select_t>::iterator it=select->begin(); 40 it!=select->end(); 41 it++) 42 { 43 num_bank=num_bank_offset+it->grp; 44 45 // log_printf(TRACE,Issue_queue,FUNCTION," * Bank [%d]",num_bank); 32 log_printf(TRACE,Issue_queue,FUNCTION," * REEXECUTE [%d]",i); 33 34 internal_REEXECUTE_ACK [i] = (_reexecute_queue.size()+i) < _param->_size_reexecute_queue; 35 36 log_printf(TRACE,Issue_queue,FUNCTION," * ACK : %d",internal_REEXECUTE_ACK [i]); 37 38 PORT_WRITE(out_REEXECUTE_ACK [i], internal_REEXECUTE_ACK [i]); 39 } 40 41 // =================================================================== 42 // =====[ ISSUE_IN ]================================================== 43 // =================================================================== 44 { 45 Tcontrol_t ack [_param->_nb_rename_unit][_param->_max_nb_inst_rename]; 46 47 // Initialisation 48 for (uint32_t i=0; i<_param->_nb_bank; i++) 49 internal_BANK_IN_ACK [i] = false; 50 51 for (uint32_t i=0; i<_param->_nb_rename_unit; i++) 52 for (uint32_t j=0; j<_param->_nb_inst_rename[i]; j++) 53 ack [i][j] = false; 54 55 std::list<generic::priority::select_t> * select_reg = _priority_reg->select(); // same select for all issue 56 57 // issue_in interface 58 std::list<generic::priority::select_t> * select_in = _priority_in ->select(); // same select for all issue 59 for (std::list<generic::priority::select_t>::iterator it=select_in ->begin(); 60 it!=select_in ->end(); 61 it++) 62 { 63 // Get num interface 64 uint32_t num_rename_unit = it->grp; 65 uint32_t num_inst_rename = it->elt; 66 67 log_printf(TRACE,Issue_queue,FUNCTION," * ISSUE_IN [%d][%d]",num_rename_unit,num_inst_rename); 68 69 // scan all bank 70 for (std::list<generic::priority::select_t>::iterator it=select_reg->begin(); 71 it!=select_reg->end(); 72 it++) 73 { 74 uint32_t num_bank = it->grp; 75 76 log_printf(TRACE,Issue_queue,FUNCTION," * BANK [%d]",num_bank); 77 78 // test if bank is not busy (full or previous access) 79 if (not internal_BANK_IN_ACK [num_bank] and (_issue_queue[num_bank].size() < _param->_size_bank)) 80 { 81 log_printf(TRACE,Issue_queue,FUNCTION," * find"); 82 83 // find 84 ack [num_rename_unit][num_inst_rename] = true; 85 internal_BANK_IN_ACK [num_bank] = true; 86 internal_BANK_IN_NUM_RENAME_UNIT [num_bank] = num_rename_unit; 87 internal_BANK_IN_NUM_INST [num_bank] = num_inst_rename; 88 89 break; // Stop scan 90 } 91 else 92 log_printf(TRACE,Issue_queue,FUNCTION," * not find"); 93 } 94 } 95 96 for (uint32_t i=0; i<_param->_nb_rename_unit; i++) 97 for (uint32_t j=0; j<_param->_nb_inst_rename[i]; j++) 98 PORT_WRITE(out_ISSUE_IN_ACK [i][j],ack [i][j]); 99 } 100 101 // =================================================================== 102 // =====[ ISSUE_OUT ]================================================= 103 // =================================================================== 104 { 105 Tcontrol_t val [_param->_nb_inst_issue]; 106 107 for (uint32_t i=0; i<_param->_nb_inst_issue; i++) 108 val [i] = 0; 109 110 // From Reexecute_queue 111 112 // uint32_t num_reexecute_entry = 0; 113 for (std::list<entry_t*>::iterator it=_reexecute_queue.begin(); 114 it!=_reexecute_queue.end(); 115 ++it) 116 { 117 entry_t* entry = (*it); 118 119 for (uint32_t i=0; i<_param->_nb_inst_issue; i++) 120 // test if no previous transaction and can accept this type 121 if ((val[i] == 0) and _param->_table_issue_type [i][entry->_type]) 122 { 123 // find a issue port 124 val [i] = 1; 46 125 47 if (not _issue_queue [num_bank].empty()) 48 { 49 // log_printf(TRACE,Issue_queue,FUNCTION," * Not Empty !!!"); 50 val = true; 51 52 internal_BANK_OUT_NUM_INST [num_bank] = i; 53 break; // quit scearch loop 54 } 55 } 56 57 PORT_WRITE(out_ISSUE_OUT_VAL [i], val); 58 59 if (val) 60 { 61 // have find a bank with a data 62 internal_BANK_OUT_VAL [num_bank] = true; 63 64 entry_t* entry = _issue_queue [num_bank].front(); 65 66 if (_param->_have_port_context_id) 67 PORT_WRITE(out_ISSUE_OUT_CONTEXT_ID [i], entry->_context_id ); 68 if (_param->_have_port_front_end_id) 69 PORT_WRITE(out_ISSUE_OUT_FRONT_END_ID [i], entry->_front_end_id ); 70 if (_param->_have_port_rob_ptr ) 71 PORT_WRITE(out_ISSUE_OUT_PACKET_ID [i], entry->_packet_id ); 72 PORT_WRITE(out_ISSUE_OUT_OPERATION [i], entry->_operation ); 73 PORT_WRITE(out_ISSUE_OUT_TYPE [i], entry->_type ); 74 PORT_WRITE(out_ISSUE_OUT_STORE_QUEUE_PTR_WRITE [i], entry->_store_queue_ptr_write); 75 if (_param->_have_port_load_queue_ptr) 76 PORT_WRITE(out_ISSUE_OUT_LOAD_QUEUE_PTR_WRITE [i], entry->_load_queue_ptr_write ); 77 PORT_WRITE(out_ISSUE_OUT_HAS_IMMEDIAT [i], entry->_has_immediat ); 78 PORT_WRITE(out_ISSUE_OUT_IMMEDIAT [i], entry->_immediat ); 79 PORT_WRITE(out_ISSUE_OUT_READ_RA [i], entry->_read_ra ); 80 PORT_WRITE(out_ISSUE_OUT_NUM_REG_RA [i], entry->_num_reg_ra ); 81 PORT_WRITE(out_ISSUE_OUT_READ_RB [i], entry->_read_rb ); 82 PORT_WRITE(out_ISSUE_OUT_NUM_REG_RB [i], entry->_num_reg_rb ); 83 PORT_WRITE(out_ISSUE_OUT_READ_RC [i], entry->_read_rc ); 84 PORT_WRITE(out_ISSUE_OUT_NUM_REG_RC [i], entry->_num_reg_rc ); 85 PORT_WRITE(out_ISSUE_OUT_WRITE_RD [i], entry->_write_rd ); 86 PORT_WRITE(out_ISSUE_OUT_NUM_REG_RD [i], entry->_num_reg_rd ); 87 PORT_WRITE(out_ISSUE_OUT_WRITE_RE [i], entry->_write_re ); 88 PORT_WRITE(out_ISSUE_OUT_NUM_REG_RE [i], entry->_num_reg_re ); 89 } 90 91 num_bank_offset += _param->_nb_bank_select_out; 92 } 126 if (_param->_have_port_context_id) 127 PORT_WRITE(out_ISSUE_OUT_CONTEXT_ID [i], entry->_context_id ); 128 if (_param->_have_port_front_end_id) 129 PORT_WRITE(out_ISSUE_OUT_FRONT_END_ID [i], entry->_front_end_id ); 130 if (_param->_have_port_rob_ptr ) 131 PORT_WRITE(out_ISSUE_OUT_PACKET_ID [i], entry->_packet_id ); 132 PORT_WRITE(out_ISSUE_OUT_OPERATION [i], entry->_operation ); 133 PORT_WRITE(out_ISSUE_OUT_TYPE [i], entry->_type ); 134 PORT_WRITE(out_ISSUE_OUT_STORE_QUEUE_PTR_WRITE [i], entry->_store_queue_ptr_write); 135 if (_param->_have_port_load_queue_ptr) 136 PORT_WRITE(out_ISSUE_OUT_LOAD_QUEUE_PTR_WRITE [i], entry->_load_queue_ptr_write ); 137 PORT_WRITE(out_ISSUE_OUT_HAS_IMMEDIAT [i], entry->_has_immediat ); 138 PORT_WRITE(out_ISSUE_OUT_IMMEDIAT [i], entry->_immediat ); 139 PORT_WRITE(out_ISSUE_OUT_READ_RA [i], entry->_read_ra ); 140 PORT_WRITE(out_ISSUE_OUT_NUM_REG_RA [i], entry->_num_reg_ra ); 141 PORT_WRITE(out_ISSUE_OUT_READ_RB [i], entry->_read_rb ); 142 PORT_WRITE(out_ISSUE_OUT_NUM_REG_RB [i], entry->_num_reg_rb ); 143 PORT_WRITE(out_ISSUE_OUT_READ_RC [i], entry->_read_rc ); 144 PORT_WRITE(out_ISSUE_OUT_NUM_REG_RC [i], entry->_num_reg_rc ); 145 PORT_WRITE(out_ISSUE_OUT_WRITE_RD [i], entry->_write_rd ); 146 PORT_WRITE(out_ISSUE_OUT_NUM_REG_RD [i], entry->_num_reg_rd ); 147 PORT_WRITE(out_ISSUE_OUT_WRITE_RE [i], entry->_write_re ); 148 PORT_WRITE(out_ISSUE_OUT_NUM_REG_RE [i], entry->_num_reg_re ); 149 150 internal_ISSUE_OUT_FROM_REEXECUTE [i] = true; 151 // internal_ISSUE_OUT_NUM_BANK [i] = num_reexecute_entry; 152 internal_ISSUE_OUT_ENTRY [i] = entry; 153 154 break; // stop scan 155 } 156 // num_reexecute_entry ++; 157 } 158 159 // From Issue_queue 160 161 std::list<generic::priority::select_t> * select = _priority_out->select(); // same select for all issue 162 163 for (std::list<generic::priority::select_t>::iterator it=select->begin(); 164 it!=select->end(); 165 it++) 166 { 167 uint32_t num_bank=it->grp; 168 169 // log_printf(TRACE,Issue_queue,Issue_queue,FUNCTION," * Bank [%d]",num_bank); 170 171 // Have instruction ? 172 if (not _issue_queue [num_bank].empty()) 173 { 174 // log_printf(TRACE,Issue_queue,Issue_queue,FUNCTION," * Not Empty !!!"); 175 176 entry_t* entry = _issue_queue [num_bank].front(); 177 178 for (uint32_t i=0; i<_param->_nb_inst_issue; i++) 179 // test if no previous transaction and can accept this type 180 if ((val[i] == 0) and _param->_table_issue_type [i][entry->_type]) 181 { 182 // find a issue port 183 val [i] = 1; 184 185 if (_param->_have_port_context_id) 186 PORT_WRITE(out_ISSUE_OUT_CONTEXT_ID [i], entry->_context_id ); 187 if (_param->_have_port_front_end_id) 188 PORT_WRITE(out_ISSUE_OUT_FRONT_END_ID [i], entry->_front_end_id ); 189 if (_param->_have_port_rob_ptr ) 190 PORT_WRITE(out_ISSUE_OUT_PACKET_ID [i], entry->_packet_id ); 191 PORT_WRITE(out_ISSUE_OUT_OPERATION [i], entry->_operation ); 192 PORT_WRITE(out_ISSUE_OUT_TYPE [i], entry->_type ); 193 PORT_WRITE(out_ISSUE_OUT_STORE_QUEUE_PTR_WRITE [i], entry->_store_queue_ptr_write); 194 if (_param->_have_port_load_queue_ptr) 195 PORT_WRITE(out_ISSUE_OUT_LOAD_QUEUE_PTR_WRITE [i], entry->_load_queue_ptr_write ); 196 PORT_WRITE(out_ISSUE_OUT_HAS_IMMEDIAT [i], entry->_has_immediat ); 197 PORT_WRITE(out_ISSUE_OUT_IMMEDIAT [i], entry->_immediat ); 198 PORT_WRITE(out_ISSUE_OUT_READ_RA [i], entry->_read_ra ); 199 PORT_WRITE(out_ISSUE_OUT_NUM_REG_RA [i], entry->_num_reg_ra ); 200 PORT_WRITE(out_ISSUE_OUT_READ_RB [i], entry->_read_rb ); 201 PORT_WRITE(out_ISSUE_OUT_NUM_REG_RB [i], entry->_num_reg_rb ); 202 PORT_WRITE(out_ISSUE_OUT_READ_RC [i], entry->_read_rc ); 203 PORT_WRITE(out_ISSUE_OUT_NUM_REG_RC [i], entry->_num_reg_rc ); 204 PORT_WRITE(out_ISSUE_OUT_WRITE_RD [i], entry->_write_rd ); 205 PORT_WRITE(out_ISSUE_OUT_NUM_REG_RD [i], entry->_num_reg_rd ); 206 PORT_WRITE(out_ISSUE_OUT_WRITE_RE [i], entry->_write_re ); 207 PORT_WRITE(out_ISSUE_OUT_NUM_REG_RE [i], entry->_num_reg_re ); 208 209 internal_ISSUE_OUT_FROM_REEXECUTE [i] = false; 210 internal_ISSUE_OUT_NUM_BANK [i] = num_bank; 211 internal_ISSUE_OUT_ENTRY [i] = entry; 212 213 break; // stop scan 214 } 215 } 216 } 217 218 for (uint32_t i=0; i<_param->_nb_inst_issue; i++) 219 { 220 internal_ISSUE_OUT_VAL [i] = val [i]; 221 PORT_WRITE(out_ISSUE_OUT_VAL [i], internal_ISSUE_OUT_VAL [i]); 222 } 223 } 93 224 94 225 log_end(Issue_queue,FUNCTION); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_transition.cpp
r109 r110 32 32 for (uint32_t i=0; i<_param->_nb_bank; i++) 33 33 _issue_queue [i].clear(); 34 _reexecute_queue.clear(); 34 35 } 35 36 else … … 42 43 // =====[ ISSUE_IN ]================================================== 43 44 // =================================================================== 45 44 46 for (uint32_t i=0; i<_param->_nb_bank; i++) 45 47 if (internal_BANK_IN_ACK [i]) 46 48 { 47 entry_t * entry = NULL; 48 49 if (internal_BANK_IN_IS_REEXECUTE [i]) 50 { 51 uint32_t y = internal_BANK_IN_NUM_INST [i]; 52 53 if (PORT_READ(in_REEXECUTE_VAL [y])) 54 { 55 log_printf(TRACE,Issue_queue,FUNCTION," * ISSUE_IN [%d] - Transaction with REEXECUTE [%d]",i,y); 49 uint32_t x = internal_BANK_IN_NUM_RENAME_UNIT [i]; 50 uint32_t y = internal_BANK_IN_NUM_INST [i]; 51 52 if (PORT_READ(in_ISSUE_IN_VAL[x][y])) 53 { 54 log_printf(TRACE,Issue_queue,FUNCTION," * ISSUE_IN [%d] - Transaction with ISSUE_IN [%d][%d]",i,x,y); 55 56 56 #ifdef STATISTICS 57 if (usage_is_set(_usage,USE_STATISTICS)) 58 (*_stat_nb_inst_reexecute) ++; 59 #endif 60 entry = new entry_t 61 ( 62 (_param->_have_port_context_id )?PORT_READ(in_REEXECUTE_CONTEXT_ID [y]):0, 63 (_param->_have_port_front_end_id )?PORT_READ(in_REEXECUTE_FRONT_END_ID [y]):0, 64 (_param->_have_port_rob_ptr )?PORT_READ(in_REEXECUTE_PACKET_ID [y]):0, 65 PORT_READ(in_REEXECUTE_OPERATION [y]), 66 PORT_READ(in_REEXECUTE_TYPE [y]), 67 PORT_READ(in_REEXECUTE_STORE_QUEUE_PTR_WRITE [y]), 68 (_param->_have_port_load_queue_ptr)?PORT_READ(in_REEXECUTE_LOAD_QUEUE_PTR_WRITE [y]):0, 69 PORT_READ(in_REEXECUTE_HAS_IMMEDIAT [y]), 70 PORT_READ(in_REEXECUTE_IMMEDIAT [y]), 71 PORT_READ(in_REEXECUTE_READ_RA [y]), 72 PORT_READ(in_REEXECUTE_NUM_REG_RA [y]), 73 PORT_READ(in_REEXECUTE_READ_RB [y]), 74 PORT_READ(in_REEXECUTE_NUM_REG_RB [y]), 75 PORT_READ(in_REEXECUTE_READ_RC [y]), 76 PORT_READ(in_REEXECUTE_NUM_REG_RC [y]), 77 PORT_READ(in_REEXECUTE_WRITE_RD [y]), 78 PORT_READ(in_REEXECUTE_NUM_REG_RD [y]), 79 PORT_READ(in_REEXECUTE_WRITE_RE [y]), 80 PORT_READ(in_REEXECUTE_NUM_REG_RE [y]) 81 ); 82 } 83 } 84 else 85 { 86 uint32_t x = internal_BANK_IN_NUM_RENAME_UNIT [i]; 87 uint32_t y = internal_BANK_IN_NUM_INST [i]; 88 89 if (PORT_READ(in_ISSUE_IN_VAL[x][y])) 90 { 91 log_printf(TRACE,Issue_queue,FUNCTION," * ISSUE_IN [%d] - Transaction with ISSUE_IN [%d][%d]",i,x,y); 92 57 if (usage_is_set(_usage,USE_STATISTICS)) 58 (*_stat_nb_inst_issue_in [x]) ++; 59 #endif 60 entry_t * entry = new entry_t 61 ( 62 (_param->_have_port_context_id )?PORT_READ(in_ISSUE_IN_CONTEXT_ID [x][y]):0, 63 (_param->_have_port_front_end_id )?PORT_READ(in_ISSUE_IN_FRONT_END_ID [x][y]):0, 64 (_param->_have_port_rob_ptr )?PORT_READ(in_ISSUE_IN_PACKET_ID [x][y]):0, 65 PORT_READ(in_ISSUE_IN_OPERATION [x][y]), 66 PORT_READ(in_ISSUE_IN_TYPE [x][y]), 67 PORT_READ(in_ISSUE_IN_STORE_QUEUE_PTR_WRITE [x][y]), 68 (_param->_have_port_load_queue_ptr)?PORT_READ(in_ISSUE_IN_LOAD_QUEUE_PTR_WRITE [x][y]):0, 69 PORT_READ(in_ISSUE_IN_HAS_IMMEDIAT [x][y]), 70 PORT_READ(in_ISSUE_IN_IMMEDIAT [x][y]), 71 PORT_READ(in_ISSUE_IN_READ_RA [x][y]), 72 PORT_READ(in_ISSUE_IN_NUM_REG_RA [x][y]), 73 PORT_READ(in_ISSUE_IN_READ_RB [x][y]), 74 PORT_READ(in_ISSUE_IN_NUM_REG_RB [x][y]), 75 PORT_READ(in_ISSUE_IN_READ_RC [x][y]), 76 PORT_READ(in_ISSUE_IN_NUM_REG_RC [x][y]), 77 PORT_READ(in_ISSUE_IN_WRITE_RD [x][y]), 78 PORT_READ(in_ISSUE_IN_NUM_REG_RD [x][y]), 79 PORT_READ(in_ISSUE_IN_WRITE_RE [x][y]), 80 PORT_READ(in_ISSUE_IN_NUM_REG_RE [x][y]) 81 ); 82 83 _issue_queue [i].push_back(entry); 84 } 85 } 86 87 // =================================================================== 88 // =====[ REEXECUTE_UNIT ]============================================ 89 // =================================================================== 90 91 for (uint32_t i=0; i<_param->_nb_inst_reexecute; ++i) 92 if (PORT_READ(in_REEXECUTE_VAL [i]) and internal_REEXECUTE_ACK [i]) 93 { 94 log_printf(TRACE,Issue_queue,FUNCTION," * REEXECUTE [%d]",i); 93 95 #ifdef STATISTICS 94 if (usage_is_set(_usage,USE_STATISTICS)) 95 (*_stat_nb_inst_issue_in [x]) ++; 96 #endif 97 entry = new entry_t 98 ( 99 (_param->_have_port_context_id )?PORT_READ(in_ISSUE_IN_CONTEXT_ID [x][y]):0, 100 (_param->_have_port_front_end_id )?PORT_READ(in_ISSUE_IN_FRONT_END_ID [x][y]):0, 101 (_param->_have_port_rob_ptr )?PORT_READ(in_ISSUE_IN_PACKET_ID [x][y]):0, 102 PORT_READ(in_ISSUE_IN_OPERATION [x][y]), 103 PORT_READ(in_ISSUE_IN_TYPE [x][y]), 104 PORT_READ(in_ISSUE_IN_STORE_QUEUE_PTR_WRITE [x][y]), 105 (_param->_have_port_load_queue_ptr)?PORT_READ(in_ISSUE_IN_LOAD_QUEUE_PTR_WRITE [x][y]):0, 106 PORT_READ(in_ISSUE_IN_HAS_IMMEDIAT [x][y]), 107 PORT_READ(in_ISSUE_IN_IMMEDIAT [x][y]), 108 PORT_READ(in_ISSUE_IN_READ_RA [x][y]), 109 PORT_READ(in_ISSUE_IN_NUM_REG_RA [x][y]), 110 PORT_READ(in_ISSUE_IN_READ_RB [x][y]), 111 PORT_READ(in_ISSUE_IN_NUM_REG_RB [x][y]), 112 PORT_READ(in_ISSUE_IN_READ_RC [x][y]), 113 PORT_READ(in_ISSUE_IN_NUM_REG_RC [x][y]), 114 PORT_READ(in_ISSUE_IN_WRITE_RD [x][y]), 115 PORT_READ(in_ISSUE_IN_NUM_REG_RD [x][y]), 116 PORT_READ(in_ISSUE_IN_WRITE_RE [x][y]), 117 PORT_READ(in_ISSUE_IN_NUM_REG_RE [x][y]) 118 ); 119 } 120 } 121 122 if (entry != NULL) 123 _issue_queue [i].push_back(entry); 124 } 96 if (usage_is_set(_usage,USE_STATISTICS)) 97 (*_stat_nb_inst_reexecute) ++; 98 #endif 99 entry_t * entry = new entry_t 100 ( 101 (_param->_have_port_context_id )?PORT_READ(in_REEXECUTE_CONTEXT_ID [i]):0, 102 (_param->_have_port_front_end_id )?PORT_READ(in_REEXECUTE_FRONT_END_ID [i]):0, 103 (_param->_have_port_rob_ptr )?PORT_READ(in_REEXECUTE_PACKET_ID [i]):0, 104 PORT_READ(in_REEXECUTE_OPERATION [i]), 105 PORT_READ(in_REEXECUTE_TYPE [i]), 106 PORT_READ(in_REEXECUTE_STORE_QUEUE_PTR_WRITE [i]), 107 (_param->_have_port_load_queue_ptr)?PORT_READ(in_REEXECUTE_LOAD_QUEUE_PTR_WRITE [i]):0, 108 PORT_READ(in_REEXECUTE_HAS_IMMEDIAT [i]), 109 PORT_READ(in_REEXECUTE_IMMEDIAT [i]), 110 PORT_READ(in_REEXECUTE_READ_RA [i]), 111 PORT_READ(in_REEXECUTE_NUM_REG_RA [i]), 112 PORT_READ(in_REEXECUTE_READ_RB [i]), 113 PORT_READ(in_REEXECUTE_NUM_REG_RB [i]), 114 PORT_READ(in_REEXECUTE_READ_RC [i]), 115 PORT_READ(in_REEXECUTE_NUM_REG_RC [i]), 116 PORT_READ(in_REEXECUTE_WRITE_RD [i]), 117 PORT_READ(in_REEXECUTE_NUM_REG_RD [i]), 118 PORT_READ(in_REEXECUTE_WRITE_RE [i]), 119 PORT_READ(in_REEXECUTE_NUM_REG_RE [i]) 120 ); 121 122 _reexecute_queue.push_back(entry); 123 } 125 124 126 125 // =================================================================== 127 126 // =====[ ISSUE_OUT ]================================================= 128 127 // =================================================================== 129 for (uint32_t i=0; i<_param->_nb_bank; i++) 130 { 131 // log_printf(TRACE,Issue_queue,FUNCTION," * internal_BANK_OUT [%d] val %d, num_inst %d",i,internal_BANK_OUT_VAL [i],internal_BANK_OUT_NUM_INST [i]); 132 133 if (internal_BANK_OUT_VAL [i]) 134 { 135 #ifdef STATISTICS 136 if (usage_is_set(_usage,USE_STATISTICS)) 137 (*_stat_nb_inst_issue_out) ++; 138 #endif 139 140 uint32_t x = internal_BANK_OUT_NUM_INST [i]; 141 // log_printf(TRACE,Issue_queue,FUNCTION," * ISSUE_OUT_ACK : %d",PORT_READ(in_ISSUE_OUT_ACK [x])); 142 143 if (PORT_READ(in_ISSUE_OUT_ACK [x])) 144 { 145 log_printf(TRACE,Issue_queue,FUNCTION," * ISSUE_OUT [%d] - Transaction with ISSUE_OUT [%d]",i,x); 146 147 148 entry_t * entry = _issue_queue [i].front(); 149 _issue_queue [i].pop_front(); 150 delete entry; 151 } 152 } 153 } 128 129 for (uint32_t i=0; i<_param->_nb_inst_issue; ++i) 130 if (internal_ISSUE_OUT_VAL [i] and PORT_READ(in_ISSUE_OUT_ACK [i])) 131 { 132 entry_t * entry = internal_ISSUE_OUT_ENTRY [i]; 133 134 if (internal_ISSUE_OUT_FROM_REEXECUTE [i]) 135 { 136 log_printf(TRACE,Issue_queue,FUNCTION," * ISSUE_OUT [%d] - From Reexecute_queue",i); 137 138 _reexecute_queue.remove(entry); 139 } 140 else 141 { 142 // front ... 143 uint32_t num_bank = internal_ISSUE_OUT_NUM_BANK [i]; 144 145 log_printf(TRACE,Issue_queue,FUNCTION," * ISSUE_OUT [%d] - From issue_queue [%d]",i,num_bank); 146 147 _issue_queue [num_bank].remove(entry); 148 } 149 150 delete entry; 151 } 154 152 } 155 153 154 #if defined(DEBUG) and defined(DEBUG_Issue_queue) and (DEBUG >= DEBUG_TRACE) 156 155 log_printf(TRACE,Issue_queue,FUNCTION," * Dump Issue_queue"); 156 157 157 for (uint32_t i=0; i<_param->_nb_bank; i++) 158 158 { 159 #ifdef STATISTICS160 if (usage_is_set(_usage,USE_STATISTICS))161 *(_stat_bank_nb_inst [i]) += _issue_queue[i].size();162 #endif163 159 log_printf(TRACE,Issue_queue,FUNCTION," * Bank [%d] size : %d",i,(int)_issue_queue[i].size()); 164 160 … … 199 195 ++j; 200 196 } 201 202 197 } 198 199 { 200 log_printf(TRACE,Issue_queue,FUNCTION," * Reexecute_queue - size : %d",(int)_reexecute_queue.size()); 201 202 uint32_t i = 0; 203 204 for (std::list<entry_t*>::iterator it=_reexecute_queue.begin();it!=_reexecute_queue.end(); ++it) 205 { 206 log_printf(TRACE,Issue_queue,FUNCTION," [%.4d] %.2d %.2d %.4d, %.2d %.3d, %.2d %.2d, %.1d %.8x, %.1d %.4d, %.1d %.4d, %.1d %.4d, %.1d %.4d, %.1d %.4d", 207 i, 208 209 (*it)->_context_id , 210 (*it)->_front_end_id , 211 (*it)->_packet_id , 212 213 (*it)->_type , 214 (*it)->_operation , 215 216 (*it)->_store_queue_ptr_write, 217 (*it)->_load_queue_ptr_write , 218 219 (*it)->_has_immediat , 220 (*it)->_immediat , 221 222 (*it)->_read_ra , 223 (*it)->_num_reg_ra , 224 225 (*it)->_read_rb , 226 (*it)->_num_reg_rb , 227 228 (*it)->_read_rc , 229 (*it)->_num_reg_rc , 230 231 (*it)->_write_rd , 232 (*it)->_num_reg_rd , 233 234 (*it)->_write_re , 235 (*it)->_num_reg_re ); 236 ++i; 237 } 238 } 239 #endif 240 241 #ifdef STATISTICS 242 if (usage_is_set(_usage,USE_STATISTICS)) 243 for (uint32_t i=0; i<_param->_nb_bank; i++) 244 *(_stat_bank_nb_inst [i]) += _issue_queue[i].size(); 245 #endif 203 246 204 247 #if defined(STATISTICS) or defined(VHDL_TESTBENCH) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Parameters.cpp
r109 r110 56 56 _table_routing = table_routing ; 57 57 _table_issue_type = table_issue_type ; 58 _size_reexecute_queue = nb_inst_reexecute ; 58 59 59 60 log_printf(TRACE,Issue_queue,FUNCTION," * table_routing [nb_rename_unit][nb_inst_issue]"); … … 70 71 71 72 _max_nb_inst_rename = max<uint32_t>(_nb_inst_rename,_nb_rename_unit); 72 _nb_bank_select_out = _nb_bank/nb_inst_issue;73 73 74 74 _size_bank = _size_queue / _nb_bank; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/src/test.cpp
r88 r110 26 26 // _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); 27 27 // _usage = usage_unset(_usage,USE_POSITION ); 28 _usage = usage_unset(_usage,USE_STATISTICS );28 // _usage = usage_unset(_usage,USE_STATISTICS ); 29 29 // _usage = usage_unset(_usage,USE_INFORMATION ); 30 30 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/include/OOO_Engine_Glue.h
r88 r110 52 52 #ifdef STATISTICS 53 53 public : Stat * _stat; 54 55 private : counter_t * _stat_nb_inst_issue_stall_by_registerfile; 56 //private : counter_t * _stat_nb_inst_issue_stall_by_rename_unit ; 57 private : counter_t * _stat_nb_inst_issue_stall_by_commit_unit ; 58 private : counter_t * _stat_nb_inst_issue_stall_by_issue_queue ; 54 59 #endif 55 60 … … 122 127 public : SC_OUT(Tspecial_address_t ) *** out_INSERT_COMMIT_UNIT_NUM_REG_RE_PHY_NEW ;//[nb_rename_unit][nb_inst_insert] 123 128 124 public : SC_OUT(Tcontrol_t ) *** out_INSERT_ISSUE_QUEUE_VAL ;//[nb_rename_unit][nb_inst_ rename]125 public : SC_IN (Tcontrol_t ) *** in_INSERT_ISSUE_QUEUE_ACK ;//[nb_rename_unit][nb_inst_ rename]126 public : SC_OUT(Tcontext_t ) *** out_INSERT_ISSUE_QUEUE_CONTEXT_ID ;//[nb_rename_unit][nb_inst_ rename]127 public : SC_OUT(Tcontext_t ) *** out_INSERT_ISSUE_QUEUE_FRONT_END_ID ;//[nb_rename_unit][nb_inst_ rename]128 public : SC_OUT(Toperation_t ) *** out_INSERT_ISSUE_QUEUE_OPERATION ;//[nb_rename_unit][nb_inst_ rename]129 public : SC_OUT(Ttype_t ) *** out_INSERT_ISSUE_QUEUE_TYPE ;//[nb_rename_unit][nb_inst_ rename]130 public : SC_OUT(Tlsq_ptr_t ) *** out_INSERT_ISSUE_QUEUE_STORE_QUEUE_PTR_WRITE ;//[nb_rename_unit][nb_inst_ rename]131 public : SC_OUT(Tlsq_ptr_t ) *** out_INSERT_ISSUE_QUEUE_LOAD_QUEUE_PTR_WRITE ;//[nb_rename_unit][nb_inst_ rename]132 public : SC_OUT(Tcontrol_t ) *** out_INSERT_ISSUE_QUEUE_HAS_IMMEDIAT ;//[nb_rename_unit][nb_inst_ rename]133 public : SC_OUT(Tgeneral_data_t ) *** out_INSERT_ISSUE_QUEUE_IMMEDIAT ;//[nb_rename_unit][nb_inst_ rename]134 public : SC_OUT(Tcontrol_t ) *** out_INSERT_ISSUE_QUEUE_READ_RA ;//[nb_rename_unit][nb_inst_ rename]135 public : SC_OUT(Tgeneral_address_t ) *** out_INSERT_ISSUE_QUEUE_NUM_REG_RA ;//[nb_rename_unit][nb_inst_ rename]136 public : SC_OUT(Tcontrol_t ) *** out_INSERT_ISSUE_QUEUE_READ_RB ;//[nb_rename_unit][nb_inst_ rename]137 public : SC_OUT(Tgeneral_address_t ) *** out_INSERT_ISSUE_QUEUE_NUM_REG_RB ;//[nb_rename_unit][nb_inst_ rename]138 public : SC_OUT(Tcontrol_t ) *** out_INSERT_ISSUE_QUEUE_READ_RC ;//[nb_rename_unit][nb_inst_ rename]139 public : SC_OUT(Tspecial_address_t ) *** out_INSERT_ISSUE_QUEUE_NUM_REG_RC ;//[nb_rename_unit][nb_inst_ rename]140 public : SC_OUT(Tcontrol_t ) *** out_INSERT_ISSUE_QUEUE_WRITE_RD ;//[nb_rename_unit][nb_inst_ rename]141 public : SC_OUT(Tgeneral_address_t ) *** out_INSERT_ISSUE_QUEUE_NUM_REG_RD ;//[nb_rename_unit][nb_inst_ rename]142 public : SC_OUT(Tcontrol_t ) *** out_INSERT_ISSUE_QUEUE_WRITE_RE ;//[nb_rename_unit][nb_inst_ rename]143 public : SC_OUT(Tspecial_address_t ) *** out_INSERT_ISSUE_QUEUE_NUM_REG_RE ;//[nb_rename_unit][nb_inst_ rename]129 public : SC_OUT(Tcontrol_t ) *** out_INSERT_ISSUE_QUEUE_VAL ;//[nb_rename_unit][nb_inst_insert] 130 public : SC_IN (Tcontrol_t ) *** in_INSERT_ISSUE_QUEUE_ACK ;//[nb_rename_unit][nb_inst_insert] 131 public : SC_OUT(Tcontext_t ) *** out_INSERT_ISSUE_QUEUE_CONTEXT_ID ;//[nb_rename_unit][nb_inst_insert] 132 public : SC_OUT(Tcontext_t ) *** out_INSERT_ISSUE_QUEUE_FRONT_END_ID ;//[nb_rename_unit][nb_inst_insert] 133 public : SC_OUT(Toperation_t ) *** out_INSERT_ISSUE_QUEUE_OPERATION ;//[nb_rename_unit][nb_inst_insert] 134 public : SC_OUT(Ttype_t ) *** out_INSERT_ISSUE_QUEUE_TYPE ;//[nb_rename_unit][nb_inst_insert] 135 public : SC_OUT(Tlsq_ptr_t ) *** out_INSERT_ISSUE_QUEUE_STORE_QUEUE_PTR_WRITE ;//[nb_rename_unit][nb_inst_insert] 136 public : SC_OUT(Tlsq_ptr_t ) *** out_INSERT_ISSUE_QUEUE_LOAD_QUEUE_PTR_WRITE ;//[nb_rename_unit][nb_inst_insert] 137 public : SC_OUT(Tcontrol_t ) *** out_INSERT_ISSUE_QUEUE_HAS_IMMEDIAT ;//[nb_rename_unit][nb_inst_insert] 138 public : SC_OUT(Tgeneral_data_t ) *** out_INSERT_ISSUE_QUEUE_IMMEDIAT ;//[nb_rename_unit][nb_inst_insert] 139 public : SC_OUT(Tcontrol_t ) *** out_INSERT_ISSUE_QUEUE_READ_RA ;//[nb_rename_unit][nb_inst_insert] 140 public : SC_OUT(Tgeneral_address_t ) *** out_INSERT_ISSUE_QUEUE_NUM_REG_RA ;//[nb_rename_unit][nb_inst_insert] 141 public : SC_OUT(Tcontrol_t ) *** out_INSERT_ISSUE_QUEUE_READ_RB ;//[nb_rename_unit][nb_inst_insert] 142 public : SC_OUT(Tgeneral_address_t ) *** out_INSERT_ISSUE_QUEUE_NUM_REG_RB ;//[nb_rename_unit][nb_inst_insert] 143 public : SC_OUT(Tcontrol_t ) *** out_INSERT_ISSUE_QUEUE_READ_RC ;//[nb_rename_unit][nb_inst_insert] 144 public : SC_OUT(Tspecial_address_t ) *** out_INSERT_ISSUE_QUEUE_NUM_REG_RC ;//[nb_rename_unit][nb_inst_insert] 145 public : SC_OUT(Tcontrol_t ) *** out_INSERT_ISSUE_QUEUE_WRITE_RD ;//[nb_rename_unit][nb_inst_insert] 146 public : SC_OUT(Tgeneral_address_t ) *** out_INSERT_ISSUE_QUEUE_NUM_REG_RD ;//[nb_rename_unit][nb_inst_insert] 147 public : SC_OUT(Tcontrol_t ) *** out_INSERT_ISSUE_QUEUE_WRITE_RE ;//[nb_rename_unit][nb_inst_insert] 148 public : SC_OUT(Tspecial_address_t ) *** out_INSERT_ISSUE_QUEUE_NUM_REG_RE ;//[nb_rename_unit][nb_inst_insert] 144 149 145 150 // // ~~~~~[ Interface "retire" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue_genMealy_insert_valack.cpp
r109 r110 59 59 commit_unit_ack and 60 60 not rename_unit_no_execute); 61 61 62 62 PORT_WRITE(out_INSERT_VAL [x] ,val ); 63 63 PORT_WRITE(out_INSERT_RENAME_UNIT_ACK [i][j],rename_unit_ack); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue_statistics_allocation.cpp
r88 r110 26 26 "OOO_Engine_Glue", 27 27 param_statistics); 28 29 _stat_nb_inst_issue_stall_by_registerfile = _stat->create_variable("nb_inst_issue_stall_by_registerfile"); 30 // _stat_nb_inst_issue_stall_by_rename_unit = _stat->create_variable("nb_inst_issue_stall_by_rename_unit" ); 31 _stat_nb_inst_issue_stall_by_commit_unit = _stat->create_variable("nb_inst_issue_stall_by_commit_unit" ); 32 _stat_nb_inst_issue_stall_by_issue_queue = _stat->create_variable("nb_inst_issue_stall_by_issue_queue" ); 33 34 // std::string nb_inst_issue_stall = "+ + nb_inst_issue_stall_by_registerfile nb_inst_issue_stall_by_rename_unit + nb_inst_issue_stall_by_commit_unit nb_inst_issue_stall_by_issue_queue"; 35 std::string nb_inst_issue_stall = "+ nb_inst_issue_stall_by_registerfile + nb_inst_issue_stall_by_commit_unit nb_inst_issue_stall_by_issue_queue"; 36 37 _stat->create_expr_percent ("percent_issue_stall_by_registerfile", "nb_inst_issue_stall_by_registerfile", nb_inst_issue_stall, _("Percent of instruction stalled by RegisterFile")); 38 // _stat->create_expr_percent ("percent_issue_stall_by_rename_unit" , "nb_inst_issue_stall_by_rename_unit" , nb_inst_issue_stall, _("Percent of instruction stalled by Rename_Unit") ); 39 _stat->create_expr_percent ("percent_issue_stall_by_commit_unit" , "nb_inst_issue_stall_by_commit_unit" , nb_inst_issue_stall, _("Percent of instruction stalled by Commit_Unit") ); 40 _stat->create_expr_percent ("percent_issue_stall_by_issue_queue" , "nb_inst_issue_stall_by_issue_queue" , nb_inst_issue_stall, _("Percent of instruction stalled by Issue_Queue") ); 28 41 29 42 log_end(OOO_Engine_Glue,FUNCTION); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue_transition.cpp
r88 r110 23 23 log_begin(OOO_Engine_Glue,FUNCTION); 24 24 25 #ifdef STATISTICS 26 if (usage_is_set(_usage,USE_STATISTICS)) 27 { 28 uint32_t x=0; 29 for (uint32_t i=0; i<_param->_nb_rename_unit; ++i) 30 for (uint32_t j=0; j<_param->_nb_inst_insert[i]; ++j) 31 { 32 if (PORT_READ(in_INSERT_RENAME_UNIT_VAL [i][j])) 33 { 34 if (PORT_READ(in_INSERT_ACK [x]) == 0) 35 (*_stat_nb_inst_issue_stall_by_registerfile) ++; 36 if (PORT_READ(in_INSERT_COMMIT_UNIT_ACK [i][j]) == 0) 37 (*_stat_nb_inst_issue_stall_by_commit_unit ) ++; 38 if (PORT_READ(in_INSERT_ISSUE_QUEUE_ACK [i][j]) == 0) 39 (*_stat_nb_inst_issue_stall_by_issue_queue ) ++; 40 } 41 x++; 42 } 43 } 44 #endif 45 25 46 #if defined(STATISTICS) or defined(VHDL_TESTBENCH) 26 47 end_cycle (); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/SelfTest/configuration.cfg
r81 r110 5 5 2 4 *2 # size_store_queue [0] [nb_load_store_queue] 6 6 1 4 *2 # size_load_queue [0] [nb_load_store_queue] 7 1 4 *4 # nb_inst_memory [0] [nb_load_store_queue] 7 8 0 0 +1 # link_load_store_unit_with_thread [0][0] [nb_front_end][nb_context] 8 9 1 4 *4 # nb_inst_insert -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/SelfTest/src/main.cpp
r88 r110 19 19 err (_(" * size_store_queue [nb_load_store_queue] (uint32_t)\n")); 20 20 err (_(" * size_load_queue [nb_load_store_queue] (uint32_t)\n")); 21 err (_(" * nb_inst_memory [nb_load_store_queue] (uint32_t)\n")); 21 22 err (_(" * link_load_store_unit_with_thread [nb_front_end][nb_context](uint32_t)\n")); 22 23 err (_(" * nb_inst_insert (uint32_t)\n")); … … 53 54 uint32_t _nb_load_store_queue = fromString<uint32_t>(argv[x++]); 54 55 55 if (argc != static_cast<int>(2+NB_PARAMS+_nb_front_end+ 2*_nb_load_store_queue+nb_thread))56 if (argc != static_cast<int>(2+NB_PARAMS+_nb_front_end+3*_nb_load_store_queue+nb_thread)) 56 57 usage (argc, argv); 57 58 58 59 uint32_t * _size_store_queue = new uint32_t [_nb_load_store_queue]; 59 60 uint32_t * _size_load_queue = new uint32_t [_nb_load_store_queue]; 61 uint32_t * _nb_inst_memory = new uint32_t [_nb_load_store_queue]; 60 62 61 63 for (uint32_t i=0; i<_nb_load_store_queue; i++) … … 63 65 for (uint32_t i=0; i<_nb_load_store_queue; i++) 64 66 _size_load_queue [i] = atoi(argv[x++]); 67 for (uint32_t i=0; i<_nb_load_store_queue; i++) 68 _nb_inst_memory [i] = atoi(argv[x++]); 65 69 66 70 uint32_t ** _link_load_store_unit_with_thread = new uint32_t * [_nb_front_end]; … … 84 88 _size_store_queue , 85 89 _size_load_queue , 90 _nb_inst_memory , 86 91 _link_load_store_unit_with_thread, 87 92 _nb_inst_insert , -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/include/Parameters.h
r88 r110 29 29 public : uint32_t * _size_store_queue ; //[nb_load_store_queue] 30 30 public : uint32_t * _size_load_queue ; //[nb_load_store_queue] 31 public : uint32_t * _nb_inst_memory ; //[nb_load_store_queue] 31 32 public : uint32_t ** _link_load_store_unit_with_thread; //[nb_front_end][nb_context] 32 33 public : uint32_t _nb_inst_insert ; 33 34 public : uint32_t _nb_inst_retire ; 35 36 public : uint32_t _max_size_store_queue ; 37 public : uint32_t _max_size_load_queue ; 34 38 35 39 //public : uint32_t _size_front_end_id ; … … 50 54 uint32_t * size_store_queue , 51 55 uint32_t * size_load_queue , 56 uint32_t * nb_inst_memory , 52 57 uint32_t ** link_load_store_unit_with_thread, 53 58 uint32_t nb_inst_insert , -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/src/Load_Store_pointer_unit_genMealy_insert.cpp
r81 r110 22 22 void Load_Store_pointer_unit::genMealy_insert (void) 23 23 { 24 log_printf(FUNC,Load_Store_pointer_unit,FUNCTION,"Begin"); 24 log_begin(Load_Store_pointer_unit,FUNCTION); 25 log_function(Load_Store_pointer_unit,FUNCTION,_name.c_str()); 25 26 26 bool use_lsq [_param->_nb_load_store_queue]; 27 // TODO : limité à nb_inst_memory le nombre d'accès par lsq !!! 28 29 uint32_t nb_use_lsq [_param->_nb_load_store_queue]; 30 Tlsq_ptr_t STORE_QUEUE_PTR_WRITE [_param->_nb_load_store_queue]; 31 bool STORE_QUEUE_USE [_param->_nb_load_store_queue][_param->_max_size_store_queue]; 32 Tlsq_ptr_t STORE_QUEUE_NB_USE [_param->_nb_load_store_queue]; 33 Tlsq_ptr_t LOAD_QUEUE_PTR_WRITE [_param->_nb_load_store_queue]; 34 bool LOAD_QUEUE_USE [_param->_nb_load_store_queue][_param->_max_size_load_queue]; 35 27 36 for (uint32_t i=0; i<_param->_nb_load_store_queue; i++) 28 use_lsq [i] = false; 37 { 38 nb_use_lsq [i] = _param->_nb_inst_memory[i]; 39 40 STORE_QUEUE_PTR_WRITE [i] = reg_STORE_QUEUE_PTR_WRITE [i]; 41 STORE_QUEUE_NB_USE [i] = reg_STORE_QUEUE_NB_USE [i]; 42 LOAD_QUEUE_PTR_WRITE [i] = reg_LOAD_QUEUE_PTR_WRITE [i]; 43 44 for (uint32_t j=0; j<_param->_size_store_queue[i]; j++) 45 STORE_QUEUE_USE [i][j] = reg_STORE_QUEUE_USE [i][j]; 46 for (uint32_t j=0; j<_param->_size_load_queue[i]; j++) 47 LOAD_QUEUE_USE [i][j] = reg_LOAD_QUEUE_USE [i][j]; 48 } 29 49 30 50 for (uint32_t i=0; i<_param->_nb_inst_insert; i++) 31 51 { 52 log_printf(TRACE,Load_Store_pointer_unit,FUNCTION," * INSERT [%d]",i); 53 32 54 Tcontrol_t ack = false; 33 Tlsq_ptr_t store_queue_ptr_write = 0;34 Tlsq_ptr_t load_queue_ptr_write = 0;35 55 36 56 if ( (PORT_READ(in_INSERT_VAL [i]) == true ) and 37 57 (PORT_READ(in_INSERT_TYPE [i]) == TYPE_MEMORY)) 38 58 { 59 log_printf(TRACE,Load_Store_pointer_unit,FUNCTION," * type is memory"); 60 39 61 Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_INSERT_FRONT_END_ID [i]):0; 40 62 Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_INSERT_CONTEXT_ID [i]):0; 41 42 63 uint32_t lsq = _param->_link_load_store_unit_with_thread[front_end_id][context_id]; 64 65 log_printf(TRACE,Load_Store_pointer_unit,FUNCTION," * front_end_id : %d",front_end_id); 66 log_printf(TRACE,Load_Store_pointer_unit,FUNCTION," * context_id : %d",context_id ); 67 log_printf(TRACE,Load_Store_pointer_unit,FUNCTION," * lsq : %d",lsq ); 43 68 44 69 // Test if a previous instruction use the same lsq 45 70 // Authorize once memory access by load store unit 46 if ( use_lsq [lsq] == false)71 if (nb_use_lsq [lsq] > 0) 47 72 { 48 use_lsq [lsq] = true;73 nb_use_lsq [lsq] --; 49 74 50 75 uint32_t ptr; 51 52 store_queue_ptr_write = reg_STORE_QUEUE_PTR_WRITE [lsq]; 53 load_queue_ptr_write = reg_LOAD_QUEUE_PTR_WRITE [lsq]; 76 77 PORT_WRITE(out_INSERT_STORE_QUEUE_PTR_WRITE [i], STORE_QUEUE_PTR_WRITE [lsq]); 78 if (_param->_have_port_load_queue_ptr) 79 PORT_WRITE(out_INSERT_LOAD_QUEUE_PTR_WRITE [i], LOAD_QUEUE_PTR_WRITE [lsq]); 80 81 log_printf(TRACE,Load_Store_pointer_unit,FUNCTION," * sq_ptr_write : %d",STORE_QUEUE_PTR_WRITE [lsq]); 82 log_printf(TRACE,Load_Store_pointer_unit,FUNCTION," * lq_ptr_write : %d",LOAD_QUEUE_PTR_WRITE [lsq]); 54 83 55 84 // operation became of decod_stage. Also operation is != store_head_ok and store_head_ko 56 85 if (is_operation_memory_store(PORT_READ(in_INSERT_OPERATION [i]))) 57 86 { 87 log_printf(TRACE,Load_Store_pointer_unit,FUNCTION," * USE_STORE_QUEUE"); 88 58 89 internal_INSERT_OPERATION_USE [i] = OPERATION_USE_STORE_QUEUE; 59 90 60 ptr = reg_STORE_QUEUE_PTR_WRITE [lsq]; 91 ptr = STORE_QUEUE_PTR_WRITE [lsq]; 92 ack = not STORE_QUEUE_USE [lsq][ptr] and (static_cast<uint32_t>(STORE_QUEUE_NB_USE [lsq]+1) < _param->_size_store_queue[lsq]); 61 93 62 ack = not reg_STORE_QUEUE_USE [lsq][ptr] and (static_cast<uint32_t>(reg_STORE_QUEUE_NB_USE [lsq]+1) < _param->_size_store_queue[lsq]); 94 if (ack) 95 { 96 STORE_QUEUE_PTR_WRITE [lsq] = (ptr+1)%_param->_size_store_queue[lsq]; 97 STORE_QUEUE_NB_USE [lsq] ++; 98 STORE_QUEUE_USE [lsq][ptr] = true; 99 } 63 100 } 64 101 else 65 102 { 103 log_printf(TRACE,Load_Store_pointer_unit,FUNCTION," * USE_LOAD_QUEUE"); 104 66 105 internal_INSERT_OPERATION_USE [i] = OPERATION_USE_LOAD_QUEUE; 67 106 68 ptr = reg_LOAD_QUEUE_PTR_WRITE [lsq]; 107 ptr = LOAD_QUEUE_PTR_WRITE [lsq]; 108 ack = (not LOAD_QUEUE_USE [lsq][ptr]); 69 109 70 ack = (not reg_LOAD_QUEUE_USE [lsq][ptr]); 110 if (ack) 111 { 112 LOAD_QUEUE_PTR_WRITE [lsq] = (ptr+1)%_param->_size_load_queue[lsq]; 113 LOAD_QUEUE_USE [lsq][ptr] = true; 114 } 71 115 } 116 117 log_printf(TRACE,Load_Store_pointer_unit,FUNCTION," * ptr : %d",ptr ); 118 log_printf(TRACE,Load_Store_pointer_unit,FUNCTION," * ack : %d",ack ); 72 119 73 120 internal_INSERT_LSQ [i] = lsq; … … 85 132 internal_INSERT_ACK [i] = ack; 86 133 PORT_WRITE(out_INSERT_ACK [i], ack); 87 PORT_WRITE(out_INSERT_STORE_QUEUE_PTR_WRITE [i], store_queue_ptr_write);88 if (_param->_have_port_load_queue_ptr)89 PORT_WRITE(out_INSERT_LOAD_QUEUE_PTR_WRITE [i], load_queue_ptr_write );90 134 } 91 135 92 log_ printf(FUNC,Load_Store_pointer_unit,FUNCTION,"End");136 log_end(Load_Store_pointer_unit,FUNCTION); 93 137 }; 94 138 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/src/Load_Store_pointer_unit_genMealy_retire.cpp
r88 r110 24 24 log_printf(FUNC,Load_Store_pointer_unit,FUNCTION,"Begin"); 25 25 26 bool use_lsq [_param->_nb_load_store_queue];27 for (uint32_t i=0; i<_param->_nb_load_store_queue; i++)28 use_lsq [i] = false;26 // bool use_lsq [_param->_nb_load_store_queue]; 27 // for (uint32_t i=0; i<_param->_nb_load_store_queue; i++) 28 // use_lsq [i] = false; 29 29 30 30 for (uint32_t i=0; i<_param->_nb_inst_retire; i++) 31 31 { 32 Tcontrol_t ack = false;32 Tcontrol_t ack = true; // always accept 33 33 Tcontrol_t use_sq = PORT_READ(in_RETIRE_USE_STORE_QUEUE [i]); 34 34 Tcontrol_t use_lq = PORT_READ(in_RETIRE_USE_LOAD_QUEUE [i]); … … 41 41 42 42 // Test if a previous instruction use the same lsq 43 // Authorize once memory access by load store unit44 if (use_lsq [lsq] == false)43 // // Authorize once memory access by load store unit 44 // if (use_lsq [lsq] == false) 45 45 { 46 use_lsq [lsq] = true;47 ack = true;46 // use_lsq [lsq] = true; 47 // ack = true; 48 48 49 49 uint32_t ptr; … … 70 70 else 71 71 { 72 ack = true;72 // ack = true; 73 73 74 74 internal_RETIRE_OPERATION_USE [i] = OPERATION_USE_NONE; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/src/Load_Store_pointer_unit_transition.cpp
r81 r110 22 22 void Load_Store_pointer_unit::transition (void) 23 23 { 24 log_printf(FUNC,Load_Store_pointer_unit,FUNCTION,"Begin"); 24 log_begin(Load_Store_pointer_unit,FUNCTION); 25 log_function(Load_Store_pointer_unit,FUNCTION,_name.c_str()); 25 26 26 27 if (PORT_READ(in_NRESET) == 0) … … 47 48 if (PORT_READ(in_INSERT_VAL [i]) and internal_INSERT_ACK [i]) 48 49 { 49 // log_printf(TRACE,Load_Store_pointer_unit,FUNCTION,"INSERT [%d]",i);50 log_printf(TRACE,Load_Store_pointer_unit,FUNCTION," * INSERT [%d]",i); 50 51 51 52 switch (internal_INSERT_OPERATION_USE [i]) … … 53 54 case OPERATION_USE_STORE_QUEUE : 54 55 { 55 // log_printf(TRACE,Load_Store_pointer_unit,FUNCTION,"* use STORE_QUEUE");56 log_printf(TRACE,Load_Store_pointer_unit,FUNCTION," * use STORE_QUEUE"); 56 57 57 58 uint32_t lsq = internal_INSERT_LSQ [i]; 58 59 Tlsq_ptr_t ptr = internal_INSERT_PTR [i]; 59 60 60 // log_printf(TRACE,Load_Store_pointer_unit,FUNCTION,"* lsq : %d",lsq);61 // log_printf(TRACE,Load_Store_pointer_unit,FUNCTION,"* ptr : %d",ptr);61 log_printf(TRACE,Load_Store_pointer_unit,FUNCTION," * lsq : %d",lsq); 62 log_printf(TRACE,Load_Store_pointer_unit,FUNCTION," * ptr : %d",ptr); 62 63 63 64 reg_STORE_QUEUE_PTR_WRITE [lsq] = (ptr+1)%_param->_size_store_queue[lsq]; … … 69 70 case OPERATION_USE_LOAD_QUEUE : 70 71 { 71 // log_printf(TRACE,Load_Store_pointer_unit,FUNCTION,"* use LOAD_QUEUE");72 log_printf(TRACE,Load_Store_pointer_unit,FUNCTION," * use LOAD_QUEUE"); 72 73 73 74 uint32_t lsq = internal_INSERT_LSQ [i]; 74 75 Tlsq_ptr_t ptr = internal_INSERT_PTR [i]; 75 76 76 // log_printf(TRACE,Load_Store_pointer_unit,FUNCTION,"* lsq : %d",lsq);77 // log_printf(TRACE,Load_Store_pointer_unit,FUNCTION,"* ptr : %d",ptr);77 log_printf(TRACE,Load_Store_pointer_unit,FUNCTION," * lsq : %d",lsq); 78 log_printf(TRACE,Load_Store_pointer_unit,FUNCTION," * ptr : %d",ptr); 78 79 79 80 reg_LOAD_QUEUE_PTR_WRITE [lsq] = (ptr+1)%_param->_size_load_queue[lsq]; … … 95 96 if (PORT_READ(in_RETIRE_VAL [i]) and internal_RETIRE_ACK [i]) 96 97 { 97 // log_printf(TRACE,Load_Store_pointer_unit,FUNCTION,"RETIRE [%d]",i);98 log_printf(TRACE,Load_Store_pointer_unit,FUNCTION," * RETIRE [%d]",i); 98 99 99 100 switch (internal_RETIRE_OPERATION_USE [i]) … … 101 102 case OPERATION_USE_STORE_QUEUE : 102 103 { 103 // log_printf(TRACE,Load_Store_pointer_unit,FUNCTION,"* use STORE_QUEUE");104 log_printf(TRACE,Load_Store_pointer_unit,FUNCTION," * use STORE_QUEUE"); 104 105 105 106 uint32_t lsq = internal_RETIRE_LSQ [i]; 106 107 Tlsq_ptr_t ptr = internal_RETIRE_PTR [i]; 107 108 108 // log_printf(TRACE,Load_Store_pointer_unit,FUNCTION,"* lsq : %d",lsq);109 // log_printf(TRACE,Load_Store_pointer_unit,FUNCTION,"* ptr : %d",ptr);109 log_printf(TRACE,Load_Store_pointer_unit,FUNCTION," * lsq : %d",lsq); 110 log_printf(TRACE,Load_Store_pointer_unit,FUNCTION," * ptr : %d",ptr); 110 111 111 112 // reg_STORE_QUEUE_PTR_WRITE [lsq] = ((ptr==0)?_param->_size_store_queue[lsq]:ptr)-1; … … 117 118 case OPERATION_USE_LOAD_QUEUE : 118 119 { 119 // log_printf(TRACE,Load_Store_pointer_unit,FUNCTION,"* use LOAD_QUEUE");120 log_printf(TRACE,Load_Store_pointer_unit,FUNCTION," * use LOAD_QUEUE"); 120 121 121 122 uint32_t lsq = internal_RETIRE_LSQ [i]; 122 123 Tlsq_ptr_t ptr = internal_RETIRE_PTR [i]; 123 124 124 // log_printf(TRACE,Load_Store_pointer_unit,FUNCTION,"* lsq : %d",lsq);125 // log_printf(TRACE,Load_Store_pointer_unit,FUNCTION,"* ptr : %d",ptr);125 log_printf(TRACE,Load_Store_pointer_unit,FUNCTION," * lsq : %d",lsq); 126 log_printf(TRACE,Load_Store_pointer_unit,FUNCTION," * ptr : %d",ptr); 126 127 127 128 // reg_LOAD_QUEUE_PTR_WRITE [lsq] = ((ptr==0)?_param->_size_load_queue[lsq]:ptr)-1; … … 138 139 } 139 140 141 // =================================================================== 142 // =====[ OTHER ]===================================================== 143 // =================================================================== 140 144 141 // for (uint32_t i=0; i<_param->_nb_load_store_queue; i++) 142 // { 143 // std::string str; 144 145 // log_printf(TRACE,Load_Store_pointer_unit,FUNCTION,"LOAD_STORE_QUEUE [%d]",i); 146 147 // log_printf(TRACE,Load_Store_pointer_unit,FUNCTION," * STORE_QUEUE_PTR_WRITE : %d",reg_STORE_QUEUE_PTR_WRITE [i]); 148 // log_printf(TRACE,Load_Store_pointer_unit,FUNCTION," * STORE_QUEUE_NB_USE : %d",reg_STORE_QUEUE_NB_USE [i]); 149 150 // str = ""; 151 // for (uint32_t j=0; j<_param->_size_store_queue[i]; j++) 152 // str += toString(reg_STORE_QUEUE_USE [i][j]) + " "; 153 // log_printf(TRACE,Load_Store_pointer_unit,FUNCTION," * %s",str.c_str()); 154 155 // log_printf(TRACE,Load_Store_pointer_unit,FUNCTION," * LOAD_QUEUE_PTR_WRITE : %d",reg_LOAD_QUEUE_PTR_WRITE [i]); 156 157 // str = ""; 158 // for (uint32_t j=0; j<_param->_size_load_queue[i]; j++) 159 // str += toString(reg_LOAD_QUEUE_USE [i][j]) + " "; 160 // log_printf(TRACE,Load_Store_pointer_unit,FUNCTION," * %s",str.c_str()); 161 // } 145 #if (DEBUG >= DEBUG_TRACE) and (DEBUG_Commit_unit == true) 146 { 147 log_printf(TRACE,Load_Store_pointer_unit,FUNCTION," * Dump Load_Store_pointer Unit"); 148 149 for (uint32_t i=0; i<_param->_nb_load_store_queue; ++i) 150 { 151 log_printf(TRACE,Load_Store_pointer_unit,FUNCTION," * Load_Store_unit [%d]",i); 152 log_printf(TRACE,Load_Store_pointer_unit,FUNCTION," * reg_STORE_QUEUE_NB_USE : %d", reg_STORE_QUEUE_NB_USE [i]); 153 log_printf(TRACE,Load_Store_pointer_unit,FUNCTION," * reg_STORE_QUEUE_PTR_WRITE : %d", reg_STORE_QUEUE_PTR_WRITE[i]); 154 log_printf(TRACE,Load_Store_pointer_unit,FUNCTION," * reg_STORE_QUEUE_USE :"); 155 for (uint32_t j=0; j<_param->_size_store_queue [i]; ++j) 156 log_printf(TRACE,Load_Store_pointer_unit,FUNCTION," [%d] %d",j,reg_STORE_QUEUE_USE [i][j]); 157 log_printf(TRACE,Load_Store_pointer_unit,FUNCTION," * reg_LOAD_QUEUE_PTR_WRITE : %d", reg_LOAD_QUEUE_PTR_WRITE [i]); 158 log_printf(TRACE,Load_Store_pointer_unit,FUNCTION," * reg_LOAD_QUEUE_USE :"); 159 for (uint32_t j=0; j<_param->_size_load_queue [i]; ++j) 160 log_printf(TRACE,Load_Store_pointer_unit,FUNCTION," [%d] %d",j,reg_LOAD_QUEUE_USE [i][j]); 161 } 162 } 163 #endif 162 164 163 165 #if defined(STATISTICS) or defined(VHDL_TESTBENCH) … … 165 167 #endif 166 168 167 log_ printf(FUNC,Load_Store_pointer_unit,FUNCTION,"End");169 log_end(Load_Store_pointer_unit,FUNCTION); 168 170 }; 169 171 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/src/Parameters.cpp
r88 r110 22 22 Parameters::Parameters (uint32_t nb_front_end , 23 23 uint32_t * nb_context , 24 // 25 // 24 // uint32_t size_front_end_id , 25 // uint32_t size_context_id , 26 26 uint32_t nb_load_store_queue , 27 27 uint32_t * size_store_queue , 28 28 uint32_t * size_load_queue , 29 uint32_t * nb_inst_memory , 29 30 uint32_t ** link_load_store_unit_with_thread, 30 31 uint32_t nb_inst_insert , … … 40 41 _size_store_queue = size_store_queue ; 41 42 _size_load_queue = size_load_queue ; 43 _nb_inst_memory = nb_inst_memory ; 42 44 _link_load_store_unit_with_thread = link_load_store_unit_with_thread; 43 45 _nb_inst_insert = nb_inst_insert ; 44 46 _nb_inst_retire = nb_inst_retire ; 45 47 46 48 test(); 49 50 _max_size_store_queue = max<uint32_t>(_size_store_queue,_nb_load_store_queue); 51 _max_size_load_queue = max<uint32_t>(_size_load_queue ,_nb_load_store_queue); 47 52 48 53 if (is_toplevel) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/include/Free_List_unit.h
r109 r110 55 55 #ifdef STATISTICS 56 56 public : Stat * _stat; 57 private : counter_t * _stat_nb_inst_pop ; 58 private : counter_t * _stat_nb_inst_pop_gpr ; 59 private : counter_t * _stat_nb_inst_pop_spr ; 60 private : counter_t * _stat_nb_inst_push_gpr; 61 private : counter_t * _stat_nb_inst_push_spr; 62 private : counter_t ** _stat_bank_gpr_nb_elt ; //[nb_bank] 63 private : counter_t ** _stat_bank_spr_nb_elt ; //[nb_bank] 57 64 #endif 58 65 … … 146 153 147 154 #ifdef STATISTICS 148 public : void statistics_declaration (morpheo::behavioural::Parameters_Statistics * param_statistics); 155 public : void statistics_allocation (morpheo::behavioural::Parameters_Statistics * param_statistics); 156 public : void statistics_deallocation (void); 149 157 #endif 150 158 #if defined(STATISTICS) or defined(VHDL_TESTBENCH) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Free_List_unit.cpp
r88 r110 58 58 log_printf(INFO,Free_List_unit,FUNCTION,"Allocation of statistics"); 59 59 60 statistics_ declaration(param_statistics);60 statistics_allocation(param_statistics); 61 61 } 62 62 #endif … … 157 157 #ifdef STATISTICS 158 158 if (usage_is_set(_usage,USE_STATISTICS)) 159 { 160 log_printf(INFO,Free_List_unit,FUNCTION,"Generate Statistics file"); 161 162 delete _stat; 163 } 159 statistics_deallocation (); 160 164 161 #endif 165 162 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Free_List_unit_statistics_allocation.cpp
r108 r110 20 20 21 21 #undef FUNCTION 22 #define FUNCTION "Free_List_unit::statistics_ declaration"23 void Free_List_unit::statistics_ declaration (morpheo::behavioural::Parameters_Statistics * param_statistics)22 #define FUNCTION "Free_List_unit::statistics_allocation" 23 void Free_List_unit::statistics_allocation (morpheo::behavioural::Parameters_Statistics * param_statistics) 24 24 { 25 25 log_printf(FUNC,Free_List_unit,FUNCTION,"Begin"); … … 28 28 "Free_List_unit", 29 29 param_statistics); 30 31 std::string sum_bank_gpr_nb_elt = "0"; 32 _stat_bank_gpr_nb_elt = new counter_t * [_param->_nb_bank]; 30 33 34 for (uint32_t i=0; i<_param->_nb_bank; ++i) 35 { 36 std::string str = "bank_gpr_nb_elt_"+toString(i); 37 38 sum_bank_gpr_nb_elt = "+ "+str+" "+sum_bank_gpr_nb_elt; 39 40 _stat_bank_gpr_nb_elt [i] = _stat->create_variable(str); 41 42 _stat->create_expr_average_by_cycle("average_occupation_bank_gpr_"+toString(i), str, "", toString(_("Average free list occupation (bank %d)"),i)); 43 _stat->create_expr_percent ("percent_occupation_bank_gpr_"+toString(i) , "average_occupation_bank_gpr_"+toString(i), toString(_param->_bank_gpr_nb_slot), toString(_("Percent free list occupation (bank %d)"),i)); 44 } 45 46 _stat->create_expr_average_by_cycle("average_occupation_bank_gpr", sum_bank_gpr_nb_elt, "", _("Average free list occupation (bank all)")); 47 _stat->create_expr_percent ("percent_occupation_bank_gpr", "average_occupation_bank_gpr", toString(_param->_bank_gpr_nb_slot*_param->_nb_bank), _("Percent free list occupation (bank all)")); 48 49 std::string sum_bank_spr_nb_elt = "0"; 50 _stat_bank_spr_nb_elt = new counter_t * [_param->_nb_bank]; 51 52 for (uint32_t i=0; i<_param->_nb_bank; ++i) 53 { 54 std::string str = "bank_spr_nb_elt_"+toString(i); 55 56 sum_bank_spr_nb_elt = "+ "+str+" "+sum_bank_spr_nb_elt; 57 58 _stat_bank_spr_nb_elt [i] = _stat->create_variable(str); 59 60 _stat->create_expr_average_by_cycle("average_occupation_bank_spr_"+toString(i), str, "", toString(_("Average free list occupation (bank %d)"),i)); 61 _stat->create_expr_percent ("percent_occupation_bank_spr_"+toString(i) , "average_occupation_bank_spr_"+toString(i), toString(_param->_bank_spr_nb_slot), toString(_("Percent free list occupation (bank %d)"),i)); 62 } 63 64 _stat->create_expr_average_by_cycle("average_occupation_bank_spr", sum_bank_spr_nb_elt, "", _("Average free list occupation (bank all)")); 65 _stat->create_expr_percent ("percent_occupation_bank_spr", "average_occupation_bank_spr", toString(_param->_bank_spr_nb_slot*_param->_nb_bank), _("Percent free list occupation (bank all)")); 66 67 _stat_nb_inst_pop = _stat->create_variable("nb_inst_pop" ); 68 _stat_nb_inst_pop_gpr = _stat->create_variable("nb_inst_pop_gpr" ); 69 _stat_nb_inst_pop_spr = _stat->create_variable("nb_inst_pop_spr" ); 70 _stat_nb_inst_push_gpr = _stat->create_variable("nb_inst_push_gpr"); 71 _stat_nb_inst_push_spr = _stat->create_variable("nb_inst_push_spr"); 72 73 _stat->create_expr_average_by_cycle("average_use_interface_pop" , "nb_inst_pop" , "", _("Average instruction per cycle on pop interface")); 74 _stat->create_expr_average_by_cycle("average_use_interface_pop_gpr" , "nb_inst_pop_gpr" , "", _("Average instruction per cycle on pop interface for gpr")); 75 _stat->create_expr_average_by_cycle("average_use_interface_pop_spr" , "nb_inst_pop_spr" , "", _("Average instruction per cycle on pop interface for spr")); 76 _stat->create_expr_average_by_cycle("average_use_interface_push_gpr", "nb_inst_push_gpr", "", _("Average instruction per cycle on push_gpr interface")); 77 _stat->create_expr_average_by_cycle("average_use_interface_push_spr", "nb_inst_push_spr", "", _("Average instruction per cycle on push_spr interface")); 78 79 _stat->create_expr_percent ("percent_inst_pop_need_gpr" , "nb_inst_pop_gpr" , "nb_inst_pop", _("Percent of pop instruction that need gpr")); 80 _stat->create_expr_percent ("percent_inst_pop_need_spr" , "nb_inst_pop_spr" , "nb_inst_pop", _("Percent of pop instruction that need spr")); 81 31 82 log_printf(FUNC,Free_List_unit,FUNCTION,"End"); 32 83 }; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Free_List_unit_transition.cpp
r109 r110 50 50 log_printf(TRACE,Free_List_unit,FUNCTION," * POP [%d]",i); 51 51 52 #ifdef STATISTICS 53 (*_stat_nb_inst_pop) ++; 54 #endif 55 52 56 if (PORT_READ(in_POP_GPR_VAL [i])) 53 _gpr_list [internal_POP_GPR_BANK[i]].pop_front(); 57 { 58 #ifdef STATISTICS 59 (*_stat_nb_inst_pop_gpr) ++; 60 #endif 61 _gpr_list [internal_POP_GPR_BANK[i]].pop_front(); 62 } 54 63 55 64 if (PORT_READ(in_POP_SPR_VAL [i])) 56 _spr_list [internal_POP_SPR_BANK[i]].pop_front(); 65 { 66 #ifdef STATISTICS 67 (*_stat_nb_inst_pop_spr) ++; 68 #endif 69 _spr_list [internal_POP_SPR_BANK[i]].pop_front(); 70 } 57 71 } 58 72 … … 67 81 log_printf(TRACE,Free_List_unit,FUNCTION," * num_reg : %d",PORT_READ(in_PUSH_GPR_NUM_REG [i])); 68 82 83 #ifdef STATISTICS 84 (*_stat_nb_inst_push_gpr) ++; 85 #endif 86 69 87 _gpr_list [internal_PUSH_GPR_BANK[i]].push_back(PORT_READ(in_PUSH_GPR_NUM_REG [i])); 70 88 } … … 79 97 log_printf(TRACE,Free_List_unit,FUNCTION," * num_reg : %d",PORT_READ(in_PUSH_SPR_NUM_REG [i])); 80 98 99 #ifdef STATISTICS 100 (*_stat_nb_inst_push_spr) ++; 101 #endif 102 81 103 _spr_list [internal_PUSH_SPR_BANK[i]].push_back(PORT_READ(in_PUSH_SPR_NUM_REG [i])); 82 104 } 105 106 #ifdef STATISTICS 107 for (uint32_t i=0; i<_param->_nb_bank; ++i) 108 { 109 (*(_stat_bank_gpr_nb_elt [i])) += _gpr_list[i].size(); 110 (*(_stat_bank_spr_nb_elt [i])) += _spr_list[i].size(); 111 } 112 #endif 83 113 84 114 #if (DEBUG >= DEBUG_TRACE) and (DEBUG_Free_List_unit == true) … … 140 170 if (1) 141 171 for (uint32_t i=0; i<_param->_nb_bank; ++i) 142 {172 { 143 173 for (std::list<Tgeneral_address_t>::iterator it1=_gpr_list[i].begin(); 144 174 it1!=_gpr_list[i].end(); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/include/Register_translation_unit_Glue.h
r98 r110 52 52 #ifdef STATISTICS 53 53 public : Stat * _stat; 54 55 private : counter_t * _stat_nb_inst_issue_rename_select; 56 private : counter_t * _stat_nb_inst_issue_rename_select_req; 57 private : counter_t * _stat_nb_inst_issue_stall_by_commit ; 58 private : counter_t * _stat_nb_inst_issue_stall_by_rat_rename ; 59 private : counter_t * _stat_nb_inst_issue_stall_by_rat_insert ; 60 private : counter_t * _stat_nb_inst_issue_stall_by_free_list ; 61 private : counter_t * _stat_nb_inst_issue_stall_by_stat_list ; 54 62 #endif 55 63 … … 139 147 140 148 // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 149 #ifdef STATISTICS 150 private : Tcontrol_t * internal_INSERT_RENAME_ACK; //[nb_inst_insert] 151 #endif 152 141 153 #endif 142 154 … … 186 198 187 199 #ifdef STATISTICS 188 public : void statistics_declaration (morpheo::behavioural::Parameters_Statistics * param_statistics); 200 public : void statistics_allocation (morpheo::behavioural::Parameters_Statistics * param_statistics); 201 public : void statistics_deallocation (void); 189 202 #endif 190 203 #if defined(STATISTICS) or defined(VHDL_TESTBENCH) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/src/Register_translation_unit_Glue.cpp
r88 r110 58 58 log_printf(INFO,Register_translation_unit_Glue,FUNCTION,"Allocation of statistics"); 59 59 60 statistics_ declaration(param_statistics);60 statistics_allocation(param_statistics); 61 61 } 62 62 #endif … … 199 199 #ifdef STATISTICS 200 200 if (usage_is_set(_usage,USE_STATISTICS)) 201 { 202 log_printf(INFO,Register_translation_unit_Glue,FUNCTION,"Generate Statistics file"); 203 204 delete _stat; 205 } 201 statistics_deallocation (); 206 202 #endif 207 203 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/src/Register_translation_unit_Glue_allocation.cpp
r98 r110 136 136 } 137 137 138 #ifdef STATISTICS 139 ALLOC1(internal_INSERT_RENAME_ACK, Tcontrol_t,_param->_nb_inst_insert); 140 #endif 141 138 142 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 139 140 143 #ifdef POSITION 141 144 if (usage_is_set(_usage,USE_POSITION)) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/src/Register_translation_unit_Glue_deallocation.cpp
r98 r110 99 99 DELETE1_SIGNAL( in_RETIRE_STAT_LIST_ACK,_param->_nb_inst_retire,1); 100 100 101 #ifdef STATISTICS 102 DELETE1(internal_INSERT_RENAME_ACK, _param->_nb_inst_insert); 103 #endif 101 104 } 105 102 106 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 103 107 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/src/Register_translation_unit_Glue_genMealy_insert_valack.cpp
r88 r110 75 75 log_printf(TRACE,Register_translation_unit_Glue,FUNCTION," * stat_list_ack (r): %d",stat_list_ack ); 76 76 77 #ifdef STATISTICS 78 internal_INSERT_RENAME_ACK [i] = rename_ack; 79 #endif 77 80 78 81 PORT_WRITE(out_INSERT_RENAME_ACK [i], rename_ack ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/src/Register_translation_unit_Glue_genMealy_retire.cpp
r88 r110 32 32 Tcontrol_t stat_list_ack = PORT_READ(in_RETIRE_STAT_LIST_ACK [i]); 33 33 34 PORT_WRITE(out_RETIRE_ACK [i], rat_ack and stat_list_ack); 35 PORT_WRITE(out_RETIRE_RAT_VAL [i], val and stat_list_ack); 36 PORT_WRITE(out_RETIRE_STAT_LIST_VAL [i], val and rat_ack); 34 Tcontrol_t ack = (true 35 // and val 36 and rat_ack 37 and stat_list_ack 38 ); 39 Tcontrol_t rat_val = (true 40 and val 41 // and rat_ack 42 and stat_list_ack 43 ); 44 Tcontrol_t stat_list_val = (true 45 and val 46 and rat_ack 47 // and stat_list_ack 48 ); 49 50 PORT_WRITE(out_RETIRE_ACK [i], ack ); 51 PORT_WRITE(out_RETIRE_RAT_VAL [i], rat_val ); 52 PORT_WRITE(out_RETIRE_STAT_LIST_VAL [i], stat_list_val); 53 54 log_printf(TRACE,Register_translation_unit_Glue,FUNCTION," * inst_insert [%d]",i); 55 log_printf(TRACE,Register_translation_unit_Glue,FUNCTION," * val (r): %d",val ); 56 log_printf(TRACE,Register_translation_unit_Glue,FUNCTION," * ack (w): %d",ack ); 57 log_printf(TRACE,Register_translation_unit_Glue,FUNCTION," * rat_val (w): %d",rat_val ); 58 log_printf(TRACE,Register_translation_unit_Glue,FUNCTION," * rat_ack (r): %d",rat_ack ); 59 log_printf(TRACE,Register_translation_unit_Glue,FUNCTION," * stat_list_val (w): %d",stat_list_val ); 60 log_printf(TRACE,Register_translation_unit_Glue,FUNCTION," * stat_list_ack (r): %d",stat_list_ack ); 37 61 } 38 62 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/src/Register_translation_unit_Glue_statistics_allocation.cpp
r108 r110 20 20 21 21 #undef FUNCTION 22 #define FUNCTION "Register_translation_unit_Glue::statistics_ declaration"23 void Register_translation_unit_Glue::statistics_ declaration (morpheo::behavioural::Parameters_Statistics * param_statistics)22 #define FUNCTION "Register_translation_unit_Glue::statistics_allocation" 23 void Register_translation_unit_Glue::statistics_allocation (morpheo::behavioural::Parameters_Statistics * param_statistics) 24 24 { 25 25 log_printf(FUNC,Register_translation_unit_Glue,FUNCTION,"Begin"); … … 28 28 "Register_translation_unit_Glue", 29 29 param_statistics); 30 31 _stat_nb_inst_issue_rename_select = _stat->create_variable("nb_inst_issue_rename_select"); 32 _stat_nb_inst_issue_rename_select_req = _stat->create_variable("nb_inst_issue_rename_select_req"); 33 34 _stat_nb_inst_issue_stall_by_commit = _stat->create_variable("nb_inst_issue_stall_by_commit"); 35 _stat_nb_inst_issue_stall_by_rat_rename = _stat->create_variable("nb_inst_issue_stall_by_rat_rename"); 36 _stat_nb_inst_issue_stall_by_rat_insert = _stat->create_variable("nb_inst_issue_stall_by_rat_insert"); 37 _stat_nb_inst_issue_stall_by_free_list = _stat->create_variable("nb_inst_issue_stall_by_free_list"); 38 _stat_nb_inst_issue_stall_by_stat_list = _stat->create_variable("nb_inst_issue_stall_by_stat_list"); 39 40 // std::string nb_inst_issue_stall = "+ + + nb_inst_issue_stall_by_commit nb_inst_issue_stall_by_rat_rename + nb_inst_issue_stall_by_rat_insert nb_inst_issue_stall_by_free_list + nb_inst_issue_stall_by_stat_list nb_inst_issue_stall_by_rename_select"; 41 std::string nb_inst_issue_stall = "+ + + nb_inst_issue_stall_by_commit nb_inst_issue_stall_by_rat_rename + nb_inst_issue_stall_by_rat_insert nb_inst_issue_stall_by_free_list nb_inst_issue_stall_by_stat_list"; 42 43 _stat->create_expr_average_by_cycle("average_req_interface_insert", "nb_inst_issue_rename_select_req", "", _("Average instruction by cycle on issue interface (request)")); 44 _stat->create_expr_average_by_cycle("average_use_interface_insert", "nb_inst_issue_rename_select" , "", _("Average instruction by cycle on issue interface")); 45 46 // _stat->create_expr_percent ("percent_issue_stall_by_rename_select", "nb_inst_issue_stall_by_rename_select", nb_inst_issue_stall, _("Percent of instruction stalled by Rename_Select")); 47 _stat->create_expr_percent ("percent_issue_stall_by_commit" , "nb_inst_issue_stall_by_commit", nb_inst_issue_stall, _("Percent of instruction stalled by Commit_unit or Issue_queue or RegisterFile")); 48 _stat->create_expr_percent ("percent_issue_stall_by_rat_rename" , "nb_inst_issue_stall_by_rat_rename", nb_inst_issue_stall, _("Percent of instruction stalled by Rat_Rename")); 49 _stat->create_expr_percent ("percent_issue_stall_by_rat_insert" , "nb_inst_issue_stall_by_rat_insert", nb_inst_issue_stall, _("Percent of instruction stalled by Rat_Insert")); 50 _stat->create_expr_percent ("percent_issue_stall_by_free_list" , "nb_inst_issue_stall_by_free_list", nb_inst_issue_stall, _("Percent of instruction stalled by Free_List")); 51 _stat->create_expr_percent ("percent_issue_stall_by_stat_list" , "nb_inst_issue_stall_by_stat_list", nb_inst_issue_stall, _("Percent of instruction stalled by Stat_List")); 30 52 31 53 log_printf(FUNC,Register_translation_unit_Glue,FUNCTION,"End"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/src/Register_translation_unit_Glue_transition.cpp
r81 r110 26 26 log_printf(FUNC,Register_translation_unit_Glue,FUNCTION,"Begin"); 27 27 28 #ifdef STATISTICS 29 if (usage_is_set(_usage,USE_STATISTICS)) 30 { 31 for (uint32_t i=0; i<_param->_nb_inst_insert; ++i) 32 // Test request 33 if (PORT_READ(in_INSERT_RENAME_VAL [i])) 34 { 35 (* _stat_nb_inst_issue_rename_select_req) ++; 36 37 if (internal_INSERT_RENAME_ACK [i]) 38 (* _stat_nb_inst_issue_rename_select)++; 39 if (PORT_READ(in_INSERT_INSERT_ACK [i]) == 0) 40 (*_stat_nb_inst_issue_stall_by_commit ) ++; 41 if (PORT_READ(in_INSERT_RAT_RENAME_ACK [i]) == 0) 42 (*_stat_nb_inst_issue_stall_by_rat_rename) ++; 43 if (PORT_READ(in_INSERT_RAT_INSERT_ACK [i]) == 0) 44 (*_stat_nb_inst_issue_stall_by_rat_insert) ++; 45 if (PORT_READ(in_INSERT_FREE_LIST_ACK [i]) == 0) 46 (*_stat_nb_inst_issue_stall_by_free_list ) ++; 47 if (PORT_READ(in_INSERT_STAT_LIST_ACK [i]) == 0) 48 (*_stat_nb_inst_issue_stall_by_stat_list ) ++; 49 } 50 } 51 #endif 52 28 53 #if defined(STATISTICS) or defined(VHDL_TESTBENCH) 29 54 end_cycle (); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/src/Rename_select_genMealy.cpp
r108 r110 43 43 for (uint32_t i=0; i<_param->_nb_inst_rename; i++) 44 44 { 45 log_printf(TRACE,Rename_select,FUNCTION," * inst_rename[%d]",i);45 log_printf(TRACE,Rename_select,FUNCTION," * RENAME_OUT [%d]",i); 46 46 47 47 // Scan all instruction until find … … 65 65 log_printf(TRACE,Rename_select,FUNCTION," * rename_out_ack : %d",PORT_READ(in_RENAME_OUT_ACK[i])); 66 66 67 Tcontext_t 68 Tcontext_t 67 Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_RENAME_IN_FRONT_END_ID [x][y]):0; 68 Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_RENAME_IN_CONTEXT_ID [x][y]):0; 69 69 70 Tcontrol_t no_execute = (PORT_READ(in_RENAME_IN_NO_EXECUTE [x][y])); 71 72 Tcontrol_t read_ra = (PORT_READ(in_RENAME_IN_READ_RA [x][y])); 73 Tcontrol_t read_rb = (PORT_READ(in_RENAME_IN_READ_RB [x][y])); 74 Tcontrol_t read_rc = (PORT_READ(in_RENAME_IN_READ_RC [x][y])); 75 Tcontrol_t write_rd = (PORT_READ(in_RENAME_IN_WRITE_RD [x][y])); 76 Tcontrol_t write_re = (PORT_READ(in_RENAME_IN_WRITE_RE [x][y])); 70 Tcontrol_t no_execute = (PORT_READ(in_RENAME_IN_NO_EXECUTE [x][y])); 71 Tcontrol_t read_ra = (PORT_READ(in_RENAME_IN_READ_RA [x][y])); 72 Tcontrol_t read_rb = (PORT_READ(in_RENAME_IN_READ_RB [x][y])); 73 Tcontrol_t read_rc = (PORT_READ(in_RENAME_IN_READ_RC [x][y])); 74 Tcontrol_t write_rd = (PORT_READ(in_RENAME_IN_WRITE_RD [x][y])); 75 Tcontrol_t write_re = (PORT_READ(in_RENAME_IN_WRITE_RE [x][y])); 77 76 78 77 // Attention, j'ai enlevé event_state de la liste de sensibilité -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Rename_unit_Glue_genMealy_insert_valack.cpp
r88 r110 25 25 log_function(Rename_unit_Glue,FUNCTION,_name.c_str()); 26 26 27 // // Transaction must be in-order 27 // // Transaction must be in-order - made in rename_select 28 28 // Tcontrol_t previous_transaction = true; 29 29 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Rename_unit_Glue_genMealy_retire_valack.cpp
r88 r110 25 25 log_function(Rename_unit_Glue,FUNCTION,_name.c_str()); 26 26 27 // Transaction must be in-order 28 Tcontrol_t previous_transaction = true;27 // Transaction must be in-order - made in commit_unit 28 // Tcontrol_t previous_transaction = true; 29 29 30 30 for (uint32_t i=0; i<_param->_nb_inst_retire; i++) … … 34 34 Tcontrol_t REGISTER_TRANSLATION_ACK = PORT_READ(in_RETIRE_REGISTER_TRANSLATION_ACK [i]); 35 35 36 Tcontrol_t ACK = ( previous_transaction and36 Tcontrol_t ACK = (// previous_transaction and 37 37 LOAD_STORE_QUEUE_POINTER_ACK and 38 38 REGISTER_TRANSLATION_ACK ); 39 Tcontrol_t LOAD_STORE_QUEUE_POINTER_VAL = ( previous_transaction and39 Tcontrol_t LOAD_STORE_QUEUE_POINTER_VAL = (// previous_transaction and 40 40 VAL and 41 41 REGISTER_TRANSLATION_ACK ); 42 Tcontrol_t REGISTER_TRANSLATION_VAL = ( previous_transaction and42 Tcontrol_t REGISTER_TRANSLATION_VAL = (// previous_transaction and 43 43 VAL and 44 44 LOAD_STORE_QUEUE_POINTER_ACK ); … … 48 48 PORT_WRITE(out_RETIRE_REGISTER_TRANSLATION_VAL [i], REGISTER_TRANSLATION_VAL ); 49 49 50 previous_transaction = VAL and ACK; 50 // previous_transaction = VAL and ACK; 51 52 log_printf(TRACE,Rename_unit_Glue,FUNCTION," * retire [%d]",i); 53 log_printf(TRACE,Rename_unit_Glue,FUNCTION," * val (commit_unit) (r) : %d",VAL ); 54 log_printf(TRACE,Rename_unit_Glue,FUNCTION," * ack (commit_unit) (w) : %d",ACK ); 55 log_printf(TRACE,Rename_unit_Glue,FUNCTION," * register_translation_val (w) : %d",REGISTER_TRANSLATION_VAL ); 56 log_printf(TRACE,Rename_unit_Glue,FUNCTION," * register_translation_ack (r) : %d",REGISTER_TRANSLATION_ACK ); 57 log_printf(TRACE,Rename_unit_Glue,FUNCTION," * load_store_queue_pointer_val (w) : %d",LOAD_STORE_QUEUE_POINTER_VAL); 58 log_printf(TRACE,Rename_unit_Glue,FUNCTION," * load_store_queue_pointer_ack (r) : %d",LOAD_STORE_QUEUE_POINTER_ACK); 51 59 } 52 60 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/config-min.cfg
r88 r110 8 8 2 2 +1 # size_store_queue [0] [nb_load_store_queue] 9 9 1 1 +1 # size_load_queue [0] [nb_load_store_queue] 10 1 1 +1 # nb_inst_memory [0] [nb_load_store_queue] 10 11 0 0 +1 # link_load_store_unit_with_thread [0][0] [nb_front_end][nb_context] 11 12 1 1 +1 # rename_select_priority -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/config-thread_1a.cfg
r88 r110 8 8 8 8 +1 # size_store_queue [0] [nb_load_store_queue] 9 9 8 8 +1 # size_load_queue [0] [nb_load_store_queue] 10 8 8 +1 # nb_inst_memory [0] [nb_load_store_queue] 10 11 0 0 +1 # link_load_store_unit_with_thread [0][0] [nb_front_end][nb_context] 11 12 1 1 +1 # rename_select_priority -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/config-thread_4a.cfg
r88 r110 8 8 8 8 +1 # size_store_queue [0] [nb_load_store_queue] 9 9 8 8 +1 # size_load_queue [0] [nb_load_store_queue] 10 4 4 +1 # nb_inst_memory [0] [nb_load_store_queue] 10 11 0 0 +1 # link_load_store_unit_with_thread [0][0] [nb_front_end][nb_context] 11 12 0 0 +1 # link_load_store_unit_with_thread [0][1] [nb_front_end][nb_context] -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/config-thread_4b.cfg
r88 r110 10 10 8 8 +1 # size_load_queue [0] [nb_load_store_queue] 11 11 4 4 +1 # size_load_queue [1] [nb_load_store_queue] 12 4 4 +1 # nb_inst_memory [0] [nb_load_store_queue] 13 2 2 +1 # nb_inst_memory [1] [nb_load_store_queue] 12 14 0 0 +1 # link_load_store_unit_with_thread [0][0] [nb_front_end][nb_context] 13 15 1 1 +1 # link_load_store_unit_with_thread [0][1] [nb_front_end][nb_context] -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/src/main.cpp
r88 r110 22 22 err (_(" * size_store_queue [nb_load_store_queue] (uint32_t )\n")); 23 23 err (_(" * size_load_queue [nb_load_store_queue] (uint32_t )\n")); 24 err (_(" * nb_inst_memory [nb_load_store_queue] (uint32_t )\n")); 24 25 err (_(" * link_load_store_unit_with_thread [nb_front_end][nb_context] (uint32_t )\n")); 25 26 err (_(" * rename_select_priority (Tpriority_t )\n")); … … 71 72 uint32_t _nb_load_store_queue = fromString<uint32_t >(argv[x++]); 72 73 73 if (argc != static_cast<int>(2+NB_PARAMS+2*_nb_front_end+ 2*_nb_load_store_queue+_sum_nb_context))74 if (argc != static_cast<int>(2+NB_PARAMS+2*_nb_front_end+3*_nb_load_store_queue+_sum_nb_context)) 74 75 usage (argc, argv); 75 76 76 77 uint32_t * _size_store_queue = new uint32_t [_nb_load_store_queue]; 77 78 uint32_t * _size_load_queue = new uint32_t [_nb_load_store_queue]; 79 uint32_t * _nb_inst_memory = new uint32_t [_nb_load_store_queue]; 78 80 79 81 for (uint32_t i=0; i<_nb_load_store_queue; i++) … … 81 83 for (uint32_t i=0; i<_nb_load_store_queue; i++) 82 84 _size_load_queue [i] = fromString<uint32_t>(argv[x++]); 85 for (uint32_t i=0; i<_nb_load_store_queue; i++) 86 _nb_inst_memory [i] = fromString<uint32_t>(argv[x++]); 83 87 84 88 uint32_t ** _link_load_store_unit_with_thread = new uint32_t * [_nb_front_end]; … … 113 117 _size_store_queue , 114 118 _size_load_queue , 119 _nb_inst_memory , 115 120 _link_load_store_unit_with_thread , 116 121 _rename_select_priority , … … 157 162 delete [] _size_store_queue; 158 163 delete [] _size_load_queue ; 164 delete [] _nb_inst_memory ; 159 165 delete [] _nb_context ; 160 166 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/include/Parameters.h
r88 r110 36 36 public : uint32_t * _size_store_queue ;//[nb_load_store_queue] 37 37 public : uint32_t * _size_load_queue ;//[nb_load_store_queue] 38 public : uint32_t * _nb_inst_memory ;//[nb_load_store_queue] 38 39 public : uint32_t ** _link_load_store_unit_with_thread ;//[nb_front_end][nb_context] 39 40 public : Tpriority_t _rename_select_priority ; … … 75 76 uint32_t * size_store_queue , 76 77 uint32_t * size_load_queue , 78 uint32_t * nb_inst_memory , 77 79 uint32_t ** link_load_store_unit_with_thread , 78 80 Tpriority_t rename_select_priority , -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Parameters.cpp
r97 r110 27 27 uint32_t * size_store_queue , 28 28 uint32_t * size_load_queue , 29 uint32_t * nb_inst_memory , 29 30 uint32_t ** link_load_store_unit_with_thread , 30 31 Tpriority_t rename_select_priority , … … 50 51 _size_store_queue = size_store_queue ; 51 52 _size_load_queue = size_load_queue ; 53 _nb_inst_memory = nb_inst_memory ; 52 54 _link_load_store_unit_with_thread = link_load_store_unit_with_thread ; 53 55 _rename_select_priority = rename_select_priority ; … … 101 103 _size_store_queue , 102 104 _size_load_queue , 105 _nb_inst_memory , 103 106 _link_load_store_unit_with_thread, 104 107 _nb_inst_insert , -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/configuration.cfg
r108 r110 54 54 2 2 +1 # size_store_queue [0][0] [nb_rename_unit][nb_load_store_queue] 55 55 1 1 +1 # size_load_queue [0][0] [nb_rename_unit][nb_load_store_queue] 56 1 1 +1 # nb_inst_memory [0][0] [nb_rename_unit][nb_load_store_queue] 56 57 0 0 +1 # link_load_store_unit_with_thread [0][0] [nb_front_end][nb_context] -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/src/main.cpp
r108 r110 7 7 8 8 #include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/include/test.h" 9 #include "Behavioural/include/Allocation.h" 9 10 10 11 #define NB_PARAMS 23 … … 69 70 err (_(" * size_store_queue [nb_rename_unit][nb_load_store_queue] (uint32_t )\n")); 70 71 err (_(" * size_load_queue [nb_rename_unit][nb_load_store_queue] (uint32_t )\n")); 72 err (_(" * nb_inst_memory [nb_rename_unit][nb_load_store_queue] (uint32_t )\n")); 71 73 err (_(" * link_load_store_unit_with_thread [nb_front_end][nb_context] (uint32_t )\n")); 72 74 … … 215 217 } 216 218 217 if (argc != static_cast<int>(2+NB_PARAMS+3*_nb_front_end+2*_sum_nb_context+11*_nb_rename_unit+_nb_execute_loop+_nb_rename_unit*_nb_inst_issue+12*_nb_inst_issue+ 2*_sum_nb_load_store_queue))219 if (argc != static_cast<int>(2+NB_PARAMS+3*_nb_front_end+2*_sum_nb_context+11*_nb_rename_unit+_nb_execute_loop+_nb_rename_unit*_nb_inst_issue+12*_nb_inst_issue+3*_sum_nb_load_store_queue)) 218 220 usage (argc, argv); 219 221 … … 233 235 for (uint32_t j=0; j<_nb_load_store_queue[i]; j++) 234 236 _size_load_queue [i][j] = fromString<uint32_t>(argv[x++]); 237 } 238 239 uint32_t ** _nb_inst_memory = new uint32_t * [_nb_rename_unit]; 240 for (uint32_t i=0; i<_nb_rename_unit; i++) 241 { 242 _nb_inst_memory [i] = new uint32_t [_nb_load_store_queue[i]]; 243 for (uint32_t j=0; j<_nb_load_store_queue[i]; j++) 244 _nb_inst_memory [i][j] = fromString<uint32_t>(argv[x++]); 235 245 } 236 246 … … 258 268 } 259 269 } 270 271 uint32_t _nb_thread ; 272 uint32_t ** _translate_num_context_to_num_thread; //[nb_front_end][nb_context] 273 274 ALLOC2(_translate_num_context_to_num_thread,uint32_t,_nb_front_end,_nb_context[it1]); 275 276 _nb_thread = 0; 277 for (uint32_t i=0; i<_nb_front_end; i++) 278 for (uint32_t j=0; j<_nb_context [i]; j++) 279 _translate_num_context_to_num_thread [i][j] = _nb_thread ++; 260 280 261 281 int _return = EXIT_SUCCESS; … … 307 327 _size_store_queue , 308 328 _size_load_queue , 329 _nb_inst_memory , 309 330 _link_load_store_unit_with_thread , 310 331 _implement_group , 332 _nb_thread , 333 _translate_num_context_to_num_thread, 311 334 true //is_toplevel 312 335 ); … … 337 360 } 338 361 362 DELETE2(_translate_num_context_to_num_thread,_nb_front_end,_nb_context[it1]); 363 339 364 for (uint32_t i=0; i<_nb_front_end; i++) 340 365 { … … 348 373 delete [] _link_load_store_unit_with_thread [i]; 349 374 delete [] _link_load_store_unit_with_thread; 375 376 for (uint32_t i=0; i<_nb_rename_unit; i++) 377 delete [] _nb_inst_memory [i]; 378 delete [] _nb_inst_memory ; 350 379 351 380 for (uint32_t i=0; i<_nb_rename_unit; i++) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/src/test.cpp
r108 r110 9 9 #include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/include/test.h" 10 10 #include "Behavioural/include/Allocation.h" 11 #include "Behavioural/include/Simulation.h" 11 12 12 13 void test (string name, … … 18 19 morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,CYCLE_MAX); 19 20 #endif 21 22 simulation_init(0,0); 23 24 debug_idle_cycle = CYCLE_MAX; 20 25 21 26 Tusage_t _usage = USE_ALL; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/include/Parameters.h
r108 r110 78 78 public : uint32_t ** _size_store_queue ;//[nb_rename_unit][nb_load_store_queue] 79 79 public : uint32_t ** _size_load_queue ;//[nb_rename_unit][nb_load_store_queue] 80 public : uint32_t ** _nb_inst_memory ;//[nb_rename_unit][nb_load_store_queue] 80 81 public : uint32_t ** _link_load_store_unit_with_thread ;//[nb_front_end][nb_context] 81 82 // SPR 82 83 public : bool *** _implement_group ;//[nb_front_end][nb_context][NB_GROUP] 84 // Others 85 public : uint32_t _nb_thread ; 86 public : uint32_t ** _translate_num_context_to_num_thread; //[nb_front_end][nb_context] 87 83 88 84 89 public : std::vector<uint32_t>*_link_front_end_with_rename_unit ;//[nb_rename_unit] … … 168 173 uint32_t ** size_store_queue ,//[nb_rename_unit][nb_load_store_queue] 169 174 uint32_t ** size_load_queue ,//[nb_rename_unit][nb_load_store_queue] 175 uint32_t ** nb_inst_memory ,//[nb_rename_unit][nb_load_store_queue] 170 176 uint32_t ** link_load_store_unit_with_thread ,//[nb_front_end][nb_context] 171 177 // SPR 172 178 bool *** implement_group ,//[nb_front_end][nb_context][NB_GROUP] 173 179 // Others 180 uint32_t nb_thread , 181 uint32_t ** translate_num_context_to_num_thread, //[nb_front_end][nb_context] 174 182 bool is_toplevel=false 175 183 ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/Parameters.cpp
r108 r110 65 65 uint32_t ** size_store_queue ,//[nb_rename_unit][nb_load_store_queue] 66 66 uint32_t ** size_load_queue ,//[nb_rename_unit][nb_load_store_queue] 67 uint32_t ** nb_inst_memory ,//[nb_rename_unit][nb_load_store_queue] 67 68 uint32_t ** link_load_store_unit_with_thread ,//[nb_front_end][nb_context] 68 69 // SPR 69 70 bool *** implement_group ,//[nb_front_end][nb_context][NB_GROUP] 71 // Others 72 uint32_t nb_thread , 73 uint32_t ** translate_num_context_to_num_thread, //[nb_front_end][nb_context] 70 74 71 75 bool is_toplevel … … 116 120 _size_store_queue = size_store_queue ; 117 121 _size_load_queue = size_load_queue ; 122 _nb_inst_memory = nb_inst_memory ; 118 123 _link_load_store_unit_with_thread = link_load_store_unit_with_thread ; 119 124 _implement_group = implement_group ; 125 126 _nb_thread = nb_thread ; 127 _translate_num_context_to_num_thread = translate_num_context_to_num_thread; 120 128 121 129 test(); … … 217 225 _size_store_queue [i], 218 226 _size_load_queue [i], 227 _nb_inst_memory [i], 219 228 _rename_unit_link_load_store_unit_with_thread [i], 220 229 _rename_select_priority [i], … … 251 260 _commit_priority , 252 261 _commit_load_balancing , 253 _nb_rename_unit_select 262 _nb_rename_unit_select , 263 _nb_thread , 264 _translate_num_context_to_num_thread 254 265 ); 255 266 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/SelfTest/src/test.cpp
r88 r110 9 9 #include "Behavioural/Core/SelfTest/include/test.h" 10 10 #include "Behavioural/include/Allocation.h" 11 #include "Behavioural/include/Simulation.h" 11 12 12 13 void test (string name, … … 18 19 morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,CYCLE_MAX); 19 20 #endif 21 22 simulation_init(0,0); 23 24 debug_idle_cycle = CYCLE_MAX; 20 25 21 26 Tusage_t _usage = USE_ALL; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/include/Parameters.h
r97 r110 248 248 public : uint32_t *** _ooo_engine_size_store_queue ;//[nb_ooo_engine][nb_rename_unit][ooo_engine_nb_load_store_unit] 249 249 public : uint32_t *** _ooo_engine_size_load_queue ;//[nb_ooo_engine][nb_rename_unit][ooo_engine_nb_load_store_unit] 250 public : uint32_t *** _ooo_engine_nb_inst_memory ;//[nb_ooo_engine][nb_rename_unit][ooo_engine_nb_load_store_unit] 250 251 public : uint32_t *** _ooo_engine_link_load_store_unit_with_context ;//[nb_ooo_engine][ooo_engine_nb_front_end][nb_context] 251 252 public : bool **** _ooo_engine_implement_group ;//[nb_ooo_engine][ooo_engine_nb_front_end][nb_context][NB_GROUP] 253 public : uint32_t *** _ooo_engine_translate_num_context_to_num_thread;//[nb_ooo_engine][ooo_engine_nb_front_end][nb_context] 252 254 253 255 // translate for execute_loop -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Parameters.cpp
r109 r110 910 910 } 911 911 912 ALLOC3(_ooo_engine_translate_num_context_to_num_thread,uint32_t ,_nb_ooo_engine,_ooo_engine_nb_front_end[it1],_ooo_engine_nb_context[it1][it2]); 913 for (uint32_t i=0; i<_nb_ooo_engine; ++i) 914 for (uint32_t j=0; j<_ooo_engine_nb_front_end[i]; ++j) 915 { 916 uint32_t num_front_end = _translate_ooo_engine_num_front_end [i][j]; 917 for (uint32_t k=0; k<_ooo_engine_nb_context[i][j]; ++k) 918 { 919 uint32_t num_thread = _link_thread_with_context[num_front_end][k]; 920 921 _ooo_engine_translate_num_context_to_num_thread [i][j][k] = num_thread; 922 } 923 } 924 912 925 ALLOC2(_ooo_engine_nb_inst_execute ,uint32_t ,_nb_ooo_engine,_ooo_engine_nb_execute_loop[it1]); 913 926 … … 1146 1159 ALLOC3(_ooo_engine_size_store_queue ,uint32_t ,_nb_ooo_engine,_nb_rename_unit[it1],_ooo_engine_nb_load_store_unit[it1][it2]); 1147 1160 ALLOC3(_ooo_engine_size_load_queue ,uint32_t ,_nb_ooo_engine,_nb_rename_unit[it1],_ooo_engine_nb_load_store_unit[it1][it2]); 1161 ALLOC3(_ooo_engine_nb_inst_memory ,uint32_t ,_nb_ooo_engine,_nb_rename_unit[it1],_ooo_engine_nb_load_store_unit[it1][it2]); 1148 1162 ALLOC3(_ooo_engine_link_load_store_unit_with_context ,uint32_t ,_nb_ooo_engine,_ooo_engine_nb_front_end[it1],_ooo_engine_nb_context[it1][it2]); 1149 1163 … … 1157 1171 _ooo_engine_size_store_queue [i][j][k] = _size_store_queue[num_load_store_unit]; 1158 1172 _ooo_engine_size_load_queue [i][j][k] = _size_load_queue [num_load_store_unit]; 1173 _ooo_engine_nb_inst_memory [i][j][k] = _nb_inst_memory [num_load_store_unit]; 1159 1174 } 1160 1175 … … 1894 1909 _ooo_engine_size_store_queue [i], 1895 1910 _ooo_engine_size_load_queue [i], 1911 _ooo_engine_nb_inst_memory [i], 1896 1912 _ooo_engine_link_load_store_unit_with_context [i], 1897 _ooo_engine_implement_group [i] 1913 _ooo_engine_implement_group [i], 1914 _nb_thread , 1915 _ooo_engine_translate_num_context_to_num_thread[i] 1898 1916 ); 1899 1917 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Simulation.h
r88 r110 19 19 namespace behavioural { 20 20 21 extern double _simulation_nb_cycle; 22 // extern double _simulation_nb_instruction; 23 // extern std::vector<double> * _simulation_nb_instruction_commited; 24 25 // Warning, now no mutek to protect this variable 26 27 // class Simulation 28 // { 29 // private : const uint32_t _num_context; 30 31 // public : Simulation (void); 32 // public : ~Simulation (void); 33 // public : void end_cycle (double nb_instruction_commited); 34 // }; 21 extern double _simulation_nb_cycle; 22 extern double _simulation_nb_instruction; 23 extern std::vector<double> _simulation_nb_instruction_commited; 35 24 36 25 bool simulation_test_end (void); 37 26 void simulation_init (double nb_cycle, 38 27 double nb_instruction); 39 40 28 }; // end namespace behavioural 41 29 }; // end namespace morpheo -
trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Version.h
r109 r110 10 10 #define MORPHEO_MAJOR_VERSION "0" 11 11 #define MORPHEO_MINOR_VERSION "2" 12 #define MORPHEO_REVISION "1 09"12 #define MORPHEO_REVISION "110" 13 13 #define MORPHEO_CODENAME "Castor" 14 14 15 #define MORPHEO_DATE_DAY "1 6"15 #define MORPHEO_DATE_DAY "19" 16 16 #define MORPHEO_DATE_MONTH "02" 17 17 #define MORPHEO_DATE_YEAR "2009" -
trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Simulation.cpp
r88 r110 13 13 namespace behavioural { 14 14 15 static bool simulation_initialized; 16 // static uint32_t _simulation_num_context_next; 17 double _simulation_nb_cycle; 18 // double _simulation_nb_instruction; 19 // std::vector<double> * _simulation_nb_instruction_commited; 20 21 // Simulation::Simulation (void): 22 // _num_context (_simulation_num_context_next) 23 // { 24 // // Test if is first context create 25 // if (_simulation_num_context_next == 0) 26 // _simulation_nb_instruction_commited = new std::vector<double>; 27 28 // _simulation_num_context_next ++; 29 // } 30 31 // Simulation::~Simulation (void) 32 // { 33 // _simulation_num_context_next --; 34 35 // // Test if is last context destroy 36 // if (_simulation_num_context_next == 0) 37 // delete _simulation_nb_instruction_commited; 38 // } 15 static bool simulation_initialized; 16 double _simulation_nb_cycle; 17 double _simulation_nb_instruction; 18 std::vector<double> _simulation_nb_instruction_commited; 39 19 40 20 void simulation_init (double nb_cycle, … … 43 23 if (not simulation_initialized) 44 24 { 45 // _simulation_num_context_next = 0;46 _simulation_nb_ cycle = nb_cycle;47 // _simulation_nb_instruction = nb_instruction;25 _simulation_nb_cycle = nb_cycle; 26 _simulation_nb_instruction = nb_instruction; 27 // _simulation_nb_instruction_commited = new std::vector<double>; 48 28 49 if (nb_instruction != 0)50 throw ERRORMORPHEO("simulation_init",_("Stop Condition on number instruction is not yet implemented"));51 52 29 simulation_initialized = true; 53 30 } … … 59 36 _simulation_nb_cycle = nb_cycle; 60 37 61 //if (_simulation_nb_instruction < nb_instruction)62 //_simulation_nb_instruction = nb_instruction;38 if (_simulation_nb_instruction < nb_instruction) 39 _simulation_nb_instruction = nb_instruction; 63 40 } 64 41 } -
trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Simulation_test_end.cpp
r88 r110 17 17 18 18 // Test if a stop condition is activate 19 if ((_simulation_nb_cycle == 0) //and20 //(_simulation_nb_instruction == 0)19 if ((_simulation_nb_cycle == 0) and 20 (_simulation_nb_instruction == 0) 21 21 ) 22 22 return false; 23 23 24 bool end_cycle = true;25 // bool end_inst = true;24 bool end_cycle; 25 bool end_inst ; 26 26 27 27 if (_simulation_nb_cycle != 0) 28 28 end_cycle = (_simulation_nb_cycle <= sc_simulation_time()); 29 else 30 end_cycle = true; 29 31 30 // if (_simulation_nb_instruction != 0) 31 // { 32 // std::vector<double>::iterator it=_simulation_nb_instruction_commited->begin(); 32 if (_simulation_nb_instruction != 0) 33 { 34 end_inst = true; 35 36 std::vector<double>::iterator it=_simulation_nb_instruction_commited.begin(); 33 37 34 // // Scan all context and test if all can finish 35 // while (end_inst and it!=_simulation_nb_instruction_commited->end()) 36 // { 37 // end_inst &= (*it <= _simulation_nb_instruction); 38 // it ++; 39 // } 40 // } 38 // Scan all context and test if all can finish 39 while (end_inst and it!=_simulation_nb_instruction_commited.end()) 40 { 41 end_inst &= (_simulation_nb_instruction <= *it); 42 it ++; 43 } 44 } 45 else 46 end_inst = true; 41 47 42 return end_cycle // and end_inst 43 ; 48 return end_cycle and end_inst; 44 49 } 45 50 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Stat_alloc_operand.cpp
r81 r110 4 4 namespace morpheo { 5 5 namespace behavioural { 6 7 #undef FUNCTION 8 #define FUNCTION "Stat::alloc_operand" 6 9 counter_t * Stat::alloc_operand (counter_type_t type, std::string varname, std::string unit, std::string description) 7 10 { 8 11 if (not is_valid_var (varname)) 9 throw(ERRORMORPHEO( "Stat::alloc_operand",_("Variable is not valid.")));12 throw(ERRORMORPHEO(FUNCTION,toString(_("<%s> : Variable \"%s\" is not valid."),_name_instance.c_str(),varname.c_str()))); 10 13 11 14 counter_t * counter = new counter_t; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Stat_create_expr.cpp
r85 r110 5 5 namespace behavioural { 6 6 7 #undef FUNCTION 8 #define FUNCTION "Stat::create_expr" 7 9 void Stat::create_expr (std::string varname, 8 10 std::string expr, … … 10 12 { 11 13 if (is_valid_var (varname)) 12 throw(ERRORMORPHEO( "Stat::create_expr",_("Variable is not valid.")));14 throw(ERRORMORPHEO(FUNCTION,toString(_("<%s> Variable \"%s\" is not valid."),_name_instance.c_str(),varname.c_str()))); 13 15 14 16 expr_t expression; -
trunk/IPs/systemC/processor/Morpheo/Common/include/Debug.h
r109 r110 50 50 extern double debug_cycle_start; 51 51 extern double debug_cycle_stop ; 52 extern double debug_cycle_idle; 52 extern double debug_idle_cycle; 53 extern uint32_t debug_idle_time; 53 54 54 55 void debug_init (void); … … 56 57 double cycle_start, 57 58 double cycle_stop , 58 double cycle_idle); 59 double idle_cycle , 60 uint32_t idle_time ); 59 61 60 62 #ifdef SYSTEMC -
trunk/IPs/systemC/processor/Morpheo/Common/src/Debug.cpp
r109 r110 16 16 double debug_cycle_start; 17 17 double debug_cycle_stop ; 18 double debug_cycle_idle; 18 double debug_idle_cycle ; 19 uint32_t debug_idle_time ; 19 20 20 21 #undef FUNCTION … … 37 38 double cycle_start, 38 39 double cycle_stop , 39 double cycle_idle) 40 double idle_cycle , 41 uint32_t idle_time ) 40 42 { 41 43 if (not debug_initialized) … … 53 55 # endif 54 56 #endif 55 debug_cycle_idle = cycle_idle; 57 debug_idle_cycle = idle_cycle; 58 debug_idle_time = idle_time ; 56 59 57 60 debug_initialized = true; -
trunk/IPs/systemC/processor/Morpheo/Files/Instance_debug.cfg
r109 r110 4 4 5 5 <thread id="0"> 6 <parameter name="size_ifetch_queue" value=" 16" />7 <parameter name="nb_inst_fetch" value=" 4" />6 <parameter name="size_ifetch_queue" value="32" /> 7 <parameter name="nb_inst_fetch" value="8" /> 8 8 <parameter name="ras_size_queue" value="8" /> 9 9 <parameter name="upt_size_queue" value="8" /> … … 16 16 17 17 <decod_bloc id="0"> 18 <parameter name="size_decod_queue" value=" 8"/>18 <parameter name="size_decod_queue" value="16"/> 19 19 <parameter name="nb_inst_decod" value="4" /> 20 20 <parameter name="nb_context_select" value="1" /> … … 25 25 <rename_bloc id="0"> 26 26 <parameter name="nb_inst_insert" value="4" /> 27 <parameter name="nb_inst_retire" value=" 1" />27 <parameter name="nb_inst_retire" value="4" /> 28 28 <parameter name="rename_select_priority" value="1" /> 29 29 <parameter name="rename_select_load_balancing" value="1" /> 30 30 <parameter name="rename_select_nb_front_end_select" value="1" /> 31 <parameter name="nb_general_register" value=" 64"/>32 <parameter name="nb_special_register" value="1 6" />33 <parameter name="nb_reg_free" value=" 4" />34 <parameter name="nb_rename_unit_bank" value=" 4" />31 <parameter name="nb_general_register" value="256"/> 32 <parameter name="nb_special_register" value="128" /> 33 <parameter name="nb_reg_free" value="8" /> 34 <parameter name="nb_rename_unit_bank" value="8" /> 35 35 <parameter name="size_read_counter" value="4" /> 36 36 </rename_bloc> … … 42 42 </read_bloc> 43 43 44 <write_bloc id="0,1,2,3 ">44 <write_bloc id="0,1,2,3,4,5,6"> 45 45 <parameter name="size_write_queue" value="4" /> 46 46 <parameter name="size_execute_queue" value="4" /> … … 104 104 <parameter name="nb_inst_issue" value="4" /> 105 105 <parameter name="nb_inst_reexecute" value="1" /> 106 <parameter name="nb_inst_commit" value=" 1" />106 <parameter name="nb_inst_commit" value="4" /> 107 107 <parameter name="nb_inst_branch_complete" value="1" /> 108 108 <parameter name="nb_rename_unit_select" value="1" /> 109 109 <parameter name="nb_execute_loop_select" value="1" /> 110 110 <parameter name="size_re_order_buffer" value="32" /> 111 <parameter name="nb_re_order_buffer_bank" value=" 4" />111 <parameter name="nb_re_order_buffer_bank" value="8" /> 112 112 <parameter name="commit_priority" value="1" /> 113 113 <parameter name="commit_load_balancing" value="1" /> … … 123 123 <execute_loop id="0"> 124 124 <parameter name="nb_read_unit" value="4" /> 125 <parameter name="nb_write_unit" value=" 4" />125 <parameter name="nb_write_unit" value="7" /> 126 126 <parameter name="nb_execute_unit" value="4" /> 127 127 <parameter name="nb_gpr_bank" value="1" /> … … 158 158 <link name="link_write_unit_with_write_bloc" src="2" dest="0.2" /> 159 159 <link name="link_write_unit_with_write_bloc" src="3" dest="0.3" /> 160 <link name="link_write_unit_with_write_bloc" src="4" dest="0.4" /> 161 <link name="link_write_unit_with_write_bloc" src="5" dest="0.5" /> 162 <link name="link_write_unit_with_write_bloc" src="6" dest="0.6" /> 160 163 <link name="link_decod_bloc_with_thread" src="0" dest="0" /> 161 164 <link name="link_rename_bloc_with_front_end" src="0" dest="0" /> … … 208 211 <link name="link_write_bloc_and_load_store_unit" src="0.0" dest="1" /> 209 212 <link name="link_write_bloc_and_load_store_unit" src="1.0" dest="1" /> 210 <link name="link_write_bloc_and_load_store_unit" src="2.0" dest="1" /> 211 <link name="link_write_bloc_and_load_store_unit" src="3.0" dest="1" /> 212 <link name="link_write_bloc_and_functionnal_unit" src="0.0" dest="1" /> 213 <link name="link_write_bloc_and_functionnal_unit" src="1.0" dest="1" /> 213 <link name="link_write_bloc_and_load_store_unit" src="2.0" dest="0" /> 214 <link name="link_write_bloc_and_load_store_unit" src="3.0" dest="0" /> 215 <link name="link_write_bloc_and_load_store_unit" src="4.0" dest="0" /> 216 <link name="link_write_bloc_and_load_store_unit" src="5.0" dest="0" /> 217 <link name="link_write_bloc_and_load_store_unit" src="6.0" dest="0" /> 218 <link name="link_write_bloc_and_functionnal_unit" src="0.0" dest="0" /> 219 <link name="link_write_bloc_and_functionnal_unit" src="1.0" dest="0" /> 214 220 <link name="link_write_bloc_and_functionnal_unit" src="2.0" dest="1" /> 215 221 <link name="link_write_bloc_and_functionnal_unit" src="3.0" dest="1" /> 216 <link name="link_write_bloc_and_functionnal_unit" src="0.1" dest="1" /> 217 <link name="link_write_bloc_and_functionnal_unit" src="1.1" dest="1" /> 222 <link name="link_write_bloc_and_functionnal_unit" src="4.0" dest="1" /> 223 <link name="link_write_bloc_and_functionnal_unit" src="5.0" dest="0" /> 224 <link name="link_write_bloc_and_functionnal_unit" src="6.0" dest="0" /> 225 <link name="link_write_bloc_and_functionnal_unit" src="0.1" dest="0" /> 226 <link name="link_write_bloc_and_functionnal_unit" src="1.1" dest="0" /> 218 227 <link name="link_write_bloc_and_functionnal_unit" src="2.1" dest="1" /> 219 228 <link name="link_write_bloc_and_functionnal_unit" src="3.1" dest="1" /> 220 <link name="link_write_bloc_and_functionnal_unit" src="0.2" dest="1" /> 221 <link name="link_write_bloc_and_functionnal_unit" src="1.2" dest="1" /> 222 <link name="link_write_bloc_and_functionnal_unit" src="2.2" dest="1" /> 223 <link name="link_write_bloc_and_functionnal_unit" src="3.2" dest="1" /> 229 <link name="link_write_bloc_and_functionnal_unit" src="4.1" dest="1" /> 230 <link name="link_write_bloc_and_functionnal_unit" src="5.1" dest="0" /> 231 <link name="link_write_bloc_and_functionnal_unit" src="6.1" dest="0" /> 232 <link name="link_write_bloc_and_functionnal_unit" src="0.2" dest="0" /> 233 <link name="link_write_bloc_and_functionnal_unit" src="1.2" dest="0" /> 234 <link name="link_write_bloc_and_functionnal_unit" src="2.2" dest="0" /> 235 <link name="link_write_bloc_and_functionnal_unit" src="3.2" dest="0" /> 236 <link name="link_write_bloc_and_functionnal_unit" src="4.2" dest="0" /> 237 <link name="link_write_bloc_and_functionnal_unit" src="5.2" dest="1" /> 238 <link name="link_write_bloc_and_functionnal_unit" src="6.2" dest="1" /> 239 224 240 <link name="link_thread_and_functionnal_unit" src="0.0" dest="1" /> 225 241 <link name="link_thread_and_functionnal_unit" src="0.1" dest="1" /> -
trunk/IPs/systemC/processor/Morpheo/Files/Morpheo.gen
r109 r110 3 3 <parameters > 4 4 <parameter name="size_data" min="32" max="64" step="* 2" default="32" level="..." description="..." /> 5 <parameter name="dispatch_priority" min="1" max="8" step=" * 2" default="1" level="..." description="..." />6 <parameter name="dispatch_load_balancing" min="1" max="8" step=" * 2" default="1" level="..." description="..." />5 <parameter name="dispatch_priority" min="1" max="8" step="+ 1" default="1" level="..." description="..." /> 6 <parameter name="dispatch_load_balancing" min="1" max="8" step="+ 1" default="1" level="..." description="..." /> 7 7 8 8 <parameter name="nb_icache_port" min="1" max="8" step="* 2" default="1" level="..." description="..." /> 9 <parameter name="icache_port_priority" min="1" max="8" step=" * 2" default="1" level="..." description="..." />10 <parameter name="icache_port_load_balancing" min="1" max="8" step=" * 2" default="1" level="..." description="..." />9 <parameter name="icache_port_priority" min="1" max="8" step="+ 1" default="1" level="..." description="..." /> 10 <parameter name="icache_port_load_balancing" min="1" max="8" step="+ 1" default="1" level="..." description="..." /> 11 11 12 12 <parameter name="nb_dcache_port" min="1" max="8" step="* 2" default="1" level="..." description="..." /> 13 <parameter name="dcache_port_priority" min="1" max="8" step=" * 2" default="1" level="..." description="..." />14 <parameter name="dcache_port_load_balancing" min="1" max="8" step=" * 2" default="1" level="..." description="..." />13 <parameter name="dcache_port_priority" min="1" max="8" step="+ 1" default="1" level="..." description="..." /> 14 <parameter name="dcache_port_load_balancing" min="1" max="8" step="+ 1" default="1" level="..." description="..." /> 15 15 16 <parameter name="nb_thread" min="1" max="8" step=" * 2" default="1" level="..." description="..." />17 <parameter name="size_ifetch_queue" min="1" max=" 16" step="* 2" default="2" level="..." description="..." />16 <parameter name="nb_thread" min="1" max="8" step="+ 1" default="1" level="..." description="..." /> 17 <parameter name="size_ifetch_queue" min="1" max="32" step="* 2" default="2" level="..." description="..." /> 18 18 <parameter name="nb_inst_fetch" min="1" max="8" step="* 2" default="1" level="..." description="..." /> 19 19 <parameter name="implement_group" default="0" level="..." description="..." /> … … 22 22 <parameter name="ufpt_size_queue" min="1" max="8" step="* 2" default="2" level="..." description="..." /> 23 23 24 <parameter name="nb_decod_bloc" min="1" max="8" step=" * 2" default="1" level="..." description="..." />25 <parameter name="size_decod_queue" min="1" max=" 8" step="* 2" default="2" level="..." description="..." />26 <parameter name="nb_inst_decod" min="1" max="8" step=" * 2" default="1" level="..." description="..." />27 <parameter name="nb_context_select" min="1" max="8" step=" * 2" default="1" level="..." description="..." />24 <parameter name="nb_decod_bloc" min="1" max="8" step="+ 1" default="1" level="..." description="..." /> 25 <parameter name="size_decod_queue" min="1" max="32" step="+ 1" default="2" level="..." description="..." /> 26 <parameter name="nb_inst_decod" min="1" max="8" step="+ 1" default="1" level="..." description="..." /> 27 <parameter name="nb_context_select" min="1" max="8" step="+ 1" default="1" level="..." description="..." /> 28 28 <parameter name="context_select_priority" min="1" max="8" step="+ 1" default="1" level="..." description="..." /> 29 29 <parameter name="context_select_load_balancing" min="1" max="8" step="+ 1" default="1" level="..." description="..." /> … … 36 36 <parameter name="rename_select_nb_front_end_select" min="1" max="8" step="+ 1" default="1" level="..." description="..." /> 37 37 <parameter name="nb_general_register" min="64" max="1024" step="* 2" default="64" level="..." description="..." /> 38 <parameter name="nb_special_register" min="4" max=" 64"step="* 2" default="4" level="..." description="..." />38 <parameter name="nb_special_register" min="4" max="512" step="* 2" default="4" level="..." description="..." /> 39 39 <parameter name="nb_reg_free" min="1" max="8" step="+ 1" default="1" level="..." description="..." /> 40 40 <parameter name="nb_rename_unit_bank" min="1" max="8" step="+ 1" default="1" level="..." description="..." /> … … 44 44 <parameter name="size_read_queue" min="1" max="8" step="* 2" default="2" level="..." description="..." /> 45 45 <parameter name="size_reservation_station" min="1" max="8" step="* 2" default="2" level="..." description="..." /> 46 <parameter name="nb_inst_retire_reservation_station" min="1" max="8" step=" * 2" default="1" level="..." description="..." />46 <parameter name="nb_inst_retire_reservation_station" min="1" max="8" step="+ 1" default="1" level="..." description="..." /> 47 47 48 48 <parameter name="nb_write_bloc" min="1" max="8" step="* 2" default="1" level="..." description="..." /> … … 58 58 <parameter name="speculative_load" min="0" max="3" step="+ 1" default="2" level="..." description="..." /> 59 59 <parameter name="nb_bypass_memory" min="0" max="8" step="+ 1" default="0" level="..." description="..." /> 60 <parameter name="nb_cache_port" min="1" max="8" step=" * 2" default="1" level="..." description="..." />61 <parameter name="nb_inst_memory" min="1" max="8" step=" * 2" default="1" level="..." description="..." />60 <parameter name="nb_cache_port" min="1" max="8" step="+ 1" default="1" level="..." description="..." /> 61 <parameter name="nb_inst_memory" min="1" max="8" step="+ 1" default="1" level="..." description="..." /> 62 62 63 63 <parameter name="nb_functionnal_unit" min="1" max="8" step="* 2" default="1" level="..." description="..." /> … … 81 81 <parameter name="dir_pht_size_counter" min="1" max="8" step="* 2" default="1" level="..." description="..." /> 82 82 <parameter name="dir_pht_nb_counter" min="1" max="8" step="* 2" default="1" level="..." description="..." /> 83 <parameter name="dir_pht_size_address_share" min="1" max="8" step=" * 2" default="1" level="..." description="..." />83 <parameter name="dir_pht_size_address_share" min="1" max="8" step="+ 1" default="1" level="..." description="..." /> 84 84 85 <parameter name="nb_ooo_engine" min="1" max="8" step=" * 2" default="1" level="..." description="..." />86 <parameter name="nb_rename_unit" min="1" max="8" step=" * 2" default="1" level="..." description="..." />85 <parameter name="nb_ooo_engine" min="1" max="8" step="+ 1" default="1" level="..." description="..." /> 86 <parameter name="nb_rename_unit" min="1" max="8" step="+ 1" default="1" level="..." description="..." /> 87 87 <parameter name="nb_inst_issue" min="1" max="8" step="* 2" default="1" level="..." description="..." /> 88 88 <parameter name="nb_inst_reexecute" min="1" max="8" step="* 2" default="1" level="..." description="..." /> … … 93 93 <parameter name="size_re_order_buffer" min="1" max="256" step="* 2" default="1" level="..." description="..." /> 94 94 <parameter name="nb_re_order_buffer_bank" min="1" max="8" step="* 2" default="1" level="..." description="..." /> 95 <parameter name="commit_priority" min="1" max="8" step=" * 2" default="1" level="..." description="..." />96 <parameter name="commit_load_balancing" min="1" max="8" step=" * 2" default="1" level="..." description="..." />95 <parameter name="commit_priority" min="1" max="8" step="+ 1" default="1" level="..." description="..." /> 96 <parameter name="commit_load_balancing" min="1" max="8" step="+ 1" default="1" level="..." description="..." /> 97 97 <parameter name="size_issue_queue" min="1" max="8" step="* 2" default="2" level="..." description="..." /> 98 98 <parameter name="nb_issue_queue_bank" min="1" max="8" step="* 2" default="1" level="..." description="..." /> … … 100 100 <parameter name="issue_load_balancing" min="1" max="8" step="* 2" default="1" level="..." description="..." /> 101 101 <parameter name="size_reexecute_queue" min="1" max="8" step="* 2" default="2" level="..." description="..." /> 102 <parameter name="reexecute_priority" min="1" max="8" step=" * 2" default="1" level="..." description="..." />103 <parameter name="reexecute_load_balancing" min="1" max="8" step=" * 2" default="1" level="..." description="..." />102 <parameter name="reexecute_priority" min="1" max="8" step="+ 1" default="1" level="..." description="..." /> 103 <parameter name="reexecute_load_balancing" min="1" max="8" step="+ 1" default="1" level="..." description="..." /> 104 104 105 <parameter name="nb_execute_loop" min="1" max="8" step=" * 2" default="1" level="..." description="..." />106 <parameter name="nb_read_unit" min="1" max="8" step=" * 2" default="1" level="..." description="..." />105 <parameter name="nb_execute_loop" min="1" max="8" step="+ 1" default="1" level="..." description="..." /> 106 <parameter name="nb_read_unit" min="1" max="8" step="+ 1" default="1" level="..." description="..." /> 107 107 <parameter name="nb_execute_unit" min="1" max="8" step="+ 1" default="1" level="..." description="..." /> 108 <parameter name="nb_write_unit" min="1" max="8" step=" * 2" default="1" level="..." description="..." />108 <parameter name="nb_write_unit" min="1" max="8" step="+ 1" default="1" level="..." description="..." /> 109 109 <parameter name="nb_gpr_bank" min="1" max="8" step="* 2" default="1" level="..." description="..." /> 110 110 <parameter name="nb_gpr_port_read_by_bank" min="1" max="8" step="* 2" default="1" level="..." description="..." /> … … 113 113 <parameter name="nb_spr_port_read_by_bank" min="1" max="8" step="* 2" default="1" level="..." description="..." /> 114 114 <parameter name="nb_spr_port_write_by_bank" min="1" max="8" step="* 2" default="1" level="..." description="..." /> 115 <parameter name="execution_unit_to_write_unit_priority" min="1" max="8" step=" * 2" default="1" level="..." description="..." />116 <parameter name="read_unit_to_execution_unit_priority" min="1" max="8" step=" * 2" default="1" level="..." description="..." />115 <parameter name="execution_unit_to_write_unit_priority" min="1" max="8" step="+ 1" default="1" level="..." description="..." /> 116 <parameter name="read_unit_to_execution_unit_priority" min="1" max="8" step="+ 1" default="1" level="..." description="..." /> 117 117 118 118 <link name="link_context_with_thread" src="thread" dest="context" description="..." /> -
trunk/IPs/systemC/processor/Morpheo/Files/Morpheo.sim
r109 r110 3 3 <parameters > 4 4 5 <parameter name="use_systemc" value="1" /> 6 <parameter name="use_vhdl" value="0" /> 7 <parameter name="use_vhdl_testbench" value="0" /> 8 <parameter name="use_vhdl_testbench_assert" value="0" /> 9 <parameter name="use_position" value="0" /> 10 <parameter name="use_statistics" value="1" /> 11 <parameter name="use_information" value="0" /> 12 <parameter name="use_header" value="0" /> 5 <parameter name="use_systemc" value="1" /> 6 <parameter name="use_vhdl" value="0" /> 7 <parameter name="use_vhdl_testbench" value="0" /> 8 <parameter name="use_vhdl_testbench_assert" value="0" /> 9 <parameter name="use_position" value="0" /> 10 <parameter name="use_statistics" value="1" /> 11 <parameter name="use_information" value="0" /> 12 <parameter name="use_header" value="0" /> 13 14 <parameter name="statistics_cycle_start" value="5" /> 15 <parameter name="statistics_period" value="0" /> 13 16 14 <parameter name="s tatistics_cycle_start" value="0"/>15 <parameter name="s tatistics_period" value="0"/>17 <parameter name="simulation_nb_cycle" value="600000" /> 18 <parameter name="simulation_nb_instruction" value="0" /> 16 19 17 <parameter name="simulation_nb_cycle" value="60000" /> 18 <parameter name="simulation_nb_instruction" value="0" /> 20 <parameter name="directory_statistics" value="." /> 21 <parameter name="directory_vhdl" value="." /> 22 <parameter name="directory_position" value="." /> 23 <parameter name="directory_log" value="." /> 19 24 20 <parameter name="directory_statistics" value="." /> 21 <parameter name="directory_vhdl" value="." /> 22 <parameter name="directory_position" value="." /> 23 <parameter name="directory_log" value="." /> 24 25 <parameter name="debug_level" value="0"/> 26 <parameter name="debug_cycle_start" value="1000" /> 27 <parameter name="debug_cycle_stop" value="1200" /> 28 <parameter name="debug_cycle_idle" value="100" /> 29 <parameter name="debug_have_log_file" value="0" /> 25 <parameter name="debug_level" value="3" /> 26 <parameter name="debug_cycle_start" value="1600" /> 27 <parameter name="debug_cycle_stop" value="1750" /> 28 <parameter name="debug_idle_cycle" value="100" /> 29 <parameter name="debug_idle_time" value="3" /> 30 <parameter name="debug_have_log_file" value="0" /> 30 31 31 < simulation component="Counter" value="systemc" />32 < simulation component="Priority" value="systemc" />33 < simulation component="Queue_Control" value="systemc" />34 < simulation component="Queue" value="systemc" />35 < simulation component="RegisterFile_Monolithic" value="systemc" />36 < simulation component="RegisterFile_Multi_Banked" value="systemc" />37 < simulation component="RegisterFile" value="systemc" />38 < simulation component="Select_Priority_Fixed" value="systemc" />39 < simulation component="Select" value="systemc" />40 < simulation component="Shifter" value="systemc" />41 < simulation component="Sort" value="systemc" />42 < simulation component="Victim_Pseudo_LRU" value="systemc" />43 < simulation component="Victim" value="systemc" />44 < simulation component="Execute_loop_Glue" value="systemc" />45 < simulation component="Functionnal_unit" value="systemc" />46 < simulation component="Load_store_unit" value="systemc" />47 < simulation component="Read_queue" value="systemc" />48 < simulation component="Reservation_station" value="systemc" />49 < simulation component="Read_unit" value="systemc" />50 < simulation component="Execute_queue" value="systemc" />51 < simulation component="Write_queue" value="systemc" />52 < simulation component="Write_unit" value="systemc" />53 < simulation component="Execution_unit_to_Write_unit" value="systemc" />54 < simulation component="Read_unit_to_Execution_unit" value="systemc" />55 < simulation component="Register_unit_Glue" value="systemc" />56 < simulation component="Register_unit" value="systemc" />57 < simulation component="Execute_loop" value="systemc" />58 < simulation component="Commit_unit" value="systemc" />59 < simulation component="Issue_queue" value="systemc" />60 < simulation component="OOO_Engine_Glue" value="systemc" />61 < simulation component="Reexecute_unit" value="systemc" />62 < simulation component="Load_Store_pointer_unit" value="systemc" />63 < simulation component="Dependency_checking_unit" value="systemc" />64 < simulation component="Free_List_unit" value="systemc" />65 < simulation component="Register_Address_Translation_unit" value="systemc" />66 < simulation component="Register_translation_unit_Glue" value="systemc" />67 < simulation component="Stat_List_unit" value="systemc" />68 < simulation component="Register_translation_unit" value="systemc" />69 < simulation component="Rename_unit_Glue" value="systemc" />70 < simulation component="Rename_select" value="systemc" />71 < simulation component="Rename_unit" value="systemc" />72 < simulation component="Special_Register_unit" value="systemc" />73 < simulation component="OOO_Engine" value="systemc" />74 < simulation component="Context_State" value="systemc" />75 < simulation component="Decod" value="systemc" />76 < simulation component="Decod_queue" value="systemc" />77 < simulation component="Decod_unit" value="systemc" />78 < simulation component="Front_end_Glue" value="systemc" />79 < simulation component="Address_management" value="systemc" />80 < simulation component="Ifetch_queue" value="systemc" />81 < simulation component="Ifetch_unit_Glue" value="systemc" />82 < simulation component="Ifetch_unit" value="systemc" />83 < simulation component="Branch_Target_Buffer_Glue" value="systemc" />84 < simulation component="Branch_Target_Buffer_Register" value="systemc" />85 < simulation component="Branch_Target_Buffer" value="systemc" />86 < simulation component="Direction_Glue" value="systemc" />87 < simulation component="Direction" value="systemc" />88 < simulation component="Prediction_unit_Glue" value="systemc" />89 < simulation component="Return_Address_Stack" value="systemc" />90 < simulation component="Update_Prediction_Table" value="systemc" />91 < simulation component="Prediction_unit" value="systemc" />92 < simulation component="Front_end" value="systemc" />93 < simulation component="Icache_Access" value="systemc" />94 < simulation component="Dcache_Access" value="systemc" />95 < simulation component="Core_Glue" value="systemc" />96 < simulation component="Core" value="systemc" />97 < simulation component="TopLevel" value="systemc" />32 <component name="Counter" simulation="systemc" debug="0" /> 33 <component name="Priority" simulation="systemc" debug="0" /> 34 <component name="Queue_Control" simulation="systemc" debug="0" /> 35 <component name="Queue" simulation="systemc" debug="0" /> 36 <component name="RegisterFile_Monolithic" simulation="systemc" debug="0" /> 37 <component name="RegisterFile_Multi_Banked" simulation="systemc" debug="0" /> 38 <component name="RegisterFile" simulation="systemc" debug="0" /> 39 <component name="Select_Priority_Fixed" simulation="systemc" debug="0" /> 40 <component name="Select" simulation="systemc" debug="0" /> 41 <component name="Shifter" simulation="systemc" debug="0" /> 42 <component name="Sort" simulation="systemc" debug="0" /> 43 <component name="Victim_Pseudo_LRU" simulation="systemc" debug="0" /> 44 <component name="Victim" simulation="systemc" debug="0" /> 45 <component name="Execute_loop_Glue" simulation="systemc" debug="0" /> 46 <component name="Functionnal_unit" simulation="systemc" debug="0" /> 47 <component name="Load_store_unit" simulation="systemc" debug="0" /> 48 <component name="Read_queue" simulation="systemc" debug="0" /> 49 <component name="Reservation_station" simulation="systemc" debug="0" /> 50 <component name="Read_unit" simulation="systemc" debug="0" /> 51 <component name="Execute_queue" simulation="systemc" debug="0" /> 52 <component name="Write_queue" simulation="systemc" debug="0" /> 53 <component name="Write_unit" simulation="systemc" debug="0" /> 54 <component name="Execution_unit_to_Write_unit" simulation="systemc" debug="0" /> 55 <component name="Read_unit_to_Execution_unit" simulation="systemc" debug="0" /> 56 <component name="Register_unit_Glue" simulation="systemc" debug="0" /> 57 <component name="Register_unit" simulation="systemc" debug="0" /> 58 <component name="Execute_loop" simulation="systemc" debug="0" /> 59 <component name="Commit_unit" simulation="systemc" debug="0" /> 60 <component name="Issue_queue" simulation="systemc" debug="0" /> 61 <component name="OOO_Engine_Glue" simulation="systemc" debug="0" /> 62 <component name="Reexecute_unit" simulation="systemc" debug="0" /> 63 <component name="Load_Store_pointer_unit" simulation="systemc" debug="0" /> 64 <component name="Dependency_checking_unit" simulation="systemc" debug="0" /> 65 <component name="Free_List_unit" simulation="systemc" debug="0" /> 66 <component name="Register_Address_Translation_unit" simulation="systemc" debug="0" /> 67 <component name="Register_translation_unit_Glue" simulation="systemc" debug="0" /> 68 <component name="Stat_List_unit" simulation="systemc" debug="0" /> 69 <component name="Register_translation_unit" simulation="systemc" debug="0" /> 70 <component name="Rename_unit_Glue" simulation="systemc" debug="0" /> 71 <component name="Rename_select" simulation="systemc" debug="0" /> 72 <component name="Rename_unit" simulation="systemc" debug="0" /> 73 <component name="Special_Register_unit" simulation="systemc" debug="0" /> 74 <component name="OOO_Engine" simulation="systemc" debug="0" /> 75 <component name="Context_State" simulation="systemc" debug="0" /> 76 <component name="Decod" simulation="systemc" debug="0" /> 77 <component name="Decod_queue" simulation="systemc" debug="0" /> 78 <component name="Decod_unit" simulation="systemc" debug="0" /> 79 <component name="Front_end_Glue" simulation="systemc" debug="0" /> 80 <component name="Address_management" simulation="systemc" debug="0" /> 81 <component name="Ifetch_queue" simulation="systemc" debug="0" /> 82 <component name="Ifetch_unit_Glue" simulation="systemc" debug="0" /> 83 <component name="Ifetch_unit" simulation="systemc" debug="0" /> 84 <component name="Branch_Target_Buffer_Glue" simulation="systemc" debug="0" /> 85 <component name="Branch_Target_Buffer_Register" simulation="systemc" debug="0" /> 86 <component name="Branch_Target_Buffer" simulation="systemc" debug="0" /> 87 <component name="Direction_Glue" simulation="systemc" debug="0" /> 88 <component name="Direction" simulation="systemc" debug="0" /> 89 <component name="Prediction_unit_Glue" simulation="systemc" debug="0" /> 90 <component name="Return_Address_Stack" simulation="systemc" debug="0" /> 91 <component name="Update_Prediction_Table" simulation="systemc" debug="0" /> 92 <component name="Prediction_unit" simulation="systemc" debug="0" /> 93 <component name="Front_end" simulation="systemc" debug="0" /> 94 <component name="Icache_Access" simulation="systemc" debug="0" /> 95 <component name="Dcache_Access" simulation="systemc" debug="0" /> 96 <component name="Core_Glue" simulation="systemc" debug="0" /> 97 <component name="Core" simulation="systemc" debug="0" /> 98 <component name="TopLevel" simulation="systemc" debug="0" /> 98 99 99 100 </parameters> -
trunk/IPs/systemC/processor/Morpheo/Script/SelfTest.sh
r105 r110 9 9 declare test_ko="Test KO"; 10 10 declare test_ok="Test OK"; 11 declare test_unknow="???????"; 11 12 declare tmp="${MORPHEO_HOME}/tmp/SelfTest"; 12 13 declare path="${MORPHEO_TOPLEVEL}/IPs/systemC/processor/Morpheo/"; … … 88 89 "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Direction_Glue" 89 90 "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction" 90 #"Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Meta_Predictor_Glue"91 "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Meta_Predictor_Glue" 91 92 # "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue" 92 93 # "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table" 93 94 # "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table" 94 #"Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Two_Level_Branch_Predictor"95 #"Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor"95 "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Two_Level_Branch_Predictor" 96 "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor" 96 97 "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue" 97 98 "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack" … … 225 226 "result") 226 227 for x in "systemc" "vhdl"; do 227 echo "${x}"; 228 color=34; 229 echo "[1;${color}m * ${x}[1;0m"; 230 228 231 for i in ${tmp}/*.${x}; do 229 232 if test -f ${i}; then … … 232 235 233 236 case "${res_test}" in 234 "${test_ok}") color=32;237 "${test_ok}") res_test=${test_ok}; color=32; 235 238 ;; 236 "${test_ko}") color=31;239 "${test_ko}") res_test=${test_ko}; color=31; 237 240 ;; 238 *) color=39;241 *) res_test=${test_unknow}; color=39; 239 242 ;; 240 243 esac 241 echo "[1;${color}m * ${res_test} - ${component}[1;0m";244 echo "[1;${color}m * ${res_test} - ${component}[1;0m"; 242 245 fi; 243 246 done; -
trunk/IPs/systemC/processor/Morpheo/TopLevel/include/Morpheo.h
r97 r110 32 32 #include "Common/include/Debug.h" 33 33 34 35 34 #include <iostream> 35 #include <csignal> 36 #include <unistd.h> 36 37 37 38 namespace morpheo { … … 184 185 #ifdef SYSTEMC 185 186 public : bool simulation_end (void); 187 private : void signal_init (void); 188 //private : void signal_handler (int value); 186 189 #endif 187 190 }; 191 192 void signal_handler (int value); 188 193 189 194 }; // end namespace morpheo -
trunk/IPs/systemC/processor/Morpheo/TopLevel/src/Morpheo.cpp
r97 r110 80 80 #endif 81 81 } 82 83 #ifdef SYSTEMC 84 // Stop alarm 85 signal_init(); 86 #endif 87 82 88 log_end(Morpheo,FUNCTION); 83 89 }; … … 88 94 { 89 95 log_begin(Morpheo,FUNCTION); 96 97 #ifdef SYSTEMC 98 // Stop alarm 99 alarm(0); 100 #endif 90 101 91 102 #ifdef STATISTICS -
trunk/IPs/systemC/processor/Morpheo/TopLevel/src/Morpheo_transition.cpp
r88 r110 20 20 { 21 21 log_begin(Morpheo,FUNCTION); 22 23 // Re init the alarm 24 alarm(debug_idle_time); 22 25 23 26 #if defined(STATISTICS) or defined(VHDL_TESTBENCH) -
trunk/Makefile.flags
r108 r110 17 17 -DDEBUG=DEBUG_TRACE \ 18 18 -DSTATISTICS \ 19 -DVHDL \ 20 -DVHDL_TESTBENCH \ 19 21 -DTRANSLATION 20 22 21 # -DVHDL \22 # -DVHDL_TESTBENCH \23 23 # -DVHDL_TESTBENCH_ASSERT \ 24 24 # -DPRINT_COLOR \ -
trunk/Softwares/Test/Test_015/src/sys/crt0.s
r101 r110 37 37 _start: 38 38 39 l.movhi r2, hi(0x000000 02) /* count max */40 l.ori r2, r2, lo(0x000000 02)39 l.movhi r2, hi(0x00000010) /* count max */ 40 l.ori r2, r2, lo(0x00000010) 41 41 42 42 /**********/
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