- Timestamp:
- Jul 5, 2007, 5:50:19 PM (17 years ago)
- Location:
- trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor
- Files:
-
- 8 deleted
- 42 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/SelfTest/src/test.cpp
r15 r42 96 96 97 97 98 _Branch_History_Table->vhdl_testbench_label("Initialisation");99 98 cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} Initialisation" << endl; 100 99 … … 129 128 sc_start(0); 130 129 131 _Branch_History_Table->vhdl_testbench_label("Loop of Test");132 130 cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} Loop of Test" << endl; 133 131 134 132 for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++) 135 133 { 136 _Branch_History_Table->vhdl_testbench_label("Iteration "+toString(iteration));137 134 num_port_branch_complete = rand() % param._nb_branch_complete; 138 135 num_port_predict = rand() % param._nb_prediction ; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/include/Branch_History_Table.h
r15 r42 27 27 #include "Behavioural/include/Vhdl.h" 28 28 #endif 29 #ifdef VHDL_TESTBENCH 30 #include "Behavioural/include/Vhdl_Testbench.h" 31 #endif 29 #include "Behavioural/include/Component.h" 32 30 33 31 using namespace std; … … 59 57 #endif 60 58 61 #ifdef VHDL_TESTBENCH 62 private : Vhdl_Testbench * _vhdl_testbench; 63 #endif 59 public : Component * _component; 60 private : Interfaces * _interfaces; 64 61 65 62 #ifdef SYSTEMC … … 83 80 84 81 // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 85 public : SC_SIGNAL(Thistory_t) ** signal_BRANCH_COMPLETE_HISTORY;86 82 #endif 87 83 … … 118 114 #endif 119 115 120 #if VHDL121 public : void vhdl (void);122 private : void vhdl_port (Vhdl & vhdl);123 private : void vhdl_type (Vhdl & vhdl);124 private : void vhdl_signal (Vhdl & vhdl);125 private : void vhdl_body (Vhdl & vhdl);126 #endif127 116 #ifdef STATISTICS 128 117 public : string statistics (uint32_t depth); 129 118 #endif 130 119 #if VHDL 120 public : void vhdl (void); 121 private : void vhdl_port (Vhdl * & vhdl); 122 private : void vhdl_type (Vhdl * & vhdl); 123 private : void vhdl_signal (Vhdl * & vhdl); 124 private : void vhdl_body (Vhdl * & vhdl); 125 #endif 131 126 #ifdef VHDL_TESTBENCH 132 private : void vhdl_testbench_port (void);133 127 private : void vhdl_testbench_transition (void); 134 128 #endif 135 public : void vhdl_testbench_label (string label);136 129 }; 137 130 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table.cpp
r15 r42 32 32 #endif 33 33 { 34 35 #ifdef SYSTEMC 36 allocation (); 37 #endif 38 34 39 #ifdef STATISTICS 35 40 // Allocation of statistics … … 39 44 #endif 40 45 41 #ifdef VHDL_TESTBENCH42 // Creation of a testbench43 // -> port44 // -> clock's signals45 _vhdl_testbench = new Vhdl_Testbench (_name);46 vhdl_testbench_port ();47 _vhdl_testbench->set_clock ("in_CLOCK",true);48 #endif49 50 46 #ifdef VHDL 51 47 // generate the vhdl … … 53 49 #endif 54 50 51 55 52 #ifdef SYSTEMC 56 allocation ();57 58 53 // // Constant 59 54 // for (uint32_t i=0; i<_param._nb_prediction ; i++) … … 77 72 Branch_History_Table::~Branch_History_Table (void) 78 73 { 79 #ifdef VHDL_TESTBENCH80 // generate the test bench81 _vhdl_testbench->generate_file();82 delete _vhdl_testbench;83 #endif84 85 74 #ifdef STATISTICS 86 75 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_allocation.cpp
r15 r42 20 20 void Branch_History_Table::allocation (void) 21 21 { 22 string rename; 23 24 in_CLOCK = new SC_CLOCK ("in_CLOCK"); 25 in_NRESET = new SC_IN (Tcontrol_t) ("in_NRESET"); 26 22 _component = new Component (); 23 24 Entity * entity = _component->set_entity (_name 25 ,"Branch_History_Table" 26 #ifdef POSITION 27 ,MIXTE 28 #endif 29 ); 30 31 _interfaces = entity->set_interfaces(); 32 33 // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 34 { 35 Interface * interface = _interfaces->set_interface("" 36 #ifdef POSITION 37 , IN 38 , SOUTH 39 , "Generalist interface" 40 #endif 41 ); 42 43 in_CLOCK = interface->set_signal_clk ("clock" ,1); 44 in_NRESET = interface->set_signal_in <Tcontrol_t> ("nreset",1,RESET_VHDL_YES); 45 } 46 47 // ~~~~~[ Interface : "predict" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 27 48 in_PREDICT_VAL = new SC_IN (Tcontrol_t) * [_param._nb_prediction]; 28 49 out_PREDICT_ACK = new SC_OUT(Tcontrol_t) * [_param._nb_prediction]; … … 32 53 for (uint32_t i=0; i<_param._nb_prediction; i++) 33 54 { 34 rename = "in_PREDICT_VAL[" +toString(i)+"]"; 35 in_PREDICT_VAL [i] = new SC_IN (Tcontrol_t) (rename.c_str()); 36 37 rename = "out_PREDICT_ACK[" +toString(i)+"]"; 38 out_PREDICT_ACK [i] = new SC_OUT(Tcontrol_t) (rename.c_str()); 39 40 rename = "in_PREDICT_ADDRESS["+toString(i)+"]"; 41 in_PREDICT_ADDRESS [i] = new SC_IN (Taddress_t) (rename.c_str()); 42 43 rename = "out_PREDICT_HISTORY["+toString(i)+"]"; 44 out_PREDICT_HISTORY [i] = new SC_OUT(Thistory_t) (rename.c_str()); 45 } 46 47 in_BRANCH_COMPLETE_VAL = new SC_IN (Tcontrol_t) * [_param._nb_branch_complete]; 48 out_BRANCH_COMPLETE_ACK = new SC_OUT (Tcontrol_t) * [_param._nb_branch_complete]; 49 in_BRANCH_COMPLETE_ADDRESS = new SC_IN (Taddress_t) * [_param._nb_branch_complete]; 50 in_BRANCH_COMPLETE_HISTORY = new SC_IN (Thistory_t) * [_param._nb_branch_complete]; 51 in_BRANCH_COMPLETE_DIRECTION= new SC_IN (Tcontrol_t) * [_param._nb_branch_complete]; 52 signal_BRANCH_COMPLETE_HISTORY = new SC_SIGNAL (Thistory_t) * [_param._nb_branch_complete]; 55 Interface_fifo * interface = _interfaces->set_interface("predict_"+toString(i) 56 #ifdef POSITION 57 , IN 58 , WEST 59 , "Interface Predict" 60 #endif 61 ); 62 63 in_PREDICT_VAL [i] = interface->set_signal_valack_in ("val" , VAL); 64 out_PREDICT_ACK [i] = interface->set_signal_valack_out ("ack" , ACK); 65 in_PREDICT_ADDRESS [i] = interface->set_signal_in <Taddress_t> ("address", static_cast<uint32_t>(ceil(log2(_param._nb_shifter)))); 66 out_PREDICT_HISTORY [i] = interface->set_signal_out <Thistory_t> ("history", _param._size_shifter); 67 } 68 69 // ~~~~~[ Interface : "branch_complete" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 70 71 in_BRANCH_COMPLETE_VAL = new SC_IN (Tcontrol_t) * [_param._nb_branch_complete]; 72 out_BRANCH_COMPLETE_ACK = new SC_OUT (Tcontrol_t) * [_param._nb_branch_complete]; 73 in_BRANCH_COMPLETE_ADDRESS = new SC_IN (Taddress_t) * [_param._nb_branch_complete]; 74 in_BRANCH_COMPLETE_HISTORY = new SC_IN (Thistory_t) * [_param._nb_branch_complete]; 75 in_BRANCH_COMPLETE_DIRECTION = new SC_IN (Tcontrol_t) * [_param._nb_branch_complete]; 53 76 54 77 for (uint32_t i=0; i<_param._nb_branch_complete; i++) 55 78 { 56 rename = "in_BRANCH_COMPLETE_VAL[" +toString(i)+"]"; 57 in_BRANCH_COMPLETE_VAL [i] = new SC_IN (Tcontrol_t) (rename.c_str()); 58 59 rename = "out_BRANCH_COMPLETE_ACK[" +toString(i)+"]"; 60 out_BRANCH_COMPLETE_ACK [i] = new SC_OUT(Tcontrol_t) (rename.c_str()); 61 62 rename = "in_BRANCH_COMPLETE_ADDRESS["+toString(i)+"]"; 63 in_BRANCH_COMPLETE_ADDRESS [i] = new SC_IN (Taddress_t) (rename.c_str()); 64 65 rename = "in_BRANCH_COMPLETE_HISTORY["+toString(i)+"]"; 66 in_BRANCH_COMPLETE_HISTORY [i] = new SC_IN (Thistory_t) (rename.c_str()); 67 68 rename = "in_BRANCH_COMPLETE_DIRECTION[" +toString(i)+"]"; 69 in_BRANCH_COMPLETE_DIRECTION[i] = new SC_IN (Tcontrol_t) (rename.c_str()); 70 71 rename = "signal_BRANCH_COMPLETE_HISTORY["+toString(i)+"]"; 72 signal_BRANCH_COMPLETE_HISTORY [i] = new SC_SIGNAL (Thistory_t) (rename.c_str()); 73 79 Interface_fifo * interface = _interfaces->set_interface("branch_complete_"+toString(i) 80 #ifdef POSITION 81 , IN 82 , EAST 83 , "Interface branch complete" 84 #endif 85 ); 86 87 in_BRANCH_COMPLETE_VAL [i] = interface->set_signal_valack_in ("val" , VAL); 88 out_BRANCH_COMPLETE_ACK [i] = interface->set_signal_valack_out ("ack" , ACK); 89 in_BRANCH_COMPLETE_ADDRESS [i] = interface->set_signal_in <Taddress_t> ("address" , static_cast<uint32_t>(ceil(log2(_param._nb_shifter)))); 90 in_BRANCH_COMPLETE_HISTORY [i] = interface->set_signal_in <Thistory_t> ("history" , _param._size_shifter); 91 in_BRANCH_COMPLETE_DIRECTION [i] = interface->set_signal_in <Tcontrol_t> ("direction", 1); 74 92 } 75 93 76 94 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 77 95 string name_component; 96 78 97 // =====[ component_Shifter ]========================================= 79 98 80 99 name_component = _name+"_Shifter"; 81 100 82 component_Shifter = new morpheo::behavioural::generic::shifter::Shifter (name_component.c_str() ,101 component_Shifter = new morpheo::behavioural::generic::shifter::Shifter (name_component.c_str() 83 102 #ifdef STATISTICS 84 _param_statistics , 85 #endif 86 *(_param._param_shifter) ); 87 88 89 // Instantiation 90 #if (defined(STATISTICS) || defined (VHDL_TESTBENCH)) 91 (*(component_Shifter->in_CLOCK)) (*(in_CLOCK)); 92 #endif 93 94 for (uint32_t i=0; i<_param._nb_branch_complete; i++) 95 { 96 (*(component_Shifter-> in_SHIFTER_DATA [i])) (*( in_BRANCH_COMPLETE_HISTORY [i])); 97 (*(component_Shifter-> in_SHIFTER_CARRY_IN [i])) (*( in_BRANCH_COMPLETE_DIRECTION[i])); 98 (*(component_Shifter->out_SHIFTER_DATA [i])) (*(signal_BRANCH_COMPLETE_HISTORY [i])); 99 } 100 103 ,_param_statistics 104 #endif 105 ,*(_param._param_shifter)); 106 107 _component->set_component (component_Shifter->_component 108 #ifdef POSITION 109 , 25 110 , 25 111 , 10 112 , 10 113 #endif 114 ); 115 101 116 // =====[ component_RegisterFile ]==================================== 102 117 … … 105 120 component_RegisterFile = new morpheo::behavioural::generic::registerfile::registerfile_monolithic::RegisterFile_Monolithic(name_component.c_str(), 106 121 #ifdef STATISTICS 107 _param_statistics , 108 #endif 109 *(_param._param_registerfile)); 122 _param_statistics , 123 #endif 124 *(_param._param_registerfile)); 125 126 _component->set_component (component_RegisterFile->_component 127 #ifdef POSITION 128 , 75 129 , 75 130 , 10 131 , 10 132 #endif 133 ); 110 134 111 // Instantiation 112 (*(component_RegisterFile->in_CLOCK )) (*(in_CLOCK )); 113 (*(component_RegisterFile->in_NRESET)) (*(in_NRESET)); 135 // ~~~~~[ Component - Instanciation ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 136 137 // =====[ component_RegisterFile - Instanciation ]==================== 138 139 #ifdef POSITION 140 _component->interface_map (_name+"_RegisterFile","", 141 _name ,""); 142 #endif 143 144 _component->port_map(_name+"_RegisterFile", "in_CLOCK" , _name,"in_CLOCK" ); 145 _component->port_map(_name+"_RegisterFile", "in_NRESET", _name,"in_NRESET"); 114 146 115 147 for (uint32_t i=0; i<_param._nb_prediction; i++) 116 148 { 117 (*(component_RegisterFile-> in_READ_VAL [i])) (*( in_PREDICT_VAL [i])); 118 (*(component_RegisterFile->out_READ_ACK [i])) (*(out_PREDICT_ACK [i])); 119 (*(component_RegisterFile-> in_READ_ADDRESS [i])) (*( in_PREDICT_ADDRESS [i])); 120 (*(component_RegisterFile->out_READ_DATA [i])) (*(out_PREDICT_HISTORY [i])); 149 #ifdef POSITION 150 _component->interface_map (_name+"_RegisterFile","read_" +toString(i), 151 _name ,"predict_"+toString(i)); 152 #endif 153 154 _component->port_map(_name+"_RegisterFile", "in_READ_"+toString(i)+"_VAL" , _name, "in_PREDICT_"+toString(i)+"_VAL" ); 155 _component->port_map(_name+"_RegisterFile","out_READ_"+toString(i)+"_ACK" , _name,"out_PREDICT_"+toString(i)+"_ACK" ); 156 _component->port_map(_name+"_RegisterFile", "in_READ_"+toString(i)+"_ADDRESS", _name, "in_PREDICT_"+toString(i)+"_ADDRESS"); 157 _component->port_map(_name+"_RegisterFile","out_READ_"+toString(i)+"_DATA" , _name,"out_PREDICT_"+toString(i)+"_HISTORY"); 121 158 } 122 159 123 160 for (uint32_t i=0; i<_param._nb_branch_complete; i++) 124 161 { 125 (*(component_RegisterFile-> in_WRITE_VAL [i])) (*( in_BRANCH_COMPLETE_VAL [i])); 126 (*(component_RegisterFile->out_WRITE_ACK [i])) (*( out_BRANCH_COMPLETE_ACK [i])); 127 (*(component_RegisterFile-> in_WRITE_ADDRESS [i])) (*( in_BRANCH_COMPLETE_ADDRESS [i])); 128 (*(component_RegisterFile-> in_WRITE_DATA [i])) (*(signal_BRANCH_COMPLETE_HISTORY [i])); 129 } 162 #ifdef POSITION 163 _component->interface_map (_name+"_RegisterFile","write_" +toString(i), 164 _name+"_Shifter" ,"shifter_"+toString(i)); 165 #endif 166 167 _component->port_map(_name+"_RegisterFile", "in_WRITE_"+toString(i)+"_VAL" , _name , "in_BRANCH_COMPLETE_"+toString(i)+"_VAL" ); 168 _component->port_map(_name+"_RegisterFile","out_WRITE_"+toString(i)+"_ACK" , _name ,"out_BRANCH_COMPLETE_"+toString(i)+"_ACK" ); 169 _component->port_map(_name+"_RegisterFile", "in_WRITE_"+toString(i)+"_ADDRESS", _name , "in_BRANCH_COMPLETE_"+toString(i)+"_ADDRESS"); 170 _component->port_map(_name+"_RegisterFile", "in_WRITE_"+toString(i)+"_DATA" , _name+"_Shifter","out_SHIFTER_" +toString(i)+"_DATA"); 171 } 172 173 // =====[ component_Shifter - Instanciation ]========================= 174 175 #if (defined(STATISTICS) || defined (VHDL_TESTBENCH)) 176 177 #ifdef POSITION 178 _component->interface_map (_name+"_Shifter","", 179 _name ,""); 180 #endif 181 182 _component->port_map(_name+"_Shifter", "in_CLOCK" , _name,"in_CLOCK" ); 183 _component->port_map(_name+"_Shifter", "in_NRESET", _name,"in_NRESET"); 184 185 #endif 186 187 for (uint32_t i=0; i<_param._nb_branch_complete; i++) 188 { 189 #ifdef POSITION 190 _component->interface_map (_name+"_Shifter","shifter_"+toString(i), 191 _name ,"branch_complete_"+toString(i)); 192 193 #endif 194 195 _component->port_map(_name+"_Shifter", "in_SHIFTER_" +toString(i)+"_DATA" , _name , "in_BRANCH_COMPLETE_"+toString(i)+"_HISTORY"); 196 _component->port_map(_name+"_Shifter", "in_SHIFTER_" +toString(i)+"_CARRY_IN", _name , "in_BRANCH_COMPLETE_"+toString(i)+"_DIRECTION"); 197 _component->port_map(_name+"_Shifter", "out_SHIFTER_"+toString(i)+"_DATA" , _name+"_RegisterFile", "in_WRITE_"+toString(i)+"_DATA"); 198 } 199 200 #ifdef POSITION 201 _component->generate_file(); 202 #endif 130 203 }; 131 204 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_deallocation.cpp
r15 r42 19 19 void Branch_History_Table::deallocation (void) 20 20 { 21 delete in_CLOCK;22 delete in_NRESET;21 delete in_CLOCK; 22 delete in_NRESET; 23 23 24 for (uint32_t i=0; i<_param._nb_prediction; i++) 25 { 26 delete in_PREDICT_VAL [i]; 27 delete out_PREDICT_ACK [i]; 28 delete in_PREDICT_ADDRESS [i]; 29 delete out_PREDICT_HISTORY [i]; 30 } 24 delete [] in_PREDICT_VAL ; 25 delete [] out_PREDICT_ACK ; 26 delete [] in_PREDICT_ADDRESS; 27 delete [] out_PREDICT_HISTORY; 31 28 32 delete in_PREDICT_VAL ; 33 delete out_PREDICT_ACK ; 34 delete in_PREDICT_ADDRESS; 35 delete out_PREDICT_HISTORY; 36 37 for (uint32_t i=0; i<_param._nb_branch_complete; i++) 38 { 39 delete in_BRANCH_COMPLETE_VAL [i]; 40 delete out_BRANCH_COMPLETE_ACK [i]; 41 delete in_BRANCH_COMPLETE_ADDRESS [i]; 42 delete in_BRANCH_COMPLETE_HISTORY [i]; 43 delete in_BRANCH_COMPLETE_DIRECTION[i]; 44 } 45 delete in_BRANCH_COMPLETE_VAL ; 46 delete out_BRANCH_COMPLETE_ACK ; 47 delete in_BRANCH_COMPLETE_ADDRESS; 48 delete in_BRANCH_COMPLETE_HISTORY; 49 delete in_BRANCH_COMPLETE_DIRECTION; 29 delete [] in_BRANCH_COMPLETE_VAL ; 30 delete [] out_BRANCH_COMPLETE_ACK ; 31 delete [] in_BRANCH_COMPLETE_ADDRESS; 32 delete [] in_BRANCH_COMPLETE_HISTORY; 33 delete [] in_BRANCH_COMPLETE_DIRECTION; 50 34 51 35 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 52 36 delete component_Shifter; 53 37 delete component_RegisterFile; 38 39 delete _component; 54 40 }; 55 41 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_vhdl.cpp
r2 r42 21 21 void Branch_History_Table::vhdl (void) 22 22 { 23 Vhdl vhdl (_name);23 Vhdl * vhdl = new Vhdl (_name); 24 24 25 vhdl .set_library_work (_name + "_Pack");26 vhdl .set_library_work (_name + "_RegisterFile_Pack");27 vhdl .set_library_work (_name + "_Shifter_Pack");25 vhdl->set_library_work (_name + "_Pack"); 26 vhdl->set_library_work (_name + "_RegisterFile_Pack"); 27 vhdl->set_library_work (_name + "_Shifter_Pack"); 28 28 29 29 vhdl_port (vhdl); … … 32 32 vhdl_body (vhdl); 33 33 34 vhdl.generate_file(); 34 vhdl->generate_file(); 35 36 delete vhdl; 35 37 }; 36 38 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_vhdl_body.cpp
r15 r42 18 18 19 19 20 void Branch_History_Table::vhdl_body (Vhdl & vhdl)20 void Branch_History_Table::vhdl_body (Vhdl * & vhdl) 21 21 { 22 // vhdl .set_body ("-- Output : always at '1'");22 // vhdl->set_body ("-- Output : always at '1'"); 23 23 // for (uint32_t i=0; i<_param._nb_branch_complete; i++) 24 // vhdl .set_body ("out_BRANCH_COMPLETE_ACK_"+toString(i)+" <= '1';");24 // vhdl->set_body ("out_BRANCH_COMPLETE_ACK_"+toString(i)+" <= '1';"); 25 25 // for (uint32_t i=0; i<_param._nb_prediction ; i++) 26 // vhdl .set_body ("out_PREDICT_ACK_"+toString(i)+" <= '1';");27 // vhdl .set_body ("");26 // vhdl->set_body ("out_PREDICT_ACK_"+toString(i)+" <= '1';"); 27 // vhdl->set_body (""); 28 28 29 29 list<string> list_port_map; … … 31 31 for (uint32_t i=0; i<_param._nb_branch_complete; i++) 32 32 { 33 vhdl .set_body_component_port_map (list_port_map," in_SHIFTER_DATA_"+toString(i)+" "," in_BRANCH_COMPLETE_HISTORY_"+toString(i));34 vhdl .set_body_component_port_map (list_port_map," in_SHIFTER_CARRY_IN_"+toString(i)+" "," in_BRANCH_COMPLETE_DIRECTION_"+toString(i));35 vhdl .set_body_component_port_map (list_port_map,"out_SHIFTER_DATA_"+toString(i)+" ","signal_BRANCH_COMPLETE_HISTORY_"+toString(i));33 vhdl->set_body_component_port_map (list_port_map," in_SHIFTER_"+toString(i)+"_DATA "," in_BRANCH_COMPLETE_"+toString(i)+"_HISTORY" ); 34 vhdl->set_body_component_port_map (list_port_map," in_SHIFTER_"+toString(i)+"_CARRY_IN "," in_BRANCH_COMPLETE_"+toString(i)+"_DIRECTION"); 35 vhdl->set_body_component_port_map (list_port_map,"out_SHIFTER_"+toString(i)+"_DATA ","signal_BRANCH_COMPLETE_"+toString(i)+"_HISTORY" ); 36 36 } 37 37 38 vhdl .set_body_component ("component_Shifter",_name+"_Shifter",list_port_map);38 vhdl->set_body_component ("component_Shifter",_name+"_Shifter",list_port_map); 39 39 40 40 list_port_map.clear(); 41 vhdl .set_body_component_port_map (list_port_map,"in_CLOCK","in_CLOCK");42 vhdl .set_body_component_port_map (list_port_map,"in_NRESET","in_NRESET");41 vhdl->set_body_component_port_map (list_port_map,"in_CLOCK","in_CLOCK"); 42 vhdl->set_body_component_port_map (list_port_map,"in_NRESET","in_NRESET"); 43 43 44 44 for (uint32_t i=0; i<_param._nb_prediction; i++) 45 45 { 46 vhdl .set_body_component_port_map (list_port_map," in_READ_VAL_"+toString(i)+" "," in_PREDICT_VAL_"+toString(i));47 vhdl .set_body_component_port_map (list_port_map,"out_READ_ACK_"+toString(i)+" ","out_PREDICT_ACK_"+toString(i));48 vhdl .set_body_component_port_map (list_port_map," in_READ_ADDRESS_"+toString(i)+" "," in_PREDICT_ADDRESS_"+toString(i));49 vhdl .set_body_component_port_map (list_port_map,"out_READ_DATA_"+toString(i)+" ","out_PREDICT_HISTORY_"+toString(i));46 vhdl->set_body_component_port_map (list_port_map," in_READ_"+toString(i)+"_VAL "," In_PREDICT_"+toString(i)+"_VAL"); 47 vhdl->set_body_component_port_map (list_port_map,"out_READ_"+toString(i)+"_ACK ","out_PREDICT_"+toString(i)+"_ACK"); 48 vhdl->set_body_component_port_map (list_port_map," in_READ_"+toString(i)+"_ADDRESS "," in_PREDICT_"+toString(i)+"_ADDRESS"); 49 vhdl->set_body_component_port_map (list_port_map,"out_READ_"+toString(i)+"_DATA ","out_PREDICT_"+toString(i)+"_HISTORY"); 50 50 } 51 51 52 52 for (uint32_t i=0; i<_param._nb_branch_complete; i++) 53 53 { 54 vhdl .set_body_component_port_map (list_port_map," in_WRITE_VAL_"+toString(i)+" "," in_BRANCH_COMPLETE_VAL_"+toString(i)+"");55 vhdl .set_body_component_port_map (list_port_map,"out_WRITE_ACK_"+toString(i)+" "," out_BRANCH_COMPLETE_ACK_"+toString(i)+"");56 vhdl .set_body_component_port_map (list_port_map," in_WRITE_ADDRESS_"+toString(i)+""," in_BRANCH_COMPLETE_ADDRESS_"+toString(i));57 vhdl .set_body_component_port_map (list_port_map," in_WRITE_DATA_"+toString(i)+" ","signal_BRANCH_COMPLETE_HISTORY_"+toString(i));54 vhdl->set_body_component_port_map (list_port_map," in_WRITE_"+toString(i)+"_VAL "," in_BRANCH_COMPLETE_"+toString(i)+"_VAL"); 55 vhdl->set_body_component_port_map (list_port_map,"out_WRITE_"+toString(i)+"_ACK "," out_BRANCH_COMPLETE_"+toString(i)+"_ACK"); 56 vhdl->set_body_component_port_map (list_port_map," in_WRITE_"+toString(i)+"_ADDRESS"," in_BRANCH_COMPLETE_"+toString(i)+"_ADDRESS"); 57 vhdl->set_body_component_port_map (list_port_map," in_WRITE_"+toString(i)+"_DATA ","signal_BRANCH_COMPLETE_"+toString(i)+"_HISTORY"); 58 58 } 59 vhdl .set_body_component ("component_RegisterFile",_name+"_RegisterFile",list_port_map);59 vhdl->set_body_component ("component_RegisterFile",_name+"_RegisterFile",list_port_map); 60 60 }; 61 61 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_vhdl_port.cpp
r15 r42 18 18 19 19 20 void Branch_History_Table::vhdl_port (Vhdl & vhdl)20 void Branch_History_Table::vhdl_port (Vhdl * & vhdl) 21 21 { 22 vhdl.set_port (" in_CLOCK" , IN, 1); 23 vhdl.set_port (" in_NRESET", IN, 1); 24 25 for (uint32_t i=0; i<_param._nb_prediction; i++) 26 { 27 vhdl.set_port(" in_PREDICT_VAL_"+toString(i)+" ", IN, 1); 28 vhdl.set_port("out_PREDICT_ACK_"+toString(i)+" ",OUT, 1); 29 vhdl.set_port(" in_PREDICT_ADDRESS_"+toString(i)+" ", IN, static_cast<uint32_t>(ceil(log2(_param._nb_shifter)))); 30 vhdl.set_port("out_PREDICT_HISTORY_"+toString(i)+" ",OUT, _param._size_shifter); 31 } 32 for (uint32_t i=0; i<_param._nb_branch_complete; i++) 33 { 34 vhdl.set_port (" in_BRANCH_COMPLETE_VAL_"+toString(i)+" ", IN, 1); 35 vhdl.set_port ("out_BRANCH_COMPLETE_ACK_"+toString(i)+" ",OUT, 1); 36 vhdl.set_port (" in_BRANCH_COMPLETE_ADDRESS_"+toString(i)+" ", IN, static_cast<uint32_t>(ceil(log2(_param._nb_shifter)))); 37 vhdl.set_port (" in_BRANCH_COMPLETE_HISTORY_"+toString(i)+" ", IN, _param._size_shifter); 38 vhdl.set_port (" in_BRANCH_COMPLETE_DIRECTION_"+toString(i)+"", IN, 1); 39 } 22 _interfaces->set_port(vhdl); 40 23 }; 41 24 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_vhdl_signal.cpp
r3 r42 17 17 namespace branch_history_table { 18 18 19 void Branch_History_Table::vhdl_signal (Vhdl & vhdl)19 void Branch_History_Table::vhdl_signal (Vhdl * & vhdl) 20 20 { 21 21 for (uint32_t i=0; i<_param._nb_branch_complete; i++) 22 vhdl .set_signal ("signal_BRANCH_COMPLETE_HISTORY_"+toString(i), _param._size_shifter);22 vhdl->set_signal ("signal_BRANCH_COMPLETE_"+toString(i)+"_HISTORY", _param._size_shifter); 23 23 }; 24 24 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_vhdl_testbench_transition.cpp
r15 r42 20 20 void Branch_History_Table::vhdl_testbench_transition (void) 21 21 { 22 // In order with file Branch_History_Table_vhdl_testbench_port.cpp 23 #ifndef SYSTEMCASS_SPECIFIC 24 sc_cycle(0); 25 #endif 22 sc_start(0); 26 23 27 _vhdl_testbench->add_input (PORT_READ( in_NRESET)); 28 29 for (uint32_t i=0; i<_param._nb_prediction; i++) 30 { 31 _vhdl_testbench->add_input (PORT_READ( in_PREDICT_VAL [i])); 32 _vhdl_testbench->add_output (PORT_READ(component_RegisterFile->out_READ_ACK [i])); 33 _vhdl_testbench->add_input (PORT_READ( in_PREDICT_ADDRESS [i])); 34 _vhdl_testbench->add_output (PORT_READ(component_RegisterFile->out_READ_DATA [i])); 35 //_vhdl_testbench->add_output (PORT_READ(out_PREDICT_HISTORY [i])); 36 } 37 38 for (uint32_t i=0; i<_param._nb_branch_complete; i++) 39 { 40 _vhdl_testbench->add_input (PORT_READ( in_BRANCH_COMPLETE_VAL [i])); 41 _vhdl_testbench->add_output (PORT_READ(component_RegisterFile->out_WRITE_ACK [i])); 42 _vhdl_testbench->add_input (PORT_READ( in_BRANCH_COMPLETE_ADDRESS [i])); 43 _vhdl_testbench->add_input (PORT_READ( in_BRANCH_COMPLETE_HISTORY [i])); 44 _vhdl_testbench->add_input (PORT_READ( in_BRANCH_COMPLETE_DIRECTION[i])); 45 } 46 47 // add_test : 48 // - True : the cycle must be compare with the output of systemC 49 // - False : no test 50 _vhdl_testbench->add_test(true); 51 52 _vhdl_testbench->new_cycle (); // always at the end 24 _interfaces->testbench(); 53 25 }; 54 26 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_vhdl_type.cpp
r2 r42 18 18 19 19 20 void Branch_History_Table::vhdl_type (Vhdl & vhdl)20 void Branch_History_Table::vhdl_type (Vhdl * & vhdl) 21 21 { 22 22 }; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/SelfTest/configuration.cfg
r2 r42 1 1 Pattern_History_Table 2 28 *2 # size_counter3 264 *4 # nb_counter4 12 +1 # nb_prediction5 12 +1 # nb_branch_complete2 8 8 *2 # size_counter 3 64 64 *4 # nb_counter 4 2 2 +1 # nb_prediction 5 2 2 +1 # nb_branch_complete -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/SelfTest/mkf.info
r15 r42 1 2 # Pattern_History_Table_0 3 target_dep all Pattern_History_Table_0.ngc 4 target_dep Pattern_History_Table_0.ngc Pattern_History_Table_0.prj 5 target_dep Pattern_History_Table_0.prj Pattern_History_Table_0_Counter_Pack.vhdl Pattern_History_Table_0_Counter.vhdl Pattern_History_Table_0_Pack.vhdl Pattern_History_Table_0_RegisterFile_Pack.vhdl Pattern_History_Table_0_RegisterFile.vhdl Pattern_History_Table_0.vhdl 6 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/SelfTest/src/test.cpp
r15 r42 7 7 */ 8 8 9 #define NB_ITERATION 10249 #define NB_ITERATION 512 10 10 11 11 #include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/SelfTest/include/test.h" … … 93 93 94 94 sc_start(0); 95 _Pattern_History_Table->vhdl_testbench_label("Initialisation");96 95 cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} Initialisation" << endl; 97 96 … … 127 126 sc_start(0); 128 127 129 _Pattern_History_Table->vhdl_testbench_label("Loop of Test");130 128 cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} Loop of Test" << endl; 131 129 132 130 for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++) 133 131 { 134 _Pattern_History_Table->vhdl_testbench_label("Iteration "+toString(iteration));135 132 num_port_branch_complete = rand() % param._nb_branch_complete; 136 133 num_port_predict = rand() % param._nb_prediction ; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/include/Pattern_History_Table.h
r15 r42 29 29 #include "Behavioural/include/Vhdl.h" 30 30 #endif 31 #ifdef VHDL_TESTBENCH 32 #include "Behavioural/include/Vhdl_Testbench.h" 33 #endif 31 #include "Behavioural/include/Component.h" 34 32 35 33 using namespace std; … … 62 60 #endif 63 61 64 #ifdef VHDL_TESTBENCH 65 private : Vhdl_Testbench * _vhdl_testbench; 66 #endif 62 public : Component * _component; 63 private : Interfaces * _interfaces; 67 64 68 65 #ifdef SYSTEMC … … 125 122 public : string statistics (uint32_t depth); 126 123 #endif 127 128 124 #if VHDL 129 125 public : void vhdl (void); 130 private : void vhdl_port (Vhdl & vhdl); 131 private : void vhdl_declaration (Vhdl & vhdl); 132 private : void vhdl_body (Vhdl & vhdl); 126 private : void vhdl_declaration (Vhdl * & vhdl); 127 private : void vhdl_body (Vhdl * & vhdl); 133 128 #endif 134 135 129 #ifdef VHDL_TESTBENCH 136 private : void vhdl_testbench_port (void);137 130 private : void vhdl_testbench_transition (void); 138 131 #endif 139 public : void vhdl_testbench_label (string label);140 132 }; 141 133 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table.cpp
r15 r42 33 33 { 34 34 log_printf(FUNC,Pattern_History_Table,"Pattern_History_Table","Begin"); 35 35 36 #ifdef SYSTEMC 37 allocation (); 38 #endif 39 36 40 #ifdef STATISTICS 37 41 // Allocation of statistics … … 39 43 param_statistics , 40 44 param); 41 #endif42 43 #ifdef VHDL_TESTBENCH44 // Creation of a testbench45 // -> port46 // -> clock's signals47 _vhdl_testbench = new Vhdl_Testbench (_name);48 vhdl_testbench_port ();49 _vhdl_testbench->set_clock ("in_CLOCK",true);50 45 #endif 51 46 … … 56 51 57 52 #ifdef SYSTEMC 58 allocation ();59 60 53 // // Constant 61 54 // for (uint32_t i=0; i<_param._nb_prediction ; i++) … … 82 75 log_printf(FUNC,Pattern_History_Table,"~Pattern_History_Table","Begin"); 83 76 84 #ifdef VHDL_TESTBENCH85 // generate the test bench86 _vhdl_testbench->generate_file();87 delete _vhdl_testbench;88 #endif89 90 77 #ifdef STATISTICS 91 78 _stat->generate_file(statistics(0)); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_allocation.cpp
r15 r42 20 20 void Pattern_History_Table::allocation (void) 21 21 { 22 string rename;23 24 22 log_printf(FUNC,Pattern_History_Table,"allocation","Begin"); 25 23 26 in_CLOCK = new SC_CLOCK ("in_CLOCK"); 27 in_NRESET = new SC_IN (Tcontrol_t) ("in_NRESET"); 28 24 _component = new Component (); 25 26 Entity * entity = _component->set_entity (_name 27 ,"Pattern_History_Table" 28 #ifdef POSITION 29 ,MIXTE 30 #endif 31 ); 32 33 _interfaces = entity->set_interfaces(); 34 35 // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 36 { 37 Interface * interface = _interfaces->set_interface("" 38 #ifdef POSITION 39 , IN 40 , SOUTH 41 , "Generalist interface" 42 #endif 43 ); 44 45 in_CLOCK = interface->set_signal_clk ("clock" ,1); 46 in_NRESET = interface->set_signal_in <Tcontrol_t> ("nreset",1,RESET_VHDL_YES); 47 } 48 49 // ~~~~~[ Interface : "predict" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 29 50 in_PREDICT_VAL = new SC_IN (Tcontrol_t) * [_param._nb_prediction]; 30 51 out_PREDICT_ACK = new SC_OUT(Tcontrol_t) * [_param._nb_prediction]; … … 34 55 for (uint32_t i=0; i<_param._nb_prediction; i++) 35 56 { 36 rename = "in_PREDICT_VAL[" +toString(i)+"]"; 37 in_PREDICT_VAL [i] = new SC_IN (Tcontrol_t) (rename.c_str()); 38 39 rename = "out_PREDICT_ACK[" +toString(i)+"]"; 40 out_PREDICT_ACK [i] = new SC_OUT(Tcontrol_t) (rename.c_str()); 41 42 rename = "in_PREDICT_ADDRESS["+toString(i)+"]"; 43 in_PREDICT_ADDRESS [i] = new SC_IN (Taddress_t) (rename.c_str()); 44 45 rename = "out_PREDICT_HISTORY["+toString(i)+"]"; 46 out_PREDICT_HISTORY [i] = new SC_OUT(Thistory_t) (rename.c_str()); 47 } 57 Interface_fifo * interface = _interfaces->set_interface("predict_"+toString(i) 58 #ifdef POSITION 59 , IN 60 , WEST 61 , "Interface Predict" 62 #endif 63 ); 64 65 in_PREDICT_VAL [i] = interface->set_signal_valack_in ("val" , VAL); 66 out_PREDICT_ACK [i] = interface->set_signal_valack_out ("ack" , ACK); 67 in_PREDICT_ADDRESS [i] = interface->set_signal_in <Taddress_t> ("address", static_cast<uint32_t>(ceil(log2(_param._nb_counter)))); 68 out_PREDICT_HISTORY [i] = interface->set_signal_out <Thistory_t> ("history", _param._size_counter); 69 } 70 71 // ~~~~~[ Interface : "branch_complete" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 48 72 49 73 in_BRANCH_COMPLETE_VAL = new SC_IN (Tcontrol_t) * [_param._nb_branch_complete]; … … 52 76 in_BRANCH_COMPLETE_HISTORY = new SC_IN (Thistory_t) * [_param._nb_branch_complete]; 53 77 in_BRANCH_COMPLETE_DIRECTION = new SC_IN (Tcontrol_t) * [_param._nb_branch_complete]; 54 signal_BRANCH_COMPLETE_HISTORY = new SC_SIGNAL (Thistory_t) * [_param._nb_branch_complete];55 78 56 79 for (uint32_t i=0; i<_param._nb_branch_complete; i++) 57 80 { 58 rename = "in_BRANCH_COMPLETE_VAL[" +toString(i)+"]"; 59 in_BRANCH_COMPLETE_VAL [i] = new SC_IN (Tcontrol_t) (rename.c_str()); 60 61 rename = "out_BRANCH_COMPLETE_ACK[" +toString(i)+"]"; 62 out_BRANCH_COMPLETE_ACK [i] = new SC_OUT(Tcontrol_t) (rename.c_str()); 63 64 rename = "in_BRANCH_COMPLETE_ADDRESS["+toString(i)+"]"; 65 in_BRANCH_COMPLETE_ADDRESS [i] = new SC_IN (Taddress_t) (rename.c_str()); 66 67 rename = "in_BRANCH_COMPLETE_HISTORY["+toString(i)+"]"; 68 in_BRANCH_COMPLETE_HISTORY [i] = new SC_IN (Thistory_t) (rename.c_str()); 69 70 rename = "in_BRANCH_COMPLETE_DIRECTION[" +toString(i)+"]"; 71 in_BRANCH_COMPLETE_DIRECTION [i] = new SC_IN (Tcontrol_t) (rename.c_str()); 72 73 rename = "signal_BRANCH_COMPLETE_HISTORY["+toString(i)+"]"; 74 signal_BRANCH_COMPLETE_HISTORY [i] = new SC_SIGNAL (Thistory_t) (rename.c_str()); 75 76 } 77 81 Interface_fifo * interface = _interfaces->set_interface("branch_complete_"+toString(i) 82 #ifdef POSITION 83 , IN 84 , EAST 85 , "Interface branch complete" 86 #endif 87 ); 88 89 in_BRANCH_COMPLETE_VAL [i] = interface->set_signal_valack_in ("val" , VAL); 90 out_BRANCH_COMPLETE_ACK [i] = interface->set_signal_valack_out ("ack" , ACK); 91 in_BRANCH_COMPLETE_ADDRESS [i] = interface->set_signal_in <Taddress_t> ("address" , static_cast<uint32_t>(ceil(log2(_param._nb_counter)))); 92 in_BRANCH_COMPLETE_HISTORY [i] = interface->set_signal_in <Thistory_t> ("history" , _param._size_counter); 93 in_BRANCH_COMPLETE_DIRECTION [i] = interface->set_signal_in <Tcontrol_t> ("direction", 1); 94 } 95 78 96 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 79 97 string name_component; 98 80 99 // =====[ component_Counter ]========================================= 81 100 82 101 name_component = _name+"_Counter"; 83 102 84 component_Counter = new morpheo::behavioural::generic::counter::Counter (name_component.c_str() ,103 component_Counter = new morpheo::behavioural::generic::counter::Counter (name_component.c_str() 85 104 #ifdef STATISTICS 86 _param_statistics , 87 #endif 88 *(_param._param_counter) ); 89 90 91 // Instantiation 105 ,_param_statistics 106 #endif 107 ,*(_param._param_counter)); 108 109 _component->set_component (component_Counter->_component 110 #ifdef POSITION 111 , 25 112 , 25 113 , 10 114 , 10 115 #endif 116 ); 117 118 // =====[ component_RegisterFile ]==================================== 119 120 name_component = _name+"_RegisterFile"; 121 122 component_RegisterFile = new morpheo::behavioural::generic::registerfile::registerfile_monolithic::RegisterFile_Monolithic(name_component.c_str(), 123 #ifdef STATISTICS 124 _param_statistics , 125 #endif 126 *(_param._param_registerfile)); 127 128 _component->set_component (component_RegisterFile->_component 129 #ifdef POSITION 130 , 75 131 , 75 132 , 10 133 , 10 134 #endif 135 ); 136 137 // ~~~~~[ Component - Instanciation ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 138 139 // =====[ component_RegisterFile - Instanciation ]==================== 140 141 #ifdef POSITION 142 _component->interface_map (_name+"_RegisterFile","", 143 _name ,""); 144 #endif 145 146 _component->port_map(_name+"_RegisterFile", "in_CLOCK" , _name,"in_CLOCK" ); 147 _component->port_map(_name+"_RegisterFile", "in_NRESET", _name,"in_NRESET"); 148 149 for (uint32_t i=0; i<_param._nb_prediction; i++) 150 { 151 #ifdef POSITION 152 _component->interface_map (_name+"_RegisterFile","read_" +toString(i), 153 _name ,"predict_"+toString(i)); 154 #endif 155 156 _component->port_map(_name+"_RegisterFile", "in_READ_"+toString(i)+"_VAL" , _name, "in_PREDICT_"+toString(i)+"_VAL" ); 157 _component->port_map(_name+"_RegisterFile","out_READ_"+toString(i)+"_ACK" , _name,"out_PREDICT_"+toString(i)+"_ACK" ); 158 _component->port_map(_name+"_RegisterFile", "in_READ_"+toString(i)+"_ADDRESS", _name, "in_PREDICT_"+toString(i)+"_ADDRESS"); 159 _component->port_map(_name+"_RegisterFile","out_READ_"+toString(i)+"_DATA" , _name,"out_PREDICT_"+toString(i)+"_HISTORY"); 160 } 161 162 for (uint32_t i=0; i<_param._nb_branch_complete; i++) 163 { 164 #ifdef POSITION 165 _component->interface_map (_name+"_RegisterFile","write_" +toString(i), 166 _name+"_Counter" ,"counter_"+toString(i)); 167 #endif 168 169 _component->port_map(_name+"_RegisterFile", "in_WRITE_"+toString(i)+"_VAL" , _name , "in_BRANCH_COMPLETE_"+toString(i)+"_VAL" ); 170 _component->port_map(_name+"_RegisterFile","out_WRITE_"+toString(i)+"_ACK" , _name ,"out_BRANCH_COMPLETE_"+toString(i)+"_ACK" ); 171 _component->port_map(_name+"_RegisterFile", "in_WRITE_"+toString(i)+"_ADDRESS", _name , "in_BRANCH_COMPLETE_"+toString(i)+"_ADDRESS"); 172 _component->port_map(_name+"_RegisterFile", "in_WRITE_"+toString(i)+"_DATA" , _name+"_Counter","out_COUNTER_" +toString(i)+"_DATA"); 173 } 174 175 // =====[ component_Counter - Instanciation ]========================= 176 92 177 #if (defined(STATISTICS) || defined (VHDL_TESTBENCH)) 93 (*(component_Counter->in_CLOCK)) (*(in_CLOCK)); 178 179 #ifdef POSITION 180 _component->interface_map (_name+"_Counter","", 181 _name ,""); 182 #endif 183 184 _component->port_map(_name+"_Counter", "in_CLOCK" , _name,"in_CLOCK" ); 185 _component->port_map(_name+"_Counter", "in_NRESET", _name,"in_NRESET"); 186 94 187 #endif 95 188 96 189 for (uint32_t i=0; i<_param._nb_branch_complete; i++) 97 190 { 98 (*(component_Counter-> in_COUNTER_DATA [i])) (*( in_BRANCH_COMPLETE_HISTORY [i])); 99 (*(component_Counter-> in_COUNTER_ADDSUB [i])) (*( in_BRANCH_COMPLETE_DIRECTION [i])); 100 (*(component_Counter->out_COUNTER_DATA [i])) (*(signal_BRANCH_COMPLETE_HISTORY [i])); 101 } 102 103 // =====[ component_RegisterFile ]==================================== 104 105 name_component = _name+"_RegisterFile"; 106 107 component_RegisterFile = new morpheo::behavioural::generic::registerfile::registerfile_monolithic::RegisterFile_Monolithic (name_component.c_str(), 108 #ifdef STATISTICS 109 _param_statistics , 110 #endif 111 *(_param._param_registerfile)); 112 113 // Instantiation 114 (*(component_RegisterFile->in_CLOCK)) (*(in_CLOCK)); 115 (*(component_RegisterFile->in_NRESET)) (*(in_NRESET)); 116 117 for (uint32_t i=0; i<_param._nb_prediction; i++) 118 { 119 (*(component_RegisterFile-> in_READ_VAL [i])) (*( in_PREDICT_VAL [i])); 120 (*(component_RegisterFile->out_READ_ACK [i])) (*(out_PREDICT_ACK [i])); 121 (*(component_RegisterFile-> in_READ_ADDRESS [i])) (*( in_PREDICT_ADDRESS [i])); 122 (*(component_RegisterFile->out_READ_DATA [i])) (*(out_PREDICT_HISTORY [i])); 123 } 124 125 for (uint32_t i=0; i<_param._nb_branch_complete; i++) 126 { 127 (*(component_RegisterFile-> in_WRITE_VAL [i])) (*( in_BRANCH_COMPLETE_VAL [i])); 128 (*(component_RegisterFile->out_WRITE_ACK [i])) (*( out_BRANCH_COMPLETE_ACK [i])); 129 (*(component_RegisterFile-> in_WRITE_ADDRESS [i])) (*( in_BRANCH_COMPLETE_ADDRESS [i])); 130 (*(component_RegisterFile-> in_WRITE_DATA [i])) (*(signal_BRANCH_COMPLETE_HISTORY [i])); 131 } 191 #ifdef POSITION 192 _component->interface_map (_name+"_Counter","counter_"+toString(i), 193 _name ,"branch_complete_"+toString(i)); 194 195 #endif 196 197 _component->port_map(_name+"_Counter", "in_COUNTER_" +toString(i)+"_DATA" , _name , "in_BRANCH_COMPLETE_"+toString(i)+"_HISTORY"); 198 _component->port_map(_name+"_Counter", "in_COUNTER_" +toString(i)+"_ADDSUB" , _name , "in_BRANCH_COMPLETE_"+toString(i)+"_DIRECTION"); 199 _component->port_map(_name+"_Counter", "out_COUNTER_"+toString(i)+"_DATA" , _name+"_RegisterFile", "in_WRITE_"+toString(i)+"_DATA"); 200 } 201 202 #ifdef POSITION 203 _component->generate_file(); 204 #endif 132 205 133 206 log_printf(FUNC,Pattern_History_Table,"allocation","End"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_deallocation.cpp
r15 r42 22 22 log_printf(FUNC,Pattern_History_Table,"deallocation","Begin"); 23 23 24 delete in_CLOCK;25 delete in_NRESET;24 delete in_CLOCK; 25 delete in_NRESET; 26 26 27 for (uint32_t i=0; i<_param._nb_prediction; i++) 28 { 29 delete in_PREDICT_VAL [i]; 30 delete out_PREDICT_ACK [i]; 31 delete in_PREDICT_ADDRESS [i]; 32 delete out_PREDICT_HISTORY [i]; 33 } 27 delete [] in_PREDICT_VAL ; 28 delete [] out_PREDICT_ACK ; 29 delete [] in_PREDICT_ADDRESS; 30 delete [] out_PREDICT_HISTORY; 34 31 35 delete in_PREDICT_VAL ; 36 delete out_PREDICT_ACK ; 37 delete in_PREDICT_ADDRESS; 38 delete out_PREDICT_HISTORY; 39 40 for (uint32_t i=0; i<_param._nb_branch_complete; i++) 41 { 42 delete in_BRANCH_COMPLETE_VAL [i]; 43 delete out_BRANCH_COMPLETE_ACK [i]; 44 delete in_BRANCH_COMPLETE_ADDRESS [i]; 45 delete in_BRANCH_COMPLETE_HISTORY [i]; 46 delete in_BRANCH_COMPLETE_DIRECTION [i]; 47 } 48 delete in_BRANCH_COMPLETE_VAL ; 49 delete out_BRANCH_COMPLETE_ACK ; 50 delete in_BRANCH_COMPLETE_ADDRESS; 51 delete in_BRANCH_COMPLETE_HISTORY; 52 delete in_BRANCH_COMPLETE_DIRECTION; 32 delete [] in_BRANCH_COMPLETE_VAL ; 33 delete [] out_BRANCH_COMPLETE_ACK ; 34 delete [] in_BRANCH_COMPLETE_ADDRESS; 35 delete [] in_BRANCH_COMPLETE_HISTORY; 36 delete [] in_BRANCH_COMPLETE_DIRECTION; 53 37 54 38 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 55 39 delete component_Counter; 56 40 delete component_RegisterFile; 41 42 delete _component; 57 43 58 44 log_printf(FUNC,Pattern_History_Table,"deallocation","End"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_vhdl.cpp
r2 r42 22 22 { 23 23 log_printf(FUNC,Pattern_History_Table,"vhdl","Begin"); 24 Vhdl vhdl (_name);24 Vhdl * vhdl = new Vhdl (_name); 25 25 26 vhdl.set_library_work (_name + "_Pack"); 27 vhdl.set_library_work (_name + "_RegisterFile_Pack"); 28 vhdl.set_library_work (_name + "_Counter_Pack"); 26 _interfaces->set_port(vhdl); 27 _component->vhdl_instance(vhdl); 29 28 30 vhdl_port (vhdl);31 29 vhdl_declaration (vhdl); 32 30 vhdl_body (vhdl); 33 31 34 vhdl.generate_file(); 32 vhdl->generate_file(); 33 34 delete vhdl; 35 35 36 log_printf(FUNC,Pattern_History_Table,"vhdl","End"); 36 37 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_vhdl_body.cpp
r15 r42 18 18 19 19 20 void Pattern_History_Table::vhdl_body (Vhdl & vhdl)20 void Pattern_History_Table::vhdl_body (Vhdl * & vhdl) 21 21 { 22 22 log_printf(FUNC,Pattern_History_Table,"vhdl_body","Begin"); 23 23 24 // vhdl .set_body ("-- Output : always at '1'");24 // vhdl->set_body ("-- Output : always at '1'"); 25 25 // for (uint32_t i=0; i<_param._nb_branch_complete; i++) 26 // vhdl .set_body ("out_BRANCH_COMPLETE_ACK_"+toString(i)+" <= '1';");26 // vhdl->set_body ("out_BRANCH_COMPLETE_ACK_"+toString(i)+" <= '1';"); 27 27 // for (uint32_t i=0; i<_param._nb_prediction ; i++) 28 // vhdl.set_body ("out_PREDICT_ACK_"+toString(i)+" <= '1';"); 29 // vhdl.set_body (""); 30 31 list<string> list_port_map; 32 33 for (uint32_t i=0; i<_param._nb_branch_complete; i++) 34 { 35 vhdl.set_body_component_port_map (list_port_map," in_COUNTER_DATA_"+toString(i)+" "," in_BRANCH_COMPLETE_HISTORY_"+toString(i)); 36 vhdl.set_body_component_port_map (list_port_map," in_COUNTER_ADDSUB_"+toString(i)+" "," in_BRANCH_COMPLETE_DIRECTION_"+toString(i) ); 37 vhdl.set_body_component_port_map (list_port_map,"out_COUNTER_DATA_"+toString(i)+" ","signal_BRANCH_COMPLETE_HISTORY_"+toString(i)); 38 } 39 vhdl.set_body_component ("component_Counter",_name+"_Counter",list_port_map); 40 41 42 list_port_map.clear(); 43 vhdl.set_body_component_port_map (list_port_map,"in_CLOCK ","in_CLOCK "); 44 vhdl.set_body_component_port_map (list_port_map,"in_NRESET","in_NRESET"); 45 46 for (uint32_t i=0; i<_param._nb_prediction; i++) 47 { 48 vhdl.set_body_component_port_map (list_port_map," in_READ_VAL_"+toString(i)+" "," in_PREDICT_VAL_"+toString(i)); 49 vhdl.set_body_component_port_map (list_port_map,"out_READ_ACK_"+toString(i)+" ","out_PREDICT_ACK_"+toString(i)); 50 vhdl.set_body_component_port_map (list_port_map," in_READ_ADDRESS_"+toString(i)+" "," in_PREDICT_ADDRESS_"+toString(i)); 51 vhdl.set_body_component_port_map (list_port_map,"out_READ_DATA_"+toString(i)+" ","out_PREDICT_HISTORY_"+toString(i)); 52 } 53 54 for (uint32_t i=0; i<_param._nb_branch_complete; i++) 55 { 56 vhdl.set_body_component_port_map (list_port_map," in_WRITE_VAL_"+toString(i)+" "," in_BRANCH_COMPLETE_VAL_"+toString(i)+""); 57 vhdl.set_body_component_port_map (list_port_map,"out_WRITE_ACK_"+toString(i)+" "," out_BRANCH_COMPLETE_ACK_"+toString(i)+""); 58 vhdl.set_body_component_port_map (list_port_map," in_WRITE_ADDRESS_"+toString(i)+""," in_BRANCH_COMPLETE_ADDRESS_"+toString(i)); 59 vhdl.set_body_component_port_map (list_port_map," in_WRITE_DATA_"+toString(i)+" ","signal_BRANCH_COMPLETE_HISTORY_"+toString(i)); 60 } 61 vhdl.set_body_component ("component_RegisterFile",_name+"_RegisterFile",list_port_map); 28 // vhdl->set_body ("out_PREDICT_ACK_"+toString(i)+" <= '1';"); 29 // vhdl->set_body (""); 62 30 63 31 log_printf(FUNC,Pattern_History_Table,"vhdl_body","End"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_vhdl_port.cpp
r15 r42 18 18 19 19 20 void Pattern_History_Table::vhdl_port (Vhdl& vhdl)21 {22 log_printf(FUNC,Pattern_History_Table,"vhdl_port","Begin");20 // void Pattern_History_Table::vhdl_port (Vhdl * & vhdl) 21 // { 22 // log_printf(FUNC,Pattern_History_Table,"vhdl_port","Begin"); 23 23 24 vhdl.set_port (" in_CLOCK" , IN, 1); 25 vhdl.set_port (" in_NRESET", IN, 1); 24 // _interfaces->set_port(vhdl); 26 25 27 for (uint32_t i=0; i<_param._nb_prediction; i++) 28 { 29 vhdl.set_port(" in_PREDICT_VAL_"+toString(i)+" ", IN, 1); 30 vhdl.set_port("out_PREDICT_ACK_"+toString(i)+" ",OUT, 1); 31 vhdl.set_port(" in_PREDICT_ADDRESS_"+toString(i)+" ", IN, static_cast<uint32_t>(ceil(log2(_param._nb_counter)))); 32 vhdl.set_port("out_PREDICT_HISTORY_"+toString(i)+" ",OUT, _param._size_counter); 33 } 34 for (uint32_t i=0; i<_param._nb_branch_complete; i++) 35 { 36 vhdl.set_port (" in_BRANCH_COMPLETE_VAL_"+toString(i)+" ", IN, 1); 37 vhdl.set_port ("out_BRANCH_COMPLETE_ACK_"+toString(i)+" ",OUT, 1); 38 vhdl.set_port (" in_BRANCH_COMPLETE_ADDRESS_"+toString(i)+" ", IN, static_cast<uint32_t>(ceil(log2(_param._nb_counter)))); 39 vhdl.set_port (" in_BRANCH_COMPLETE_HISTORY_"+toString(i)+" ", IN, _param._size_counter); 40 vhdl.set_port (" in_BRANCH_COMPLETE_DIRECTION_"+toString(i)+"", IN, 1); 41 } 42 43 log_printf(FUNC,Pattern_History_Table,"vhdl_port","End"); 44 }; 26 // log_printf(FUNC,Pattern_History_Table,"vhdl_port","End"); 27 // }; 45 28 46 29 }; // end namespace pattern_history_table -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_vhdl_signal.cpp
r2 r42 18 18 19 19 20 void Pattern_History_Table::vhdl_declaration (Vhdl & vhdl)20 void Pattern_History_Table::vhdl_declaration (Vhdl * & vhdl) 21 21 { 22 22 log_printf(FUNC,Pattern_History_Table,"vhdl_declaration","Begin"); 23 24 for (uint32_t i=0; i<_param._nb_branch_complete; i++)25 vhdl.set_signal ("signal_BRANCH_COMPLETE_HISTORY_"+toString(i), _param._size_counter);26 23 27 24 log_printf(FUNC,Pattern_History_Table,"vhdl_declaration","End"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_vhdl_testbench_transition.cpp
r15 r42 22 22 log_printf(FUNC,Pattern_History_Table,"vhdl_testbench_transition","Begin"); 23 23 24 #ifndef SYSTEMCASS_SPECIFIC 25 sc_cycle(0); 26 #endif 24 sc_start(0); 27 25 28 // In order with file Pattern_History_Table_vhdl_testbench_port.cpp 29 // Warning : if a output depend of a subcomponent, take directly the port of subcomponent 30 // (because we have no control on the ordonnancer's policy) 31 32 _vhdl_testbench->add_input (PORT_READ( in_NRESET)); 33 34 for (uint32_t i=0; i<_param._nb_prediction; i++) 35 { 36 _vhdl_testbench->add_input (PORT_READ( in_PREDICT_VAL [i])); 37 _vhdl_testbench->add_output (PORT_READ(component_RegisterFile->out_READ_ACK [i])); 38 _vhdl_testbench->add_input (PORT_READ( in_PREDICT_ADDRESS [i])); 39 _vhdl_testbench->add_output (PORT_READ(component_RegisterFile->out_READ_DATA [i])); 40 //_vhdl_testbench->add_output (PORT_READ(out_PREDICT_HISTORY [i])); 41 } 42 43 for (uint32_t i=0; i<_param._nb_branch_complete; i++) 44 { 45 _vhdl_testbench->add_input (PORT_READ( in_BRANCH_COMPLETE_VAL [i])); 46 _vhdl_testbench->add_output (PORT_READ(component_RegisterFile->out_WRITE_ACK [i])); 47 _vhdl_testbench->add_input (PORT_READ( in_BRANCH_COMPLETE_ADDRESS [i])); 48 _vhdl_testbench->add_input (PORT_READ( in_BRANCH_COMPLETE_HISTORY [i])); 49 _vhdl_testbench->add_input (PORT_READ( in_BRANCH_COMPLETE_DIRECTION[i])); 50 } 51 52 // add_test : 53 // - True : the cycle must be compare with the output of systemC 54 // - False : no test 55 _vhdl_testbench->add_test(true); 56 57 _vhdl_testbench->new_cycle (); // always at the end 26 _interfaces->testbench(); 58 27 59 28 log_printf(FUNC,Pattern_History_Table,"vhdl_testbench_transition","End"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/SelfTest/src/test.cpp
r2 r42 44 44 *********************************************************************/ 45 45 sc_clock CLOCK ("clock", 1.0, 0.5); 46 sc_signal<Tcontrol_t> NRESET; 46 47 47 48 sc_signal<Tcontrol_t> PREDICT_BHT_ACK [param._nb_prediction]; … … 68 69 cout << "<" << name << "> Instanciation of _Two_Level_Branch_Predictor_Glue" << endl; 69 70 70 #if defined(STATISTICS) or defined(VHDL_TESTBENCH)71 71 (*(_Two_Level_Branch_Predictor_Glue->in_CLOCK)) (CLOCK); 72 #endif 72 (*(_Two_Level_Branch_Predictor_Glue->in_NRESET)) (NRESET); 73 73 74 74 for (uint32_t i=0; i<param._nb_prediction; i++) … … 125 125 126 126 sc_start(0); 127 _Two_Level_Branch_Predictor_Glue->vhdl_testbench_label("Initialisation"); 127 128 128 cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} Initialisation" << endl; 129 129 130 131 _Two_Level_Branch_Predictor_Glue->vhdl_testbench_label("Test ack"); 130 NRESET.write(1); 131 132 132 cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} Test ack" << endl; 133 133 134 134 for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++) 135 135 { 136 _Two_Level_Branch_Predictor_Glue->vhdl_testbench_label("Iteration "+toString(iteration));137 138 136 // Branch History Table 139 137 if (param._have_bht) … … 191 189 192 190 193 _Two_Level_Branch_Predictor_Glue->vhdl_testbench_label("Test address");194 191 cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} Test address" << endl; 195 192 196 193 for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++) 197 194 { 198 _Two_Level_Branch_Predictor_Glue->vhdl_testbench_label("Iteration "+toString(iteration));199 200 195 predict_address = rand()%(1<<param._size_address ); 201 196 predict_bht_history = 0; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Two_Level_Branch_Predictor_Glue.h
r5 r42 25 25 #include "Behavioural/include/Vhdl.h" 26 26 #endif 27 #ifdef VHDL_TESTBENCH 28 #include "Behavioural/include/Vhdl_Testbench.h" 29 #endif 27 #include "Behavioural/include/Component.h" 30 28 31 29 using namespace std; … … 58 56 #endif 59 57 60 #ifdef VHDL_TESTBENCH 61 private : Vhdl_Testbench * _vhdl_testbench; 62 #endif 58 public : Component * _component; 59 private : Interfaces * _interfaces; 63 60 64 61 #ifdef SYSTEMC … … 66 63 // Interface 67 64 public : SC_CLOCK * in_CLOCK ; 65 public : SC_IN (Tcontrol_t) * in_NRESET ; 68 66 69 67 public : SC_IN (Tcontrol_t) ** in_PREDICT_BHT_ACK ; … … 129 127 public : string statistics (uint32_t depth); 130 128 #endif 131 132 129 #if VHDL 133 130 public : void vhdl (void); 134 private : void vhdl_port (Vhdl & vhdl);135 private : void vhdl_declaration (Vhdl & vhdl);136 private : void vhdl_body (Vhdl & vhdl);131 private : void vhdl_port (Vhdl * & vhdl); 132 private : void vhdl_declaration (Vhdl * & vhdl); 133 private : void vhdl_body (Vhdl * & vhdl); 137 134 #endif 138 139 135 #ifdef VHDL_TESTBENCH 140 private : void vhdl_testbench_port (void);141 136 private : void vhdl_testbench_transition (void); 142 137 #endif 143 public : void vhdl_testbench_label (string label);144 138 }; 145 139 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue.cpp
r3 r42 34 34 log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"Two_Level_Branch_Predictor_Glue","Begin"); 35 35 36 #ifdef SYSTEMC 37 allocation (); 38 #endif 39 36 40 #ifdef STATISTICS 37 41 // Allocation of statistics … … 41 45 #endif 42 46 43 #ifdef VHDL_TESTBENCH44 // Creation of a testbench45 // -> port46 // -> clock's signals47 _vhdl_testbench = new Vhdl_Testbench (_name);48 vhdl_testbench_port ();49 _vhdl_testbench->set_clock ("in_CLOCK",false);50 #endif51 52 47 #ifdef VHDL 53 48 // generate the vhdl … … 56 51 57 52 #ifdef SYSTEMC 58 allocation ();59 60 53 #if defined(STATISTICS) or defined(VHDL_TESTBENCH) 61 54 SC_METHOD (transition); … … 192 185 log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"~Two_Level_Branch_Predictor_Glue","Begin"); 193 186 194 #ifdef VHDL_TESTBENCH195 // generate the test bench196 _vhdl_testbench->generate_file();197 delete _vhdl_testbench;198 #endif199 200 187 #ifdef STATISTICS 201 188 _stat->generate_file(statistics(0)); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_allocation.cpp
r2 r42 24 24 log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"allocation","Begin"); 25 25 26 #if defined(STATISTICS) or defined(VHDL_TESTBENCH) 27 in_CLOCK = new SC_CLOCK ("in_CLOCK"); 26 _component = new Component (); 27 28 Entity * entity = _component->set_entity (_name 29 ,"Two_Level_Branch_Predictor_Glue" 30 #ifdef POSITION 31 ,COMBINATORY 28 32 #endif 33 ); 29 34 35 _interfaces = entity->set_interfaces(); 36 37 // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 38 { 39 Interface * interface = _interfaces->set_interface("" 40 #ifdef POSITION 41 , IN 42 , SOUTH 43 , "Generalist interface" 44 #endif 45 ); 46 47 in_CLOCK = interface->set_signal_clk ("clock" ,1,CLOCK_VHDL_NO); 48 in_NRESET = interface->set_signal_in <Tcontrol_t> ("nreset",1,RESET_VHDL_NO); 49 } 50 51 // ~~~~~[ Interface : "Predict" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 30 52 if (_param._have_bht) 31 53 { … … 45 67 for (uint32_t i=0; i<_param._nb_prediction; i++) 46 68 { 69 Interface_fifo * interface = _interfaces->set_interface("predict_"+toString(i) 70 #ifdef POSITION 71 , IN 72 , WEST 73 , "Interface Predict" 74 #endif 75 ); 76 47 77 if (_param._have_bht) 48 78 { 49 rename = " in_PREDICT_BHT_ACK_" +toString(i); 50 in_PREDICT_BHT_ACK [i] = new SC_IN (Tcontrol_t) (rename.c_str()); 51 52 rename = "out_PREDICT_BHT_ADDRESS_"+toString(i); 53 out_PREDICT_BHT_ADDRESS [i] = new SC_OUT(Taddress_t) (rename.c_str()); 79 in_PREDICT_BHT_ACK [i] = interface->set_signal_in <Tcontrol_t> ("bht_ack" ,1); 80 out_PREDICT_BHT_ADDRESS [i] = interface->set_signal_out <Taddress_t> ("bht_address",_param._bht_size_address); 54 81 } 55 82 if (_param._have_pht) 56 83 { 57 rename = " in_PREDICT_PHT_ACK_" +toString(i); 58 in_PREDICT_PHT_ACK [i] = new SC_IN (Tcontrol_t) (rename.c_str()); 59 60 rename = "out_PREDICT_PHT_ADDRESS_"+toString(i); 61 out_PREDICT_PHT_ADDRESS [i] = new SC_OUT(Taddress_t) (rename.c_str()); 84 in_PREDICT_PHT_ACK [i] = interface->set_signal_in <Tcontrol_t> ("pht_ack" ,1); 85 out_PREDICT_PHT_ADDRESS [i] = interface->set_signal_out <Taddress_t> ("pht_address",_param._pht_size_address); 62 86 } 63 87 if (_param._have_bht and _param._have_pht) 64 { 65 rename = " in_PREDICT_BHT_HISTORY_"+toString(i); 66 in_PREDICT_BHT_HISTORY [i] = new SC_IN (Tbht_history_t) (rename.c_str()); 67 } 68 rename = "out_PREDICT_ACK_" +toString(i); 69 out_PREDICT_ACK [i] = new SC_OUT(Tcontrol_t) (rename.c_str()); 70 71 rename = " in_PREDICT_ADDRESS_" +toString(i); 72 in_PREDICT_ADDRESS [i] = new SC_IN (Taddress_t) (rename.c_str()); 88 in_PREDICT_BHT_HISTORY [i] = interface->set_signal_in <Tbht_history_t> ("bht_history",_param._bht_size_history); 89 out_PREDICT_ACK [i] = interface->set_signal_out <Tcontrol_t> ("ack" ,1); 90 in_PREDICT_ADDRESS [i] = interface->set_signal_in <Taddress_t> ("address" ,_param._size_address); 73 91 } 92 93 // ~~~~~[ Interface : "branch_complete" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 74 94 75 95 if (_param._have_bht) … … 91 111 for (uint32_t i=0; i<_param._nb_branch_complete; i++) 92 112 { 113 Interface_fifo * interface = _interfaces->set_interface("branch_complete_"+toString(i) 114 #ifdef POSITION 115 , IN 116 , EAST 117 , "Interface branch complete" 118 #endif 119 ); 93 120 if (_param._have_bht) 94 121 { 95 rename = " in_BRANCH_COMPLETE_BHT_ACK_" +toString(i); 96 in_BRANCH_COMPLETE_BHT_ACK [i] = new SC_IN (Tcontrol_t) (rename.c_str()); 97 98 rename = "out_BRANCH_COMPLETE_BHT_ADDRESS_"+toString(i); 99 out_BRANCH_COMPLETE_BHT_ADDRESS [i] = new SC_OUT(Taddress_t) (rename.c_str()); 122 in_BRANCH_COMPLETE_BHT_ACK [i] = interface->set_signal_in <Tcontrol_t> ("bht_ack" ,1); 123 out_BRANCH_COMPLETE_BHT_ADDRESS [i] = interface->set_signal_out <Taddress_t> ("bht_address",_param._bht_size_address); 100 124 } 101 125 if (_param._have_pht) 102 126 { 103 rename = " in_BRANCH_COMPLETE_PHT_ACK_" +toString(i); 104 in_BRANCH_COMPLETE_PHT_ACK [i] = new SC_IN (Tcontrol_t) (rename.c_str()); 105 106 rename = "out_BRANCH_COMPLETE_PHT_ADDRESS_"+toString(i); 107 out_BRANCH_COMPLETE_PHT_ADDRESS [i] = new SC_OUT(Taddress_t) (rename.c_str()); 127 in_BRANCH_COMPLETE_PHT_ACK [i] = interface->set_signal_in <Tcontrol_t> ("pht_ack" ,1); 128 out_BRANCH_COMPLETE_PHT_ADDRESS [i] = interface->set_signal_out <Taddress_t> ("pht_address",_param._pht_size_address); 108 129 } 109 130 if (_param._have_bht and _param._have_pht) 110 { 111 rename = " in_BRANCH_COMPLETE_BHT_HISTORY_"+toString(i); 112 in_BRANCH_COMPLETE_BHT_HISTORY [i] = new SC_IN (Tbht_history_t) (rename.c_str()); 113 } 114 rename = "out_BRANCH_COMPLETE_ACK_" +toString(i); 115 out_BRANCH_COMPLETE_ACK [i] = new SC_OUT(Tcontrol_t) (rename.c_str()); 116 117 rename = " in_BRANCH_COMPLETE_ADDRESS_" +toString(i); 118 in_BRANCH_COMPLETE_ADDRESS [i] = new SC_IN (Taddress_t) (rename.c_str()); 131 in_BRANCH_COMPLETE_BHT_HISTORY [i] = interface->set_signal_in <Tbht_history_t> ("bht_history",_param._bht_size_history); 132 133 out_BRANCH_COMPLETE_ACK [i] = interface->set_signal_out <Tcontrol_t> ("ack" ,1); 134 in_BRANCH_COMPLETE_ADDRESS [i] = interface->set_signal_in <Taddress_t> ("address" ,_param._size_address); 119 135 } 120 136 121 137 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 138 139 #ifdef POSITION 140 _component->generate_file(); 141 #endif 122 142 123 143 log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"allocation","End"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_deallocation.cpp
r2 r42 22 22 log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"deallocation","Begin"); 23 23 24 delete in_CLOCK; 24 delete in_CLOCK; 25 delete in_NRESET; 25 26 26 for (uint32_t i=0; i<_param._nb_prediction; i++)27 {28 if (_param._have_bht)29 {30 delete in_PREDICT_BHT_ACK [i];31 delete out_PREDICT_BHT_ADDRESS [i];32 }33 if (_param._have_pht)34 {35 delete in_PREDICT_PHT_ACK [i];36 delete out_PREDICT_PHT_ADDRESS [i];37 }38 if (_param._have_bht and _param._have_pht)39 delete in_PREDICT_BHT_HISTORY [i];40 delete out_PREDICT_ACK [i];41 delete in_PREDICT_ADDRESS [i];42 }43 27 if (_param._have_bht) 44 28 { 45 delete in_PREDICT_BHT_ACK ;46 delete out_PREDICT_BHT_ADDRESS;29 delete [] in_PREDICT_BHT_ACK ; 30 delete [] out_PREDICT_BHT_ADDRESS; 47 31 } 48 32 if (_param._have_pht) 49 33 { 50 delete in_PREDICT_PHT_ACK ;51 delete out_PREDICT_PHT_ADDRESS;34 delete [] in_PREDICT_PHT_ACK ; 35 delete [] out_PREDICT_PHT_ADDRESS; 52 36 } 53 37 if (_param._have_bht and _param._have_pht) 54 delete in_PREDICT_BHT_HISTORY;38 delete [] in_PREDICT_BHT_HISTORY; 55 39 56 delete out_PREDICT_ACK ;57 delete in_PREDICT_ADDRESS ;40 delete [] out_PREDICT_ACK ; 41 delete [] in_PREDICT_ADDRESS ; 58 42 59 for (uint32_t i=0; i<_param._nb_branch_complete; i++)60 {61 if (_param._have_bht)62 {63 delete in_BRANCH_COMPLETE_BHT_ACK [i];64 delete out_BRANCH_COMPLETE_BHT_ADDRESS [i];65 }66 if (_param._have_pht)67 {68 delete in_BRANCH_COMPLETE_PHT_ACK [i];69 delete out_BRANCH_COMPLETE_PHT_ADDRESS [i];70 }71 if (_param._have_bht and _param._have_pht)72 delete in_BRANCH_COMPLETE_BHT_HISTORY [i];73 delete out_BRANCH_COMPLETE_ACK [i];74 delete in_BRANCH_COMPLETE_ADDRESS [i];75 }76 43 if (_param._have_bht) 77 44 { 78 delete in_BRANCH_COMPLETE_BHT_ACK ;79 delete out_BRANCH_COMPLETE_BHT_ADDRESS;45 delete [] in_BRANCH_COMPLETE_BHT_ACK ; 46 delete [] out_BRANCH_COMPLETE_BHT_ADDRESS; 80 47 } 81 48 if (_param._have_pht) 82 49 { 83 delete in_BRANCH_COMPLETE_PHT_ACK ;84 delete out_BRANCH_COMPLETE_PHT_ADDRESS;50 delete [] in_BRANCH_COMPLETE_PHT_ACK ; 51 delete [] out_BRANCH_COMPLETE_PHT_ADDRESS; 85 52 } 86 53 if (_param._have_bht and _param._have_pht) 87 delete in_BRANCH_COMPLETE_BHT_HISTORY;88 delete out_BRANCH_COMPLETE_ACK ;89 delete in_BRANCH_COMPLETE_ADDRESS ;54 delete [] in_BRANCH_COMPLETE_BHT_HISTORY; 55 delete [] out_BRANCH_COMPLETE_ACK ; 56 delete [] in_BRANCH_COMPLETE_ADDRESS ; 90 57 91 58 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 59 delete _component; 92 60 93 61 log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"deallocation","End"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_vhdl.cpp
r2 r42 22 22 { 23 23 log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"vhdl","Begin"); 24 Vhdl vhdl (_name); 24 25 Vhdl * vhdl = new Vhdl (_name); 25 26 26 vhdl .set_library_work (_name + "_Pack");27 vhdl->set_library_work (_name + "_Pack"); 27 28 28 29 vhdl_port (vhdl); … … 30 31 vhdl_body (vhdl); 31 32 32 vhdl.generate_file(); 33 vhdl->generate_file(); 34 35 delete vhdl; 36 33 37 log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"vhdl","End"); 34 38 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_vhdl_body.cpp
r2 r42 18 18 19 19 20 void Two_Level_Branch_Predictor_Glue::vhdl_body (Vhdl & vhdl)20 void Two_Level_Branch_Predictor_Glue::vhdl_body (Vhdl * & vhdl) 21 21 { 22 22 log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"vhdl_body","Begin"); 23 23 24 vhdl .set_body ("-- ack output");24 vhdl->set_body ("-- ack output"); 25 25 for (uint32_t i=0; i<_param._nb_prediction; i++) 26 26 { … … 28 28 29 29 if (_param._have_bht) 30 bht_ack = "in_PREDICT_ BHT_ACK_"+toString(i);30 bht_ack = "in_PREDICT_"+toString(i)+"_BHT_ACK"; 31 31 else 32 32 bht_ack = "'1'"; 33 33 34 34 if (_param._have_pht) 35 pht_ack = "in_PREDICT_ PHT_ACK_"+toString(i);35 pht_ack = "in_PREDICT_"+toString(i)+"_PHT_ACK"; 36 36 else 37 37 pht_ack = "'1'"; 38 38 39 vhdl .set_body ("out_PREDICT_ACK_"+toString(i)+"<= "+bht_ack+" and "+pht_ack+";");39 vhdl->set_body ("out_PREDICT_"+toString(i)+"_ACK <= "+bht_ack+" and "+pht_ack+";"); 40 40 } 41 41 … … 45 45 46 46 if (_param._have_bht) 47 bht_ack = "in_BRANCH_COMPLETE_ BHT_ACK_"+toString(i);47 bht_ack = "in_BRANCH_COMPLETE_"+toString(i)+"_BHT_ACK"; 48 48 else 49 49 bht_ack = "'1'"; 50 50 51 51 if (_param._have_pht) 52 pht_ack = "in_BRANCH_COMPLETE_ PHT_ACK_"+toString(i);52 pht_ack = "in_BRANCH_COMPLETE_"+toString(i)+"_PHT_ACK"; 53 53 else 54 54 pht_ack = "'1'"; 55 55 56 vhdl .set_body ("out_BRANCH_COMPLETE_ACK_"+toString(i)+"<= "+bht_ack+" and "+pht_ack+";");56 vhdl->set_body ("out_BRANCH_COMPLETE_"+toString(i)+"_ACK <= "+bht_ack+" and "+pht_ack+";"); 57 57 } 58 58 59 vhdl .set_body ("");60 vhdl .set_body ("-- address output");59 vhdl->set_body (""); 60 vhdl->set_body ("-- address output"); 61 61 62 62 for (uint32_t i=0; i<_param._nb_prediction; i++) … … 64 64 // The address is higher than the address size of bht 65 65 if (_param._have_bht) 66 vhdl .set_body ("out_PREDICT_BHT_ADDRESS_"+toString(i)+" <= in_PREDICT_ADDRESS_"+toString(i)+std_logic_range(_param._bht_size_address)+";");66 vhdl->set_body ("out_PREDICT_"+toString(i)+"_BHT_ADDRESS <= in_PREDICT_"+toString(i)+"_ADDRESS"+std_logic_range(_param._bht_size_address)+";"); 67 67 68 68 if (_param._have_pht) … … 93 93 { 94 94 min = _param._pht_size_address_shift; 95 vhdl .set_body ("out_PREDICT_PHT_ADDRESS_"+toString(i)+std_logic_range(min) + " <= in_PREDICT_BHT_HISTORY_"+toString(i)+std_logic_range(min)+";");95 vhdl->set_body ("out_PREDICT_"+toString(i)+"_PHT_ADDRESS"+std_logic_range(min) + " <= in_PREDICT_"+toString(i)+"_BHT_HISTORY"+std_logic_range(min)+";"); 96 96 } 97 97 … … 99 99 { 100 100 max = _param._bht_size_history; 101 vhdl .set_body ("out_PREDICT_PHT_ADDRESS_"+toString(i)+std_logic_range(_param._pht_size_address-1,max) + " <= in_PREDICT_ADDRESS_"+toString(i)+std_logic_range(_param._pht_size_address-1-_param._pht_size_address_shift, _param._pht_size_address_share)+";");101 vhdl->set_body ("out_PREDICT_"+toString(i)+"_PHT_ADDRESS"+std_logic_range(_param._pht_size_address-1,max) + " <= in_PREDICT_"+toString(i)+"_ADDRESS"+std_logic_range(_param._pht_size_address-1-_param._pht_size_address_shift, _param._pht_size_address_share)+";"); 102 102 } 103 103 104 104 // intersection 105 105 if (_param._pht_size_address_share > 0) 106 vhdl .set_body ("out_PREDICT_PHT_ADDRESS_"+toString(i)+std_logic_range(max-1,min) + " <= in_PREDICT_ADDRESS_"+toString(i)+std_logic_range(_param._pht_size_address_share-1,0)+" xor in_PREDICT_BHT_HISTORY_"+toString(i)+std_logic_range(max-1,min)+";");106 vhdl->set_body ("out_PREDICT_"+toString(i)+"_PHT_ADDRESS"+std_logic_range(max-1,min) + " <= in_PREDICT_"+toString(i)+"_ADDRESS"+std_logic_range(_param._pht_size_address_share-1,0)+" xor in_PREDICT_"+toString(i)+"_BHT_HISTORY"+std_logic_range(max-1,min)+";"); 107 107 } 108 108 else 109 vhdl .set_body ("out_PREDICT_PHT_ADDRESS_"+toString(i)+" <= in_PREDICT_ADDRESS_"+toString(i)+std_logic_range(_param._pht_size_address)+";");109 vhdl->set_body ("out_PREDICT_"+toString(i)+"_PHT_ADDRESS <= in_PREDICT_"+toString(i)+"_ADDRESS"+std_logic_range(_param._pht_size_address)+";"); 110 110 } 111 111 } … … 115 115 // The address is higher than the address size of bht 116 116 if (_param._have_bht) 117 vhdl .set_body ("out_BRANCH_COMPLETE_BHT_ADDRESS_"+toString(i)+" <= in_BRANCH_COMPLETE_ADDRESS_"+toString(i)+std_logic_range(_param._bht_size_address)+";");117 vhdl->set_body ("out_BRANCH_COMPLETE_"+toString(i)+"_BHT_ADDRESS <= in_BRANCH_COMPLETE_"+toString(i)+"_ADDRESS"+std_logic_range(_param._bht_size_address)+";"); 118 118 119 119 if (_param._have_pht) … … 129 129 { 130 130 min = _param._pht_size_address_shift; 131 vhdl .set_body ("out_BRANCH_COMPLETE_PHT_ADDRESS_"+toString(i)+std_logic_range(min) + " <= in_BRANCH_COMPLETE_BHT_HISTORY_"+toString(i)+std_logic_range(min)+";");131 vhdl->set_body ("out_BRANCH_COMPLETE_"+toString(i)+"_PHT_ADDRESS"+std_logic_range(min) + " <= in_BRANCH_COMPLETE_"+toString(i)+"_BHT_HISTORY"+std_logic_range(min)+";"); 132 132 } 133 133 … … 135 135 { 136 136 max = _param._bht_size_history; 137 vhdl .set_body ("out_BRANCH_COMPLETE_PHT_ADDRESS_"+toString(i)+std_logic_range(_param._pht_size_address-1,max) + " <= in_BRANCH_COMPLETE_ADDRESS_"+toString(i)+std_logic_range(_param._pht_size_address-1-_param._pht_size_address_shift, _param._pht_size_address_share)+";");137 vhdl->set_body ("out_BRANCH_COMPLETE_"+toString(i)+"_PHT_ADDRESS"+std_logic_range(_param._pht_size_address-1,max) + " <= in_BRANCH_COMPLETE_"+toString(i)+"_ADDRESS"+std_logic_range(_param._pht_size_address-1-_param._pht_size_address_shift, _param._pht_size_address_share)+";"); 138 138 } 139 139 140 140 // intersection 141 141 if (_param._pht_size_address_share > 0) 142 vhdl .set_body ("out_BRANCH_COMPLETE_PHT_ADDRESS_"+toString(i)+std_logic_range(max-1,min) + " <= in_BRANCH_COMPLETE_ADDRESS_"+toString(i)+std_logic_range(_param._pht_size_address_share-1,0)+" xor in_BRANCH_COMPLETE_BHT_HISTORY_"+toString(i)+std_logic_range(max-1,min)+";");142 vhdl->set_body ("out_BRANCH_COMPLETE_"+toString(i)+"_PHT_ADDRESS"+std_logic_range(max-1,min) + " <= in_BRANCH_COMPLETE_"+toString(i)+"_ADDRESS"+std_logic_range(_param._pht_size_address_share-1,0)+" xor in_BRANCH_COMPLETE_"+toString(i)+"_BHT_HISTORY"+std_logic_range(max-1,min)+";"); 143 143 } 144 144 else 145 vhdl .set_body ("out_BRANCH_COMPLETE_PHT_ADDRESS_"+toString(i)+" <= in_BRANCH_COMPLETE_ADDRESS_"+toString(i)+std_logic_range(_param._pht_size_address)+";");145 vhdl->set_body ("out_BRANCH_COMPLETE_"+toString(i)+"_PHT_ADDRESS <= in_BRANCH_COMPLETE_"+toString(i)+"_ADDRESS"+std_logic_range(_param._pht_size_address)+";"); 146 146 } 147 147 } -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_vhdl_declaration.cpp
r2 r42 18 18 19 19 20 void Two_Level_Branch_Predictor_Glue::vhdl_declaration (Vhdl & vhdl)20 void Two_Level_Branch_Predictor_Glue::vhdl_declaration (Vhdl * & vhdl) 21 21 { 22 22 log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"vhdl_declaration","Begin"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_vhdl_port.cpp
r3 r42 18 18 19 19 20 void Two_Level_Branch_Predictor_Glue::vhdl_port (Vhdl & vhdl)20 void Two_Level_Branch_Predictor_Glue::vhdl_port (Vhdl * & vhdl) 21 21 { 22 22 log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"vhdl_port","Begin"); 23 23 24 for (uint32_t i=0; i<_param._nb_prediction; i++) 25 { 26 if (_param._have_bht) 27 { 28 vhdl.set_port (" in_PREDICT_BHT_ACK_" +toString(i), IN, 1); 29 vhdl.set_port ("out_PREDICT_BHT_ADDRESS_"+toString(i),OUT,_param._bht_size_address); 30 } 31 if (_param._have_bht and _param._have_pht) 32 vhdl.set_port (" in_PREDICT_BHT_HISTORY_"+toString(i), IN,_param._bht_size_history); 33 if (_param._have_pht) 34 { 35 vhdl.set_port (" in_PREDICT_PHT_ACK_" +toString(i), IN, 1); 36 vhdl.set_port ("out_PREDICT_PHT_ADDRESS_"+toString(i),OUT,_param._pht_size_address); 37 } 38 39 vhdl.set_port ("out_PREDICT_ACK_" +toString(i),OUT, 1); 40 vhdl.set_port (" in_PREDICT_ADDRESS_" +toString(i), IN,_param._size_address); 41 } 42 43 for (uint32_t i=0; i<_param._nb_branch_complete; i++) 44 { 45 if (_param._have_bht) 46 { 47 vhdl.set_port (" in_BRANCH_COMPLETE_BHT_ACK_" +toString(i), IN, 1); 48 vhdl.set_port ("out_BRANCH_COMPLETE_BHT_ADDRESS_"+toString(i),OUT,_param._bht_size_address); 49 } 50 if (_param._have_bht and _param._have_pht) 51 vhdl.set_port (" in_BRANCH_COMPLETE_BHT_HISTORY_"+toString(i), IN,_param._bht_size_history); 52 if (_param._have_pht) 53 { 54 vhdl.set_port (" in_BRANCH_COMPLETE_PHT_ACK_" +toString(i), IN, 1); 55 vhdl.set_port ("out_BRANCH_COMPLETE_PHT_ADDRESS_"+toString(i),OUT,_param._pht_size_address); 56 } 57 vhdl.set_port ("out_BRANCH_COMPLETE_ACK_" +toString(i),OUT, 1); 58 vhdl.set_port (" in_BRANCH_COMPLETE_ADDRESS_" +toString(i), IN,_param._size_address); 59 } 24 _interfaces->set_port(vhdl); 60 25 61 26 log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"vhdl_port","End"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_vhdl_testbench_transition.cpp
r2 r42 22 22 log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"vhdl_testbench_transition","Begin"); 23 23 24 #ifndef SYSTEMCASS_SPECIFIC 25 sc_cycle(0); 26 #endif 24 sc_start(0); 27 25 28 // In order with file Two_Level_Branch_Predictor_Glue_vhdl_testbench_port.cpp 29 // Warning : if a output depend of a subcomponent, take directly the port of subcomponent 30 // (because we have no control on the ordonnancer's policy) 31 32 // _vhdl_testbench->add_input (PORT_READ( in_NRESET)); 33 for (uint32_t i=0; i<_param._nb_prediction; i++) 34 { 35 if (_param._have_bht) 36 { 37 _vhdl_testbench->add_input (PORT_READ( in_PREDICT_BHT_ACK [i])); 38 _vhdl_testbench->add_output (PORT_READ(out_PREDICT_BHT_ADDRESS [i])); 39 } 40 if (_param._have_bht and _param._have_pht) 41 _vhdl_testbench->add_input (PORT_READ( in_PREDICT_BHT_HISTORY [i])); 42 if (_param._have_pht) 43 { 44 _vhdl_testbench->add_input (PORT_READ( in_PREDICT_PHT_ACK [i])); 45 _vhdl_testbench->add_output (PORT_READ(out_PREDICT_PHT_ADDRESS [i])); 46 } 47 _vhdl_testbench->add_output (PORT_READ(out_PREDICT_ACK [i])); 48 _vhdl_testbench->add_input (PORT_READ( in_PREDICT_ADDRESS [i])); 49 } 50 51 for (uint32_t i=0; i<_param._nb_branch_complete; i++) 52 { 53 if (_param._have_bht) 54 { 55 _vhdl_testbench->add_input (PORT_READ( in_BRANCH_COMPLETE_BHT_ACK [i])); 56 _vhdl_testbench->add_output (PORT_READ(out_BRANCH_COMPLETE_BHT_ADDRESS [i])); 57 } 58 if (_param._have_bht and _param._have_pht) 59 _vhdl_testbench->add_input (PORT_READ( in_BRANCH_COMPLETE_BHT_HISTORY [i])); 60 if (_param._have_pht) 61 { 62 _vhdl_testbench->add_input (PORT_READ( in_BRANCH_COMPLETE_PHT_ACK [i])); 63 _vhdl_testbench->add_output (PORT_READ(out_BRANCH_COMPLETE_PHT_ADDRESS [i])); 64 } 65 _vhdl_testbench->add_output (PORT_READ(out_BRANCH_COMPLETE_ACK [i])); 66 _vhdl_testbench->add_input (PORT_READ( in_BRANCH_COMPLETE_ADDRESS [i])); 67 } 68 // add_test : 69 // - True : the cycle must be compare with the output of systemC 70 // - False : no test 71 _vhdl_testbench->add_test(true); 72 73 _vhdl_testbench->new_cycle (); // always at the end 26 _interfaces->testbench(); 74 27 75 28 log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"vhdl_testbench_transition","End"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/include/Two_Level_Branch_Predictor.h
r15 r42 30 30 #include "Behavioural/include/Vhdl.h" 31 31 #endif 32 #ifdef VHDL_TESTBENCH 33 #include "Behavioural/include/Vhdl_Testbench.h" 34 #endif 32 #include "Behavioural/include/Component.h" 35 33 36 34 using namespace std; … … 62 60 #endif 63 61 64 #ifdef VHDL_TESTBENCH 65 private : Vhdl_Testbench * _vhdl_testbench; 66 #endif 62 public : Component * _component; 63 private : Interfaces * _interfaces; 67 64 68 65 #ifdef SYSTEMC … … 138 135 #if VHDL 139 136 public : void vhdl (void); 140 private : void vhdl_port (Vhdl & vhdl);141 private : void vhdl_declaration (Vhdl & vhdl);142 private : void vhdl_body (Vhdl & vhdl);137 private : void vhdl_port (Vhdl * & vhdl); 138 private : void vhdl_declaration (Vhdl * & vhdl); 139 private : void vhdl_body (Vhdl * & vhdl); 143 140 #endif 144 145 141 #ifdef VHDL_TESTBENCH 146 private : void vhdl_testbench_port (void);147 142 private : void vhdl_testbench_transition (void); 148 143 #endif 149 public : void vhdl_testbench_label (string label);150 144 }; 151 145 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor.cpp
r5 r42 33 33 log_printf(FUNC,Two_Level_Branch_Predictor,"Two_Level_Branch_Predictor","Begin"); 34 34 35 #ifdef SYSTEMC 36 allocation (); 37 #endif 38 35 39 #ifdef STATISTICS 36 40 // Allocation of statistics … … 38 42 param_statistics , 39 43 param); 40 #endif41 42 #ifdef VHDL_TESTBENCH43 // Creation of a testbench44 // -> port45 // -> clock's signals46 _vhdl_testbench = new Vhdl_Testbench (_name);47 vhdl_testbench_port ();48 _vhdl_testbench->set_clock ("in_CLOCK",true);49 44 #endif 50 45 … … 55 50 56 51 #ifdef SYSTEMC 57 allocation ();58 59 52 #if (defined(STATISTICS) || defined (VHDL_TESTBENCH)) 60 53 SC_METHOD (transition); … … 79 72 log_printf(FUNC,Two_Level_Branch_Predictor,"~Two_Level_Branch_Predictor","Begin"); 80 73 81 #ifdef VHDL_TESTBENCH82 // generate the test bench83 _vhdl_testbench->generate_file();84 delete _vhdl_testbench;85 #endif86 87 74 #ifdef STATISTICS 88 75 _stat->generate_file(statistics(0)); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_allocation.cpp
r15 r42 22 22 log_printf(FUNC,Two_Level_Branch_Predictor,"allocation","Begin"); 23 23 24 in_CLOCK = new SC_CLOCK ("in_CLOCK"); 25 in_NRESET = new SC_IN (Tcontrol_t) ("in_NRESET"); 24 _component = new Component (); 25 26 Entity * entity = _component->set_entity (_name 27 ,"Two_Level_Branch_Predictor" 28 #ifdef POSITION 29 ,MIXTE 30 #endif 31 ); 32 33 _interfaces = entity->set_interfaces(); 34 35 // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 36 { 37 Interface * interface = _interfaces->set_interface("" 38 #ifdef POSITION 39 , IN 40 , SOUTH 41 , "Generalist interface" 42 #endif 43 ); 44 45 in_CLOCK = interface->set_signal_clk ("clock" ,1); 46 in_NRESET = interface->set_signal_in <Tcontrol_t> ("nreset",1,RESET_VHDL_YES); 47 } 48 49 // ~~~~~[ Interface : "predict" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 26 50 27 51 in_PREDICT_VAL = new SC_IN (Tcontrol_t) * [_param._nb_prediction ]; … … 32 56 if (_param._have_pht) 33 57 out_PREDICT_PHT_HISTORY = new SC_OUT(Tpht_history_t) * [_param._nb_prediction ]; 34 if (_param._have_bht)35 {36 signal_PREDICT_BHT_ACK = new SC_SIGNAL(Tcontrol_t) * [_param._nb_prediction];37 signal_PREDICT_BHT_ADDRESS = new SC_SIGNAL(Taddress_t) * [_param._nb_prediction];38 }39 if (_param._have_pht)40 {41 signal_PREDICT_PHT_ACK = new SC_SIGNAL(Tcontrol_t) * [_param._nb_prediction];42 signal_PREDICT_PHT_ADDRESS = new SC_SIGNAL(Taddress_t) * [_param._nb_prediction];43 }44 58 45 59 for (uint32_t i=0; i<_param._nb_prediction; i++) 46 60 { 47 rename = "in_PREDICT_VAL_" +toString(i); 48 in_PREDICT_VAL [i] = new SC_IN (Tcontrol_t) (rename.c_str()); 49 50 rename = "out_PREDICT_ACK_" +toString(i); 51 out_PREDICT_ACK [i] = new SC_OUT(Tcontrol_t) (rename.c_str()); 52 53 rename = "in_PREDICT_ADDRESS_" +toString(i); 54 in_PREDICT_ADDRESS [i] = new SC_IN (Taddress_t) (rename.c_str()); 55 61 Interface_fifo * interface = _interfaces->set_interface("predict_"+toString(i) 62 #ifdef POSITION 63 , IN 64 , WEST 65 , "Interface Predict" 66 #endif 67 ); 68 69 in_PREDICT_VAL [i] = interface->set_signal_valack_in ("val" , VAL); 70 out_PREDICT_ACK [i] = interface->set_signal_valack_out ("ack" , ACK); 71 in_PREDICT_ADDRESS [i] = interface->set_signal_in <Taddress_t> ("address", _param._size_address); 56 72 if (_param._have_bht) 57 { 58 rename = "out_PREDICT_BHT_HISTORY_"+toString(i); 59 out_PREDICT_BHT_HISTORY [i] = new SC_OUT(Tbht_history_t) (rename.c_str()); 60 } 61 73 out_PREDICT_BHT_HISTORY [i] = interface->set_signal_out <Tbht_history_t> ("bht_history", _param._bht_size_shifter); 62 74 if (_param._have_pht) 63 { 64 rename = "out_PREDICT_PHT_HISTORY_"+toString(i); 65 out_PREDICT_PHT_HISTORY [i] = new SC_OUT(Tpht_history_t) (rename.c_str()); 66 } 67 68 if (_param._have_bht) 69 { 70 rename = "signal_PREDICT_BHT_ACK_" +toString(i); 71 signal_PREDICT_BHT_ACK [i] = new SC_SIGNAL(Tcontrol_t) (rename.c_str()); 72 73 rename = "signal_PREDICT_BHT_ADDRESS_"+toString(i); 74 signal_PREDICT_BHT_ADDRESS [i] = new SC_SIGNAL(Taddress_t) (rename.c_str()); 75 } 76 77 if (_param._have_pht) 78 { 79 rename = "signal_PREDICT_PHT_ACK_" +toString(i); 80 signal_PREDICT_PHT_ACK [i] = new SC_SIGNAL(Tcontrol_t) (rename.c_str()); 81 82 rename = "signal_PREDICT_PHT_ADDRESS_"+toString(i); 83 signal_PREDICT_PHT_ADDRESS [i] = new SC_SIGNAL(Taddress_t) (rename.c_str()); 84 } 85 } 75 out_PREDICT_PHT_HISTORY [i] = interface->set_signal_out <Tpht_history_t> ("pht_history", _param._pht_size_counter); 76 } 77 78 // ~~~~~[ Interface : "branch_complete" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 86 79 87 80 in_BRANCH_COMPLETE_VAL = new SC_IN (Tcontrol_t) * [_param._nb_branch_complete]; … … 93 86 in_BRANCH_COMPLETE_PHT_HISTORY = new SC_IN (Tpht_history_t) * [_param._nb_branch_complete]; 94 87 in_BRANCH_COMPLETE_DIRECTION = new SC_IN (Tcontrol_t) * [_param._nb_branch_complete]; 95 if (_param._have_bht)96 {97 signal_BRANCH_COMPLETE_BHT_ACK = new SC_SIGNAL(Tcontrol_t) * [_param._nb_branch_complete];98 signal_BRANCH_COMPLETE_BHT_ADDRESS = new SC_SIGNAL(Taddress_t) * [_param._nb_branch_complete];99 }100 if (_param._have_pht)101 {102 signal_BRANCH_COMPLETE_PHT_ACK = new SC_SIGNAL(Tcontrol_t) * [_param._nb_branch_complete];103 signal_BRANCH_COMPLETE_PHT_ADDRESS = new SC_SIGNAL(Taddress_t) * [_param._nb_branch_complete];104 }105 88 106 89 for (uint32_t i=0; i<_param._nb_branch_complete; i++) 107 90 { 108 rename = "in_BRANCH_COMPLETE_VAL_" +toString(i); 109 in_BRANCH_COMPLETE_VAL [i] = new SC_IN (Tcontrol_t) (rename.c_str()); 110 111 rename = "out_BRANCH_COMPLETE_ACK_" +toString(i); 112 out_BRANCH_COMPLETE_ACK [i] = new SC_OUT(Tcontrol_t) (rename.c_str()); 113 114 rename = "in_BRANCH_COMPLETE_ADDRESS_" +toString(i); 115 in_BRANCH_COMPLETE_ADDRESS [i] = new SC_IN (Taddress_t) (rename.c_str()); 116 91 in_BRANCH_COMPLETE_VAL [i] = new interface->set_signal_valack_in ("val" , VAL); 92 out_BRANCH_COMPLETE_ACK [i] = new interface->set_signal_valack_out ("ack" , ACK); 93 in_BRANCH_COMPLETE_ADDRESS [i] = new interface->set_signal_in <Taddress_t > ("address" , _param._size_address); 117 94 if (_param._have_bht) 118 { 119 rename = "in_BRANCH_COMPLETE_BHT_HISTORY_"+toString(i); 120 in_BRANCH_COMPLETE_BHT_HISTORY [i] = new SC_IN (Tbht_history_t) (rename.c_str()); 121 } 95 in_BRANCH_COMPLETE_BHT_HISTORY [i] = new interface->set_signal_in <Tbht_history_t> ("bht_history", _param._bht_size_shifter); 122 96 if (_param._have_pht) 123 { 124 rename = "in_BRANCH_COMPLETE_PHT_HISTORY_"+toString(i); 125 in_BRANCH_COMPLETE_PHT_HISTORY [i] = new SC_IN (Tpht_history_t) (rename.c_str()); 126 } 127 rename = "in_BRANCH_COMPLETE_DIRECTION_" +toString(i); 128 in_BRANCH_COMPLETE_DIRECTION [i] = new SC_IN (Tcontrol_t) (rename.c_str()); 129 if (_param._have_bht) 130 { 131 rename = "signal_BRANCH_COMPLETE_BHT_ACK_" +toString(i); 132 signal_BRANCH_COMPLETE_BHT_ACK [i] = new SC_SIGNAL(Tcontrol_t) (rename.c_str()); 133 134 rename = "signal_BRANCH_COMPLETE_BHT_ADDRESS_"+toString(i); 135 signal_BRANCH_COMPLETE_BHT_ADDRESS [i] = new SC_SIGNAL(Taddress_t) (rename.c_str()); 136 } 137 if (_param._have_pht) 138 { 139 rename = "signal_BRANCH_COMPLETE_PHT_ACK_" +toString(i); 140 signal_BRANCH_COMPLETE_PHT_ACK [i] = new SC_SIGNAL(Tcontrol_t) (rename.c_str()); 141 142 rename = "signal_BRANCH_COMPLETE_PHT_ADDRESS_"+toString(i); 143 signal_BRANCH_COMPLETE_PHT_ADDRESS [i] = new SC_SIGNAL(Taddress_t) (rename.c_str()); 144 } 97 in_BRANCH_COMPLETE_PHT_HISTORY [i] = new interface->set_signal_in <Tpht_history_t> ("pht_history", _param._pht_size_counter); 98 in_BRANCH_COMPLETE_DIRECTION [i] = new interface->set_signal_in <Tcontrol_t > ("direction" , 1); 145 99 } 146 100 … … 152 106 { 153 107 name_component = _name+"_Branch_History_Table"; 154 155 log_printf(INFO,Two_Level_Branch_Predictor,"allocation","Allocation : %s",name_component.c_str()); 156 157 component_Branch_History_Table = new morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::branch_history_table ::Branch_History_Table (name_component.c_str() , 108 109 component_Branch_History_Table = new morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::branch_history_table ::Branch_History_Table (name_component.c_str() 158 110 #ifdef STATISTICS 159 _param_statistics , 160 #endif 161 *(_param._param_branch_history_table)); 162 163 // Instantiation 164 (*(component_Branch_History_Table->in_CLOCK )) (*(in_CLOCK )); 165 (*(component_Branch_History_Table->in_NRESET)) (*(in_NRESET)); 166 167 for (uint32_t i=0; i<_param._nb_prediction; i++) 168 { 169 (*(component_Branch_History_Table-> in_PREDICT_VAL [i])) (*( in_PREDICT_VAL [i])); 170 (*(component_Branch_History_Table->out_PREDICT_ACK [i])) (*(signal_PREDICT_BHT_ACK [i])); 171 (*(component_Branch_History_Table-> in_PREDICT_ADDRESS [i])) (*(signal_PREDICT_BHT_ADDRESS [i])); 172 (*(component_Branch_History_Table->out_PREDICT_HISTORY [i])) (*( out_PREDICT_BHT_HISTORY [i])); 173 } 174 175 for (uint32_t i=0; i<_param._nb_branch_complete; i++) 176 { 177 (*(component_Branch_History_Table-> in_BRANCH_COMPLETE_VAL [i])) (*( in_BRANCH_COMPLETE_VAL [i])); 178 (*(component_Branch_History_Table->out_BRANCH_COMPLETE_ACK [i])) (*(signal_BRANCH_COMPLETE_BHT_ACK [i])); 179 (*(component_Branch_History_Table-> in_BRANCH_COMPLETE_ADDRESS [i])) (*(signal_BRANCH_COMPLETE_BHT_ADDRESS [i])); 180 (*(component_Branch_History_Table-> in_BRANCH_COMPLETE_HISTORY [i])) (*( in_BRANCH_COMPLETE_BHT_HISTORY [i])); 181 (*(component_Branch_History_Table-> in_BRANCH_COMPLETE_DIRECTION [i])) (*( in_BRANCH_COMPLETE_DIRECTION [i])); 182 } 183 } 184 111 ,_param_statistics 112 #endif 113 ,*(_param._param_counter)); 114 115 _component->set_component (component_Branch_History_Table->_component 116 #ifdef POSITION 117 , 75 118 , 25 119 , 10 120 , 10 121 #endif 122 ); 123 } 124 185 125 // =====[ component_Pattern_History_Table ]=========================== 186 126 if (_param._have_pht) … … 188 128 name_component = _name+"_Pattern_History_Table"; 189 129 190 log_printf(INFO,Two_Level_Branch_Predictor,"allocation","Allocation : %s",name_component.c_str()); 191 192 component_Pattern_History_Table = new morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::pattern_history_table::Pattern_History_Table (name_component.c_str() , 130 component_Pattern_History_Table = new morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::pattern_history_table ::Pattern_History_Table (name_component.c_str() 193 131 #ifdef STATISTICS 194 _param_statistics , 195 #endif 196 *(_param._param_pattern_history_table)); 197 198 // Instantiation 199 (*(component_Pattern_History_Table->in_CLOCK)) (*(in_CLOCK)); 200 (*(component_Pattern_History_Table->in_NRESET)) (*(in_NRESET)); 201 132 ,_param_statistics 133 #endif 134 ,*(_param._param_counter)); 135 136 _component->set_component (component_Pattern_History_Table->_component 137 #ifdef POSITION 138 , 75 139 , 75 140 , 10 141 , 10 142 #endif 143 ); 144 } 145 146 // =====[ component_Two_Level_Branch_Predictor_Glue ]================= 147 148 name_component = _name+"_Two_Level_Branch_Predictor_Glue"; 149 150 component_Two_Level_Branch_Predictor_Glue = new morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::two_level_branch_predictor_glue::Two_Level_Branch_Predictor_Glue (name_component.c_str() 151 #ifdef STATISTICS 152 ,_param_statistics 153 #endif 154 ,*(_param._param_counter)); 155 156 _component->set_component (component_Pattern_History_Table->_component 157 #ifdef POSITION 158 , 50 159 , 75 160 , 10 161 , 10 162 #endif 163 ); 164 165 // ~~~~~[ Component - Instanciation ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 166 167 // =====[ component_Branch_History_Table - Instanciation ]============ 168 if (_param._have_bht) 169 { 170 #ifdef POSITION 171 _component->interface_map (_name+"_Branch_History_Table","", 172 _name ,""); 173 #endif 174 175 _component->port_map(_name+"_Branch_History_Table", "in_CLOCK" , _name,"in_CLOCK" ); 176 _component->port_map(_name+"_Branch_History_Table", "in_NRESET", _name,"in_NRESET"); 177 202 178 for (uint32_t i=0; i<_param._nb_prediction; i++) 203 179 { 204 (*(component_Pattern_History_Table-> in_PREDICT_VAL [i])) (*( in_PREDICT_VAL [i])); 205 (*(component_Pattern_History_Table->out_PREDICT_ACK [i])) (*(signal_PREDICT_PHT_ACK [i])); 206 (*(component_Pattern_History_Table-> in_PREDICT_ADDRESS [i])) (*(signal_PREDICT_PHT_ADDRESS [i])); 207 (*(component_Pattern_History_Table->out_PREDICT_HISTORY [i])) (*( out_PREDICT_PHT_HISTORY [i])); 180 #ifdef POSITION 181 _component->interface_map (_name+"_Branch_History_Table","predict_"+toString(i), 182 _name ,"predict_"+toString(i)); 183 #endif 184 _component->port_map(_name+"_Branch_History_Table", "in_PREDICT_"+toString(i)+"_VAL" , _name , "in_PREDICT_"+toString(i)+"_VAL" ); 185 _component->port_map(_name+"_Branch_History_Table","out_PREDICT_"+toString(i)+"_ACK" , _name+"_Two_Level_Branch_Predictor_Glue", "in_PREDICT_"+toString(i)+"_BHT_ACK" ); 186 _component->port_map(_name+"_Branch_History_Table", "in_PREDICT_"+toString(i)+"_ADDRESS", _name+"_Two_Level_Branch_Predictor_Glue","out_PREDICT_"+toString(i)+"_BHT_ADDRESS"); 187 _component->port_map(_name+"_Branch_History_Table","out_PREDICT_"+toString(i)+"_HISTORY", _name ,"out_PREDICT_"+toString(i)+"_BHT_HISTORY"); 208 188 } 209 189 210 190 for (uint32_t i=0; i<_param._nb_branch_complete; i++) 211 191 { 212 (*(component_Pattern_History_Table-> in_BRANCH_COMPLETE_VAL [i])) (*( in_BRANCH_COMPLETE_VAL [i])); 213 (*(component_Pattern_History_Table->out_BRANCH_COMPLETE_ACK [i])) (*(signal_BRANCH_COMPLETE_PHT_ACK [i])); 214 (*(component_Pattern_History_Table-> in_BRANCH_COMPLETE_ADDRESS [i])) (*(signal_BRANCH_COMPLETE_PHT_ADDRESS [i])); 215 (*(component_Pattern_History_Table-> in_BRANCH_COMPLETE_HISTORY [i])) (*( in_BRANCH_COMPLETE_PHT_HISTORY [i])); 216 (*(component_Pattern_History_Table-> in_BRANCH_COMPLETE_DIRECTION [i])) (*( in_BRANCH_COMPLETE_DIRECTION [i])); 217 } 218 } 219 220 // =====[ component_Two_Level_Branch_Predictor_Glue ]=========================== 221 name_component = _name+"_Two_Level_Branch_Predictor_Glue"; 222 223 log_printf(INFO,Two_Level_Branch_Predictor,"allocation","Allocation : %s",name_component.c_str()); 224 225 component_Two_Level_Branch_Predictor_Glue = new morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::two_level_branch_predictor_glue::Two_Level_Branch_Predictor_Glue (name_component.c_str() , 226 #ifdef STATISTICS 227 _param_statistics , 228 #endif 229 *(_param._param_two_level_branch_predictor_glue)); 230 231 // Instantiation 232 #if defined(STATISTICS) or defined(VHDL_TESTBENCH) 233 (*(component_Two_Level_Branch_Predictor_Glue->in_CLOCK)) (*(in_CLOCK)); 234 #endif 235 for (uint32_t i=0; i<_param._nb_prediction; i++) 236 { 192 #ifdef POSITION 193 _component->interface_map (_name+"_Branch_History_Table","branch_complete_"+toString(i), 194 _name ,"branch_complete_"+toString(i)); 195 #endif 196 _component->port_map(_name+"_Branch_History_Table", "in_BRANCH_COMPLETE_"+toString(i)+"_VAL" , _name , "in_BRANCH_COMPLETE_"+toString(i)+"_VAL" ); 197 _component->port_map(_name+"_Branch_History_Table","out_BRANCH_COMPLETE_"+toString(i)+"_ACK" , _name+"_Two_Level_Branch_Predictor_Glue", "in_BRANCH_COMPLETE_"+toString(i)+"_BHT_ACK" ); 198 _component->port_map(_name+"_Branch_History_Table", "in_BRANCH_COMPLETE_"+toString(i)+"_ADDRESS" , _name+"_Two_Level_Branch_Predictor_Glue","out_BRANCH_COMPLETE_"+toString(i)+"_BHT_ADDRESS" ); 199 _component->port_map(_name+"_Branch_History_Table", "in_BRANCH_COMPLETE_"+toString(i)+"_HISTORY" , _name , "in_BRANCH_COMPLETE_"+toString(i)+"_BHT_HISTORY" ); 200 _component->port_map(_name+"_Branch_History_Table", "in_BRANCH_COMPLETE_"+toString(i)+"_DIRECTION", _name , "in_BRANCH_COMPLETE_"+toString(i)+"_DIRECTION" ); 201 } 202 } 203 204 // =====[ component_Pattern_History_Table - Instanciation ]=========== 205 if (_param._have_pht) 206 { 207 #ifdef POSITION 208 _component->interface_map (_name+"_Pattern_History_Table","", 209 _name ,""); 210 #endif 211 212 _component->port_map(_name+"_Pattern_History_Table", "in_CLOCK" , _name,"in_CLOCK" ); 213 _component->port_map(_name+"_Pattern_History_Table", "in_NRESET", _name,"in_NRESET"); 214 215 for (uint32_t i=0; i<_param._nb_prediction; i++) 216 { 217 #ifdef POSITION 218 _component->interface_map (_name+"_Pattern_History_Table","predict_"+toString(i), 219 _name ,"predict_"+toString(i)); 220 #endif 221 _component->port_map(_name+"_Pattern_History_Table", "in_PREDICT_"+toString(i)+"_VAL" , _name , "in_PREDICT_"+toString(i)+"_VAL" ); 222 _component->port_map(_name+"_Pattern_History_Table","out_PREDICT_"+toString(i)+"_ACK" , _name+"_Two_Level_Branch_Predictor_Glue", "in_PREDICT_"+toString(i)+"_PHT_ACK" ); 223 _component->port_map(_name+"_Pattern_History_Table", "in_PREDICT_"+toString(i)+"_ADDRESS", _name+"_Two_Level_Branch_Predictor_Glue","out_PREDICT_"+toString(i)+"_PHT_ADDRESS"); 224 _component->port_map(_name+"_Pattern_History_Table","out_PREDICT_"+toString(i)+"_HISTORY", _name ,"out_PREDICT_"+toString(i)+"_PHT_HISTORY"); 225 } 226 227 for (uint32_t i=0; i<_param._nb_branch_complete; i++) 228 { 229 #ifdef POSITION 230 _component->interface_map (_name+"_Pattern_History_Table","branch_complete_"+toString(i), 231 _name ,"branch_complete_"+toString(i)); 232 #endif 233 _component->port_map(_name+"_Pattern_History_Table", "in_BRANCH_COMPLETE_"+toString(i)+"_VAL" , _name , "in_BRANCH_COMPLETE_"+toString(i)+"_VAL" ); 234 _component->port_map(_name+"_Pattern_History_Table","out_BRANCH_COMPLETE_"+toString(i)+"_ACK" , _name+"_Two_Level_Branch_Predictor_Glue", "in_BRANCH_COMPLETE_"+toString(i)+"_PHT_ACK" ); 235 _component->port_map(_name+"_Pattern_History_Table", "in_BRANCH_COMPLETE_"+toString(i)+"_ADDRESS" , _name+"_Two_Level_Branch_Predictor_Glue","out_BRANCH_COMPLETE_"+toString(i)+"_PHT_ADDRESS" ); 236 _component->port_map(_name+"_Pattern_History_Table", "in_BRANCH_COMPLETE_"+toString(i)+"_HISTORY" , _name , "in_BRANCH_COMPLETE_"+toString(i)+"_PHT_HISTORY" ); 237 _component->port_map(_name+"_Pattern_History_Table", "in_BRANCH_COMPLETE_"+toString(i)+"_DIRECTION", _name , "in_BRANCH_COMPLETE_"+toString(i)+"_DIRECTION" ); 238 } 239 } 240 241 // =====[ component_Two_Level_Branch_Predictor_Glue - Instanciation ]= 242 #ifdef POSITION 243 _component->interface_map (_name+"_Two_Level_Branch_Predictor_Glue","", 244 _name ,""); 245 #endif 246 _component->port_map(_name+"_Two_Level_Branch_Predictor_Glue", "in_CLOCK" , _name,"in_CLOCK" ); 247 _component->port_map(_name+"_Two_Level_Branch_Predictor_Glue", "in_NRESET", _name,"in_NRESET"); 248 249 for (uint32_t i=0; i<_param._nb_prediction; i++) 250 { 237 251 if (_param._have_bht) 238 252 { 239 (*(component_Two_Level_Branch_Predictor_Glue-> in_PREDICT_BHT_ACK [i])) (*(signal_PREDICT_BHT_ACK [i])); 240 (*(component_Two_Level_Branch_Predictor_Glue->out_PREDICT_BHT_ADDRESS [i])) (*(signal_PREDICT_BHT_ADDRESS [i])); 241 } 242 if (_param._have_pht) 243 { 244 (*(component_Two_Level_Branch_Predictor_Glue-> in_PREDICT_PHT_ACK [i])) (*(signal_PREDICT_PHT_ACK [i])); 245 (*(component_Two_Level_Branch_Predictor_Glue->out_PREDICT_PHT_ADDRESS [i])) (*(signal_PREDICT_PHT_ADDRESS [i])); 246 } 247 if (_param._have_bht and _param._have_pht) 248 { 249 (*(component_Two_Level_Branch_Predictor_Glue-> in_PREDICT_BHT_HISTORY [i])) (*( out_PREDICT_BHT_HISTORY [i])); 250 } 251 (*(component_Two_Level_Branch_Predictor_Glue->out_PREDICT_ACK [i])) (*( out_PREDICT_ACK [i])); 252 (*(component_Two_Level_Branch_Predictor_Glue-> in_PREDICT_ADDRESS [i])) (*( in_PREDICT_ADDRESS [i])); 253 } 253 _component->port_map(_name+"_Two_Level_Branch_Predictor_Glue", "in_PREDICT_"+toString(i)+"_BHT_ACK" , _name+"_Branch_History_Table" , "out_PREDICT_"+toString(i)+"_BHT_ACK" ); 254 _component->port_map(_name+"_Two_Level_Branch_Predictor_Glue", "out_PREDICT_"+toString(i)+"_BHT_ADDRESS", _name+"_Branch_History_Table" , "in_PREDICT_"+toString(i)+"_BHT_ADDRESS"); 255 } 256 if (_param._have_pht) 257 { 258 _component->port_map(_name+"_Two_Level_Branch_Predictor_Glue", "in_PREDICT_"+toString(i)+"_PHT_ACK" , _name+"_Pattern_History_Table", "out_PREDICT_"+toString(i)+"_PHT_ACK" ); 259 _component->port_map(_name+"_Two_Level_Branch_Predictor_Glue", "out_PREDICT_"+toString(i)+"_PHT_ADDRESS", _name+"_Pattern_History_Table", "in_PREDICT_"+toString(i)+"_PHT_ADDRESS"); 260 } 261 if (_param._have_bht and _param._have_pht) 262 _component->port_map(_name+"_Two_Level_Branch_Predictor_Glue", "in_PREDICT_"+toString(i)+"_BHT_HISTORY" , _name , "in_PREDICT_"+toString(i)+"_BHT_HISTORY"); 263 _component->port_map(_name+"_Two_Level_Branch_Predictor_Glue","out_PREDICT_"+toString(i)+"_ACK" , _name ,"out_PREDICT_"+toString(i)+"_ACK"); 264 _component->port_map(_name+"_Two_Level_Branch_Predictor_Glue", "in_PREDICT_"+toString(i)+"_ADDRESS" , _name , "in_PREDICT_"+toString(i)+"_ADDRESS"); 265 } 254 266 255 267 for (uint32_t i=0; i<_param._nb_branch_complete; i++) … … 257 269 if (_param._have_bht) 258 270 { 259 (*(component_Two_Level_Branch_Predictor_Glue-> in_BRANCH_COMPLETE_BHT_ACK [i])) (*(signal_BRANCH_COMPLETE_BHT_ACK [i])); 260 (*(component_Two_Level_Branch_Predictor_Glue->out_BRANCH_COMPLETE_BHT_ADDRESS [i])) (*(signal_BRANCH_COMPLETE_BHT_ADDRESS [i])); 261 } 262 if (_param._have_pht) 263 { 264 (*(component_Two_Level_Branch_Predictor_Glue-> in_BRANCH_COMPLETE_PHT_ACK [i])) (*(signal_BRANCH_COMPLETE_PHT_ACK [i])); 265 (*(component_Two_Level_Branch_Predictor_Glue->out_BRANCH_COMPLETE_PHT_ADDRESS [i])) (*(signal_BRANCH_COMPLETE_PHT_ADDRESS [i])); 266 } 267 if (_param._have_bht and _param._have_pht) 268 { 269 (*(component_Two_Level_Branch_Predictor_Glue-> in_BRANCH_COMPLETE_BHT_HISTORY [i])) (*( in_BRANCH_COMPLETE_BHT_HISTORY [i])); 270 } 271 (*(component_Two_Level_Branch_Predictor_Glue->out_BRANCH_COMPLETE_ACK [i])) (*( out_BRANCH_COMPLETE_ACK [i])); 272 (*(component_Two_Level_Branch_Predictor_Glue-> in_BRANCH_COMPLETE_ADDRESS [i])) (*( in_BRANCH_COMPLETE_ADDRESS [i])); 271 _component->port_map(_name+"_Two_Level_Branch_Predictor_Glue", "in_BRANCH_COMPLETE_"+toString(i)+"_BHT_ACK" , _name+"_Branch_History_Table" , "out_BRANCH_COMPLETE_"+toString(i)+"_BHT_ACK" ); 272 _component->port_map(_name+"_Two_Level_Branch_Predictor_Glue", "out_BRANCH_COMPLETE_"+toString(i)+"_BHT_ADDRESS", _name+"_Branch_History_Table" , "in_BRANCH_COMPLETE_"+toString(i)+"_BHT_ADDRESS"); 273 } 274 if (_param._have_pht) 275 { 276 _component->port_map(_name+"_Two_Level_Branch_Predictor_Glue", "in_BRANCH_COMPLETE_"+toString(i)+"_PHT_ACK" , _name+"_Pattern_History_Table", "out_BRANCH_COMPLETE_"+toString(i)+"_PHT_ACK" ); 277 _component->port_map(_name+"_Two_Level_Branch_Predictor_Glue", "out_BRANCH_COMPLETE_"+toString(i)+"_PHT_ADDRESS", _name+"_Pattern_History_Table", "in_BRANCH_COMPLETE_"+toString(i)+"_PHT_ADDRESS"); 278 } 279 if (_param._have_bht and _param._have_pht) 280 _component->port_map(_name+"_Two_Level_Branch_Predictor_Glue", "in_BRANCH_COMPLETE_"+toString(i)+"_BHT_HISTORY" , _name , "in_BRANCH_COMPLETE_"+toString(i)+"_BHT_HISTORY"); 281 _component->port_map(_name+"_Two_Level_Branch_Predictor_Glue","out_BRANCH_COMPLETE_"+toString(i)+"_ACK" , _name ,"out_BRANCH_COMPLETE_"+toString(i)+"_ACK"); 282 _component->port_map(_name+"_Two_Level_Branch_Predictor_Glue", "in_BRANCH_COMPLETE_"+toString(i)+"_ADDRESS" , _name , "in_BRANCH_COMPLETE_"+toString(i)+"_ADDRESS"); 273 283 } 274 284 285 #ifdef POSITION 286 _component->generate_file(); 287 #endif 288 275 289 log_printf(FUNC,Two_Level_Branch_Predictor,"allocation","End"); 276 290 }; 291 292 293 294 295 296 297 298 // void Two_Level_Branch_Predictor::allocation (void) 299 // { 300 // string rename; 301 302 // log_printf(FUNC,Two_Level_Branch_Predictor,"allocation","Begin"); 303 304 // _component = new Component (); 305 306 // Entity * entity = _component->set_entity (_name 307 // #ifdef POSITION 308 // ,"Two_Level_Branch_Predictor" 309 // ,MIXTE 310 // #endif 311 // ); 312 313 // _interfaces = entity->set_interfaces(); 314 315 // // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 316 // { 317 // Interface * interface = _interfaces->set_interface("" 318 // #ifdef POSITION 319 // , IN 320 // , SOUTH 321 // , "Generalist interface" 322 // #endif 323 // ); 324 325 // in_CLOCK = interface->set_signal_clk ("clock" ,1); 326 // in_NRESET = interface->set_signal_in <Tcontrol_t> ("nreset",1,RESET_VHDL_YES); 327 // } 328 329 // // ~~~~~[ Interface : "predict" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 330 331 // in_PREDICT_VAL = new SC_IN (Tcontrol_t) * [_param._nb_prediction ]; 332 // out_PREDICT_ACK = new SC_OUT(Tcontrol_t) * [_param._nb_prediction ]; 333 // in_PREDICT_ADDRESS = new SC_IN (Taddress_t) * [_param._nb_prediction ]; 334 // if (_param._have_bht) 335 // out_PREDICT_BHT_HISTORY = new SC_OUT(Tbht_history_t) * [_param._nb_prediction ]; 336 // if (_param._have_pht) 337 // out_PREDICT_PHT_HISTORY = new SC_OUT(Tpht_history_t) * [_param._nb_prediction ]; 338 // // if (_param._have_bht) 339 // // { 340 // // signal_PREDICT_BHT_ACK = new SC_SIGNAL(Tcontrol_t) * [_param._nb_prediction]; 341 // // signal_PREDICT_BHT_ADDRESS = new SC_SIGNAL(Taddress_t) * [_param._nb_prediction]; 342 // // } 343 // // if (_param._have_pht) 344 // // { 345 // // signal_PREDICT_PHT_ACK = new SC_SIGNAL(Tcontrol_t) * [_param._nb_prediction]; 346 // // signal_PREDICT_PHT_ADDRESS = new SC_SIGNAL(Taddress_t) * [_param._nb_prediction]; 347 // // } 348 349 // for (uint32_t i=0; i<_param._nb_prediction; i++) 350 // { 351 // rename = "in_PREDICT_VAL_" +toString(i); 352 // in_PREDICT_VAL [i] = new SC_IN (Tcontrol_t) (rename.c_str()); 353 354 // rename = "out_PREDICT_ACK_" +toString(i); 355 // out_PREDICT_ACK [i] = new SC_OUT(Tcontrol_t) (rename.c_str()); 356 357 // rename = "in_PREDICT_ADDRESS_" +toString(i); 358 // in_PREDICT_ADDRESS [i] = new SC_IN (Taddress_t) (rename.c_str()); 359 360 // if (_param._have_bht) 361 // { 362 // rename = "out_PREDICT_BHT_HISTORY_"+toString(i); 363 // out_PREDICT_BHT_HISTORY [i] = new SC_OUT(Tbht_history_t) (rename.c_str()); 364 // } 365 366 // if (_param._have_pht) 367 // { 368 // rename = "out_PREDICT_PHT_HISTORY_"+toString(i); 369 // out_PREDICT_PHT_HISTORY [i] = new SC_OUT(Tpht_history_t) (rename.c_str()); 370 // } 371 372 // // if (_param._have_bht) 373 // // { 374 // // rename = "signal_PREDICT_BHT_ACK_" +toString(i); 375 // // signal_PREDICT_BHT_ACK [i] = new SC_SIGNAL(Tcontrol_t) (rename.c_str()); 376 377 // // rename = "signal_PREDICT_BHT_ADDRESS_"+toString(i); 378 // // signal_PREDICT_BHT_ADDRESS [i] = new SC_SIGNAL(Taddress_t) (rename.c_str()); 379 // // } 380 381 // // if (_param._have_pht) 382 // // { 383 // // rename = "signal_PREDICT_PHT_ACK_" +toString(i); 384 // // signal_PREDICT_PHT_ACK [i] = new SC_SIGNAL(Tcontrol_t) (rename.c_str()); 385 386 // // rename = "signal_PREDICT_PHT_ADDRESS_"+toString(i); 387 // // signal_PREDICT_PHT_ADDRESS [i] = new SC_SIGNAL(Taddress_t) (rename.c_str()); 388 // // } 389 // } 390 391 // in_BRANCH_COMPLETE_VAL = new SC_IN (Tcontrol_t) * [_param._nb_branch_complete]; 392 // out_BRANCH_COMPLETE_ACK = new SC_OUT(Tcontrol_t) * [_param._nb_branch_complete]; 393 // in_BRANCH_COMPLETE_ADDRESS = new SC_IN (Taddress_t) * [_param._nb_branch_complete]; 394 // if (_param._have_bht) 395 // in_BRANCH_COMPLETE_BHT_HISTORY = new SC_IN (Tbht_history_t) * [_param._nb_branch_complete]; 396 // if (_param._have_pht) 397 // in_BRANCH_COMPLETE_PHT_HISTORY = new SC_IN (Tpht_history_t) * [_param._nb_branch_complete]; 398 // in_BRANCH_COMPLETE_DIRECTION = new SC_IN (Tcontrol_t) * [_param._nb_branch_complete]; 399 // // if (_param._have_bht) 400 // // { 401 // // signal_BRANCH_COMPLETE_BHT_ACK = new SC_SIGNAL(Tcontrol_t) * [_param._nb_branch_complete]; 402 // // signal_BRANCH_COMPLETE_BHT_ADDRESS = new SC_SIGNAL(Taddress_t) * [_param._nb_branch_complete]; 403 // // } 404 // // if (_param._have_pht) 405 // // { 406 // // signal_BRANCH_COMPLETE_PHT_ACK = new SC_SIGNAL(Tcontrol_t) * [_param._nb_branch_complete]; 407 // // signal_BRANCH_COMPLETE_PHT_ADDRESS = new SC_SIGNAL(Taddress_t) * [_param._nb_branch_complete]; 408 // // } 409 410 // for (uint32_t i=0; i<_param._nb_branch_complete; i++) 411 // { 412 // rename = "in_BRANCH_COMPLETE_VAL_" +toString(i); 413 // in_BRANCH_COMPLETE_VAL [i] = new SC_IN (Tcontrol_t) (rename.c_str()); 414 415 // rename = "out_BRANCH_COMPLETE_ACK_" +toString(i); 416 // out_BRANCH_COMPLETE_ACK [i] = new SC_OUT(Tcontrol_t) (rename.c_str()); 417 418 // rename = "in_BRANCH_COMPLETE_ADDRESS_" +toString(i); 419 // in_BRANCH_COMPLETE_ADDRESS [i] = new SC_IN (Taddress_t) (rename.c_str()); 420 421 // if (_param._have_bht) 422 // { 423 // rename = "in_BRANCH_COMPLETE_BHT_HISTORY_"+toString(i); 424 // in_BRANCH_COMPLETE_BHT_HISTORY [i] = new SC_IN (Tbht_history_t) (rename.c_str()); 425 // } 426 // if (_param._have_pht) 427 // { 428 // rename = "in_BRANCH_COMPLETE_PHT_HISTORY_"+toString(i); 429 // in_BRANCH_COMPLETE_PHT_HISTORY [i] = new SC_IN (Tpht_history_t) (rename.c_str()); 430 // } 431 // rename = "in_BRANCH_COMPLETE_DIRECTION_" +toString(i); 432 // in_BRANCH_COMPLETE_DIRECTION [i] = new SC_IN (Tcontrol_t) (rename.c_str()); 433 // // if (_param._have_bht) 434 // // { 435 // // rename = "signal_BRANCH_COMPLETE_BHT_ACK_" +toString(i); 436 // // signal_BRANCH_COMPLETE_BHT_ACK [i] = new SC_SIGNAL(Tcontrol_t) (rename.c_str()); 437 438 // // rename = "signal_BRANCH_COMPLETE_BHT_ADDRESS_"+toString(i); 439 // // signal_BRANCH_COMPLETE_BHT_ADDRESS [i] = new SC_SIGNAL(Taddress_t) (rename.c_str()); 440 // // } 441 // // if (_param._have_pht) 442 // // { 443 // // rename = "signal_BRANCH_COMPLETE_PHT_ACK_" +toString(i); 444 // // signal_BRANCH_COMPLETE_PHT_ACK [i] = new SC_SIGNAL(Tcontrol_t) (rename.c_str()); 445 446 // // rename = "signal_BRANCH_COMPLETE_PHT_ADDRESS_"+toString(i); 447 // // signal_BRANCH_COMPLETE_PHT_ADDRESS [i] = new SC_SIGNAL(Taddress_t) (rename.c_str()); 448 // // } 449 // } 450 451 // // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 452 // string name_component; 453 454 // // =====[ component_Branch_History_Table ]============================ 455 // if (_param._have_bht) 456 // { 457 // name_component = _name+"_Branch_History_Table"; 458 459 // log_printf(INFO,Two_Level_Branch_Predictor,"allocation","Allocation : %s",name_component.c_str()); 460 461 // component_Branch_History_Table = new morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::branch_history_table ::Branch_History_Table (name_component.c_str() , 462 // #ifdef STATISTICS 463 // _param_statistics , 464 // #endif 465 // *(_param._param_branch_history_table)); 466 467 // // Instantiation 468 // (*(component_Branch_History_Table->in_CLOCK )) (*(in_CLOCK )); 469 // (*(component_Branch_History_Table->in_NRESET)) (*(in_NRESET)); 470 471 // for (uint32_t i=0; i<_param._nb_prediction; i++) 472 // { 473 // (*(component_Branch_History_Table-> in_PREDICT_VAL [i])) (*( in_PREDICT_VAL [i])); 474 // (*(component_Branch_History_Table->out_PREDICT_ACK [i])) (*(signal_PREDICT_BHT_ACK [i])); 475 // (*(component_Branch_History_Table-> in_PREDICT_ADDRESS [i])) (*(signal_PREDICT_BHT_ADDRESS [i])); 476 // (*(component_Branch_History_Table->out_PREDICT_HISTORY [i])) (*( out_PREDICT_BHT_HISTORY [i])); 477 // } 478 479 // for (uint32_t i=0; i<_param._nb_branch_complete; i++) 480 // { 481 // (*(component_Branch_History_Table-> in_BRANCH_COMPLETE_VAL [i])) (*( in_BRANCH_COMPLETE_VAL [i])); 482 // (*(component_Branch_History_Table->out_BRANCH_COMPLETE_ACK [i])) (*(signal_BRANCH_COMPLETE_BHT_ACK [i])); 483 // (*(component_Branch_History_Table-> in_BRANCH_COMPLETE_ADDRESS [i])) (*(signal_BRANCH_COMPLETE_BHT_ADDRESS [i])); 484 // (*(component_Branch_History_Table-> in_BRANCH_COMPLETE_HISTORY [i])) (*( in_BRANCH_COMPLETE_BHT_HISTORY [i])); 485 // (*(component_Branch_History_Table-> in_BRANCH_COMPLETE_DIRECTION [i])) (*( in_BRANCH_COMPLETE_DIRECTION [i])); 486 // } 487 // } 488 489 // // =====[ component_Pattern_History_Table ]=========================== 490 // if (_param._have_pht) 491 // { 492 // name_component = _name+"_Pattern_History_Table"; 493 494 // log_printf(INFO,Two_Level_Branch_Predictor,"allocation","Allocation : %s",name_component.c_str()); 495 496 // component_Pattern_History_Table = new morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::pattern_history_table::Pattern_History_Table (name_component.c_str() , 497 // #ifdef STATISTICS 498 // _param_statistics , 499 // #endif 500 // *(_param._param_pattern_history_table)); 501 502 // // Instantiation 503 // (*(component_Pattern_History_Table->in_CLOCK)) (*(in_CLOCK)); 504 // (*(component_Pattern_History_Table->in_NRESET)) (*(in_NRESET)); 505 506 // for (uint32_t i=0; i<_param._nb_prediction; i++) 507 // { 508 // (*(component_Pattern_History_Table-> in_PREDICT_VAL [i])) (*( in_PREDICT_VAL [i])); 509 // (*(component_Pattern_History_Table->out_PREDICT_ACK [i])) (*(signal_PREDICT_PHT_ACK [i])); 510 // (*(component_Pattern_History_Table-> in_PREDICT_ADDRESS [i])) (*(signal_PREDICT_PHT_ADDRESS [i])); 511 // (*(component_Pattern_History_Table->out_PREDICT_HISTORY [i])) (*( out_PREDICT_PHT_HISTORY [i])); 512 // } 513 514 // for (uint32_t i=0; i<_param._nb_branch_complete; i++) 515 // { 516 // (*(component_Pattern_History_Table-> in_BRANCH_COMPLETE_VAL [i])) (*( in_BRANCH_COMPLETE_VAL [i])); 517 // (*(component_Pattern_History_Table->out_BRANCH_COMPLETE_ACK [i])) (*(signal_BRANCH_COMPLETE_PHT_ACK [i])); 518 // (*(component_Pattern_History_Table-> in_BRANCH_COMPLETE_ADDRESS [i])) (*(signal_BRANCH_COMPLETE_PHT_ADDRESS [i])); 519 // (*(component_Pattern_History_Table-> in_BRANCH_COMPLETE_HISTORY [i])) (*( in_BRANCH_COMPLETE_PHT_HISTORY [i])); 520 // (*(component_Pattern_History_Table-> in_BRANCH_COMPLETE_DIRECTION [i])) (*( in_BRANCH_COMPLETE_DIRECTION [i])); 521 // } 522 // } 523 524 // // =====[ component_Two_Level_Branch_Predictor_Glue ]=========================== 525 // name_component = _name+"_Two_Level_Branch_Predictor_Glue"; 526 527 // log_printf(INFO,Two_Level_Branch_Predictor,"allocation","Allocation : %s",name_component.c_str()); 528 529 // component_Two_Level_Branch_Predictor_Glue = new morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::two_level_branch_predictor_glue::Two_Level_Branch_Predictor_Glue (name_component.c_str() , 530 // #ifdef STATISTICS 531 // _param_statistics , 532 // #endif 533 // *(_param._param_two_level_branch_predictor_glue)); 534 535 // // Instantiation 536 // #if defined(STATISTICS) or defined(VHDL_TESTBENCH) 537 // (*(component_Two_Level_Branch_Predictor_Glue->in_CLOCK)) (*(in_CLOCK)); 538 // #endif 539 // for (uint32_t i=0; i<_param._nb_prediction; i++) 540 // { 541 // if (_param._have_bht) 542 // { 543 // (*(component_Two_Level_Branch_Predictor_Glue-> in_PREDICT_BHT_ACK [i])) (*(signal_PREDICT_BHT_ACK [i])); 544 // (*(component_Two_Level_Branch_Predictor_Glue->out_PREDICT_BHT_ADDRESS [i])) (*(signal_PREDICT_BHT_ADDRESS [i])); 545 // } 546 // if (_param._have_pht) 547 // { 548 // (*(component_Two_Level_Branch_Predictor_Glue-> in_PREDICT_PHT_ACK [i])) (*(signal_PREDICT_PHT_ACK [i])); 549 // (*(component_Two_Level_Branch_Predictor_Glue->out_PREDICT_PHT_ADDRESS [i])) (*(signal_PREDICT_PHT_ADDRESS [i])); 550 // } 551 // if (_param._have_bht and _param._have_pht) 552 // { 553 // (*(component_Two_Level_Branch_Predictor_Glue-> in_PREDICT_BHT_HISTORY [i])) (*( out_PREDICT_BHT_HISTORY [i])); 554 // } 555 // (*(component_Two_Level_Branch_Predictor_Glue->out_PREDICT_ACK [i])) (*( out_PREDICT_ACK [i])); 556 // (*(component_Two_Level_Branch_Predictor_Glue-> in_PREDICT_ADDRESS [i])) (*( in_PREDICT_ADDRESS [i])); 557 // } 558 559 // for (uint32_t i=0; i<_param._nb_branch_complete; i++) 560 // { 561 // if (_param._have_bht) 562 // { 563 // (*(component_Two_Level_Branch_Predictor_Glue-> in_BRANCH_COMPLETE_BHT_ACK [i])) (*(signal_BRANCH_COMPLETE_BHT_ACK [i])); 564 // (*(component_Two_Level_Branch_Predictor_Glue->out_BRANCH_COMPLETE_BHT_ADDRESS [i])) (*(signal_BRANCH_COMPLETE_BHT_ADDRESS [i])); 565 // } 566 // if (_param._have_pht) 567 // { 568 // (*(component_Two_Level_Branch_Predictor_Glue-> in_BRANCH_COMPLETE_PHT_ACK [i])) (*(signal_BRANCH_COMPLETE_PHT_ACK [i])); 569 // (*(component_Two_Level_Branch_Predictor_Glue->out_BRANCH_COMPLETE_PHT_ADDRESS [i])) (*(signal_BRANCH_COMPLETE_PHT_ADDRESS [i])); 570 // } 571 // if (_param._have_bht and _param._have_pht) 572 // { 573 // (*(component_Two_Level_Branch_Predictor_Glue-> in_BRANCH_COMPLETE_BHT_HISTORY [i])) (*( in_BRANCH_COMPLETE_BHT_HISTORY [i])); 574 // } 575 // (*(component_Two_Level_Branch_Predictor_Glue->out_BRANCH_COMPLETE_ACK [i])) (*( out_BRANCH_COMPLETE_ACK [i])); 576 // (*(component_Two_Level_Branch_Predictor_Glue-> in_BRANCH_COMPLETE_ADDRESS [i])) (*( in_BRANCH_COMPLETE_ADDRESS [i])); 577 // } 578 579 // log_printf(FUNC,Two_Level_Branch_Predictor,"allocation","End"); 580 // }; 277 581 278 582 }; // end namespace two_level_branch_predictor -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_deallocation.cpp
r15 r42 23 23 delete in_NRESET; 24 24 25 for (uint32_t i=0; i<_param._nb_prediction; i++) 26 { 27 delete in_PREDICT_VAL [i]; 28 delete out_PREDICT_ACK [i]; 29 delete in_PREDICT_ADDRESS [i]; 30 if (_param._have_bht) 31 delete out_PREDICT_BHT_HISTORY [i]; 32 if (_param._have_pht) 33 delete out_PREDICT_PHT_HISTORY [i]; 34 if (_param._have_bht) 35 { 36 delete signal_PREDICT_BHT_ACK [i]; 37 delete signal_PREDICT_BHT_ADDRESS [i]; 38 } 39 if (_param._have_pht) 40 { 41 delete signal_PREDICT_PHT_ACK [i]; 42 delete signal_PREDICT_PHT_ADDRESS [i]; 43 } 25 delete [] in_PREDICT_VAL ; 26 delete [] out_PREDICT_ACK ; 27 delete [] in_PREDICT_ADDRESS ; 28 if (_param._have_bht) 29 delete [] out_PREDICT_BHT_HISTORY; 30 if (_param._have_pht) 31 delete [] out_PREDICT_PHT_HISTORY; 44 32 45 } 46 47 delete in_PREDICT_VAL ; 48 delete out_PREDICT_ACK ; 49 delete in_PREDICT_ADDRESS ; 33 delete [] in_BRANCH_COMPLETE_VAL ; 34 delete [] out_BRANCH_COMPLETE_ACK ; 35 delete [] in_BRANCH_COMPLETE_ADDRESS ; 50 36 if (_param._have_bht) 51 delete out_PREDICT_BHT_HISTORY;37 delete [] in_BRANCH_COMPLETE_BHT_HISTORY; 52 38 if (_param._have_pht) 53 delete out_PREDICT_PHT_HISTORY; 54 if (_param._have_bht) 55 { 56 delete signal_PREDICT_BHT_ACK ; 57 delete signal_PREDICT_BHT_ADDRESS; 58 } 59 if (_param._have_pht) 60 { 61 delete signal_PREDICT_PHT_ACK ; 62 delete signal_PREDICT_PHT_ADDRESS; 63 } 64 65 for (uint32_t i=0; i<_param._nb_branch_complete; i++) 66 { 67 delete in_BRANCH_COMPLETE_VAL [i]; 68 delete out_BRANCH_COMPLETE_ACK [i]; 69 delete in_BRANCH_COMPLETE_ADDRESS [i]; 70 if (_param._have_bht) 71 delete in_BRANCH_COMPLETE_BHT_HISTORY [i]; 72 if (_param._have_pht) 73 delete in_BRANCH_COMPLETE_PHT_HISTORY [i]; 74 delete in_BRANCH_COMPLETE_DIRECTION [i]; 75 if (_param._have_bht) 76 { 77 delete signal_BRANCH_COMPLETE_BHT_ACK [i]; 78 delete signal_BRANCH_COMPLETE_BHT_ADDRESS [i]; 79 } 80 if (_param._have_pht) 81 { 82 delete signal_BRANCH_COMPLETE_PHT_ACK [i]; 83 delete signal_BRANCH_COMPLETE_PHT_ADDRESS [i]; 84 } 85 } 86 87 delete in_BRANCH_COMPLETE_VAL ; 88 delete out_BRANCH_COMPLETE_ACK ; 89 delete in_BRANCH_COMPLETE_ADDRESS ; 90 if (_param._have_bht) 91 delete in_BRANCH_COMPLETE_BHT_HISTORY; 92 if (_param._have_pht) 93 delete in_BRANCH_COMPLETE_PHT_HISTORY; 94 delete in_BRANCH_COMPLETE_DIRECTION ; 95 if (_param._have_bht) 96 { 97 delete signal_BRANCH_COMPLETE_BHT_ACK ; 98 delete signal_BRANCH_COMPLETE_BHT_ADDRESS; 99 } 100 if (_param._have_pht) 101 { 102 delete signal_BRANCH_COMPLETE_PHT_ACK ; 103 delete signal_BRANCH_COMPLETE_PHT_ADDRESS; 104 } 39 delete [] in_BRANCH_COMPLETE_PHT_HISTORY; 40 delete [] in_BRANCH_COMPLETE_DIRECTION ; 105 41 106 42 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ … … 111 47 delete component_Pattern_History_Table; 112 48 delete component_Two_Level_Branch_Predictor_Glue; 49 delete _component; 113 50 114 51 log_printf(FUNC,Two_Level_Branch_Predictor,"deallocation","End"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_vhdl.cpp
r3 r42 21 21 { 22 22 log_printf(FUNC,Two_Level_Branch_Predictor,"vhdl","Begin"); 23 Vhdl vhdl (_name);23 Vhdl * vhdl = new Vhdl (_name); 24 24 25 vhdl .set_library_work (_name + "_Pack");25 vhdl->set_library_work (_name + "_Pack"); 26 26 if (_param._have_bht) 27 vhdl .set_library_work (_name + "_Branch_History_Table_Pack");27 vhdl->set_library_work (_name + "_Branch_History_Table_Pack"); 28 28 if (_param._have_pht) 29 vhdl .set_library_work (_name + "_Pattern_History_Table_Pack");30 vhdl .set_library_work (_name + "_Two_Level_Branch_Predictor_Glue_Pack");29 vhdl->set_library_work (_name + "_Pattern_History_Table_Pack"); 30 vhdl->set_library_work (_name + "_Two_Level_Branch_Predictor_Glue_Pack"); 31 31 32 32 vhdl_port (vhdl); … … 34 34 vhdl_body (vhdl); 35 35 36 vhdl.generate_file(); 36 vhdl->generate_file(); 37 38 delete vhdl; 39 37 40 log_printf(FUNC,Two_Level_Branch_Predictor,"vhdl","End"); 38 41 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_vhdl_body.cpp
r15 r42 17 17 18 18 19 void Two_Level_Branch_Predictor::vhdl_body (Vhdl & vhdl)19 void Two_Level_Branch_Predictor::vhdl_body (Vhdl * & vhdl) 20 20 { 21 21 log_printf(FUNC,Two_Level_Branch_Predictor,"vhdl_body","Begin"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_vhdl_declaration.cpp
r3 r42 17 17 18 18 19 void Two_Level_Branch_Predictor::vhdl_declaration (Vhdl & vhdl)19 void Two_Level_Branch_Predictor::vhdl_declaration (Vhdl * & vhdl) 20 20 { 21 21 log_printf(FUNC,Two_Level_Branch_Predictor,"vhdl_declaration","Begin"); … … 25 25 if (_param._have_bht) 26 26 { 27 vhdl .set_signal ("signal_PREDICT_BHT_ACK_"+toString(i), 1);28 vhdl .set_signal ("signal_PREDICT_BHT_ADDRESS_"+toString(i), _param._bht_size_address);29 vhdl .set_signal ("signal_PREDICT_BHT_HISTORY_"+toString(i), _param._bht_size_shifter);27 vhdl->set_signal ("signal_PREDICT_BHT_ACK_"+toString(i), 1); 28 vhdl->set_signal ("signal_PREDICT_BHT_ADDRESS_"+toString(i), _param._bht_size_address); 29 vhdl->set_signal ("signal_PREDICT_BHT_HISTORY_"+toString(i), _param._bht_size_shifter); 30 30 } 31 31 if (_param._have_pht) 32 32 { 33 vhdl .set_signal ("signal_PREDICT_PHT_ACK_"+toString(i), 1);34 vhdl .set_signal ("signal_PREDICT_PHT_ADDRESS_"+toString(i), _param._pht_size_address);33 vhdl->set_signal ("signal_PREDICT_PHT_ACK_"+toString(i), 1); 34 vhdl->set_signal ("signal_PREDICT_PHT_ADDRESS_"+toString(i), _param._pht_size_address); 35 35 } 36 36 } … … 40 40 if (_param._have_bht) 41 41 { 42 vhdl .set_signal ("signal_BRANCH_COMPLETE_BHT_ACK_"+toString(i), 1);43 vhdl .set_signal ("signal_BRANCH_COMPLETE_BHT_ADDRESS_"+toString(i), _param._bht_size_address);42 vhdl->set_signal ("signal_BRANCH_COMPLETE_BHT_ACK_"+toString(i), 1); 43 vhdl->set_signal ("signal_BRANCH_COMPLETE_BHT_ADDRESS_"+toString(i), _param._bht_size_address); 44 44 } 45 45 if (_param._have_pht) 46 46 { 47 vhdl .set_signal ("signal_BRANCH_COMPLETE_PHT_ACK_"+toString(i), 1);48 vhdl .set_signal ("signal_BRANCH_COMPLETE_PHT_ADDRESS_"+toString(i), _param._pht_size_address);47 vhdl->set_signal ("signal_BRANCH_COMPLETE_PHT_ACK_"+toString(i), 1); 48 vhdl->set_signal ("signal_BRANCH_COMPLETE_PHT_ADDRESS_"+toString(i), _param._pht_size_address); 49 49 } 50 50 } -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_vhdl_port.cpp
r15 r42 16 16 namespace two_level_branch_predictor { 17 17 18 void Two_Level_Branch_Predictor::vhdl_port (Vhdl & vhdl)18 void Two_Level_Branch_Predictor::vhdl_port (Vhdl * & vhdl) 19 19 { 20 20 log_printf(FUNC,Two_Level_Branch_Predictor,"vhdl_port","Begin"); 21 21 22 vhdl.set_port (" in_CLOCK ", IN, 1); 23 vhdl.set_port (" in_NRESET", IN, 1); 24 25 for (uint32_t i=0; i<_param._nb_prediction; i++) 26 { 27 vhdl.set_port (" in_PREDICT_VAL_"+toString(i)+" ", IN, 1); 28 vhdl.set_port ("out_PREDICT_ACK_"+toString(i)+" ",OUT, 1); 29 vhdl.set_port (" in_PREDICT_ADDRESS_"+toString(i)+" ", IN,_param._size_address); 30 if (_param._have_bht) 31 vhdl.set_port ("out_PREDICT_BHT_HISTORY_"+toString(i)+" ",OUT,_param._bht_size_shifter); 32 if (_param._have_pht) 33 vhdl.set_port ("out_PREDICT_PHT_HISTORY_"+toString(i)+" ",OUT,_param._pht_size_counter); 34 } 35 36 for (uint32_t i=0; i<_param._nb_branch_complete; i++) 37 { 38 vhdl.set_port (" in_BRANCH_COMPLETE_VAL_"+toString(i)+" ", IN, 1); 39 vhdl.set_port ("out_BRANCH_COMPLETE_ACK_"+toString(i)+" ",OUT, 1); 40 vhdl.set_port (" in_BRANCH_COMPLETE_ADDRESS_"+toString(i)+" ", IN,_param._size_address); 41 if (_param._have_bht) 42 vhdl.set_port (" in_BRANCH_COMPLETE_BHT_HISTORY_"+toString(i)+"", IN,_param._bht_size_shifter); 43 if (_param._have_pht) 44 vhdl.set_port (" in_BRANCH_COMPLETE_PHT_HISTORY_"+toString(i)+"", IN,_param._pht_size_counter); 45 vhdl.set_port (" in_BRANCH_COMPLETE_DIRECTION_"+toString(i)+" ", IN, 1); 46 } 22 _interfaces->set_port(vhdl); 47 23 48 24 log_printf(FUNC,Two_Level_Branch_Predictor,"vhdl_port","End"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_vhdl_testbench_transition.cpp
r15 r42 21 21 log_printf(FUNC,Two_Level_Branch_Predictor,"vhdl_testbench_transition","Begin"); 22 22 23 #ifndef SYSTEMCASS_SPECIFIC 24 sc_cycle(0); 25 #endif 23 sc_start(0); 26 24 27 _vhdl_testbench->add_input (PORT_READ( in_NRESET)); 28 29 // In order with file Two_Level_Branch_Predictor_vhdl_testbench_port.cpp 30 // Warning : if a output depend of a subcomponent, take directly the port of subcomponent 31 // (because we have no control on the ordonnancer's policy) 32 33 for (uint32_t i=0; i<_param._nb_prediction; i++) 34 { 35 _vhdl_testbench->add_input (PORT_READ( in_PREDICT_VAL [i])); 36 _vhdl_testbench->add_output(PORT_READ(component_Two_Level_Branch_Predictor_Glue-> 37 out_PREDICT_ACK [i])); 38 _vhdl_testbench->add_input (PORT_READ( in_PREDICT_ADDRESS [i])); 39 if (_param._have_bht) 40 _vhdl_testbench->add_output(PORT_READ(component_Branch_History_Table -> 41 component_RegisterFile -> 42 out_READ_DATA [i])); 43 if (_param._have_pht) 44 _vhdl_testbench->add_output(PORT_READ(component_Pattern_History_Table -> 45 component_RegisterFile -> 46 out_READ_DATA [i])); 47 } 48 49 for (uint32_t i=0; i<_param._nb_branch_complete; i++) 50 { 51 _vhdl_testbench->add_input (PORT_READ( in_BRANCH_COMPLETE_VAL [i])); 52 _vhdl_testbench->add_output(PORT_READ(component_Two_Level_Branch_Predictor_Glue-> 53 out_BRANCH_COMPLETE_ACK [i])); 54 _vhdl_testbench->add_input (PORT_READ( in_BRANCH_COMPLETE_ADDRESS [i])); 55 if (_param._have_bht) 56 _vhdl_testbench->add_input (PORT_READ( in_BRANCH_COMPLETE_BHT_HISTORY [i])); 57 if (_param._have_pht) 58 _vhdl_testbench->add_input (PORT_READ( in_BRANCH_COMPLETE_PHT_HISTORY [i])); 59 _vhdl_testbench->add_input (PORT_READ( in_BRANCH_COMPLETE_DIRECTION [i])); 60 } 61 62 // add_test : 63 // - True : the cycle must be compare with the output of systemC 64 // - False : no test 65 _vhdl_testbench->add_test(true); 66 67 _vhdl_testbench->new_cycle (); // always at the end 25 _interfaces->testbench(); 68 26 69 27 log_printf(FUNC,Two_Level_Branch_Predictor,"vhdl_testbench_transition","End");
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