Changeset 78 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit
- Timestamp:
- Mar 27, 2008, 11:04:49 AM (16 years ago)
- Location:
- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit
- Files:
-
- 6 added
- 26 edited
- 3 moved
Legend:
- Unmodified
- Added
- Removed
-
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/Makefile.deps
r72 r78 20 20 Functionnal_unit_LIBRARY = -lFunctionnal_unit \ 21 21 $(Custom_LIBRARY) \ 22 -lFunctionnal_unit \ 22 23 $(Behavioural_LIBRARY) 23 24 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/Operation/include/Operation.h
r72 r78 13 13 #include "Common/include/ErrorMorpheo.h" 14 14 #include "Behavioural/include/Types.h" 15 #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/ include/Types.h"15 #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/Operation/include/Types.h" 16 16 17 17 namespace morpheo { -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/Operation/include/Types.h
r76 r78 148 148 }; 149 149 150 typedef void function_execute_t (morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::functionnal_unit::execute_operation_t *, 151 morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::functionnal_unit::execute_register_t *, 152 morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::functionnal_unit::execute_param_t *); 153 154 typedef void function_execute_end_cycle_t (morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::functionnal_unit::execute_register_t *, 155 morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::functionnal_unit::execute_param_t *); 150 typedef void function_execute_t 151 (morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::functionnal_unit::execute_operation_t *, 152 morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::functionnal_unit::execute_register_t *, 153 morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::functionnal_unit::execute_param_t *); 154 155 typedef void function_execute_end_cycle_t 156 (morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::functionnal_unit::execute_register_t *, 157 morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::functionnal_unit::execute_param_t *); 156 158 157 159 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/Operation/src/Operation.cpp
r76 r78 7 7 */ 8 8 9 #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/ include/Operation.h"9 #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/Operation/include/Operation.h" 10 10 11 11 #define neg(data) (~(data)+1) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/SelfTest/configuration.cfg
r77 r78 8 8 2 2 +1 # size_special_data 9 9 16 16 +1 # nb_special_register 10 4 4 *2 # size_store_queue 11 1 4 *4 # size_load_queue -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/SelfTest/src/main.cpp
r77 r78 9 9 #include "Behavioural/Custom/include/Custom_example.h" 10 10 11 #define NB_PARAMS 811 #define NB_PARAMS 10 12 12 13 13 void usage (int argc, char * argv[]) … … 23 23 err (_(" * size_special_data (uint32_t)\n")); 24 24 err (_(" * nb_special_register (uint32_t)\n")); 25 err (_(" * size_store_queue (uint32_t)\n")); 26 err (_(" * size_load_queue (uint32_t)\n")); 25 27 exit (1); 26 28 } … … 46 48 const uint32_t size_special_data = atoi(argv[x++]); 47 49 const uint32_t nb_special_register = atoi(argv[x++]); 50 const uint32_t size_store_queue = atoi(argv[x++]); 51 const uint32_t size_load_queue = atoi(argv[x++]); 48 52 49 53 execute_timing_t ** timing = new execute_timing_t * [MAX_TYPE]; … … 68 72 size_special_data , 69 73 nb_special_register , 74 size_store_queue , 75 size_load_queue , 70 76 timing , 71 77 &(morpheo::behavioural::custom::example_get_custom_information) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/SelfTest/src/test.cpp
r76 r78 142 142 sc_signal<Toperation_t > in_EXECUTE_IN_OPERATION (rename.c_str()); 143 143 sc_signal<Ttype_t > in_EXECUTE_IN_TYPE (rename.c_str()); 144 sc_signal<Tlsq_ptr_t > in_EXECUTE_IN_STORE_QUEUE_PTR_WRITE (rename.c_str()); 145 sc_signal<Tlsq_ptr_t > in_EXECUTE_IN_LOAD_QUEUE_PTR_WRITE (rename.c_str()); 144 146 sc_signal<Tcontrol_t > in_EXECUTE_IN_HAS_IMMEDIAT (rename.c_str()); 145 147 sc_signal<Tgeneral_data_t > in_EXECUTE_IN_IMMEDIAT (rename.c_str()); … … 160 162 sc_signal<Tpacket_t > out_EXECUTE_OUT_PACKET_ID (rename.c_str()); 161 163 //sc_signal<Toperation_t > out_EXECUTE_OUT_OPERATION (rename.c_str()); 162 //sc_signal<Ttype_t > out_EXECUTE_OUT_TYPE (rename.c_str());164 sc_signal<Ttype_t > out_EXECUTE_OUT_TYPE (rename.c_str()); 163 165 sc_signal<Tcontrol_t > out_EXECUTE_OUT_WRITE_RD (rename.c_str()); 164 166 sc_signal<Tgeneral_address_t> out_EXECUTE_OUT_NUM_REG_RD (rename.c_str()); … … 191 193 (*(_Functionnal_unit-> in_EXECUTE_IN_OPERATION )) ( in_EXECUTE_IN_OPERATION ); 192 194 (*(_Functionnal_unit-> in_EXECUTE_IN_TYPE )) ( in_EXECUTE_IN_TYPE ); 195 (*(_Functionnal_unit-> in_EXECUTE_IN_STORE_QUEUE_PTR_WRITE)) ( in_EXECUTE_IN_STORE_QUEUE_PTR_WRITE); 196 if (_param->_have_port_load_queue_ptr) 197 (*(_Functionnal_unit-> in_EXECUTE_IN_LOAD_QUEUE_PTR_WRITE )) ( in_EXECUTE_IN_LOAD_QUEUE_PTR_WRITE ); 193 198 (*(_Functionnal_unit-> in_EXECUTE_IN_HAS_IMMEDIAT )) ( in_EXECUTE_IN_HAS_IMMEDIAT ); 194 199 (*(_Functionnal_unit-> in_EXECUTE_IN_IMMEDIAT )) ( in_EXECUTE_IN_IMMEDIAT ); … … 212 217 (*(_Functionnal_unit->out_EXECUTE_OUT_PACKET_ID )) (out_EXECUTE_OUT_PACKET_ID ); 213 218 //(*(_Functionnal_unit->out_EXECUTE_OUT_OPERATION )) (out_EXECUTE_OUT_OPERATION ); 214 //(*(_Functionnal_unit->out_EXECUTE_OUT_TYPE )) (out_EXECUTE_OUT_TYPE );219 (*(_Functionnal_unit->out_EXECUTE_OUT_TYPE )) (out_EXECUTE_OUT_TYPE ); 215 220 (*(_Functionnal_unit->out_EXECUTE_OUT_WRITE_RD )) (out_EXECUTE_OUT_WRITE_RD ); 216 221 (*(_Functionnal_unit->out_EXECUTE_OUT_NUM_REG_RD )) (out_EXECUTE_OUT_NUM_REG_RD ); … … 616 621 in_EXECUTE_IN_OPERATION .write(transaction_in.front()._operation ); 617 622 in_EXECUTE_IN_TYPE .write(transaction_in.front()._type ); 623 in_EXECUTE_IN_STORE_QUEUE_PTR_WRITE.write(0); 624 if (_param->_have_port_load_queue_ptr) 625 in_EXECUTE_IN_LOAD_QUEUE_PTR_WRITE .write(0); 618 626 in_EXECUTE_IN_HAS_IMMEDIAT .write(transaction_in.front()._has_immediat ); 619 627 in_EXECUTE_IN_IMMEDIAT .write(transaction_in.front()._immediat ); … … 641 649 TEST(Tcontext_t , out_EXECUTE_OUT_OOO_ENGINE_ID.read(), transaction_out.front()._ooo_engine_id); 642 650 //TEST(Toperation_t , out_EXECUTE_OUT_OPERATION .read(), transaction_out.front()._operation ); 643 //TEST(Ttype_t , out_EXECUTE_OUT_TYPE .read(), transaction_out.front()._type );651 TEST(Ttype_t , out_EXECUTE_OUT_TYPE .read(), transaction_out.front()._type ); 644 652 TEST(Tcontrol_t , out_EXECUTE_OUT_WRITE_RE .read(), transaction_out.front()._write_re ); 645 653 TEST(Tgeneral_address_t, out_EXECUTE_OUT_NUM_REG_RD .read(), transaction_out.front()._num_reg_rd ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/include/Functionnal_unit.h
r76 r78 10 10 */ 11 11 12 #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/include/Operation.h"13 14 12 #ifdef SYSTEMC 15 13 #include "systemc.h" … … 20 18 #include "Common/include/Debug.h" 21 19 #include "Behavioural/include/Types.h" 20 #include "Behavioural/include/Identification.h" 22 21 22 #include "Behavioural/include/Types.h" 23 23 #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/include/Parameters.h" 24 #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/ include/Types.h"24 #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/Operation/include/Operation.h" 25 25 #ifdef STATISTICS 26 26 #include "Behavioural/include/Stat.h" … … 86 86 public : SC_IN (Toperation_t ) * in_EXECUTE_IN_OPERATION ; 87 87 public : SC_IN (Ttype_t ) * in_EXECUTE_IN_TYPE ; 88 public : SC_IN (Tlsq_ptr_t ) * in_EXECUTE_IN_STORE_QUEUE_PTR_WRITE; 89 public : SC_IN (Tlsq_ptr_t ) * in_EXECUTE_IN_LOAD_QUEUE_PTR_WRITE; 88 90 public : SC_IN (Tcontrol_t ) * in_EXECUTE_IN_HAS_IMMEDIAT ; 89 91 public : SC_IN (Tgeneral_data_t ) * in_EXECUTE_IN_IMMEDIAT ; … … 104 106 public : SC_OUT(Tpacket_t ) * out_EXECUTE_OUT_PACKET_ID ; 105 107 //public : SC_OUT(Toperation_t ) * out_EXECUTE_OUT_OPERATION ; 106 //public : SC_OUT(Ttype_t ) * out_EXECUTE_OUT_TYPE ;108 public : SC_OUT(Ttype_t ) * out_EXECUTE_OUT_TYPE ; 107 109 public : SC_OUT(Tcontrol_t ) * out_EXECUTE_OUT_WRITE_RD ; 108 110 public : SC_OUT(Tgeneral_address_t) * out_EXECUTE_OUT_NUM_REG_RD ; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/include/Parameters.h
r77 r78 11 11 #include "Common/include/Debug.h" 12 12 #include "Behavioural/include/Parameters.h" 13 #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/ include/Types.h"13 #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/Operation/include/Types.h" 14 14 #include "Behavioural/Custom/include/Custom.h" 15 #include "Behavioural/Custom/include/Custom_default.h" 15 16 #include <math.h> 16 17 … … 36 37 public : const uint32_t _size_special_data ; 37 38 public : const uint32_t _nb_special_register ; 39 public : const uint32_t _size_store_queue ; 40 public : const uint32_t _size_load_queue ; 41 38 42 public : execute_timing_t ** _timing ; 39 43 public : morpheo::behavioural::custom::custom_information_t (*_get_custom_information) (uint32_t); … … 50 54 public : const bool _have_port_ooo_engine_id ; 51 55 public : const bool _have_port_packet_id ; 56 public : const bool _have_port_load_queue_ptr ; 52 57 53 58 public : const bool _have_groupe_MAC ; … … 62 67 uint32_t size_special_data , 63 68 uint32_t nb_special_register, 69 uint32_t size_store_queue , 70 uint32_t size_load_queue , 64 71 execute_timing_t** timing , 65 72 morpheo::behavioural::custom::custom_information_t (*get_custom_information) (uint32_t)); … … 67 74 public : ~Parameters () ; 68 75 69 public : std::stringmsg_error (void);76 public : Parameters_test msg_error (void); 70 77 71 78 public : std::string print (uint32_t depth); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_allocation.cpp
r77 r78 71 71 in_EXECUTE_IN_OPERATION = interface->set_signal_in <Toperation_t > ("operation" , _param->_size_operation ); 72 72 in_EXECUTE_IN_TYPE = interface->set_signal_in <Ttype_t > ("type" , _param->_size_type ); 73 in_EXECUTE_IN_STORE_QUEUE_PTR_WRITE = interface->set_signal_in <Tlsq_ptr_t> ("store_queue_ptr_write",log2(_param->_size_store_queue)); 74 if (_param->_have_port_load_queue_ptr) 75 in_EXECUTE_IN_LOAD_QUEUE_PTR_WRITE = interface->set_signal_in <Tlsq_ptr_t> ("load_queue_ptr_write" ,log2(_param->_size_load_queue)); 73 76 in_EXECUTE_IN_HAS_IMMEDIAT = interface->set_signal_in <Tcontrol_t > ("has_immediat" , 1); 74 77 in_EXECUTE_IN_IMMEDIAT = interface->set_signal_in <Tgeneral_data_t > ("immediat" , _param->_size_general_data); … … 102 105 out_EXECUTE_OUT_PACKET_ID = interface->set_signal_out<Tpacket_t > ("packet_id" ,_param->_size_packet_id ); 103 106 //out_EXECUTE_OUT_OPERATION = interface->set_signal_out<Toperation_t > ("operation" ,_param->_size_operation ); 104 //out_EXECUTE_OUT_TYPE = interface->set_signal_out<Ttype_t > ("type" ,_param->_size_type );107 out_EXECUTE_OUT_TYPE = interface->set_signal_out<Ttype_t > ("type" ,_param->_size_type ); 105 108 out_EXECUTE_OUT_WRITE_RD = interface->set_signal_out<Tcontrol_t > ("write_rd" ,1); 106 109 out_EXECUTE_OUT_NUM_REG_RD = interface->set_signal_out<Tgeneral_address_t> ("num_reg_rd" ,_param->_size_general_register); … … 111 114 out_EXECUTE_OUT_EXCEPTION = interface->set_signal_out<Texception_t > ("exception" ,_param->_size_exception); 112 115 out_EXECUTE_OUT_NO_SEQUENCE = interface->set_signal_out<Tcontrol_t > ("no_sequence" ,1); 113 out_EXECUTE_OUT_ADDRESS = interface->set_signal_out<Tgeneral_data_t > ("address ",_param->_size_general_data);116 out_EXECUTE_OUT_ADDRESS = interface->set_signal_out<Tgeneral_data_t > ("address" ,_param->_size_general_data); 114 117 } 115 118 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_deallocation.cpp
r76 r78 41 41 delete in_EXECUTE_IN_OPERATION ; 42 42 delete in_EXECUTE_IN_TYPE ; 43 delete in_EXECUTE_IN_STORE_QUEUE_PTR_WRITE; 44 if (_param->_have_port_load_queue_ptr) 45 delete in_EXECUTE_IN_LOAD_QUEUE_PTR_WRITE ; 43 46 delete in_EXECUTE_IN_HAS_IMMEDIAT ; 44 47 delete in_EXECUTE_IN_IMMEDIAT ; … … 62 65 delete out_EXECUTE_OUT_PACKET_ID ; 63 66 //delete out_EXECUTE_OUT_OPERATION ; 64 //delete out_EXECUTE_OUT_TYPE ;67 delete out_EXECUTE_OUT_TYPE ; 65 68 delete out_EXECUTE_OUT_WRITE_RD ; 66 69 delete out_EXECUTE_OUT_NUM_REG_RD ; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_genMoore.cpp
r72 r78 37 37 PORT_WRITE(out_EXECUTE_OUT_PACKET_ID ,_execute_operation->_packet_id ); 38 38 //PORT_WRITE(out_EXECUTE_OUT_OPERATION ,_execute_operation->_operation ); 39 //PORT_WRITE(out_EXECUTE_OUT_TYPE ,_execute_operation->_type );39 PORT_WRITE(out_EXECUTE_OUT_TYPE ,_execute_operation->_type ); 40 40 PORT_WRITE(out_EXECUTE_OUT_WRITE_RD ,_execute_operation->_write_rd ); 41 41 PORT_WRITE(out_EXECUTE_OUT_NUM_REG_RD ,_execute_operation->_num_reg_rd ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Parameters.cpp
r77 r78 28 28 uint32_t size_special_data , 29 29 uint32_t nb_special_register, 30 uint32_t size_store_queue , 31 uint32_t size_load_queue , 30 32 execute_timing_t** timing , 31 33 morpheo::behavioural::custom::custom_information_t (*get_custom_information) (uint32_t)) : … … 38 40 _size_special_data (size_special_data ), 39 41 _nb_special_register (nb_special_register ), 40 42 _size_store_queue (size_store_queue ), 43 _size_load_queue (size_load_queue ), 44 41 45 _size_context_id (log2(nb_context )), 42 46 _size_front_end_id (log2(nb_front_end )), 43 47 _size_ooo_engine_id (log2(nb_ooo_engine )), 44 48 _size_packet_id (log2(nb_packet )), 45 _size_general_register (log2( _size_general_register)),46 _size_special_register (log2( _size_special_register)),49 _size_general_register (log2(nb_general_register)), 50 _size_special_register (log2(nb_special_register)), 47 51 48 52 _have_port_context_id (_size_context_id > 0), … … 50 54 _have_port_ooo_engine_id (_size_ooo_engine_id > 0), 51 55 _have_port_packet_id (_size_packet_id > 0), 56 _have_port_load_queue_ptr(_size_load_queue > 1), 52 57 53 58 _have_groupe_MAC ( (timing[TYPE_SPECIAL][OPERATION_SPECIAL_L_MAC ]._latence > 0) or … … 58 63 59 64 _timing = timing; 60 _get_custom_information = get_custom_information; 65 66 if (get_custom_information == NULL) 67 _get_custom_information = &(morpheo::behavioural::custom::default_get_custom_information); 68 else 69 _get_custom_information = get_custom_information; 61 70 62 71 test(); … … 76 85 _size_special_data (param._size_special_data ), 77 86 _nb_special_register (param._nb_special_register ), 87 _size_store_queue (param._size_store_queue ), 88 _size_load_queue (param._size_load_queue ), 78 89 79 90 _size_context_id (param._size_context_id ), … … 88 99 _have_port_ooo_engine_id (param._have_port_ooo_engine_id), 89 100 _have_port_packet_id (param._have_port_packet_id ), 101 _have_port_load_queue_ptr(param._have_port_load_queue_ptr), 90 102 91 103 _have_groupe_MAC (param._have_groupe_MAC ) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Parameters_msg_error.cpp
r77 r78 22 22 #undef FUNCTION 23 23 #define FUNCTION "Functionnal_unit::msg_error" 24 std::stringParameters::msg_error(void)24 Parameters_test Parameters::msg_error(void) 25 25 { 26 26 log_printf(FUNC,Functionnal_unit,FUNCTION,"Begin"); 27 27 28 std::string msg = "";28 Parameters_test test("Functionnal_unit"); 29 29 30 30 for (uint32_t i=0; i<_nb_type; i++) 31 31 for (uint32_t j=0; j<_nb_operation; j++) 32 32 if (_timing[i][j]._delay != _timing[i][j]._latence) 33 msg = " - For the type '"+toString(i)+"', and the operation '"+toString(j)+"', the delay and the latence must be equal.";33 test.error("For the type '"+toString(i)+"', and the operation '"+toString(j)+"', the delay and the latence must be equal."); 34 34 35 35 if (_have_groupe_MAC and ((_timing[TYPE_SPECIAL][OPERATION_SPECIAL_L_MAC ]._latence == 0) or 36 36 (_timing[TYPE_SPECIAL][OPERATION_SPECIAL_L_MACRC]._latence == 0) or 37 37 (_timing[TYPE_SPECIAL][OPERATION_SPECIAL_L_MSB ]._latence == 0))) 38 msg = " - The functionnal unit implement a MAC unit, the latence to operation OPERATION_ALU_L_MAC, OPERATION_ALU_L_MACRC and OPERATION_ALU_L_MSB must be higher than 0."; 39 40 return msg; 38 test.error("The functionnal unit implement a MAC unit, the latence to operation OPERATION_ALU_L_MAC, OPERATION_ALU_L_MACRC and OPERATION_ALU_L_MSB must be higher than 0."); 41 39 42 40 log_printf(FUNC,Functionnal_unit,FUNCTION,"End"); 41 42 return test; 43 43 }; 44 44 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/configuration.cfg
r77 r78 5 5 2 2 +1 # nb_port_check 6 6 2 2 +1 # speculative_load {none,access,commit,bypass} 7 0 0 +1 # bypass_memory 7 8 2 2 *2 # nb_context 1 1 *2 8 9 2 2 *2 # nb_front_end 1 1 *2 … … 10 11 64 64 *2 # nb_packet 11 12 32 32 *2 # size_general_data 13 2 2 *2 # size_special_data 12 14 32 32 *2 # nb_general_register 15 16 16 *2 # nb_special_register -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/src/main.cpp
r77 r78 10 10 #define number_of_test 2 11 11 12 #define NB_PARAMS 1 112 #define NB_PARAMS 14 13 13 14 14 void usage (int argc, char * argv[]) … … 21 21 << " - nb_port_check (uint32_t)" << endl 22 22 << " - speculative_load (uint32_t)" << endl 23 << " - nb_bypass_memory (uint32_t)" << endl 23 24 << " - nb_context (uint32_t)" << endl 24 25 << " - nb_front_end (uint32_t)" << endl … … 26 27 << " - nb_packet (uint32_t)" << endl 27 28 << " - size_general_data (uint32_t)" << endl 29 << " - size_special_data (uint32_t)" << endl 28 30 << " - nb_general_register (uint32_t)" << endl 31 << " - nb_special_register (uint32_t)" << endl 29 32 << "" << endl; 30 33 … … 58 61 const uint32_t _nb_port_check = atoi(argv[x++]); 59 62 const Tspeculative_load_t _speculative_load = fromString<Tspeculative_load_t>(argv[x++]); 63 const uint32_t _nb_bypass_memory = atoi(argv[x++]); 60 64 const uint32_t _nb_context = atoi(argv[x++]); 61 65 const uint32_t _nb_front_end = atoi(argv[x++]); … … 63 67 const uint32_t _nb_packet = atoi(argv[x++]); 64 68 const uint32_t _size_general_data = atoi(argv[x++]); 69 const uint32_t _size_special_data = atoi(argv[x++]); 65 70 const uint32_t _nb_general_register = atoi(argv[x++]); 71 const uint32_t _nb_special_register = atoi(argv[x++]); 66 72 67 73 try … … 74 80 _nb_port_check , 75 81 _speculative_load , 82 _nb_bypass_memory , 76 83 _nb_context , 77 84 _nb_front_end , … … 79 86 _nb_packet , 80 87 _size_general_data , 81 _nb_general_register ); 88 _size_special_data , 89 _nb_general_register , 90 _nb_special_register ); 82 91 83 92 cout << param->print(1); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/src/test1.cpp
r72 r78 73 73 sc_signal<Tlsq_ptr_t > * in_MEMORY_IN_STORE_QUEUE_PTR_WRITE = new sc_signal<Tlsq_ptr_t > (rename.c_str()); 74 74 sc_signal<Tlsq_ptr_t > * in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE = new sc_signal<Tlsq_ptr_t > (rename.c_str()); 75 //sc_signal<Tcontrol_t > * in_MEMORY_IN_HAS_IMMEDIAT = new sc_signal<Tcontrol_t > (rename.c_str());75 sc_signal<Tcontrol_t > * in_MEMORY_IN_HAS_IMMEDIAT = new sc_signal<Tcontrol_t > (rename.c_str()); 76 76 sc_signal<Tgeneral_data_t > * in_MEMORY_IN_IMMEDIAT = new sc_signal<Tgeneral_data_t > (rename.c_str()); 77 77 sc_signal<Tgeneral_data_t > * in_MEMORY_IN_DATA_RA = new sc_signal<Tgeneral_data_t > (rename.c_str()); 78 78 sc_signal<Tgeneral_data_t > * in_MEMORY_IN_DATA_RB = new sc_signal<Tgeneral_data_t > (rename.c_str()); 79 //sc_signal<Tspecial_data_t > * in_MEMORY_IN_DATA_RC = new sc_signal<Tspecial_data_t > (rename.c_str());80 //sc_signal<Tcontrol_t > * in_MEMORY_IN_WRITE_RD = new sc_signal<Tcontrol_t > (rename.c_str());79 sc_signal<Tspecial_data_t > * in_MEMORY_IN_DATA_RC = new sc_signal<Tspecial_data_t > (rename.c_str()); 80 sc_signal<Tcontrol_t > * in_MEMORY_IN_WRITE_RD = new sc_signal<Tcontrol_t > (rename.c_str()); 81 81 sc_signal<Tgeneral_address_t> * in_MEMORY_IN_NUM_REG_RD = new sc_signal<Tgeneral_address_t> (rename.c_str()); 82 //sc_signal<Tcontrol_t > * in_MEMORY_IN_WRITE_RE = new sc_signal<Tcontrol_t > (rename.c_str());83 //sc_signal<Tspecial_address_t> * in_MEMORY_IN_NUM_REG_RE = new sc_signal<Tspecial_address_t> (rename.c_str());82 sc_signal<Tcontrol_t > * in_MEMORY_IN_WRITE_RE = new sc_signal<Tcontrol_t > (rename.c_str()); 83 sc_signal<Tspecial_address_t> * in_MEMORY_IN_NUM_REG_RE = new sc_signal<Tspecial_address_t> (rename.c_str()); 84 84 85 85 sc_signal<Tcontrol_t > * out_MEMORY_OUT_VAL = new sc_signal<Tcontrol_t >(rename.c_str()); … … 89 89 sc_signal<Tcontext_t > * out_MEMORY_OUT_OOO_ENGINE_ID = new sc_signal<Tcontext_t >(rename.c_str()); 90 90 sc_signal<Tpacket_t > * out_MEMORY_OUT_PACKET_ID = new sc_signal<Tpacket_t >(rename.c_str()); 91 // sc_signal<Toperation_t > * out_MEMORY_OUT_OPERATION = new sc_signal<Toperation_t >(rename.c_str()); 92 sc_signal<Ttype_t > * out_MEMORY_OUT_TYPE = new sc_signal<Ttype_t >(rename.c_str()); 91 93 sc_signal<Tcontrol_t > * out_MEMORY_OUT_WRITE_RD = new sc_signal<Tcontrol_t >(rename.c_str()); 92 94 sc_signal<Tgeneral_address_t> * out_MEMORY_OUT_NUM_REG_RD = new sc_signal<Tgeneral_address_t>(rename.c_str()); 93 95 sc_signal<Tgeneral_data_t > * out_MEMORY_OUT_DATA_RD = new sc_signal<Tgeneral_data_t >(rename.c_str()); 94 //sc_signal<Tcontrol_t > * out_MEMORY_OUT_WRITE_RE = new sc_signal<Tcontrol_t >(rename.c_str());95 //sc_signal<Tspecial_address_t> * out_MEMORY_OUT_NUM_REG_RE = new sc_signal<Tspecial_address_t>(rename.c_str());96 //sc_signal<Tspecial_data_t > * out_MEMORY_OUT_DATA_RE = new sc_signal<Tspecial_data_t >(rename.c_str());96 sc_signal<Tcontrol_t > * out_MEMORY_OUT_WRITE_RE = new sc_signal<Tcontrol_t >(rename.c_str()); 97 sc_signal<Tspecial_address_t> * out_MEMORY_OUT_NUM_REG_RE = new sc_signal<Tspecial_address_t>(rename.c_str()); 98 sc_signal<Tspecial_data_t > * out_MEMORY_OUT_DATA_RE = new sc_signal<Tspecial_data_t >(rename.c_str()); 97 99 sc_signal<Texception_t > * out_MEMORY_OUT_EXCEPTION = new sc_signal<Texception_t >(rename.c_str()); 100 sc_signal<Tcontrol_t > * out_MEMORY_OUT_NO_SEQUENCE = new sc_signal<Tcontrol_t >(rename.c_str()); 101 sc_signal<Tgeneral_data_t > * out_MEMORY_OUT_ADDRESS = new sc_signal<Tgeneral_data_t >(rename.c_str()); 98 102 99 103 sc_signal<Tcontrol_t > * out_DCACHE_REQ_VAL = new sc_signal<Tcontrol_t >(rename.c_str()); … … 112 116 sc_signal<Tdcache_error_t > * in_DCACHE_RSP_ERROR = new sc_signal<Tdcache_error_t >(rename.c_str()); 113 117 114 sc_signal<Tcontrol_t > ** out_BYPASS_MEMORY_VAL = new sc_signal<Tcontrol_t > * [_param->_ size_load_queue];115 sc_signal<Tcontext_t > ** out_BYPASS_MEMORY_OOO_ENGINE_ID = new sc_signal<Tcontext_t > * [_param->_ size_load_queue];116 sc_signal<Tgeneral_address_t> ** out_BYPASS_MEMORY_NUM_REG = new sc_signal<Tgeneral_address_t> * [_param->_ size_load_queue];117 sc_signal<Tgeneral_data_t > ** out_BYPASS_MEMORY_DATA = new sc_signal<Tgeneral_data_t > * [_param->_ size_load_queue];118 sc_signal<Tcontrol_t > ** out_BYPASS_MEMORY_VAL = new sc_signal<Tcontrol_t > * [_param->_nb_bypass_memory]; 119 sc_signal<Tcontext_t > ** out_BYPASS_MEMORY_OOO_ENGINE_ID = new sc_signal<Tcontext_t > * [_param->_nb_bypass_memory]; 120 sc_signal<Tgeneral_address_t> ** out_BYPASS_MEMORY_NUM_REG = new sc_signal<Tgeneral_address_t> * [_param->_nb_bypass_memory]; 121 sc_signal<Tgeneral_data_t > ** out_BYPASS_MEMORY_DATA = new sc_signal<Tgeneral_data_t > * [_param->_nb_bypass_memory]; 118 122 119 for (uint32_t i=0; i<_param->_ size_load_queue; i++)123 for (uint32_t i=0; i<_param->_nb_bypass_memory; i++) 120 124 { 121 125 out_BYPASS_MEMORY_VAL [i] = new sc_signal<Tcontrol_t >(rename.c_str()); … … 137 141 (*(_Load_store_unit->out_MEMORY_IN_ACK ))(*(out_MEMORY_IN_ACK )); 138 142 if (_param->_have_port_context_id) 139 143 (*(_Load_store_unit-> in_MEMORY_IN_CONTEXT_ID ))(*( in_MEMORY_IN_CONTEXT_ID )); 140 144 if (_param->_have_port_front_end_id) 141 145 (*(_Load_store_unit-> in_MEMORY_IN_FRONT_END_ID ))(*( in_MEMORY_IN_FRONT_END_ID )); 142 146 if (_param->_have_port_ooo_engine_id) 143 147 (*(_Load_store_unit-> in_MEMORY_IN_OOO_ENGINE_ID ))(*( in_MEMORY_IN_OOO_ENGINE_ID )); 144 148 if (_param->_have_port_packet_id) 145 149 (*(_Load_store_unit-> in_MEMORY_IN_PACKET_ID ))(*( in_MEMORY_IN_PACKET_ID )); 146 150 (*(_Load_store_unit-> in_MEMORY_IN_OPERATION ))(*( in_MEMORY_IN_OPERATION )); 151 (*(_Load_store_unit-> in_MEMORY_IN_TYPE ))(*( in_MEMORY_IN_TYPE )); 147 152 (*(_Load_store_unit-> in_MEMORY_IN_STORE_QUEUE_PTR_WRITE))(*( in_MEMORY_IN_STORE_QUEUE_PTR_WRITE)); 153 if (_param->_have_port_load_queue_ptr) 148 154 (*(_Load_store_unit-> in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ))(*( in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE )); 149 //(*(_Load_store_unit-> in_MEMORY_IN_HAS_IMMEDIAT ))(*( in_MEMORY_IN_HAS_IMMEDIAT ));155 (*(_Load_store_unit-> in_MEMORY_IN_HAS_IMMEDIAT ))(*( in_MEMORY_IN_HAS_IMMEDIAT )); 150 156 (*(_Load_store_unit-> in_MEMORY_IN_IMMEDIAT ))(*( in_MEMORY_IN_IMMEDIAT )); 151 157 (*(_Load_store_unit-> in_MEMORY_IN_DATA_RA ))(*( in_MEMORY_IN_DATA_RA )); 152 158 (*(_Load_store_unit-> in_MEMORY_IN_DATA_RB ))(*( in_MEMORY_IN_DATA_RB )); 153 //(*(_Load_store_unit-> in_MEMORY_IN_DATA_RC ))(*( in_MEMORY_IN_DATA_RC ));154 //(*(_Load_store_unit-> in_MEMORY_IN_WRITE_RD ))(*( in_MEMORY_IN_WRITE_RD ));159 (*(_Load_store_unit-> in_MEMORY_IN_DATA_RC ))(*( in_MEMORY_IN_DATA_RC )); 160 (*(_Load_store_unit-> in_MEMORY_IN_WRITE_RD ))(*( in_MEMORY_IN_WRITE_RD )); 155 161 (*(_Load_store_unit-> in_MEMORY_IN_NUM_REG_RD ))(*( in_MEMORY_IN_NUM_REG_RD )); 156 //(*(_Load_store_unit-> in_MEMORY_IN_WRITE_RE ))(*( in_MEMORY_IN_WRITE_RE ));157 //(*(_Load_store_unit-> in_MEMORY_IN_NUM_REG_RE ))(*( in_MEMORY_IN_NUM_REG_RE ));162 (*(_Load_store_unit-> in_MEMORY_IN_WRITE_RE ))(*( in_MEMORY_IN_WRITE_RE )); 163 (*(_Load_store_unit-> in_MEMORY_IN_NUM_REG_RE ))(*( in_MEMORY_IN_NUM_REG_RE )); 158 164 159 165 (*(_Load_store_unit->out_MEMORY_OUT_VAL ))(*(out_MEMORY_OUT_VAL )); 160 166 (*(_Load_store_unit-> in_MEMORY_OUT_ACK ))(*( in_MEMORY_OUT_ACK )); 161 167 if (_param->_have_port_context_id) 162 168 (*(_Load_store_unit->out_MEMORY_OUT_CONTEXT_ID ))(*(out_MEMORY_OUT_CONTEXT_ID )); 163 169 if (_param->_have_port_front_end_id) 164 170 (*(_Load_store_unit->out_MEMORY_OUT_FRONT_END_ID ))(*(out_MEMORY_OUT_FRONT_END_ID )); 165 171 if (_param->_have_port_ooo_engine_id) 166 172 (*(_Load_store_unit->out_MEMORY_OUT_OOO_ENGINE_ID ))(*(out_MEMORY_OUT_OOO_ENGINE_ID )); 167 173 if (_param->_have_port_packet_id) 168 (*(_Load_store_unit->out_MEMORY_OUT_PACKET_ID ))(*(out_MEMORY_OUT_PACKET_ID )); 174 (*(_Load_store_unit->out_MEMORY_OUT_PACKET_ID ))(*(out_MEMORY_OUT_PACKET_ID )); 175 // (*(_Load_store_unit->out_MEMORY_OUT_OPERATION ))(*(out_MEMORY_OUT_OPERATION )); 176 (*(_Load_store_unit->out_MEMORY_OUT_TYPE ))(*(out_MEMORY_OUT_TYPE )); 169 177 (*(_Load_store_unit->out_MEMORY_OUT_WRITE_RD ))(*(out_MEMORY_OUT_WRITE_RD )); 170 178 (*(_Load_store_unit->out_MEMORY_OUT_NUM_REG_RD ))(*(out_MEMORY_OUT_NUM_REG_RD )); 171 179 (*(_Load_store_unit->out_MEMORY_OUT_DATA_RD ))(*(out_MEMORY_OUT_DATA_RD )); 172 //(*(_Load_store_unit->out_MEMORY_OUT_WRITE_RE ))(*(out_MEMORY_OUT_WRITE_RE ));173 //(*(_Load_store_unit->out_MEMORY_OUT_NUM_REG_RE ))(*(out_MEMORY_OUT_NUM_REG_RE ));174 //(*(_Load_store_unit->out_MEMORY_OUT_DATA_RE ))(*(out_MEMORY_OUT_DATA_RE ));180 (*(_Load_store_unit->out_MEMORY_OUT_WRITE_RE ))(*(out_MEMORY_OUT_WRITE_RE )); 181 (*(_Load_store_unit->out_MEMORY_OUT_NUM_REG_RE ))(*(out_MEMORY_OUT_NUM_REG_RE )); 182 (*(_Load_store_unit->out_MEMORY_OUT_DATA_RE ))(*(out_MEMORY_OUT_DATA_RE )); 175 183 (*(_Load_store_unit->out_MEMORY_OUT_EXCEPTION ))(*(out_MEMORY_OUT_EXCEPTION )); 184 (*(_Load_store_unit->out_MEMORY_OUT_NO_SEQUENCE ))(*(out_MEMORY_OUT_NO_SEQUENCE )); 185 (*(_Load_store_unit->out_MEMORY_OUT_ADDRESS ))(*(out_MEMORY_OUT_ADDRESS )); 176 186 177 187 (*(_Load_store_unit->out_DCACHE_REQ_VAL ))(*(out_DCACHE_REQ_VAL )); … … 192 202 (*(_Load_store_unit-> in_DCACHE_RSP_ERROR ))(*( in_DCACHE_RSP_ERROR )); 193 203 194 if (_param->_speculative_load == SPECULATIVE_LOAD_BYPASS)195 204 { 196 for (uint32_t i=0; i<_param->_ size_load_queue; i++)205 for (uint32_t i=0; i<_param->_nb_bypass_memory; i++) 197 206 { 198 207 (*(_Load_store_unit->out_BYPASS_MEMORY_VAL [i]))(*(out_BYPASS_MEMORY_VAL [i])); … … 486 495 in_MEMORY_IN_TYPE ->write (fifo_request.top()._type ); 487 496 in_MEMORY_IN_STORE_QUEUE_PTR_WRITE->write (fifo_request.top()._store_queue_ptr_write); 497 if (_param->_have_port_load_queue_ptr) 488 498 in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ->write (fifo_request.top()._load_queue_ptr_write ); 489 499 in_MEMORY_IN_IMMEDIAT ->write (fifo_request.top()._immediat ); … … 563 573 TEST(Tcontext_t , out_MEMORY_OUT_OOO_ENGINE_ID->read(), tab_request[packet_id]._ooo_engine_id); 564 574 TEST(Tpacket_t , out_MEMORY_OUT_PACKET_ID ->read(), tab_request[packet_id]._packet_id ); 575 // TEST(Toperation_t , out_MEMORY_OUT_OPERATION ->read(), tab_request[packet_id]._operation ); 576 TEST(Ttype_t , out_MEMORY_OUT_TYPE ->read(), TYPE_MEMORY ); 565 577 TEST(Tcontrol_t , out_MEMORY_OUT_WRITE_RD ->read(), tab_request[packet_id]._write_rd ); 566 578 TEST(Tgeneral_address_t, out_MEMORY_OUT_NUM_REG_RD ->read(), tab_request[packet_id]._num_reg_rd ); … … 682 694 delete in_MEMORY_IN_STORE_QUEUE_PTR_WRITE; 683 695 delete in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ; 684 //delete in_MEMORY_IN_HAS_IMMEDIAT;696 delete in_MEMORY_IN_HAS_IMMEDIAT; 685 697 delete in_MEMORY_IN_IMMEDIAT ; 686 698 delete in_MEMORY_IN_DATA_RA ; 687 699 delete in_MEMORY_IN_DATA_RB ; 688 //delete in_MEMORY_IN_DATA_RC ;689 //delete in_MEMORY_IN_WRITE_RD ;700 delete in_MEMORY_IN_DATA_RC ; 701 delete in_MEMORY_IN_WRITE_RD ; 690 702 delete in_MEMORY_IN_NUM_REG_RD ; 691 //delete in_MEMORY_IN_WRITE_RE ;692 //delete in_MEMORY_IN_NUM_REG_RE ;703 delete in_MEMORY_IN_WRITE_RE ; 704 delete in_MEMORY_IN_NUM_REG_RE ; 693 705 694 706 delete out_MEMORY_OUT_VAL ; … … 698 710 delete out_MEMORY_OUT_OOO_ENGINE_ID; 699 711 delete out_MEMORY_OUT_PACKET_ID ; 712 // delete out_MEMORY_OUT_OPERATION ; 713 delete out_MEMORY_OUT_TYPE ; 700 714 delete out_MEMORY_OUT_WRITE_RD ; 701 715 delete out_MEMORY_OUT_NUM_REG_RD; 702 716 delete out_MEMORY_OUT_DATA_RD ; 703 //delete out_MEMORY_OUT_WRITE_RE ;704 //delete out_MEMORY_OUT_NUM_REG_RE;705 //delete out_MEMORY_OUT_DATA_RE ;717 delete out_MEMORY_OUT_WRITE_RE ; 718 delete out_MEMORY_OUT_NUM_REG_RE; 719 delete out_MEMORY_OUT_DATA_RE ; 706 720 delete out_MEMORY_OUT_EXCEPTION ; 721 delete out_MEMORY_OUT_NO_SEQUENCE; 722 delete out_MEMORY_OUT_ADDRESS ; 707 723 708 724 delete out_DCACHE_REQ_VAL ; … … 721 737 delete in_DCACHE_RSP_ERROR ; 722 738 723 if (_param->_speculative_load == SPECULATIVE_LOAD_BYPASS)724 739 { 725 740 delete [] out_BYPASS_MEMORY_VAL ; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/src/test2.cpp
r77 r78 52 52 2, //_nb_port_check 53 53 SPECULATIVE_LOAD_COMMIT, //_speculative_load 54 0, //_nb_bypass_memory 54 55 1, //_nb_context 55 56 1, //_nb_front_end … … 57 58 128,//_nb_packet 58 59 32, //_size_general_data 59 64 //_nb_general_register 60 2 , //_size_special_data 61 64, //_nb_general_register 62 16 //_nb_special_register 60 63 ); 61 64 … … 89 92 sc_signal<Tlsq_ptr_t > * in_MEMORY_IN_STORE_QUEUE_PTR_WRITE = new sc_signal<Tlsq_ptr_t > (rename.c_str()); 90 93 sc_signal<Tlsq_ptr_t > * in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE = new sc_signal<Tlsq_ptr_t > (rename.c_str()); 91 //sc_signal<Tcontrol_t > * in_MEMORY_IN_HAS_IMMEDIAT = new sc_signal<Tcontrol_t > (rename.c_str());94 sc_signal<Tcontrol_t > * in_MEMORY_IN_HAS_IMMEDIAT = new sc_signal<Tcontrol_t > (rename.c_str()); 92 95 sc_signal<Tgeneral_data_t > * in_MEMORY_IN_IMMEDIAT = new sc_signal<Tgeneral_data_t > (rename.c_str()); 93 96 sc_signal<Tgeneral_data_t > * in_MEMORY_IN_DATA_RA = new sc_signal<Tgeneral_data_t > (rename.c_str()); 94 97 sc_signal<Tgeneral_data_t > * in_MEMORY_IN_DATA_RB = new sc_signal<Tgeneral_data_t > (rename.c_str()); 95 //sc_signal<Tspecial_data_t > * in_MEMORY_IN_DATA_RC = new sc_signal<Tspecial_data_t > (rename.c_str());96 //sc_signal<Tcontrol_t > * in_MEMORY_IN_WRITE_RD = new sc_signal<Tcontrol_t > (rename.c_str());98 sc_signal<Tspecial_data_t > * in_MEMORY_IN_DATA_RC = new sc_signal<Tspecial_data_t > (rename.c_str()); 99 sc_signal<Tcontrol_t > * in_MEMORY_IN_WRITE_RD = new sc_signal<Tcontrol_t > (rename.c_str()); 97 100 sc_signal<Tgeneral_address_t> * in_MEMORY_IN_NUM_REG_RD = new sc_signal<Tgeneral_address_t> (rename.c_str()); 98 //sc_signal<Tcontrol_t > * in_MEMORY_IN_WRITE_RE = new sc_signal<Tcontrol_t > (rename.c_str());99 //sc_signal<Tspecial_address_t> * in_MEMORY_IN_NUM_REG_RE = new sc_signal<Tspecial_address_t> (rename.c_str());101 sc_signal<Tcontrol_t > * in_MEMORY_IN_WRITE_RE = new sc_signal<Tcontrol_t > (rename.c_str()); 102 sc_signal<Tspecial_address_t> * in_MEMORY_IN_NUM_REG_RE = new sc_signal<Tspecial_address_t> (rename.c_str()); 100 103 101 104 sc_signal<Tcontrol_t > * out_MEMORY_OUT_VAL = new sc_signal<Tcontrol_t >(rename.c_str()); … … 105 108 sc_signal<Tcontext_t > * out_MEMORY_OUT_OOO_ENGINE_ID = new sc_signal<Tcontext_t >(rename.c_str()); 106 109 sc_signal<Tpacket_t > * out_MEMORY_OUT_PACKET_ID = new sc_signal<Tpacket_t >(rename.c_str()); 110 // sc_signal<Toperation_t > * out_MEMORY_OUT_OPERATION = new sc_signal<Toperation_t >(rename.c_str()); 111 sc_signal<Ttype_t > * out_MEMORY_OUT_TYPE = new sc_signal<Ttype_t >(rename.c_str()); 107 112 sc_signal<Tcontrol_t > * out_MEMORY_OUT_WRITE_RD = new sc_signal<Tcontrol_t >(rename.c_str()); 108 113 sc_signal<Tgeneral_address_t> * out_MEMORY_OUT_NUM_REG_RD = new sc_signal<Tgeneral_address_t>(rename.c_str()); 109 114 sc_signal<Tgeneral_data_t > * out_MEMORY_OUT_DATA_RD = new sc_signal<Tgeneral_data_t >(rename.c_str()); 110 //sc_signal<Tcontrol_t > * out_MEMORY_OUT_WRITE_RE = new sc_signal<Tcontrol_t >(rename.c_str());111 //sc_signal<Tspecial_address_t> * out_MEMORY_OUT_NUM_REG_RE = new sc_signal<Tspecial_address_t>(rename.c_str());112 //sc_signal<Tspecial_data_t > * out_MEMORY_OUT_DATA_RE = new sc_signal<Tspecial_data_t >(rename.c_str());115 sc_signal<Tcontrol_t > * out_MEMORY_OUT_WRITE_RE = new sc_signal<Tcontrol_t >(rename.c_str()); 116 sc_signal<Tspecial_address_t> * out_MEMORY_OUT_NUM_REG_RE = new sc_signal<Tspecial_address_t>(rename.c_str()); 117 sc_signal<Tspecial_data_t > * out_MEMORY_OUT_DATA_RE = new sc_signal<Tspecial_data_t >(rename.c_str()); 113 118 sc_signal<Texception_t > * out_MEMORY_OUT_EXCEPTION = new sc_signal<Texception_t >(rename.c_str()); 119 sc_signal<Tcontrol_t > * out_MEMORY_OUT_NO_SEQUENCE = new sc_signal<Tcontrol_t >(rename.c_str()); 120 sc_signal<Tgeneral_data_t > * out_MEMORY_OUT_ADDRESS = new sc_signal<Tgeneral_data_t >(rename.c_str()); 114 121 115 122 sc_signal<Tcontrol_t > * out_DCACHE_REQ_VAL = new sc_signal<Tcontrol_t >(rename.c_str()); … … 128 135 sc_signal<Tdcache_error_t > * in_DCACHE_RSP_ERROR = new sc_signal<Tdcache_error_t >(rename.c_str()); 129 136 130 sc_signal<Tcontrol_t > ** out_BYPASS_MEMORY_VAL = new sc_signal<Tcontrol_t > * [_param->_ size_load_queue];131 sc_signal<Tcontext_t > ** out_BYPASS_MEMORY_OOO_ENGINE_ID = new sc_signal<Tcontext_t > * [_param->_ size_load_queue];132 sc_signal<Tgeneral_address_t> ** out_BYPASS_MEMORY_NUM_REG = new sc_signal<Tgeneral_address_t> * [_param->_ size_load_queue];133 sc_signal<Tgeneral_data_t > ** out_BYPASS_MEMORY_DATA = new sc_signal<Tgeneral_data_t > * [_param->_ size_load_queue];137 sc_signal<Tcontrol_t > ** out_BYPASS_MEMORY_VAL = new sc_signal<Tcontrol_t > * [_param->_nb_bypass_memory]; 138 sc_signal<Tcontext_t > ** out_BYPASS_MEMORY_OOO_ENGINE_ID = new sc_signal<Tcontext_t > * [_param->_nb_bypass_memory]; 139 sc_signal<Tgeneral_address_t> ** out_BYPASS_MEMORY_NUM_REG = new sc_signal<Tgeneral_address_t> * [_param->_nb_bypass_memory]; 140 sc_signal<Tgeneral_data_t > ** out_BYPASS_MEMORY_DATA = new sc_signal<Tgeneral_data_t > * [_param->_nb_bypass_memory]; 134 141 135 for (uint32_t i=0; i<_param->_ size_load_queue; i++)142 for (uint32_t i=0; i<_param->_nb_bypass_memory; i++) 136 143 { 137 144 out_BYPASS_MEMORY_VAL [i] = new sc_signal<Tcontrol_t >(rename.c_str()); … … 161 168 (*(_Load_store_unit-> in_MEMORY_IN_PACKET_ID ))(*( in_MEMORY_IN_PACKET_ID )); 162 169 (*(_Load_store_unit-> in_MEMORY_IN_OPERATION ))(*( in_MEMORY_IN_OPERATION )); 170 (*(_Load_store_unit-> in_MEMORY_IN_TYPE ))(*( in_MEMORY_IN_TYPE )); 163 171 (*(_Load_store_unit-> in_MEMORY_IN_STORE_QUEUE_PTR_WRITE))(*( in_MEMORY_IN_STORE_QUEUE_PTR_WRITE)); 172 if (_param->_have_port_load_queue_ptr) 164 173 (*(_Load_store_unit-> in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ))(*( in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE )); 165 //(*(_Load_store_unit-> in_MEMORY_IN_HAS_IMMEDIAT ))(*( in_MEMORY_IN_HAS_IMMEDIAT ));174 (*(_Load_store_unit-> in_MEMORY_IN_HAS_IMMEDIAT ))(*( in_MEMORY_IN_HAS_IMMEDIAT )); 166 175 (*(_Load_store_unit-> in_MEMORY_IN_IMMEDIAT ))(*( in_MEMORY_IN_IMMEDIAT )); 167 176 (*(_Load_store_unit-> in_MEMORY_IN_DATA_RA ))(*( in_MEMORY_IN_DATA_RA )); 168 177 (*(_Load_store_unit-> in_MEMORY_IN_DATA_RB ))(*( in_MEMORY_IN_DATA_RB )); 169 //(*(_Load_store_unit-> in_MEMORY_IN_DATA_RC ))(*( in_MEMORY_IN_DATA_RC ));170 //(*(_Load_store_unit-> in_MEMORY_IN_WRITE_RD ))(*( in_MEMORY_IN_WRITE_RD ));178 (*(_Load_store_unit-> in_MEMORY_IN_DATA_RC ))(*( in_MEMORY_IN_DATA_RC )); 179 (*(_Load_store_unit-> in_MEMORY_IN_WRITE_RD ))(*( in_MEMORY_IN_WRITE_RD )); 171 180 (*(_Load_store_unit-> in_MEMORY_IN_NUM_REG_RD ))(*( in_MEMORY_IN_NUM_REG_RD )); 172 //(*(_Load_store_unit-> in_MEMORY_IN_WRITE_RE ))(*( in_MEMORY_IN_WRITE_RE ));173 //(*(_Load_store_unit-> in_MEMORY_IN_NUM_REG_RE ))(*( in_MEMORY_IN_NUM_REG_RE ));181 (*(_Load_store_unit-> in_MEMORY_IN_WRITE_RE ))(*( in_MEMORY_IN_WRITE_RE )); 182 (*(_Load_store_unit-> in_MEMORY_IN_NUM_REG_RE ))(*( in_MEMORY_IN_NUM_REG_RE )); 174 183 175 184 (*(_Load_store_unit->out_MEMORY_OUT_VAL ))(*(out_MEMORY_OUT_VAL )); … … 183 192 if (_param->_have_port_packet_id) 184 193 (*(_Load_store_unit->out_MEMORY_OUT_PACKET_ID ))(*(out_MEMORY_OUT_PACKET_ID )); 194 // (*(_Load_store_unit->out_MEMORY_OUT_OPERATION ))(*(out_MEMORY_OUT_OPERATION )); 195 (*(_Load_store_unit->out_MEMORY_OUT_TYPE ))(*(out_MEMORY_OUT_TYPE )); 185 196 (*(_Load_store_unit->out_MEMORY_OUT_WRITE_RD ))(*(out_MEMORY_OUT_WRITE_RD )); 186 197 (*(_Load_store_unit->out_MEMORY_OUT_NUM_REG_RD ))(*(out_MEMORY_OUT_NUM_REG_RD )); 187 198 (*(_Load_store_unit->out_MEMORY_OUT_DATA_RD ))(*(out_MEMORY_OUT_DATA_RD )); 188 //(*(_Load_store_unit->out_MEMORY_OUT_WRITE_RE ))(*(out_MEMORY_OUT_WRITE_RE ));189 //(*(_Load_store_unit->out_MEMORY_OUT_NUM_REG_RE ))(*(out_MEMORY_OUT_NUM_REG_RE ));190 //(*(_Load_store_unit->out_MEMORY_OUT_DATA_RE ))(*(out_MEMORY_OUT_DATA_RE ));199 (*(_Load_store_unit->out_MEMORY_OUT_WRITE_RE ))(*(out_MEMORY_OUT_WRITE_RE )); 200 (*(_Load_store_unit->out_MEMORY_OUT_NUM_REG_RE ))(*(out_MEMORY_OUT_NUM_REG_RE )); 201 (*(_Load_store_unit->out_MEMORY_OUT_DATA_RE ))(*(out_MEMORY_OUT_DATA_RE )); 191 202 (*(_Load_store_unit->out_MEMORY_OUT_EXCEPTION ))(*(out_MEMORY_OUT_EXCEPTION )); 203 (*(_Load_store_unit->out_MEMORY_OUT_NO_SEQUENCE ))(*(out_MEMORY_OUT_NO_SEQUENCE )); 204 (*(_Load_store_unit->out_MEMORY_OUT_ADDRESS ))(*(out_MEMORY_OUT_ADDRESS )); 192 205 193 206 (*(_Load_store_unit->out_DCACHE_REQ_VAL ))(*(out_DCACHE_REQ_VAL )); … … 208 221 (*(_Load_store_unit-> in_DCACHE_RSP_ERROR ))(*( in_DCACHE_RSP_ERROR )); 209 222 210 if (_param->_speculative_load == SPECULATIVE_LOAD_BYPASS)211 223 { 212 for (uint32_t i=0; i<_param->_ size_load_queue; i++)224 for (uint32_t i=0; i<_param->_nb_bypass_memory; i++) 213 225 { 214 226 (*(_Load_store_unit->out_BYPASS_MEMORY_VAL [i]))(*(out_BYPASS_MEMORY_VAL [i])); … … 448 460 in_MEMORY_IN_TYPE ->write (fifo_request.top()._type ); 449 461 in_MEMORY_IN_STORE_QUEUE_PTR_WRITE->write (fifo_request.top()._store_queue_ptr_write); 462 if (_param->_have_port_load_queue_ptr) 450 463 in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ->write (fifo_request.top()._load_queue_ptr_write ); 451 464 in_MEMORY_IN_IMMEDIAT ->write (fifo_request.top()._immediat ); … … 533 546 TEST(Tcontext_t , out_MEMORY_OUT_FRONT_END_ID ->read(), tab_request[packet_id]._front_end_id ); 534 547 TEST(Tcontext_t , out_MEMORY_OUT_OOO_ENGINE_ID->read(), tab_request[packet_id]._ooo_engine_id); 548 // TEST(Toperation_t , out_MEMORY_OUT_OPERATION ->read(), tab_request[packet_id]._operation ); 549 TEST(Ttype_t , out_MEMORY_OUT_TYPE ->read(), TYPE_MEMORY ); 535 550 536 551 if (is_operation_memory_load (tab_request[packet_id]._operation)) … … 721 736 delete in_MEMORY_IN_STORE_QUEUE_PTR_WRITE; 722 737 delete in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ; 723 //delete in_MEMORY_IN_HAS_IMMEDIAT;738 delete in_MEMORY_IN_HAS_IMMEDIAT; 724 739 delete in_MEMORY_IN_IMMEDIAT ; 725 740 delete in_MEMORY_IN_DATA_RA ; 726 741 delete in_MEMORY_IN_DATA_RB ; 727 //delete in_MEMORY_IN_DATA_RC ;728 //delete in_MEMORY_IN_WRITE_RD ;742 delete in_MEMORY_IN_DATA_RC ; 743 delete in_MEMORY_IN_WRITE_RD ; 729 744 delete in_MEMORY_IN_NUM_REG_RD ; 730 //delete in_MEMORY_IN_WRITE_RE ;731 //delete in_MEMORY_IN_NUM_REG_RE ;745 delete in_MEMORY_IN_WRITE_RE ; 746 delete in_MEMORY_IN_NUM_REG_RE ; 732 747 733 748 delete out_MEMORY_OUT_VAL ; … … 737 752 delete out_MEMORY_OUT_OOO_ENGINE_ID; 738 753 delete out_MEMORY_OUT_PACKET_ID ; 754 // delete out_MEMORY_OUT_OPERATION ; 755 delete out_MEMORY_OUT_TYPE ; 739 756 delete out_MEMORY_OUT_WRITE_RD ; 740 757 delete out_MEMORY_OUT_NUM_REG_RD; 741 758 delete out_MEMORY_OUT_DATA_RD ; 742 //delete out_MEMORY_OUT_WRITE_RE ;743 //delete out_MEMORY_OUT_NUM_REG_RE;744 //delete out_MEMORY_OUT_DATA_RE ;759 delete out_MEMORY_OUT_WRITE_RE ; 760 delete out_MEMORY_OUT_NUM_REG_RE; 761 delete out_MEMORY_OUT_DATA_RE ; 745 762 delete out_MEMORY_OUT_EXCEPTION ; 763 delete out_MEMORY_OUT_NO_SEQUENCE; 764 delete out_MEMORY_OUT_ADDRESS ; 746 765 747 766 delete out_DCACHE_REQ_VAL ; … … 760 779 delete in_DCACHE_RSP_ERROR ; 761 780 762 if (_param->_speculative_load == SPECULATIVE_LOAD_BYPASS)763 781 { 764 782 delete [] out_BYPASS_MEMORY_VAL ; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h
r76 r78 5 5 * $Id$ 6 6 * 7 * [ 7 * [ Description ] 8 8 * 9 9 * Ce composant peut être amélioré en placant deux ptr de lecture au lieu d'un : un pour l'accès au cache et un pour le commit … … 46 46 #endif 47 47 { 48 // -----[ 48 // -----[ fields ]---------------------------------------------------- 49 49 // Parameters 50 50 protected : const std::string _name; … … 53 53 54 54 #ifdef STATISTICS 55 p rivate: Stat * _stat;55 public : Stat * _stat; 56 56 57 57 private : counter_t * _stat_use_store_queue; … … 83 83 84 84 #ifdef SYSTEMC 85 // ~~~~~[ 85 // ~~~~~[ Interface ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 86 86 // Interface 87 87 public : SC_CLOCK * in_CLOCK ; 88 88 public : SC_IN (Tcontrol_t) * in_NRESET ; 89 89 90 // ~~~~~[ 90 // ~~~~~[ Interface "memory_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 91 91 public : SC_IN (Tcontrol_t ) * in_MEMORY_IN_VAL ; 92 92 public : SC_OUT(Tcontrol_t ) * out_MEMORY_IN_ACK ; … … 96 96 public : SC_IN (Tpacket_t ) * in_MEMORY_IN_PACKET_ID ; 97 97 public : SC_IN (Toperation_t ) * in_MEMORY_IN_OPERATION ; 98 //public : SC_IN (Ttype_t ) * in_MEMORY_IN_TYPE ;98 public : SC_IN (Ttype_t ) * in_MEMORY_IN_TYPE ; 99 99 public : SC_IN (Tlsq_ptr_t ) * in_MEMORY_IN_STORE_QUEUE_PTR_WRITE; 100 100 public : SC_IN (Tlsq_ptr_t ) * in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ; 101 //public : SC_IN (Tcontrol_t ) * in_MEMORY_IN_HAS_IMMEDIAT;101 public : SC_IN (Tcontrol_t ) * in_MEMORY_IN_HAS_IMMEDIAT; 102 102 public : SC_IN (Tgeneral_data_t ) * in_MEMORY_IN_IMMEDIAT ; // memory address 103 103 public : SC_IN (Tgeneral_data_t ) * in_MEMORY_IN_DATA_RA ; // memory address 104 104 public : SC_IN (Tgeneral_data_t ) * in_MEMORY_IN_DATA_RB ; // data (store) 105 //public : SC_IN (Tspecial_data_t ) * in_MEMORY_IN_DATA_RC ;106 //public : SC_IN (Tcontrol_t ) * in_MEMORY_IN_WRITE_RD ; // = (operation==load)105 public : SC_IN (Tspecial_data_t ) * in_MEMORY_IN_DATA_RC ; 106 public : SC_IN (Tcontrol_t ) * in_MEMORY_IN_WRITE_RD ; // = (operation==load) 107 107 public : SC_IN (Tgeneral_address_t) * in_MEMORY_IN_NUM_REG_RD ; // destination (load) 108 //public : SC_IN (Tcontrol_t ) * in_MEMORY_IN_WRITE_RE ;109 //public : SC_IN (Tspecial_address_t) * in_MEMORY_IN_NUM_REG_RE ;110 111 // ~~~~~[ 108 public : SC_IN (Tcontrol_t ) * in_MEMORY_IN_WRITE_RE ; 109 public : SC_IN (Tspecial_address_t) * in_MEMORY_IN_NUM_REG_RE ; 110 111 // ~~~~~[ Interface "memory_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 112 112 public : SC_OUT(Tcontrol_t ) * out_MEMORY_OUT_VAL ; 113 113 public : SC_IN (Tcontrol_t ) * in_MEMORY_OUT_ACK ; … … 116 116 public : SC_OUT(Tcontext_t ) * out_MEMORY_OUT_OOO_ENGINE_ID; 117 117 public : SC_OUT(Tpacket_t ) * out_MEMORY_OUT_PACKET_ID ; 118 //public : SC_OUT(Toperation_t ) * out_MEMORY_OUT_OPERATION ; 119 public : SC_OUT(Ttype_t ) * out_MEMORY_OUT_TYPE ; 118 120 public : SC_OUT(Tcontrol_t ) * out_MEMORY_OUT_WRITE_RD ; // = (operation==load) 119 121 public : SC_OUT(Tgeneral_address_t) * out_MEMORY_OUT_NUM_REG_RD; // destination (load) 120 122 public : SC_OUT(Tgeneral_data_t ) * out_MEMORY_OUT_DATA_RD ; // data (load) 121 //public : SC_OUT(Tcontrol_t ) * out_MEMORY_OUT_WRITE_RE ;122 //public : SC_OUT(Tspecial_address_t) * out_MEMORY_OUT_NUM_REG_RE;123 //public : SC_OUT(Tspecial_data_t ) * out_MEMORY_OUT_DATA_RE ;123 public : SC_OUT(Tcontrol_t ) * out_MEMORY_OUT_WRITE_RE ; 124 public : SC_OUT(Tspecial_address_t) * out_MEMORY_OUT_NUM_REG_RE; 125 public : SC_OUT(Tspecial_data_t ) * out_MEMORY_OUT_DATA_RE ; 124 126 public : SC_OUT(Texception_t ) * out_MEMORY_OUT_EXCEPTION ; 125 126 // ~~~~~[ Interface "dcache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 127 public : SC_OUT(Tcontrol_t ) * out_MEMORY_OUT_NO_SEQUENCE; 128 public : SC_OUT(Tgeneral_data_t ) * out_MEMORY_OUT_ADDRESS ; 129 130 131 // ~~~~~[ Interface "dcache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 127 132 public : SC_OUT(Tcontrol_t ) * out_DCACHE_REQ_VAL ; 128 133 public : SC_IN (Tcontrol_t ) * in_DCACHE_REQ_ACK ; … … 133 138 public : SC_OUT(Tdcache_data_t ) * out_DCACHE_REQ_WDATA ; 134 139 135 // ~~~~~[ Interface "dcache_rsp"]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~140 // ~~~~~[ Interface "dcache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 136 141 public : SC_IN (Tcontrol_t ) * in_DCACHE_RSP_VAL ; 137 142 public : SC_OUT(Tcontrol_t ) * out_DCACHE_RSP_ACK ; … … 141 146 public : SC_IN (Tdcache_error_t ) * in_DCACHE_RSP_ERROR ; 142 147 143 // ~~~~~[ 148 // ~~~~~[ Interface "bypass_memory" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 144 149 public : SC_OUT(Tcontrol_t ) ** out_BYPASS_MEMORY_VAL ; 145 150 public : SC_OUT(Tcontext_t ) ** out_BYPASS_MEMORY_OOO_ENGINE_ID; … … 147 152 public : SC_OUT(Tgeneral_data_t ) ** out_BYPASS_MEMORY_DATA ; 148 153 149 // ~~~~~[ 154 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 150 155 protected : Tstore_queue_entry_t * _store_queue; 151 156 protected : Tload_queue_entry_t * _load_queue; … … 160 165 public : void (morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Load_store_unit::*function_genMealy_retire) (void); 161 166 162 // ~~~~~[ 163 164 // ~~~~~[ 167 // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 168 169 // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 165 170 166 171 // Registers … … 182 187 #endif 183 188 184 // -----[ 189 // -----[ methods ]--------------------------------------------------- 185 190 186 191 #ifdef SYSTEMC -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Parameters.h
r77 r78 32 32 public : const uint32_t _nb_port_check ; 33 33 public : const Tspeculative_load_t _speculative_load ; 34 public : const uint32_t _nb_bypass_memory ; 34 35 //public : const uint32_t _nb_cache_port ; 35 36 public : const uint32_t _nb_context ; … … 38 39 public : const uint32_t _nb_packet ; 39 40 public : const uint32_t _size_general_data ; 41 public : const uint32_t _size_special_data ; 40 42 public : const uint32_t _nb_general_register ; 43 public : const uint32_t _nb_special_register ; 41 44 42 45 public : const uint32_t _size_address_store_queue ; … … 48 51 public : const uint32_t _size_packet_id ; 49 52 public : const uint32_t _size_general_register ; 53 public : const uint32_t _size_special_register ; 50 54 public : const uint32_t _size_dcache_context_id ; 51 55 public : const uint32_t _size_dcache_packet_id ; … … 56 60 public : const bool _have_port_packet_id ; 57 61 public : const bool _have_port_dcache_context_id ; 62 public : const bool _have_port_load_queue_ptr ; 58 63 59 64 public : const Tdcache_address_t _mask_address_lsb ; … … 66 71 uint32_t nb_port_check , 67 72 Tspeculative_load_t speculative_load , 73 uint32_t nb_bypass_memory , 68 74 uint32_t nb_context , 69 75 uint32_t nb_front_end , … … 71 77 uint32_t nb_packet , 72 78 uint32_t size_general_data , 73 uint32_t nb_general_register ); 79 uint32_t size_special_data , 80 uint32_t nb_general_register , 81 uint32_t nb_special_register ); 74 82 75 83 public : Parameters (Parameters & param) ; 76 84 public : ~Parameters () ; 77 85 78 public : std::stringmsg_error (void);86 public : Parameters_test msg_error (void); 79 87 80 88 public : std::string print (uint32_t depth); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Types.h
r71 r78 33 33 typedef enum 34 34 { 35 NO_SPECULATIVE_LOAD ,//each load wait all previous store before the data cache access36 SPECULATIVE_LOAD_ACCESS,//each load wait all previous store before the commiting37 SPECULATIVE_LOAD_COMMIT,//each load commit the result before the end of dependence's check38 SPECULATIVE_LOAD_BYPASS//each load bypass the result before the end of dependence's check35 NO_SPECULATIVE_LOAD //each load wait all previous store before the data cache access 36 ,SPECULATIVE_LOAD_ACCESS //each load wait all previous store before the commiting 37 ,SPECULATIVE_LOAD_COMMIT //each load commit the result before the end of dependence's check 38 //,SPECULATIVE_LOAD_BYPASS //each load bypass the result before the end of dependence's check 39 39 } Tspeculative_load_t; 40 40 … … 212 212 case morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::SPECULATIVE_LOAD_ACCESS : return "speculative_load_access"; break; 213 213 case morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::SPECULATIVE_LOAD_COMMIT : return "speculative_load_commit"; break; 214 case morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::SPECULATIVE_LOAD_BYPASS : return "speculative_load_bypass"; break;214 // case morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::SPECULATIVE_LOAD_BYPASS : return "speculative_load_bypass"; break; 215 215 default : return "" ; break; 216 216 } … … 228 228 (x.compare("speculative_load_commit") == 0)) 229 229 return morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::SPECULATIVE_LOAD_COMMIT; 230 if ( (x.compare("3") == 0) or231 (x.compare("speculative_load_bypass") == 0))232 return morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::SPECULATIVE_LOAD_BYPASS;230 // if ( (x.compare("3") == 0) or 231 // (x.compare("speculative_load_bypass") == 0)) 232 // return morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::SPECULATIVE_LOAD_BYPASS; 233 233 234 234 throw (ErrorMorpheo ("<fromString> : Unknow string : \""+x+"\"")); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit.cpp
r71 r78 69 69 case NO_SPECULATIVE_LOAD : 70 70 case SPECULATIVE_LOAD_ACCESS : 71 71 //case SPECULATIVE_LOAD_BYPASS : 72 72 default : 73 73 { -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_allocation.cpp
r75 r78 72 72 in_MEMORY_IN_PACKET_ID = interface->set_signal_in <Tpacket_t > ("packet_id" ,_param->_size_packet_id ); 73 73 in_MEMORY_IN_OPERATION = interface->set_signal_in <Toperation_t > ("operation" ,_param->_size_operation ); 74 in_MEMORY_IN_TYPE = interface->set_signal_in <Ttype_t > ("type" ,_param->_size_type ); 74 75 in_MEMORY_IN_STORE_QUEUE_PTR_WRITE = interface->set_signal_in <Tlsq_ptr_t > ("store_queue_ptr_write" ,_param->_size_address_store_queue+1); // +1 cf load_queue usage 76 if (_param->_have_port_load_queue_ptr) 75 77 in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE = interface->set_signal_in <Tlsq_ptr_t > ("load_queue_ptr_write" ,_param->_size_address_load_queue ); 76 //in_MEMORY_IN_HAS_IMMEDIAT = interface->set_signal_in <Tcontrol_t > ("has_immediat",1 );78 in_MEMORY_IN_HAS_IMMEDIAT = interface->set_signal_in <Tcontrol_t > ("has_immediat",1 ); 77 79 in_MEMORY_IN_IMMEDIAT = interface->set_signal_in <Tgeneral_data_t > ("immediat" ,_param->_size_general_data ); 78 80 in_MEMORY_IN_DATA_RA = interface->set_signal_in <Tgeneral_data_t > ("data_ra" ,_param->_size_general_data ); 79 81 in_MEMORY_IN_DATA_RB = interface->set_signal_in <Tgeneral_data_t > ("data_rb" ,_param->_size_general_data ); 80 //in_MEMORY_IN_DATA_RC = interface->set_signal_in <Tspecial_data_t > ("data_rc" ,_param->_size_special_data );81 //in_MEMORY_IN_WRITE_RD = interface->set_signal_in <Tcontrol_t > ("write_rd" ,1 );82 in_MEMORY_IN_DATA_RC = interface->set_signal_in <Tspecial_data_t > ("data_rc" ,_param->_size_special_data ); 83 in_MEMORY_IN_WRITE_RD = interface->set_signal_in <Tcontrol_t > ("write_rd" ,1 ); 82 84 in_MEMORY_IN_NUM_REG_RD = interface->set_signal_in <Tgeneral_address_t> ("num_reg_rd" ,1 ); 83 //in_MEMORY_IN_WRITE_RE = interface->set_signal_in <Tcontrol_t > ("write_re" ,1 );84 //in_MEMORY_IN_NUM_REG_RE = interface->set_signal_in <Tspecial_address_t> ("num_reg_re" ,1 );85 in_MEMORY_IN_WRITE_RE = interface->set_signal_in <Tcontrol_t > ("write_re" ,1 ); 86 in_MEMORY_IN_NUM_REG_RE = interface->set_signal_in <Tspecial_address_t> ("num_reg_re" ,1 ); 85 87 } 86 88 … … 105 107 if (_param->_have_port_packet_id) 106 108 out_MEMORY_OUT_PACKET_ID = interface->set_signal_out <Tpacket_t > ("packet_id" ,_param->_size_packet_id ); 109 // out_MEMORY_OUT_OPERATION = interface->set_signal_out <Toperation_t > ("operation" ,_param->_size_operation ); 110 out_MEMORY_OUT_TYPE = interface->set_signal_out <Ttype_t > ("type" ,_param->_size_type ); 107 111 out_MEMORY_OUT_WRITE_RD = interface->set_signal_out <Tcontrol_t > ("write_rd" ,1 ); 108 112 out_MEMORY_OUT_NUM_REG_RD = interface->set_signal_out <Tgeneral_address_t> ("num_reg_rd" ,_param->_size_general_register ); 109 113 out_MEMORY_OUT_DATA_RD = interface->set_signal_out <Tgeneral_data_t > ("data_rd" ,_param->_size_general_data ); 110 // out_MEMORY_OUT_WRITE_RE = interface->set_signal_out <Tcontrol_t > ("write_rd" ,1 );111 //out_MEMORY_OUT_NUM_REG_RE = interface->set_signal_out <Tspecial_address_t> ("num_reg_re" ,_param->_size_general_register );112 //out_MEMORY_OUT_DATA_RE = interface->set_signal_out <Tspecial_data_t > ("data_re" ,_param->_size_general_data );114 out_MEMORY_OUT_WRITE_RE = interface->set_signal_out <Tcontrol_t > ("write_re" ,1 ); 115 out_MEMORY_OUT_NUM_REG_RE = interface->set_signal_out <Tspecial_address_t> ("num_reg_re" ,_param->_size_general_register ); 116 out_MEMORY_OUT_DATA_RE = interface->set_signal_out <Tspecial_data_t > ("data_re" ,_param->_size_general_data ); 113 117 out_MEMORY_OUT_EXCEPTION = interface->set_signal_out <Texception_t > ("exception" ,_param->_size_exception ); 118 out_MEMORY_OUT_NO_SEQUENCE = interface->set_signal_out <Tcontrol_t > ("no_sequence" ,1 ); 119 out_MEMORY_OUT_ADDRESS = interface->set_signal_out <Tgeneral_data_t > ("address" ,_param->_size_general_data ); 114 120 } 115 121 … … 153 159 // ~~~~~[ Interface "bypass_memory" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 154 160 155 161 // if (_param->_speculative_load == SPECULATIVE_LOAD_BYPASS) 156 162 { 157 out_BYPASS_MEMORY_VAL = new SC_OUT(Tcontrol_t ) * [_param->_ size_load_queue];163 out_BYPASS_MEMORY_VAL = new SC_OUT(Tcontrol_t ) * [_param->_nb_bypass_memory]; 158 164 if (_param->_have_port_ooo_engine_id) 159 out_BYPASS_MEMORY_OOO_ENGINE_ID= new SC_OUT(Tcontext_t ) * [_param->_ size_load_queue];160 out_BYPASS_MEMORY_NUM_REG = new SC_OUT(Tgeneral_address_t) * [_param->_ size_load_queue];161 out_BYPASS_MEMORY_DATA = new SC_OUT(Tgeneral_data_t ) * [_param->_ size_load_queue];165 out_BYPASS_MEMORY_OOO_ENGINE_ID= new SC_OUT(Tcontext_t ) * [_param->_nb_bypass_memory]; 166 out_BYPASS_MEMORY_NUM_REG = new SC_OUT(Tgeneral_address_t) * [_param->_nb_bypass_memory]; 167 out_BYPASS_MEMORY_DATA = new SC_OUT(Tgeneral_data_t ) * [_param->_nb_bypass_memory]; 162 168 163 for (uint32_t i=0; i<_param->_ size_load_queue; i++)169 for (uint32_t i=0; i<_param->_nb_bypass_memory; i++) 164 170 { 165 171 Interface_fifo * interface = _interfaces->set_interface("memory_out" -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_deallocation.cpp
r71 r78 44 44 delete in_MEMORY_IN_PACKET_ID ; 45 45 delete in_MEMORY_IN_OPERATION ; 46 delete in_MEMORY_IN_TYPE ; 46 47 delete in_MEMORY_IN_STORE_QUEUE_PTR_WRITE; 48 if (_param->_have_port_load_queue_ptr) 47 49 delete in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ; 48 //delete in_MEMORY_IN_HAS_IMMEDIAT;50 delete in_MEMORY_IN_HAS_IMMEDIAT; 49 51 delete in_MEMORY_IN_IMMEDIAT ; 50 52 delete in_MEMORY_IN_DATA_RA ; 51 53 delete in_MEMORY_IN_DATA_RB ; 52 //delete in_MEMORY_IN_DATA_RC ;53 //delete in_MEMORY_IN_WRITE_RD ;54 delete in_MEMORY_IN_DATA_RC ; 55 delete in_MEMORY_IN_WRITE_RD ; 54 56 delete in_MEMORY_IN_NUM_REG_RD ; 55 //delete in_MEMORY_IN_WRITE_RE ;56 //delete in_MEMORY_IN_NUM_REG_RE ;57 delete in_MEMORY_IN_WRITE_RE ; 58 delete in_MEMORY_IN_NUM_REG_RE ; 57 59 58 60 delete out_MEMORY_OUT_VAL ; … … 66 68 if (_param->_have_port_packet_id) 67 69 delete out_MEMORY_OUT_PACKET_ID ; 70 // delete out_MEMORY_OUT_OPERATION ; 71 delete out_MEMORY_OUT_TYPE ; 68 72 delete out_MEMORY_OUT_WRITE_RD ; 69 73 delete out_MEMORY_OUT_NUM_REG_RD; 70 74 delete out_MEMORY_OUT_DATA_RD ; 71 //delete out_MEMORY_OUT_WRITE_RE ;72 //delete out_MEMORY_OUT_NUM_REG_RE;73 //delete out_MEMORY_OUT_DATA_RE ;75 delete out_MEMORY_OUT_WRITE_RE ; 76 delete out_MEMORY_OUT_NUM_REG_RE; 77 delete out_MEMORY_OUT_DATA_RE ; 74 78 delete out_MEMORY_OUT_EXCEPTION ; 79 delete out_MEMORY_OUT_NO_SEQUENCE; 80 delete out_MEMORY_OUT_ADDRESS ; 75 81 76 82 delete out_DCACHE_REQ_VAL ; … … 91 97 delete in_DCACHE_RSP_ERROR ; 92 98 93 if (_param->_speculative_load == SPECULATIVE_LOAD_BYPASS) 94 { 95 delete [] out_BYPASS_MEMORY_VAL ; 96 if (_param->_have_port_ooo_engine_id) 97 delete [] out_BYPASS_MEMORY_OOO_ENGINE_ID; 98 delete [] out_BYPASS_MEMORY_NUM_REG ; 99 delete [] out_BYPASS_MEMORY_DATA ; 100 } 99 delete [] out_BYPASS_MEMORY_VAL ; 100 if (_param->_have_port_ooo_engine_id) 101 delete [] out_BYPASS_MEMORY_OOO_ENGINE_ID; 102 delete [] out_BYPASS_MEMORY_NUM_REG ; 103 delete [] out_BYPASS_MEMORY_DATA ; 101 104 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 102 105 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMoore.cpp
r71 r78 120 120 if (_param->_have_port_packet_id) 121 121 PORT_WRITE(out_MEMORY_OUT_PACKET_ID , memory_out_packet_id ); 122 // PORT_WRITE(out_MEMORY_OUT_OPERATION , memory_out_operation ); 123 PORT_WRITE(out_MEMORY_OUT_TYPE , TYPE_MEMORY ); 122 124 PORT_WRITE(out_MEMORY_OUT_WRITE_RD , memory_out_write_rd ); 123 125 PORT_WRITE(out_MEMORY_OUT_NUM_REG_RD , memory_out_num_reg_rd ); … … 126 128 // PORT_WRITE(out_MEMORY_OUT_NUM_REG_RE , memory_out_num_reg_re ); 127 129 // PORT_WRITE(out_MEMORY_OUT_DATA_RE , memory_out_data_re ); 130 PORT_WRITE(out_MEMORY_OUT_WRITE_RE , 0); 131 PORT_WRITE(out_MEMORY_OUT_NUM_REG_RE , 0); 132 PORT_WRITE(out_MEMORY_OUT_DATA_RE , 0); 128 133 PORT_WRITE(out_MEMORY_OUT_EXCEPTION , memory_out_exception ); 129 134 PORT_WRITE(out_MEMORY_OUT_NO_SEQUENCE , 0); 135 PORT_WRITE(out_MEMORY_OUT_ADDRESS , 0); 130 136 // ~~~~~[ Interface "dache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 131 137 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_transition.cpp
r75 r78 265 265 // others in speculation_access_queue 266 266 267 #ifdef DEBUG_TEST 268 if (PORT_READ(in_MEMORY_IN_TYPE) != TYPE_MEMORY) 269 throw ERRORMORPHEO(FUNCTION,"The type is different at 'TYPE_MEMORY'"); 270 #endif 267 271 Toperation_t operation = PORT_READ(in_MEMORY_IN_OPERATION); 268 272 Tgeneral_data_t address = (PORT_READ(in_MEMORY_IN_IMMEDIAT) + … … 376 380 _store_queue [index]._packet_id = (not _param->_have_port_packet_id )?0:PORT_READ(in_MEMORY_IN_PACKET_ID ); 377 381 _store_queue [index]._operation = operation; 378 _store_queue [index]._load_queue_ptr_write = PORT_READ(in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE);382 _store_queue [index]._load_queue_ptr_write = (not _param->_have_port_load_queue_ptr)?0:PORT_READ(in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE); 379 383 _store_queue [index]._address = address; 380 384 … … 415 419 416 420 _speculative_access_queue [index]._operation = operation; 417 _speculative_access_queue [index]._load_queue_ptr_write = PORT_READ(in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE);421 _speculative_access_queue [index]._load_queue_ptr_write = (not _param->_have_port_load_queue_ptr)?0:PORT_READ(in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE); 418 422 _speculative_access_queue [index]._store_queue_ptr_write= PORT_READ(in_MEMORY_IN_STORE_QUEUE_PTR_WRITE); 419 423 _speculative_access_queue [index]._address = address; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Parameters.cpp
r77 r78 25 25 uint32_t nb_port_check , 26 26 Tspeculative_load_t speculative_load , 27 uint32_t nb_bypass_memory , 27 28 uint32_t nb_context , 28 29 uint32_t nb_front_end , … … 30 31 uint32_t nb_packet , 31 32 uint32_t size_general_data , 32 uint32_t nb_general_register ): 33 uint32_t size_special_data , 34 uint32_t nb_general_register , 35 uint32_t nb_special_register ): 33 36 _size_store_queue (size_store_queue ), 34 37 _size_load_queue (size_load_queue ), … … 36 39 _nb_port_check (nb_port_check ), 37 40 _speculative_load (speculative_load ), 41 _nb_bypass_memory (nb_bypass_memory ), 38 42 _nb_context (nb_context ), 39 43 _nb_front_end (nb_front_end ), … … 41 45 _nb_packet (nb_packet ), 42 46 _size_general_data (size_general_data ), 47 _size_special_data (size_special_data ), 43 48 _nb_general_register (nb_general_register ), 49 _nb_special_register (nb_special_register ), 44 50 45 51 _size_address_store_queue (log2(size_store_queue )), … … 52 58 _size_packet_id (log2(nb_packet )), 53 59 _size_general_register (log2(nb_general_register)), 60 _size_special_register (log2(nb_special_register)), 54 61 _size_dcache_context_id (_size_context_id + _size_front_end_id + _size_ooo_engine_id), 55 62 _size_dcache_packet_id ((log2((size_store_queue>size_load_queue)?size_store_queue:size_load_queue))+1), … … 60 67 _have_port_packet_id (_size_packet_id >0), 61 68 _have_port_dcache_context_id (_size_dcache_context_id>0), 69 _have_port_load_queue_ptr (_size_load_queue>1), 62 70 63 71 _mask_address_lsb (gen_mask<Tdcache_address_t>(log2(size_general_data/8))), … … 77 85 _nb_port_check (param._nb_port_check ), 78 86 _speculative_load (param._speculative_load ), 87 _nb_bypass_memory (param._nb_bypass_memory ), 79 88 _nb_context (param._nb_context ), 80 89 _nb_front_end (param._nb_front_end ), … … 82 91 _nb_packet (param._nb_packet ), 83 92 _size_general_data (param._size_general_data ), 93 _size_special_data (param._size_special_data ), 84 94 _nb_general_register (param._nb_general_register ), 95 _nb_special_register (param._nb_special_register ), 85 96 86 97 _size_address_store_queue (param._size_address_store_queue ), … … 93 104 _size_packet_id (param._size_packet_id ), 94 105 _size_general_register (param._size_general_register ), 106 _size_special_register (param._size_special_register ), 95 107 _size_dcache_context_id (param._size_dcache_context_id ), 96 108 _size_dcache_packet_id (param._size_dcache_packet_id ), … … 100 112 _have_port_ooo_engine_id (param._have_port_ooo_engine_id), 101 113 _have_port_packet_id (param._have_port_packet_id ), 102 103 114 _have_port_dcache_context_id(param._have_port_dcache_context_id), 115 _have_port_load_queue_ptr(param._have_port_load_queue_ptr), 104 116 105 117 _mask_address_lsb (param._mask_address_lsb), -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Parameters_msg_error.cpp
r71 r78 21 21 #undef FUNCTION 22 22 #define FUNCTION "Load_store_unit::msg_error" 23 std::stringParameters::msg_error(void)23 Parameters_test Parameters::msg_error(void) 24 24 { 25 25 log_printf(FUNC,Load_store_unit,FUNCTION,"Begin"); 26 26 27 std::string msg = "";27 Parameters_test test("Load_store_unit"); 28 28 29 29 switch (_speculative_load) … … 31 31 case SPECULATIVE_LOAD_COMMIT : 32 32 { 33 if (not (_nb_bypass_memory == 0)) 34 test.error("Bypass memory is not supported. Please wait a next revision."); 35 33 36 break; 34 37 } 35 38 case NO_SPECULATIVE_LOAD : 36 39 case SPECULATIVE_LOAD_ACCESS : 37 case SPECULATIVE_LOAD_BYPASS :40 // case SPECULATIVE_LOAD_BYPASS : 38 41 default : 39 42 { 40 msg += " - Speculative load scheme is not supported : " +toString(_speculative_load); 43 if (not (_nb_bypass_memory == 0)) 44 test.error("In the load scheme '"+toString(_speculative_load)+"', they have none bypass."); 45 46 test.error("Speculative load scheme '"+toString(_speculative_load)+"' is not supported. Please wait a next revision."); 41 47 break; 42 48 } 43 49 } 44 50 45 return msg; 51 if (not (_size_store_queue >= 2)) 52 test.error("Store queue must have at less two slot."); 53 54 if (not (_nb_bypass_memory <= _size_load_queue)) 55 test.error("Bypass number must be less than load_queue's size."); 46 56 47 57 log_printf(FUNC,Load_store_unit,FUNCTION,"End"); 58 59 return test; 60 48 61 }; 49 62 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Parameters_print.cpp
r77 r78 33 33 xml.singleton_begin("nb_port_check "); xml.attribut("value",toString(_nb_port_check )); xml.singleton_end(); 34 34 xml.singleton_begin("speculative_load "); xml.attribut("value",toString(_speculative_load )); xml.singleton_end(); 35 xml.singleton_begin("nb_bypass_memory "); xml.attribut("value",toString(_nb_bypass_memory )); xml.singleton_end(); 35 36 xml.singleton_begin("nb_context "); xml.attribut("value",toString(_nb_context )); xml.singleton_end(); 36 37 xml.singleton_begin("nb_front_end "); xml.attribut("value",toString(_nb_front_end )); xml.singleton_end();
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