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Diff Rev Age Author Log Message
(edit) @460   11 years devigne Introducing merged components between the last trunk TSAR version and …
(edit) @459   11 years devigne Erasing ODCCP branch to ease the merge of this branch with the trunk
(edit) @458   11 years lgarcia Cosmetic (suppression of warning in memcache and vcache)
(edit) @457   11 years lgarcia fixing merging bug in vci_mem_cache.cpp
(edit) @456   11 years lgarcia Introduction of RWT branch New components : -dspin_rwt_param (Cleanup …
(edit) @455   11 years cfuguet Merged /trunk/modules/vci_mem_cache:449 with …
(edit) @454   11 years haoliu modified CC_RECEIVE FSM and CC_CHECK FSM (icache and dcache) for new …
(edit) @453   11 years devigne Rename dspin_dhccp_param into dspin_odccp_param
(edit) @452   11 years devigne Introduction of ODCCP branch New components : -dspin_odccp_param …
(edit) @448   11 years cfuguet Modification in branches/v5/platforms/tsar_generic_xbar: - Adding a …
(edit) @447   11 years cfuguet Adding tsar_generic_xbar platform in branches/v5/platforms: - This …
(edit) @446   11 years cfuguet Modifications in vci_cc_vcache_wrapper: - Merging the states …
(edit) @445   11 years cfuguet Bugfix in vci_mem_cache: - Adding missing "strings" for …
(edit) @444   11 years cfuguet Modifications in branches/v5/modules/vci_cc_vcache_wrapper: - …
(edit) @443   11 years cfuguet Merging branch/v5/vci_cc_vcache_wrapper with trunk modifications to …
(edit) @442   11 years cfuguet Modifications in branches/v5/communication/dspin_dhccp_param: - …
(edit) @441   11 years cfuguet Modifications in branches/v5/vci_mem_cache: - Changing name of CC …
(edit) @440   11 years cfuguet Merging branch/v5/vci_mem_cache with trunk modifications to start the …
(edit) @420   11 years porquet various modifications to the platform - make simulation parameters a …
(edit) @419   11 years porquet modifications in Makefile - I can't stand this banner anymore - rule …
(edit) @418   11 years porquet just for me
(edit) @414   12 years porquet oups in segmentation.h
(edit) @410   12 years porquet add a new platform tsarv4 - mono mipsel32 - xicu, blockdevice, tty …
(edit) @407   12 years porquet add missing header (for ::read, ::write, etc.)
(edit) @380   12 years simerabe Another bugfix
(edit) @371   12 years joannou Create TsarV4 branch from trunk as of now
(edit) @370   12 years joannou In tsarv5_generic_mmu : * top.cpp : go look for hard_config.h in …
(edit) @369   12 years joannou Bugfix in vci_cc_vcache_wrapper v5 : forgot to copy the nline when …
(edit) @367   12 years cfuguet Modification in v5/vci_mem_cache Aligning to left the SRCID into the …
(edit) @366   12 years joannou In vci_cc_vcache_wrapper v5, * now using the new generic_cache_tsar …
(edit) @364   12 years haoliu Bug fix in dcache fsm, in dcache_xtn_dc_inval_go state, set the slot …
(edit) @363   12 years joannou In tsarv5_generic_mmu platform, in tsar cluster, added l_width to …
(edit) @362   12 years cfuguet Bugfix in vci_mem_cache: In function "copy()" of the xram_transaction …
(edit) @360   12 years joannou In tsarv5_generic_mmu platform (tsarcluster): * connected vci to dspin …
(edit) @359   12 years joannou bugfix : correctly updating the r_preempt register
(edit) @358   12 years simerabe bugfix : preempt in case of broadcast, palloc in case of single flit
(edit) @357   12 years simerabe fixbug : test on eop in case of single_flit coherence request
(edit) @356   12 years cfuguet Modifying comments in the dspin_dhccp_param to comply the type …
(edit) @355   12 years joannou In vci_cc_vcache_wrapper v5 - added check for p_dspin_in.write in …
(edit) @354   12 years cfuguet Bugfix in branches/v5/vci_mem_cache Adding missing condition in …
(edit) @353   12 years cfuguet Bugfix in branches/v5/vci_mem_cache Adding missing fifo get in case of …
(edit) @351   12 years joannou Got rid of intermediate v5 version. _dspin_coherence versions changed …
(edit) @350   12 years alain Introducing Platform tsarv5_dspin_array, that can be used for TSAR …
(edit) @346   12 years alain New contructors for vci_mem_cache & vci_cc_vcache, as we don't need …
(edit) @345   12 years alain Introducing the cluster component in tsarv5_generic_mmu platform.
(edit) @344   12 years alain Introducing the tsarv5_generic_mmu platform.
(edit) @343   12 years cfuguet Using the Xicu SOFT IRQs (IPIs). Adding them on the Xicu constructor
(edit) @342   12 years joannou Introducing tsar_generic_mmu_dspin_coherence platform (ring dspin for …
(edit) @341   12 years joannou In vci_cc_vcache_wrapper_dspin_coherence, DCACHE_TLB_PTE1_MISS and …
(edit) @339   12 years cfuguet Erasing always false condition in the if statement of the …
(edit) @338   12 years joannou * In vci_cc_vcache_wrapper_dspin_coherence, modified both states …
(edit) @336   12 years cfuguet Bug fix in the vci_cc_vcache_wrapper and vci_mem_cache components (and …
(edit) @335   12 years joannou Added llsc table initialization in both vci_mem_cache and …
(edit) @333   12 years joannou - In vci_cc_vcache_wrapper_dspin_coherence : initializing …
(edit) @332   12 years joannou Updated top.cpp in tsar_mono_mmu_dspin_coherence to respect new file …
(edit) @331   12 years joannou Renaming all files form vci_cc_vcache_wrapper_dspin_coherence and …
(edit) @330   12 years joannou * Commented debug in dspin_local_ring_fast_c * Added test on plen …
(edit) @329   12 years joannou Added test on INST/DATA for the CLACK in the …
(edit) @328   12 years cfuguet Including TYPE_CLEANUP_ACK_INST and TYPE_CLEANUP_ACK_DATA in the …
(edit) @327   12 years simerabe introducing topcell examples using dspin ring interconnect
(edit) @326   12 years simerabe introducing 2 new components : simple and local ring interconnect …
(edit) @325   12 years joannou bugfix in vci_cc_vcache_wrapper_dspin_coherence : - consume fifo in …
(edit) @323   12 years joannou removed unusefull flipflop r_*cache_cc_fifo_done + syntax correction …
(edit) @321   12 years joannou bugfix in vci_cc_vcache_wrapper_dspin_coherence in coherence type checking
(edit) @320   12 years cfuguet vci_mem_cache_dspin_coherence: - Fixing typo error in …
(edit) @319   12 years cfuguet Fix bug in vci_mem_cache_dspin_coherence. The write signal in the …
(edit) @318   12 years joannou vci_cc_vcache_wrapper_dspin_coherence now use DspinDhccpParam::* types …
(edit) @317   12 years cfuguet Introducing missing debug strings in the vci_mem_cache cpp file
(edit) @316   12 years joannou Introducing new tsar_mono_mmu_dspin_coherence platform Same as …
(edit) @315   12 years joannou Introducing new dspin interface for …
(edit) @313   12 years cfuguet Erasing useless template parameters for the …
(edit) @312   12 years cfuguet Updating width of the way index in DSPIN coherence flits. Using 2 bits …
(edit) @311   12 years cfuguet Including GET and SET methods for the FROM_L1_BC and FROM_MC_BC bit in …
(edit) @310   12 years cfuguet Introducing FROM_L1_BC and FROM_MC_BC in dspin param class to access …
(edit) @309   12 years joannou Bugfix : typo in component name (was 'dhcpp', is now 'dhccp')
(edit) @308   12 years cfuguet Fixing parameter name error in metadata of vci_mem_cache
(edit) @307   12 years cfuguet Including vci_mem_cache v5 using dspin interface for the coherence …
(edit) @306   12 years joannou Added tsar_mono_mmu and tsar_generic_mmu platforms
(edit) @305   12 years joannou In vci_mem_cache component: Adding an assert for cleanup commands …
(edit) @304   12 years joannou Bug fixing in vci_cc_vcache_wrapper component : - In TGT_RSP_DCACHE, …
(edit) @300   12 years joannou Moved tsar modules vci_cc_vcache_wrapper and vci_mem_cache under the …
(edit) @299   12 years alain bug fixing: coherence interrupt must be taken in the MISS_DIR_UPDT states.
(edit) @296   12 years alain introducing major modifications in vci_cc_vcache_wrappers - remove …
(edit) @295   12 years cfuguet Introducing branches/v5/ components directory. This branch will be …
(add) @294   12 years cfuguet Creating branch repertory for the TSAR svn repository. Copying the …
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