[56] | 1 | % vim:set spell: |
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| 2 | % vim:spell spelllang=en: |
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| 3 | |
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[23] | 4 | \begin{taskinfo} |
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[126] | 5 | \let\BULL\leader |
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| 6 | \let\UPMC\enable |
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[23] | 7 | \let\TIMA\enable |
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[126] | 8 | \let\THALES\enable |
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[113] | 9 | \let\XILINX\enable |
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[23] | 10 | \end{taskinfo} |
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| 11 | % |
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| 12 | \begin{objectif} |
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| 13 | This task pools the features dedicated to HPC system design. It is described on |
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| 14 | figures~\ref{coach-flow} and \ref{archi-hpc}. It consists in |
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| 15 | \begin{itemize} |
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[111] | 16 | \item Providing a software tool that helps the HPC designer to find a good partition of the initial application |
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[56] | 17 | (figure~\ref{archi-hpc}). |
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[126] | 18 | \item specification of the communication schemes between the software part running on the PC and the |
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| 19 | FPGA-SoC. |
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[38] | 20 | \item Implementing the communication scheme at all levels: partition help, software |
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[23] | 21 | implementation both on the PC and in the operating system of the FPGA-SoC, hardware. |
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[278] | 22 | %\item Providing support for dynamic partial reconfiguration of \xilinx FPGA in order |
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| 23 | %to optimize FPGA ressource usage. |
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[23] | 24 | \end{itemize} |
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[56] | 25 | |
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[23] | 26 | The low level hardware transmission support will be the PCI/X bus which allows high bit-rate |
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[237] | 27 | transfers. The reasons of this choice are that both \altera and \xilinx provide PCI/X IP for |
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[23] | 28 | their FPGA and that GPU HPC softwares use also it. |
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[111] | 29 | %This will allow us at least to be inspired by GPU communication schemes and may be to reuse |
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| 30 | %parts of the GPU softwares. |
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[56] | 31 | |
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[23] | 32 | \end{objectif} |
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| 33 | % |
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[52] | 34 | \begin{workpackage} |
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[278] | 35 | \subtask{Implementation of API between PC and FPGA-SoC} |
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[144] | 36 | This \ST deals with the COACH HPC feature that consists in accelerating an existing |
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[278] | 37 | application running on a PC by migrating critical parts into a SoC implemented on an |
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[144] | 38 | FPGA plugged to the PC PCI/X bus. |
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| 39 | The main steps and components of this \ST are: |
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| 40 | \begin{itemize} |
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| 41 | \item The definition of the communication middleware as a software API (Application |
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| 42 | Programing Interface) between the application part running on the PC and the |
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| 43 | application part running on the FPGA-SoC. |
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| 44 | \item A software for helping the end-user to partition applications (figure~\ref{archi-hpc}). |
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| 45 | This software is a library implementing the communication API with features to profile |
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| 46 | the partitioned application. |
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| 47 | \item The implementation of the communication API on the both sides (PC part and FPGA-SoC). |
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| 48 | \end{itemize} |
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[23] | 49 | \begin{livrable} |
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[231] | 50 | \itemL{0}{6}{d}{\Sbull}{HPC communication API}{3:0:0} |
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[52] | 51 | \setMacroInAuxFile{hpcCommApi} |
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[111] | 52 | Specification describing the API. |
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[144] | 53 | \itemL{6}{12}{x}{\Supmc}{HPC partionning helper}{1:0:0} |
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| 54 | \setMacroInAuxFile{hpcCommHelper} |
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[155] | 55 | A library implementing the communication API defined in the {\hpcCommApi} deliverable. |
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[278] | 56 | This library is dedicated to help the end-user to partition an application for HPC. |
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[154] | 57 | \itemL{12}{21}{x}{\Supmc}{HPC API for Linux PC}{0:2.5:0} |
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[144] | 58 | \setMacroInAuxFile{hpcCommLinux} |
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[278] | 59 | The PC part of the HPC communication API that communicates with the FPGA-SOC, a |
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| 60 | library and a LINUX module. |
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| 61 | % \itemL{12}{21}{x}{\Supmc}{HPC API for MUTEKH OS}{0:2.5:0} |
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| 62 | % \setMacroInAuxFile{hpcMutekDriver} |
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| 63 | % The FPGA-SoC part of the communication API, a driver. |
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[144] | 64 | \itemL{21}{24}{x}{\Stima}{HPC API for DNA OS}{0:3:0} |
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| 65 | \setMacroInAuxFile{hpcDnaDriver} |
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[278] | 66 | The FPGA-SoC part of the communication API. |
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| 67 | % Port of the {\hpcMutekDriver} driver on the DNA OS. |
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| 68 | % \itemL{24}{33}{x}{\Supmc}{HPC API}{0:0:1} |
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| 69 | % Bug corrections and enhancements of communication middleware |
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| 70 | % (\novers{\hpcCommApi}, \novers{\hpcCommHelper}, \novers{\hpcCommLinux}, |
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| 71 | % \novers{\hpcMutekDriver}, \novers{\hpcDnaDriver}). |
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[23] | 72 | \end{livrable} |
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[144] | 73 | |
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[278] | 74 | \subtask{SystemC model of the PCI/X} |
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| 75 | This \ST deals with the implementation of hardware and SystemC modules |
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[134] | 76 | required by the neutral architectural template for using the PCI/X IP of \altera and \xilinx. |
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[23] | 77 | \begin{livrable} |
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[278] | 78 | % FIXME: moved to task 3 (CSG) |
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| 79 | % \itemL{9}{18}{h}{\Stima}{HPC hardware \xilinx}{3:9:0} |
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| 80 | % \setMacroInAuxFile{hpcPlbBridge} |
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| 81 | % The synthesizable VHDL description of a PLB/VCI bridge and its corresponding SystemC model. |
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| 82 | % \itemL{9}{18}{h}{\Supmc}{HPC hardware \altera}{1:2:0} |
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| 83 | % \setMacroInAuxFile{hpcAvalonBridge} |
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| 84 | % The synthesizable VHDL description of an AVALON/VCI bridge and its corresponding SystemC model. |
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[59] | 85 | \itemL{9}{24}{h}{\Supmc}{PCI/X traffic generator}{1:1:0} |
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| 86 | The SystemC description of a component that generates PCI/X traffic. It is |
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| 87 | required to prototype FPGA-SoC dedicated to HPC. |
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[23] | 88 | \end{livrable} |
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[59] | 89 | |
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[278] | 90 | % \subtask This \ST consists in integrating dynamic partial reconfiguration of \xilinx FPGA in the CSG design flow. |
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| 91 | % It also includes appropriate SoC-FPGA OS drivers and a modification of the profiling library. |
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| 92 | % \begin{livrable} |
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| 93 | % \itemL{24}{36}{x}{\Supmc}{CSG support for \ganttlf reconfiguration}{0:0:2} |
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| 94 | % Modification of the CSG software to support statically reconfigurable tasks. |
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| 95 | % \itemL{18}{36}{x}{\Stima}{CSG module for \ganttlf dynamic reconfiguration}{0:4:12} |
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| 96 | % This livrable is a CSG module allowing to partition the task graph along |
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| 97 | % the dynamic partial reconfiguration regions. The resulting task-region assignement |
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| 98 | % is directly used for generation of bitstreams. The module also produces reconfiguration |
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| 99 | % management software to be run on the SoC-FPGA. |
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| 100 | % \itemL{18}{30}{x}{\Stima}{Dynamic reconfiguration \ganttlf for DNA drivers}{0:3:3} |
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| 101 | % \setMacroInAuxFile{hpcDynconfDriver} |
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| 102 | % The drivers required by the DNA OS in order to manage dynamic partial |
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| 103 | % reconfiguration inside the SoC-FPGA. |
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| 104 | % \itemL{30}{36}{x}{\Supmc}{Dynamic reconfiguration \ganttlf for MUTEKH drivers}{0:0:1} |
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| 105 | % Port of the {\hpcDynconfDriver} drivers on the MUTEKH OS. |
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| 106 | % \itemL{24}{36}{x}{\Stima}{Profiler for \ganttlf dynamic reconfiguration}{0:0:6} |
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| 107 | % Extension of the HPC partionning helper in order to integrate dynamic partial |
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| 108 | % reconfiguration dedicated features (reconfiguration time of regions, variable |
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| 109 | % number of coprocessors). |
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| 110 | % \itemL{24}{36}{d}{\Sxilinx}{Optimisation for \xilinx \ganttlf dynamic reconfiguration}{0:0:2} |
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| 111 | % \xilinx will work with \tima in order to better take into account during |
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| 112 | % partitioning decisions specific constraints due to partial reconfiguration process. |
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| 113 | % The deliverable is a document describing the \xilinx specific constraints. |
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| 114 | % \end{livrable} |
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| 115 | % %\item This \ST is the delivery of 2 PCI/X \mustbecompleted{FIXME: Stratix4} FPGA board |
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| 116 | % % with its PCI/X IP. These boards are dedicated to the COACH HPC development. |
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| 117 | % % They are based on \mustbecompleted{FIXME:stratix4} FPGA device of 400,000 LUT. |
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| 118 | % % \begin{livrable} |
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| 119 | % % \itemL{0}{6}{m}{\Saltera}{HPC development boards}{0:0:0} Two PCI/X FPGA boards. |
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| 120 | % % \end{livrable} |
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[23] | 121 | \end{workpackage} |
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