[56] | 1 | % vim:set spell: |
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| 2 | % vim:spell spelllang=en: |
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| 3 | |
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[23] | 4 | \begin{taskinfo} |
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[126] | 5 | \let\BULL\leader |
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| 6 | \let\UPMC\enable |
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[23] | 7 | \let\TIMA\enable |
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[126] | 8 | \let\THALES\enable |
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[113] | 9 | \let\XILINX\enable |
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[23] | 10 | \end{taskinfo} |
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| 11 | % |
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| 12 | \begin{objectif} |
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[287] | 13 | This task deals with the COACH HPC feature that consists in accelerating an existing |
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| 14 | application running on a PC by migrating critical parts into a SoC implemented on an |
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| 15 | FPGA plugged to the PC PCI/X bus (figures~\ref{coach-flow} and \ref{archi-hpc}). |
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| 16 | It consists in: |
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[23] | 17 | \begin{itemize} |
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[287] | 18 | \item Specification and implementation of the communication schemes between the software part running on the PC and the |
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[126] | 19 | FPGA-SoC. |
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[287] | 20 | \item Providing a performance analysis tool helping user in the HPC partitionning (figure~\ref{archi-hpc}). |
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| 21 | \item Providing support for configuration of the FPGA in order to set up the HPC environement. |
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[23] | 22 | \end{itemize} |
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[56] | 23 | |
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[23] | 24 | The low level hardware transmission support will be the PCI/X bus which allows high bit-rate |
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[237] | 25 | transfers. The reasons of this choice are that both \altera and \xilinx provide PCI/X IP for |
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[23] | 26 | their FPGA and that GPU HPC softwares use also it. |
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[111] | 27 | %This will allow us at least to be inspired by GPU communication schemes and may be to reuse |
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| 28 | %parts of the GPU softwares. |
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[56] | 29 | |
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[23] | 30 | \end{objectif} |
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| 31 | % |
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[52] | 32 | \begin{workpackage} |
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[278] | 33 | \subtask{Implementation of API between PC and FPGA-SoC} |
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[23] | 34 | \begin{livrable} |
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[231] | 35 | \itemL{0}{6}{d}{\Sbull}{HPC communication API}{3:0:0} |
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[52] | 36 | \setMacroInAuxFile{hpcCommApi} |
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[111] | 37 | Specification describing the API. |
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[144] | 38 | \itemL{6}{12}{x}{\Supmc}{HPC partionning helper}{1:0:0} |
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| 39 | \setMacroInAuxFile{hpcCommHelper} |
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[155] | 40 | A library implementing the communication API defined in the {\hpcCommApi} deliverable. |
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[278] | 41 | This library is dedicated to help the end-user to partition an application for HPC. |
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[154] | 42 | \itemL{12}{21}{x}{\Supmc}{HPC API for Linux PC}{0:2.5:0} |
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[144] | 43 | \setMacroInAuxFile{hpcCommLinux} |
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[278] | 44 | The PC part of the HPC communication API that communicates with the FPGA-SOC, a |
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| 45 | library and a LINUX module. |
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| 46 | % \itemL{12}{21}{x}{\Supmc}{HPC API for MUTEKH OS}{0:2.5:0} |
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| 47 | % \setMacroInAuxFile{hpcMutekDriver} |
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| 48 | % The FPGA-SoC part of the communication API, a driver. |
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[144] | 49 | \itemL{21}{24}{x}{\Stima}{HPC API for DNA OS}{0:3:0} |
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| 50 | \setMacroInAuxFile{hpcDnaDriver} |
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[278] | 51 | The FPGA-SoC part of the communication API. |
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| 52 | % Port of the {\hpcMutekDriver} driver on the DNA OS. |
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| 53 | % \itemL{24}{33}{x}{\Supmc}{HPC API}{0:0:1} |
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| 54 | % Bug corrections and enhancements of communication middleware |
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| 55 | % (\novers{\hpcCommApi}, \novers{\hpcCommHelper}, \novers{\hpcCommLinux}, |
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| 56 | % \novers{\hpcMutekDriver}, \novers{\hpcDnaDriver}). |
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[23] | 57 | \end{livrable} |
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[144] | 58 | |
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[278] | 59 | \subtask{SystemC model of the PCI/X} |
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[287] | 60 | This \ST deals with the implementation of SystemC modules |
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[134] | 61 | required by the neutral architectural template for using the PCI/X IP of \altera and \xilinx. |
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[23] | 62 | \begin{livrable} |
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[278] | 63 | % FIXME: moved to task 3 (CSG) |
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| 64 | % \itemL{9}{18}{h}{\Stima}{HPC hardware \xilinx}{3:9:0} |
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| 65 | % \setMacroInAuxFile{hpcPlbBridge} |
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| 66 | % The synthesizable VHDL description of a PLB/VCI bridge and its corresponding SystemC model. |
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| 67 | % \itemL{9}{18}{h}{\Supmc}{HPC hardware \altera}{1:2:0} |
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| 68 | % \setMacroInAuxFile{hpcAvalonBridge} |
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| 69 | % The synthesizable VHDL description of an AVALON/VCI bridge and its corresponding SystemC model. |
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[59] | 70 | \itemL{9}{24}{h}{\Supmc}{PCI/X traffic generator}{1:1:0} |
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| 71 | The SystemC description of a component that generates PCI/X traffic. It is |
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| 72 | required to prototype FPGA-SoC dedicated to HPC. |
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[23] | 73 | \end{livrable} |
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[59] | 74 | |
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[287] | 75 | \subtask{HPC environment set up} |
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| 76 | |
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[278] | 77 | % It also includes appropriate SoC-FPGA OS drivers and a modification of the profiling library. |
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[287] | 78 | \begin{livrable} |
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| 79 | \itemL{24}{36}{x}{\Stima}{Support for HPC environment set up}{0:0:2} |
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| 80 | Modification of the CSG software to set-up the HPC environement: Bitsream loader. |
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| 81 | \end{livrable} |
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[278] | 82 | % \itemL{18}{36}{x}{\Stima}{CSG module for \ganttlf dynamic reconfiguration}{0:4:12} |
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| 83 | % This livrable is a CSG module allowing to partition the task graph along |
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| 84 | % the dynamic partial reconfiguration regions. The resulting task-region assignement |
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| 85 | % is directly used for generation of bitstreams. The module also produces reconfiguration |
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| 86 | % management software to be run on the SoC-FPGA. |
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| 87 | % \itemL{18}{30}{x}{\Stima}{Dynamic reconfiguration \ganttlf for DNA drivers}{0:3:3} |
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| 88 | % \setMacroInAuxFile{hpcDynconfDriver} |
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| 89 | % The drivers required by the DNA OS in order to manage dynamic partial |
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| 90 | % reconfiguration inside the SoC-FPGA. |
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| 91 | % \itemL{30}{36}{x}{\Supmc}{Dynamic reconfiguration \ganttlf for MUTEKH drivers}{0:0:1} |
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| 92 | % Port of the {\hpcDynconfDriver} drivers on the MUTEKH OS. |
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| 93 | % \itemL{24}{36}{x}{\Stima}{Profiler for \ganttlf dynamic reconfiguration}{0:0:6} |
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| 94 | % Extension of the HPC partionning helper in order to integrate dynamic partial |
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| 95 | % reconfiguration dedicated features (reconfiguration time of regions, variable |
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| 96 | % number of coprocessors). |
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| 97 | % \itemL{24}{36}{d}{\Sxilinx}{Optimisation for \xilinx \ganttlf dynamic reconfiguration}{0:0:2} |
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| 98 | % \xilinx will work with \tima in order to better take into account during |
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| 99 | % partitioning decisions specific constraints due to partial reconfiguration process. |
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| 100 | % The deliverable is a document describing the \xilinx specific constraints. |
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| 101 | % \end{livrable} |
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| 102 | % %\item This \ST is the delivery of 2 PCI/X \mustbecompleted{FIXME: Stratix4} FPGA board |
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| 103 | % % with its PCI/X IP. These boards are dedicated to the COACH HPC development. |
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| 104 | % % They are based on \mustbecompleted{FIXME:stratix4} FPGA device of 400,000 LUT. |
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| 105 | % % \begin{livrable} |
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| 106 | % % \itemL{0}{6}{m}{\Saltera}{HPC development boards}{0:0:0} Two PCI/X FPGA boards. |
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[23] | 107 | \end{workpackage} |
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