Changeset 99 for anr


Ignore:
Timestamp:
Feb 8, 2010, 12:11:05 AM (15 years ago)
Author:
coach
Message:

IA: 1) mise en page et verification de 2, 2.1, 2.2 4.1. 2) entrer bull/xilinx/navtel dans 6.1 3) xilinx dans 7.

Location:
anr
Files:
12 edited

Legend:

Unmodified
Added
Removed

  • anr/Makefile

    r91 r99  
    1515                table_tima_full.tex table_tima_short.tex \
    1616                table_lip_full.tex table_lip_short.tex \
     17                table_ubs_full.tex table_ubs_short.tex \
     18                table_xilinx_full.tex table_xilinx_short.tex \
    1719
    1820# PROGRAMS

  • anr/anr.tex

    r97 r99  
    1 \documentclass[12pt,a4paper]{article}
     1\documentclass[11pt,a4paper]{article}
    22
    33\usepackage[french]{babel}
    … …  
    1414\usepackage{geometry}
    1515\usepackage{textcomp}
    16 \geometry{verbose,a4paper,tmargin=3cm,bmargin=2cm,lmargin=2cm,rmargin=3cm}
     16\geometry{verbose,a4paper,tmargin=3cm,bmargin=2cm,lmargin=2cm,rmargin=2cm}
    1717
    1818\usepackage{anr}
    … …  
    3131\definecolor{rouge}{rgb}{1.0,0.2,0.2}
    3232\def\mustbecompleted#1{}
     33\def\parlf{\vspace*{1.0ex}\par}
    3334
    3435%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
    3536\def\Sformat#1{\begin{small}\textsc{#1}\end{small}}
    3637\def\irisa{IRISA\xspace}          \def\Sirisa{\Sformat{IRI}\xspace}
    37 \def\citi{CITI\xspace}            \def\Sciti{\Sformat{CITI}\xspace}
     38%\def\citi{CITI\xspace}            \def\Sciti{\Sformat{CITI}\xspace}
    3839\def\lip{LIP\xspace}              \def\Slip{\Sformat{LIP}\xspace}
    3940\def\tima{TIMA\xspace}            \def\Stima{\Sformat{TIMA}\xspace}
    40 \def\ubs{UBS\xspace}              \def\Subs{\Sformat{UBS}\xspace}
     41\def\ubs{LAB-STICC\xspace}        \def\Subs{\Sformat{UBS}\xspace}
    4142\def\upmc{LIP6\xspace}            \def\Supmc{\Sformat{LIP6}\xspace}
    4243\def\altera{ALTERA\xspace}        \def\Saltera{\Sformat{ALTE}\xspace}
    … …  
    6263\def\anrdoc#1{\noindent\begin{scriptsize}\textcolor{red}{#1}\end{scriptsize}\ifhmode\par\fi}
    6364% Comment the next macro to suppress the pagefeed
    64 \let\pagefeed\newpage
     65%\let\pagefeed\newpage
    6566% Comment the next macro to suppress it
    66 \def\mustbecompleted#1{\textcolor{gris}{#1}}
     67\def\mustbecompleted#1{\textcolor{red}{#1}}
    6768% FIN CONFIG
    6869%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
    … …  
    191192% 4.3
    192193\pagefeed\subsection{Description of the tasks}
     194\label{task-description}
    193195\anrdoc{(idéalement 1 ou 2 pages par tâche)
    194196Pour chaque tâche, décrire:\begin{itemize}
    … …  
    226228
    227229\subsubsection{Task 8: \textit{Dissemination}}
     230\label{task-7}
    228231\input{task-7}
    229232

  • anr/dependence-task-h.fig

    r78 r99  
    1414        0 0 1.00 60.00 120.00
    1515         -681 690 -231 1275
    16 2 1 0 3 0 7 90 -1 -1 0.000 0 0 -1 1 0 2
    17         0 0 1.00 60.00 120.00
    18          -2070 1350 -1620 1350
    19 2 1 0 3 0 7 100 -1 -1 0.000 0 0 -1 1 0 10
    20         0 0 1.00 60.00 120.00
    21          405 1350 450 1350 540 1350 585 1350 630 1350 675 1350
    22          720 1350 765 1350 810 1350 855 1350
    23162 2 1 1 0 7 80 -1 -1 4.000 0 0 -1 0 0 5
    2417         -1665 2475 1800 2475 1800 225 -1665 225 -1665 2475
    … …  
    50432 2 0 1 0 7 80 -1 -1 0.000 0 0 -1 0 0 5
    5144         -2700 1125 -2070 1125 -2070 1575 -2700 1575 -2700 1125
     452 1 0 4 0 7 90 -1 -1 0.000 0 0 -1 1 0 2
     46        0 0 1.00 60.00 120.00
     47         -2070 1350 -1620 1350
     482 1 0 4 0 7 100 -1 -1 0.000 0 0 -1 1 0 10
     49        0 0 1.00 60.00 120.00
     50         405 1350 450 1350 540 1350 585 1350 630 1350 675 1350
     51         720 1350 765 1350 810 1350 855 1350
    52524 0 0 70 -1 18 16 0.0000 4 195 315 3330 90 T1\001
    53534 1 0 90 -1 18 16 0.0000 4 195 315 2925 945 T7\001

  • anr/section-1.tex

    r97 r99  
    44integration of heterogeneous technologies and requires the design of
    55complex Multi-Processors System on Chip (MPSoC).
    6 \par
     6\\
    77During the last decade, the design of ASICs (Application Specific
    88Integrated Circuits) appeared to be more and more reserved to high volume markets, because
    … …  
    2020major companies to design innovative devices and to enter new, low and
    2121medium volume markets.
    22 \par
     22\parlf
    2323The objective of COACH is to provide an integrated design flow, based on the
    2424SoCLib infrastructure~\cite{soclib}, and optimized for the design of
    … …  
    3131They can also be extension boards connected to a PC to accelerate a specific computation,
    3232as in High-Performance Computing (HPC) or High-Speed Signal Processing (HSSP).
    33 \par
     33\parlf
    3434%verrous scientifiques et techniques
    35 \vspace*{.9ex}\par
    3635The COACH environment will integrate several hardware and software technologies:
    3736\begin{description}
    … …  
    6665    \item An \altera architectural template based on the \altera IP core library and the
    6766      AVALON system bus.
    68     \item A \xilinx architectural template based on the Xlinx IP core library and the OPB
     67    \item A \xilinx architectural template based on the Xlinx IP core library and the PLB
    6968      system bus.
    7069    \end{enumerate}
    … …  
    8281%independant from both the architectural template and from the selected FPGA
    8382%family.
    84 
     83\parlf
    8584% le programme de travail
    86 \vspace*{.9ex}\par
    8785%The COACH project targets fundamental issues related to design methodologies for
    8886%digital systems by providing estimation, exploration and design tools targeting both
    … …  
    106104Finally it will use the \xilinx and \altera RTL tools to generate the FPGA configuration
    107105bitstreams.
    108 \par
     106\parlf
    109107The COACH proposal has been prepared during one year by a technical working group
    110108involving the 5 academic partners (one monthly meeting from january 2009 to february
    … …  
    115113Because the SocLib platform is the base of this project, it may be described as an
    116114extension of the SoCLib platform.
    117 
    118115%The main development steps of the COACH project are:
    119116%\begin{enumerate}
    … …  
    135132%    dynamic reconfiguration of FPGA devices.
    136133%\end{enumerate}
    137 
    138 \par
     134\parlf
    139135Two major FPGA companies are involved in the project : \xilinx will contribute
    140136as a contractual partner providing documentation and manpower; \altera will contribute as a supporter,
    141 providing documentation and development boards (\altera). These two companies are strongly motivated
     137providing documentation and development boards. These two companies are strongly motivated
    142138to help the COACH project to generate efficient bitsream for both FPGA families.
    143139The role of the industrial partners \bull, \thales, \navtel and \zied is to provide
    144140real use cases to benchmark the COACH design environment.
    145 \par
     141\parlf
    146142Following the general policy of the SoCLib platform, the COACH project will be an open
    147143infrastructure, available in the framework of the SoCLib server.

  • anr/section-2.1.tex

    r97 r99  
     1\begin{table}\leavevmode\center
     2\begin{small}\begin{tabular}{|l|l|l|l|}\hline
     3Segment                 & 2010   & 2011    & 2012 \\\hline\hline
     4Communications          & 1,867  & 1,946   & 2,096 \\
     5High end                & 467    & 511     & 550 \\\hline
     6Consumer                & 550    & 592     & 672 \\
     7High end                & 53     & 62      & 75 \\\hline
     8Automotive              & 243    & 286     & 358 \\
     9High end                & -      & -       & - \\\hline
     10Industrial              & 1,102  & 1,228   & 1,406 \\
     11High end                & 177    & 188     & 207 \\\hline
     12Military/Aereo          & 566    & 636     & 717 \\
     13High end                & 56     & 65      & 82 \\\hline\hline
     14Total FPGA/PLD          & 4,659  & 5,015   & 5,583 \\
     15Total High-End  FPGA    & 753    & 826     & 914 \\\hline
     16\end{tabular}\end{small}
     17\caption{\label{fpga_market} Gartner estimation of worldwide FPGA/PLD consumption (Millions \$)}
     18\end{table}
     19%
    120Microelectronic components allow the integration of complicated functions into products, increases
    221commercial attractivity of these products and improves their competitivity.
    322Multimedia and tele-communication sectors have taken advantage from microelectronics facilities
    423thanks to the developpment of design methodologies and tools for embedded systems.
    5 \par
    624Unfortunately, the Non Recurring Engineering (NRE) costs involded in designing
    725and manufacturing ASICs is very high.
    … …  
    1129Consequently, it is generally unfeasible to design and fabricate ASICs for low and medium
    1230volume markets.
    13 \par
     31\parlf
    1432Today, FPGAs become important actors in the computational domain that was originally dominated
    1533by microprocessors and ASICs. Just like microprocessors, FPGA based systems can be reprogrammed
    … …  
    2038choice for low-to-medium volume applications.
    2139Since their introduction in the mid eighties, FPGAs evolved from a simple,
    22 low-capacity gate array to devices (Altera STRATIX III, Xilinx Virtex V) that
     40low-capacity gate array to devices (\altera STRATIX III, Xilinx Virtex V) that
    2341provide a mix of coarse-grained data path units, memory blocks, microprocessor cores,
    2442on chip A/D conversion, and gate counts by millions. This high logic capacity allows to implement
    2543complex systems like multi-processors platform with application dedicated coprocessors.
    2644Table~\ref{fpga_market} shows the estimation of FPGA worldwide market in the next years in
    27 various application domains.
     45various application domains. The ``high end'' lines concern only FPGA with high logic
     46capacity for complex system implementations.
    2847This market is in significant expansion and is estimated to 914\,M\$ in 2012.
    29 
    30 \begin{table}\leavevmode\center
    31 \begin{tabular}{|l|l|l|l|}\hline
    32 Segment         & 2010  & 2011  & 2012 \\\hline\hline
    33 Communications  & 1,867 & 1,946 & 2,096 \\
    34 High end        & 467   & 511   & 550 \\\hline
    35 Consumer        & 550   & 592   & 672 \\
    36 High end        & 53    & 62    & 75 \\\hline
    37 Automotive      & 243   & 286   & 358 \\
    38 High end        & -     & -     & - \\\hline
    39 Industrial      & 1,102 & 1,228 & 1,406 \\
    40 High end        & 177   & 188   & 207 \\\hline
    41 Military/Aereo  & 566   & 636   & 717 \\
    42 High end        & 56    & 65    & 82 \\\hline\hline
    43 Total FPGA/PLD  & 4,659 & 5,015 & 5,583 \\
    44 Total High-End  FPGA    & 753   & 826   & 914 \\\hline
    45 \end{tabular}
    46 \caption{\label{fpga_market} Gartner estimation of worldwide FPGA/PLD consumption (Millions \$)}
    47 \end{table}
    48 \par
    49 
    50 This market is dominated by Multi-core CPUs and GPUs based solutions and the expansion of FPGA-based solutions
    51 is limited by the lack of design flow automation. Nowadays, there are neither commercial
    52 nor academic  tools covering the whole design process from the system level specification to the bit stream
    53 generation.
    54 %For instance, with SOPC Builder from Altera, users can select and parameterize IP components
    55 %from an extensive drop-down list of communication, digital signal processor (DSP), microprocessor
    56 %and bus interface cores, as well as incorporate their own IP. Designers can then generate
    57 %a synthesized netlist, simulation test bench and custom software library that reflect the hardware
    58 %configuration.
    59 %Nevertheless, SOPC Builder does not provide any facilities to synthesize coprocessors\emph{I
    60 (%Steven) disagree : the C2H compiler bundled with SOPCBuilder does a pretty good job at this} and to
    61 %simulate the platform at a high design level (systemC).
    62 %In addition, SOPC Builder is proprietary and only works together with Altera's Quartus compilation
    63 %tool to implement designs on Altera devices (Stratix, Arria, Cyclone).
    64 %PICO [CITATION] and CATAPULT [CITATION] allow to synthesize coprocessors from a C++ description.
    65 %Nevertheless, they can only deal with data dominated applications and they do not handle the platform level.
    66 %The Xilinx System Generator for DSP [http://www.xilinx.com/tools/sysgen.htm] is a plug-in to
    67 %Simulink that enables designers to develop high-performance DSP systems for Xilinx FPGAs.
    68 %Designers can design and simulate a system using MATLAB and Simulink. The tool will then
    69 %automatically generate synthesizable Hardware Description Language (HDL) code mapped to Xilinx
    70 %pre-optimized algorithms.
    71 %However, this tool targets only DSP based algorithms.
    72 
    73 Consequently, a designer developping an embedded system needs to master
    74 four different design environment : a virtual prototyping environment such as SoCLib for system level exploration,
    75 an architecture compiler (such as SOPC Builder from Altera, or System generator from Xilinx) to define the
    76 hardware architecture, one or several HLS tools (such as PICO [CITATION] ou CATAPULT [CITATION]) for
    77 coprocessor synthesis, and finally a backend synthesis tool (such as Quartus or YYYY) for the bit-stream generation.
    78 
     48The HPC market size is estimated today by FPGA providers at 214\,M\$.
     49Using FPGA limits the NRE costs to the design cost.
     50This boosts the developpment of automatic design tools and methodologies.
     51%
     52%Today, several companies (atipa, blue-arc, Bull, Chelsio, Convey, CRAY, DataDirect, DELL, hp,
     53%Wild Systems, IBM, Intel, Microsoft, Myricom, NEC, nvidia etc) are making systems where demand
     54%for very high performance (HPC) primes over other requirements. They tend to use the highest
     55%performing devices like Multi-core CPUs, GPUs, large FPGAs, custom ICs and the most innovative
     56%architectures and algorithms. These companies show up in different "traditional" applications and market
     57%segments like computing clusters (ad-hoc), servers and storage, networking and Telecom, ASIC
     58%emulation and prototyping, military/aereo etc. The HPC market size is estimated today by FPGA providers
     59%at 214\,M\$.
     60%%%
     61\parlf
     62This market is dominated by Multi-core CPUs and GPUs based solutions and the expansion
     63of FPGA-based solutions is limited by the lack of design flow automation.
     64Nowadays, there are neither commercial nor academic tools covering the whole design process
     65from the system level specification to the bit stream generation.
     66\\
     67% IA to Alain: J'ai remis (et ameliore un peu) ca car sinon le Consequently 20 lignes
     68%              au dessous n'a pas de sens.
     69% Deplus dans les demandes ANR de la section, il est demande: analyse de la concurrence
     70For instance, with SOPC Builder~\cite{spoc-builder} from \altera, designers can select and
     71parameterize components from an extensive drop-down list of IP cores (I/O core, DSP,
     72processor,  bus core, ...) as well as incorporate their own IP.
     73Designers can then generate a synthesized netlist, simulation test bench and custom
     74software library that reflect the hardware configuration.
     75%% Steven disagree : the C2H compiler bundled with SOPCBuilder does a pretty good job at this.
     76%% IA: ces lignes ont ete verifiees et corrigée pa altera. De plus C2H est plutot limite.
     77Nevertheless, SOPC Builder does not provide any facilities to synthesize coprocessors and to
     78simulate the platform at a high design level (systemC).
     79In addition, SOPC Builder is proprietary and only works together with \altera's Quartus compilation
     80tool to implement designs on \altera devices (Stratix, Arria, Cyclone).
     81\\
     82For instance, PICO~\cite{pico} and CATAPULT-C~\cite{catapult-c} allow to synthesize
     83coprocessors from a C++ description.
     84Nevertheless, they can only deal with data dominated applications and they do not handle
     85the platform level.
     86\\
     87Similarly, the System Generator for DSP~\cite{system-generateur-for-dsp} is a plug-in to
     88Simulink that enables designers to develop high-performance DSP systems for \xilinx FPGAs.
     89Designers can design and simulate a system using MATLAB and Simulink. The tool will then
     90automatically generate synthesizable Hardware Description Language (HDL) code mapped to
     91\xilinx pre-optimized macro-cells.
     92However, this tool targets only DSP based algorithms.
     93\\
     94Consequently, a designer developping an embedded system needs to master four different
     95design environments:
     96\begin{enumerate}
     97  \item a virtual prototyping environment such as SoCLib for system level exploration,
     98  \item an architecture compiler (such as SOPC Builder from \altera, or System generator from Xilinx)
     99        to define the hardware architecture,
     100  \item one or several HLS tools (such as PICO~\cite{pico} or CATAPULT-C~\cite{catapult-c}) for
     101        coprocessor synthesis,
     102  \item and finally backend synthesis tools (such as Quartus or Synopsys) for the bit-stream generation.
     103\end{enumerate}
     104Furthermore, mixing these tools requires an important interfacing effort and this makes
     105the design process very complex and achievable only by designers skilled in many domains.
     106\begin{center}\begin{minipage}{.8\linewidth}\textit{
    79107The aim of the COACH project is to integrate all these design steps into a single design framework.
    80108and to allow \textbf{pure software} developpers to develop embedded systems.
    81 \par
    82 We believe that the combination of a design environment dedicated to software developpers and the FPGA target,
     109}\end{minipage}\end{center}
     110\parlf
     111We believe that the combination of a design environment dedicated to software developpers
     112and the FPGA target,
    83113allows small and even very small companies to propose embedded system and accelerating solutions
    84114for standard software applications with acceptable prices.
    85 
    86115This new market may explode in the same way as the micro-computer market in the eighties,
    87116whose success was due to the low cost of the first micro-processors (compared to main frames)
    88117and the advent of high level programming languages which allowed a high number of programmers
    89118to launch start-ups in software engineering.
    90 

  • anr/section-2.2.tex

    r97 r99  
    99This project proposes an open-source framework for mapping multi-tasks software applications
    1010on Field Programmable Gate Array circuits (FPGA).
    11 
    12 \par
     11%%%
     12\parlf
    1313COACH will contribute to build an open development and run-time
    1414environment, including communication middleware and tools to support
    1515developers in the production of embedded software, through all phases of the software lifecycle,
    1616from requirements analysis until deployment and maintenance.
    17 
    1817More specifically, COACH focuses on:
    1918\begin{itemize}
    … …  
    2625environment, suitable for co-operative and distributed development.
    2726\end{itemize}
    28 
     27%%%
     28\parlf
    2929COACH outcome will contribute to strengthen Europe's competitive position by developing
    3030technologies and methodologies for product development, focusing (in compliance with the
    … …  
    3333in COACH will enable new and emerging information technologies for the development,
    3434manufacturing and integration of devices and related software into end-products.
    35 
    36 \par
     35%%%
     36\parlf
    3737The COACH project will benefit from a number of previous projects:
    38 \begin{itemize}
    39 \item SOCLIB :
    40 The SoCLib ANR platform (2007-2009) is an open infrastructure developped by 10 academic laboratories
    41 and 6 industrial companies.
    42 It supports system level virtual prototyping of shared memory, multi-processors
    43 architectures, and provides tools to map multi-tasks software application on these
    44 architectures, for reliable performance evaluation.
    45 The core  of this platform is a library of SystemC simulation models for
    46 general purpose IP cores such as processors, buses, networks, memories, IO controller.
    47 The platform provides also embedded operating systems and software/hardware
    48 communication middleware.
    49 The synthesisable VHDL models of IPs are not part of the SoCLib platform, and
    50 this project enhances SoCLib by providing the synthesisable VHDL models required
    51 for FPGA synthesis.
    52 \item ROMA :
    53 The ROMA ANR project (2007-2009) involving IRISA, LIRMM, CEA List THOMSON France R\&D, proposes to develop a
    54 reconfigurable processor, exhibiting high silicon density and power efficiency, able to adapt its
    55 computing structure to computation patterns that can be speed-up and/or power efficient.
    56 The ROMA project study a pipeline-based of evolved low-power coarse grain reconfigurable
    57 operators to avoid traditional overhead, in reconfigurable devices, related to
    58 the interconnection network.
    59 The project will  borrow from the ROMA ANR xxproject (2007-2009) and the ongoing
    60 joint INRIA-STMicro Nano2012 project to adapt existing pattern
    61 extraction algorithms and datapath merging techniques to the synthesis of customized
    62 ASIP processors.
    63 \item TSAR :
    64 The TSAR MEDEA+ project (2008-2010) involving BULL, THALES and the LIP6 targets the design of a
    65 scalable, coherent shared memory, multi-cores processor architecture, and uses the SoCLib
    66 plaform for virtual prototyping. The COACH project will benefit from the synthesizable VHDL
    67 models developped in the framework of TSAR (MIPS32 processor core, and RING interconnect).
    68 \item BioWic
    69 On the HPC application side, we also hope to benefit from the experience in
    70 hardware acceleration of bioinformatic algorithms/workfows gathered by the
    71 CAIRN group in the context of the ANR BioWic project (2009-2011), so as to
    72 be able to validate the framework on real-life HPC applications.
    73 \end{itemize}
    74 
    75 
    76 \par
     38\begin{description}
     39  \item[SOCLIB]
     40    The SoCLib ANR platform (2007-2009) is an open infrastructure developped by 10 academic laboratories
     41    and 6 industrial companies.
     42    It supports system level virtual prototyping of shared memory, multi-processors
     43    architectures, and provides tools to map multi-tasks software application on these
     44    architectures, for reliable performance evaluation.
     45    The core of this platform is a library of SystemC simulation models for
     46    general purpose IP cores such as processors, buses, networks, memories, IO controller.
     47    The platform provides also embedded operating systems and software/hardware
     48    communication middleware.
     49    The synthesisable VHDL models of IPs are not part of the SoCLib platform, and
     50    this project enhances SoCLib by providing the synthesisable VHDL models required
     51    for FPGA synthesis.
     52  \item[ROMA]
     53    The ROMA ANR project (2007-2009) involving IRISA, LIRMM, CEA List THOMSON France R\&D, proposes to develop a
     54    reconfigurable processor, exhibiting high silicon density and power efficiency, able to adapt its
     55    computing structure to computation patterns that can be speed-up and/or power efficient.
     56    The ROMA project study a pipeline-based of evolved low-power coarse grain reconfigurable
     57    operators to avoid traditional overhead, in reconfigurable devices, related to
     58    the interconnection network.
     59    The project will borrow from the ROMA ANR xxproject (2007-2009) and the ongoing
     60    joint INRIA-STMicro Nano2012 project to adapt existing pattern
     61    extraction algorithms and datapath merging techniques to the synthesis of customized
     62    ASIP processors.
     63  \item[TSAR]
     64    The TSAR MEDEA+ project (2008-2010) involving BULL, THALES and the \upmc targets the design of a
     65    scalable, coherent shared memory, multi-cores processor architecture, and uses the SoCLib
     66    plaform for virtual prototyping. The COACH project will benefit from the synthesizable VHDL
     67    models developped in the framework of TSAR (MIPS32 processor core, and RING interconnect).
     68  \item[BioWic]
     69    On the HPC application side, we also hope to benefit from the experience in
     70    hardware acceleration of bioinformatic algorithms/workfows gathered by the
     71    CAIRN group in the context of the ANR BioWic project (2009-2011), so as to
     72    be able to validate the framework on real-life HPC applications.
     73\end{description}
     74%%%
     75\parlf
    7776The laboratories involved in the COACH project have a well estabished expertise
    7877in the following domains:
    7978\begin{itemize}
    80 \item
    81 In the field of High Level Synthesis (HLS), the project
    82 leverages on know-how acquired over the last 15 years with the GAUT~\cite{gaut08} project
    83 developped by the Lab-STIC laboratory, and with the UGH~\cite{ugh08} project developped
    84 by the LIP6 and TIMA laboratories.
     79  \item
     80    In the field of High Level Synthesis (HLS), the project
     81    leverages on know-how acquired over the last 15 years with the GAUT~\cite{gaut08} project
     82    developped by the \ubs laboratory, and with the UGH~\cite{ugh08} project developped
     83    by the \upmc and \tima laboratories.
     84  \item
     85    Regarding system level architecture, the project is based on the know-how
     86    acquired by the \upmc and \tima laboratories in the framework of various projects 
     87    (COSY~\cite{disydent}, or MEDEA-MESA~\cite{dspin}), in the field of communication
     88    architectures for shared memory multi-processors systems.
     89    As an example, the DSPIN network on chip, is now used by BULL in the TSAR project.
     90  \item
     91    Regarding Application Specific Instruction Processor (ASIP) design, the
     92    CAIRN group at INRIA Bretagne Atlantique benefits from several years of
     93    expertise in the domain of retargetable compiler
     94    (Armor/Calife~\cite{CODES99} since 1996, and the Gecos
     95    compilers~\cite{ASAP05} since 2002).
    8596\item
    86 Regarding system level architecture, the project is based on the know-how
    87 acquired by the LIP6 and TIMA laboratories in the framework of various projects 
    88 (COSY \cite{disydent}, or MEDEA MESA \cite{dspin}), in the field of communication
    89 architectures for shared memory multi-processors systems.
    90 As an example, the DSPIN network on chip, is now used by BULL in the TSAR project.
    91 \item
    92 Regarding Application Specific Instruction Processor (ASIP) design, the
    93 CAIRN group at INRIA Bretagne Atlantique benefits from several years of
    94 expertise in the domain of retargetable compiler
    95 (Armor/Calife\cite{CODES99} since 1996, and the Gecos
    96 compilers\cite{ASAP05} since 2002).
    97 \item
    98 In the field of compilers, the Compsys group was founded in 2002
    99 by several senior researchers with experience in
    100 high performance computing and automatic parallelization. They have been
    101 among the initiators of the polyhedral model, a theory which serve to
    102 unify many parallelism detection and exploitation techniques for regular
    103 programs. It is expected that the techniques developped by Compsys for
    104 parallelism detection, scheduling, process construction and memory management
    105 will be very useful as a Rfront end for the a high-level synthesis tools.
     97    In the field of compilers, the Compsys group was founded in 2002
     98    by several senior researchers with experience in
     99    high performance computing and automatic parallelization. They have been
     100    among the initiators of the polyhedral model, a theory which serve to
     101    unify many parallelism detection and exploitation techniques for regular
     102    programs. It is expected that the techniques developped by Compsys for
     103    parallelism detection, scheduling, process construction and memory management
     104    will be very useful as a front-end for the a high-level synthesis tools.
    106105\end{itemize}
    107 
    108 
    109 \par
    110 % FIXME A VERIFIER L'appel d'offre
     106%%%
     107\parlf
    111108Finally, it is worth to note that this project cover priorities defined by the commission
    112109experts in the field of Information Technolgies Society (IST) for Embedded
    … …  
    115112considering resources constraints (delais, power, memory, etc.), security and quality
    116113services$>>$.
    117 
    118 

  • anr/section-2.tex

    r97 r99  
    1 The first objective of COACH is to provide SMEs (Small and Medium Enterprises) an open-source framework to
    2 design embedded system on FPGA devices.
    3 
     1Embedded systems (SoC and MPSoC) became an inevitable evolution in microelectronic industry.
    42Due to the exploding fabrication costs, the ASIC technology (Application Specific Integrated Circuit)
    5 is not an option for most SMEs. Fortunately, the new FPGA (Field Programmable Gate Array) components,
    6 such as the Virtex5 family from Xilinx, or the Stratix4 family from Altera can implement a complete
    7 multi-processor architecture on a single chip.
    8 
    9 %But the design of a SoC (System on Chip) or MPSoC (Multi-Processor System on Chip) is a complex
    10 %task, requiring adequate design methods to efficiently model, explore, and analyze the
    11 %interactions between the software application and the hardware architectures. Moreover, most SMEs do not have
    12 %in-home expertise in the field of hardware design or VHDL/Verilog modeling.
    13 %In order to meet the increasing performance requirements, to decrease the development cost, and to
    14 %shorten the time-to-market, they need new design methodologies.
    15 
     3is not an option for SMEs (Small and Medium Enterprises).
     4Fortunately, the new FPGA (Field Programmable Gate Array) components,
     5such as the Virtex5 family from \xilinx, or the Stratix4 family from \altera can implement a complete
     6multi-processor architecture on a single device.
     7But the design of embedded system is a long and complex task that requires expertise in software,
     8software/hardware partionning, operating system, hardware design, VHDL/Verilog modeling.
     9Only very few SMEs have these multiple expertises and are present on the embedded system market.
     10\begin{center}\begin{minipage}{.8\linewidth}\textit{
     11The major objective of COACH is to provide to SMEs an open-source framework to design
     12embedded systems on FPGA devices.
     13}\end{minipage}\end{center}
    1614%Current design methodologies provide quite low-level abstraction capabilities, and
    1715%there is an urgent need to leverage system level exploration through the use of a high-level
    1816%specification of the application and  design space exploration tools.
    19 
    2017%The first system oriented approaches are appearing, among which those
    2118%based on C/C++ and SystemC are the most popular, but few of them are specifically targetting FPGAs.
    22 
     19%%%
     20\parlf
    2321The COACH project will leverage on the expertise gained in the field of virtual prototyping
    2422with the SoCLib platform, to propose a new design flow based on a small number of architectural templates.
    … …  
    2927template can be enriched by dedicated hardware coprocessors, obtained by high level synthesis (HLS) tools.
    3028During this project, the COACH partners will develop three different architectural templates:
    31 
    3229\begin{enumerate}
    3330\item An \altera architectural template based on the \altera IP core library and the AVALON system bus.
    34 \item A \xilinx architectural template based on the Xlinx IP core library and the OPB system bus.
    35 \item A Neutral architectural template based on the SoCLib IP core library and the VCI/OCP communication infrastructure.
     31\item A \xilinx architectural template based on the \xilinx IP core library and the PLB system bus.
     32\item A Neutral architectural template based on the SoCLib IP core library and the VCI/OCP
     33      communication infrastructure.
    3634\end{enumerate}
    37 
    3835The proposed design flow starts from a high level description of the application, specified as a set of
    3936parallel tasks written in C, without any assumption on the hardware or software implementation
    4037of these tasks. It let the system
    41 designer in charge of expessing the coarse grain parallelism of the application, gives the designer
     38designer in charge of expressing the coarse grain parallelism of the application, gives the designer
    4239the possibility to explore various mapping of the application on the selected template architecture,
    4340and offers a high predictability of results with respect to cost and performance objectives.
    44 
     41\\
    4542When this interactive, system level, design space exploration is completed (converging to
    4643a specific mapping on a specific version of the selected architectural template), the rest of the flow
    … …  
    4845code for the software running on the embedded processors, and the bit-stream to program the the target FPGA
    4946will be automatically generated by the COACH tools.
    50 
    51 \par
     47%
     48\parlf
    5249The strength of the COACH approach is the strong integration of the high-level synthesis tools
    5350in a plat-form based design flow supporting virtual prototyping and design space exploration.
    … …  
    6057%in Paris from january 2009 to february 2010, to analyse the issues of interfacing and integrating
    6158%those various technologies, and to define the detailed architecture of the proposed design flow.
    62 \par
    63 
     59%%%
     60\parlf
     61In HPC (High Performance Computing), the kind of targeted application is an existing one
     62running on a PC.
     63The COACH framework helps designer to accelerate it by migrating critical parts into a
     64SoC embedded into an FPGA device plugged to the PC PCI/X bus.
     65\begin{center}\begin{minipage}{.8\linewidth}\textit{
     66The second objective of COACH is to extend the framework to HPC.
     67}\end{minipage}\end{center}
     68This will allow SMEs to enter HPC market for the applications that are
     69unadapted to the current GPU based solutions.
     70%%%
     71\parlf
    6472In summary, the COACH project is clearly oriented toward industry, even if most technology building blocks
    6573have been previously developed by academic laboratories.
    … …  
    98106%Every point of the design space can be implemented on any FPGA component,
    99107%as long as it contains the hardware ressources required by the selected architectural template.
    100 %Basically, COACH will support both Altera and Xilinx FPGA families.
     108%Basically, COACH will support both \altera and \xilinx FPGA families.
    101109%\end{itemize}
    102110%

  • anr/section-3.2.tex

    r71 r99  
    1818and a mapping of processes on the platform components. The supported mapping are
    1919software (the process runs on a SoC processor),
    20 XXXpeci (the process runs on a SoC processor enhanced with dedicated instructions),
    21 and hardware (the process runs into a coprocessor generated by HLS and plugged on the SoC bus).
     20ASIP (the process runs on a SoC processor enhanced with dedicated instructions),
     21and hardware (the process runs into a coprocessor that is generated by HLS and plugged on the SoC bus).
    2222\item[Application compilation] Once the SoC description is validated, COACH generates automatically
    2323an FPGA bitstream containing the hardware platform with the SoC application software and
    … …  
    7676%fin de projet.
    7777The main result is the framework. It is composed concretely of:
    78 2 HPC communication schemes with their implementation,
    79 5 HLS tools (control dominated HLS, data dominated HLS, Coarse grained HLS,
     78a communication middleware for HPC,
     795 HAS tools (control dominated HLS, data dominated HLS, Coarse grained HLS,
    8080Memory optimisation HLS and ASIP),
    81 3 systemC based virtual prototyping environment extended with synthesizable
    82 RTL IP cores (generic, ALTERA/NIOS/AVALON, XILINX/MICROBLAZE/OPB),
     813 architectural templates that are synthesizable and that can be prototyped,
    8382one design space exploration tool,
    84 2 operating system (OS).
     832 operating systems (DNA/OS and MUTEK.
    8584\\
    86 The framework fonctionality will be demonstrated with XXX-EXAMPLE1, XXX-EXAMPLE2
    87 and XXX-EXAMPLE3 on 4 archictures (generic/XILINX, generic/ALTERA,
    88 proprietary/XILINX, proprietary/ALTERA).
    89 
     85The framework fonctionality will be demonstrated with the demonstrators
     86(see task-7 page~\pageref{task-7}) and the tutorial example (see task-8
     87page~\ref{subtask-tutorial}.

  • anr/section-4.1.tex

    r65 r99  
    1717In figures, the dotted boxes are the softwares or formats that COACH
    1818has to provide and to support.
    19 \vspace*{.75ex}\par
     19\parlf
    2020For the system generation presented in figure~\ref{archi-csg}, the conductor
    2121is the tool \verb!CSG! (COACH System Generator). Its inputs are a process
    … …  
    3535FPGA device\footnote{Additional partial bitstreams are generated in case of
    3636 dynamic partial reconfiguration}.
    37 \\
    3837%To proove CSG that COACH is open and CSG is really configurable, COACH will
    3938%basically support 3 architecture template (the COACH template based on a
    4039%MIPS processors and a VCI token ring, the Altera template based on the NIOS
    41 %and AVALON bus, the Xilinx template based on the MICROBLAZE and OPB bus)
     40%and AVALON bus, the Xilinx template based on the MICROBLAZE and PLB bus)
    4241%and 2 operating systems (DNA/OS and MUTEK). Furthermore, thus is enforced
    4342%by the \mustbecompleted{FIXME:zied} contribution that consists in
    … …  
    4645%Finally, it is important to notice that this work is a strong
    4746%enhancement of the SocLib software.
    48 \vspace*{.75ex}\par
     47\parlf
    4948The software architecture for HAS is presented in figure~\ref{archi-hls}.
    5049The input is a single task of the process network. The HAS tools do not work
    … …  
    6160Furthermore, the back-end tools uses a macro-cell library (functional and memory
    6261unit).
    63 \vspace*{.75ex}\par
     62\parlf
    6463In addition to digital system design, HPC requires a supplementary
    6564partitioning step presented in figure~\ref{archi-hpc}. The designer
    … …  
    7069simulator. Once the partitioning is validated, the design of the FPGA part
    7170is done through \verb!CSG! (figure~\ref{archi-csg}).
    72 \vspace*{.75ex}\par
    7371\mustbecompleted{FIXME == MODIFICATION DE LA FIGURE}
    74 The project is split into 8 tasks numbered from 0 to 7.
    75 The first task (task 0) is the project management, the last one (task 7) is
    76 the dissemination the other task are listed below:
    77 \begin{enumerate}
    78 \item\textbf{\Backbone:} This task tackles the fundamental points of the
     72\parlf
     73The project is split into 8 tasks numbered from 1 to 8. There are described
     74bellow and detailled in section \ref{task-description}.
     75\begin{description}
     76\item[Task-1: \textit{Project management}]
     77    This task relies to the monitoring of the COACH project.
     78\item[Task-2: \textit{\Backbone}] This task tackles the fundamental points of the
    7979        project such as the defintion of the COACH inputs and outputs,
    8080    the internal formats (e.g. \xcoach), the architectural templates and
    8181    the design flow.
    82 \item\textbf{System generation:} This task addresses the prototyping and
     82\item[task-3: \textit{System generation}] This task addresses the prototyping and
    8383    the generation of digital system. Apart from HAS that belong to the task 3
    8484    and 4, its components are those presented figure~\ref{archi-csg}
    8585    (e.g.  \verb!CSG!, operating systems).
    86 \item\textbf{HAS front-end:} This task mainly focusses on four functionalities:
     86\item[Task-4: \textit{HAS front-end}] This task mainly focusses on four functionalities:
    8787    optimization of the memory usage, parallelism enhancement through loop
    8888    transformations, coarse grain parallelization and ASIP generation.
    89 \item\textbf{HAS back-end:} This task groups two functionalities:
     89\item[Task-5: \textit{HAS back-end}] This task groups two functionalities:
    9090    High-Level Synthesis of data dominated description and HLS of control
    9191    dominated description.
    … …  
    9393    that will allow the coprocessors to respect the processor \& the bus
    9494    frequency.
    95 \item\textbf{Communication between PC \& FPGA-SoC:}
     95\item[Task-6: \textit{PC/FPGA communication middleware}]
    9696    This task pools the features dedicated to HPC. The main are the
    9797    partitioning validation (see figure~\ref{archi-hpc}), the sytem drivers for
    9898    both PC and FPGA-SoC sides, the hardware communication components and
    9999        support for dynamic partial reconfiguration.
    100 \item\textbf{Demonstrators:}
     100\item[Task-7: \textit{Industrial demonstrators}]
    101101    This task groups the demonstrators of the COACH project.
    102     \mustbecompleted{FIXME}
    103 \end{enumerate}
     102    Most of them are industrial applications that will be developped with the COACH
     103    framework.
     104    Others consist in integrating COACH framework as a driver of industrial proprietary
     105    design tools.
     106\item{Task 8: \textit{Dissemination}}
     107    This task relies to the diffusion of the project results.
     108    It mainly consists of the production of 4 COACH releases (\verb!T0+12!, \verb!T0+18!,
     109    \verb!T0+24! and \verb!T0+36!)
     110    and the publication on a WEB site of a tutorial.
     111\end{description}
    104112%
    105113\begin{figure}\leavevmode\center
    … …  
    109117\end{figure}
    110118Figure~\ref{dependence-task} presents the tasks dependencies.
    111 "$task-N \longrightarrow task-M$" means that $task-N$ impacts the $task-M$.
     119"$T_N \longrightarrow T_M$" means that $T_N$ impacts the $T_M$.
    112120The more bold is the arrow, the more important is the dependency.
    113121The graph shows:
    114122\begin{itemize}
    115 \item Even that $T3$ and $T4$ functionalities are complementary, their
     123\item Even that $T4$ and $T5$ functionalities are complementary, their
    116124developments are independent (thanks to \xcoach internal format).
    117 \item $T2$ slightly depends on $T3$ and $T4$. Indeed, $T2$ may works
    118 without $T3$ and $T4$ if we limit to digital systems without hardware
     125\item $T3$ slightly depends on $T4$ and $T5$. Indeed, $T3$ may works
     126without $T4$ and $T5$ if we limit to digital systems without hardware
    119127accellerators.
    120 \item $T2$ strongly impacts on $T5$ but, $T2$ does not depend at all on
    121 $T5$. So demonstrators ($T6$) of embedded system would not be impacted if
    122 $T5$ would fail. 
    123 \item $T1$ drives all the tasks ($T2$, $T3$, $T4$, $T5$) at the heart of
     128\item $T3$ strongly impacts on $T6$ but, $T3$ does not depend at all on
     129$T6$. So demonstrators ($T7$) of embedded system would not be impacted if
     130$T6$ would fail. 
     131\item $T2$ drives all the tasks ($T3$, $T4$, $T5$, $T6$) at the heart of
    124132the COACH project.
    125 \item The demonstrators developped in $T6$, of course, strongly depends on the achievements
    126 of the prvious tasks ($T1$, $T2$, $T3$, $T4$, $T5$).
    127 \item $T7$ and $T0$ respectively depends on and impacts all the other tasks.
     133\item The demonstrators developped in $T7$, of course, strongly depends on the achievements
     134of the prvious tasks ($T2$, $T3$, $T4$, $T5$, $T6$).
     135\item $T8$ and $T1$ respectively depends on and impacts all the other tasks.
    128136\end{itemize}
    129137This organisation offers enough robustness to insure the success of the
    130 project except for the specification task $T1$.
    131 
    132 The only critical task in this chart is T1. \label{xcoach-problem}
     138project except for the specification task $T2$.
     139\\
     140The only critical task in this chart is $T2$. \label{xcoach-problem}
    133141However, the partners met
    13414210 times (a one day meeting per month) during the last year to prepare the
    135143specification and the project proposal. This gives us a degree of confidence
    136 that T1 will be completed in time.
     144that $T2$ will be completed in time.

  • anr/section-6.1.tex

    r97 r99  
    9090%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
    9191\subsubsection{\upmc}
     92
    9293University Pierre et Marie Curie (UPMC)  is the largest university in France (7400 employees,38000 students).
    9394The Laboratoire d'Informatique de Paris 6 (LIP6) is the computer science laboratory of UPMC, hosting
    9495more than 400 researchers, under the umbrella of the CNRS (Centre National de la Recherche Scientifique).
    95 The ï¿œ System on Chip ï¿œ Department of LIP6 consists of  80 people, including 40 PHD students.
     96The \og System on Chip \fg Department of LIP6 consists of  80 people, including 40 PHD students.
    9697The research focus on CAD tools and methods for VLSI and System on Chip design.
    97 \\
     98\parlf
    9899The annual budget is about 3 M{\texteuro}, and 1.5 M{\texteuro} are from research contracts.
    99100The SoC department has been involved in several european projects :IDPS, EVEREST, OMI-HIC, OMI-MACRAME,
    100101OMI-ARCHES, EUROPRO, COSY, Medea SMT, Medea MESA, Medea+ BDREAMS, Medea+ TSAR.
     102\parlf
    101103The public domain VLSI CAD system ALLIANCE, developped at UPMC is installed in more than 200 universities worldwide.
    102104The LIP6 is in charge of the technical coordination of the SoCLib national project, and is hosting
    … …  
    110112of control-dominated coprocessors.
    111113This tool will be modified to be integrated in the Coach design flow.
     114\parlf
    112115Even if the preferred dissemination policy for the Coach design flow will be the free software policy,
    113116(following the SoCLib model), the SoC department is ready to support start-ups : Six startup companies
    … …  
    115118
    116119%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
    117 \subsubsection{\altera}
    118 
    119 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
    120120\subsubsection{\xilinx}
    121121
     122\xilinx is the world leader in the domain of programmable logic circuits (FPGA).
     123\xilinx develops in one hand several FPGA architectures (CoolRunner, Spartan and Virtex
     124families) and in the other hand a software solution allowing exploiting the
     125characteristics of these FPGA.
     126\parlf
     127The tools proposed can allow the designer to describe his architecture from modeling
     128language (VHDL/Verilog) to an optimized architecture implemented to the selected
     129technology.
     130The team located at Grenoble is responsible of the logic synthesis tool development (XST)
     131of the software solution, which aggregates all the steps allowing proceeding from a  HDL
     132model to a technological netlist:
     133\begin{itemize}
     134  \item Compilation of HDL code and model generation at Register Transfer Level (RTL).
     135  \item RTL model optimizations.
     136  \item Inference and generation of optimized macro blocks (Finite states machine, counter).
     137  \item Boolean equations generation for randomly logic.
     138  \item Logical, mapping and timing optimizations.
     139\end{itemize}
     140\parlf
     141The architectures developed by \xilinx offer a collection of technological primitives
     142(variable complexity) from simple Boolean generators (LUT) to complex DSP blocks or memory
     143and whether configurable processor cores (Pico and MicroBlaze families).
     144This kind of architecture allows, thus, the designer to validate different
     145hardware/software possibilities in a High Level Synthesis (HLS) framework.
     146\parlf
     147The classical optimization techniques focus, mainly, on the frequency aspects and on
     148available resources use.
     149The optimizations, taking into account the consumption criteria, become critical due to
     150the fact of the increase of the architecture complexity and due to the use of FPGA
     151component for low power applications.
     152
    122153%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
    123154\subsubsection{\bull}
    124155
     156\bull designs and develops servers and software for an open environment, integrating the
     157most advanced technologies. It brings to its customers its expertise and know-how to help
     158them in the transformation of their information systems and to optimize their IT
     159infrastructure and their applications.
     160\parlf
     161\bull is particularly present in the public sector, banking, finance, telecommunication
     162and industry sectors. Capitalizing on its wide experience, the Group has a thorough
     163understanding of the business and specific processes of these sectors, thus enabling it to
     164efficiently advise and to accompany its customers. Its distribution network spreads to
     165over 100 countries worldwide.
     166\parlf
     167The team participating to the COACH project is from the Server Development Department
     168based in Les Clayes-sous-Bois, France. The SD Department is in charge of developing
     169hardware for open servers (e.g. NovaScale) and HPC solutions. Its main activities range
     170from architecture specification, ASIC design/verification/prototyping to board design and
     171include also specific EDA development to complement standard tools.
     172
    125173%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
    126174\subsubsection{\thales}
    … …  
    132180\subsubsection{\navtel}
    133181
     182\navtel was created in 1994 to develop flexible systems based on FPGAs and currently
     183focuses on intelligent signal mining for knowlege based signal processing systems.
     184The company main activity covers the following domains: satellite communication,
     185aeronautics, imaging and security.
     186\navtel dedicates about 70\% of its activity to client projects in satellite, aeronautical
     187and imaging systems and 30\% to its own research programmes in collaboration with French
     188and international partners.
     189\parlf
     190The multi disciplinary technical team comprises 6 engineers for signal processing and
     191hardware development and one technician.
     192\parlf
     193\navtel has its own Ph.D program which includes in the past (classification technology
     194and MIMO for FPGA implementation) and currently the preparation of a project for remote
     195sensing with signal intelligence for satellite application. The company participates in
     196national and European level projects contributing to a strategic alliance between academic
     197and  industrial partners.\\
     198The current research covers particle filter applications for communication and RADAR,
     199Cognitive Radio, Satellite communication, embedded super computing and focuses on low
     200power algorithms for implementation in FPGA and  soft computing.
     201\parlf
     202For manufacturing and industrialization, \navtel works with ISO certified partners.
     203The company clients include the CNES, ThalÚs Alenia Space, ThalÚs Communication, EADS,
     204Eutelsat, AIRBUS, Schlumberger. \navtel participates from the R\&D phase through to the
     205system delivery.
     206
     207\begin{description}
     208\item[Recognitions:]\mbox{}
     209\begin{itemize}
     210  \item EC Challenge+  programme for innovative projects (promotion 9)
     211  \item Innovation and technology development \og Troph\'{e}es R\'{e}gion Centre \fg
     212  \item Recognition by the French Senate for company creation  during the
     213        \og Semaine de l'entrepreneur \fg 2005.
     214\end{itemize}
     215\end{description}

  • anr/section-7.tex

    r87 r99  
    3131costs. The requested funding for non permanent personnels is 100\% of
    3232the total ANR requested funding.
     33    \begin{center}\input{table_lip_short.tex}\end{center}
    3334
    3435\item [Subcontracting]
    … …  
    4142The costs justified by internal invoicing procedures are evaluated to 4\%
    4243of the total requested ANR funding.\\
    43     \begin{center}\input{table_lip_short.tex}\end{center}
    4444\end{description}
    4545
    … …  
    7474The requested funding for non permanent personnels is 82\% of the total ANR
    7575requested funding.
     76\begin{center}\input{table_tima_short.tex}\end{center}
    7677\item [Subcontracting]
    7778No subcontracting costs.
    … …  
    8384The costs justified by internal invoicing procedures are evaluated to 4\%
    8485of the total requested ANR funding.\\
    85     \begin{center}\input{table_tima_short.tex}\end{center}
    86 %FIXME comment on rajoute les hommes-ans sur le WP7 pour la dissemination ?
    8786\end{description}
    8887
    8988%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
    9089\subsection{Partner 4: \ubs}
     90\begin{figure}\leavevmode\center
     91\input{table_ubs_full.tex}
     92\caption{\label{ress-detail-ubs}Man power in $mm$ for the delivrables of \ubs.}
     93\end{figure}
    9194
    9295\begin {description}
    9396\item [Equipment]
    94 \par
    9597In order to validate the design flow project, the LabSTICC  laboratory will buy FPGA developpement boards.
    9698The cost for these FPGA boards is estimated to 3\% of the total ANR funding.
    9799\item [Personnel costs]
    98 \par
    99100The faculty members involved in the project are
    100101associate professors (Philippe COUSSY, Cyrille CHAVET) or research ingeneers (Dominique HELLER).
    101102All non-permanent personnel costs are estimated in men*months
    102103for senior researchers (post-doc or research engineers).
     104
    103105The table below sumarizes the man power by task for both permanent and non-permanent
    104 personnels. The detail by delivrables is given in figure~\ref {detail-lip6}.
     106personnels. The detail by delivrables is given in figure~\ref {ress-detail-ubs}.
    105107The non-permanent personnels costs represent 50\% of the personnal costs.
    106108The requested funding for non permanent personnels is about 83\% of the total ANR
    107109requested funding.
     110\begin{center}\input{table_ubs_short.tex}\end{center}
    108111\item [Subcontracting]
    109 \par
    110112No subcontracting costs.
    111113\item [Travel]
    112 \par
    113114The travel costs are associated to management and meeting as
    114115well as participation to conferences. The travel costs are estimated
    115116to 10\% of the total requested ANR funding.
    116117\item [Expenses for inward billing]
    117 \par
    118118The costs justified by internal invoicing procedures are evaluated to 4\%
    119119of the total requested ANR funding.
    120 \mustbecompleted{FIXME: LIP6 :: Comment peut-on modifier automatiquement le contenu du tableau (sans modifier directement le
    121 fichier)}
    122 \\
    123 %\input{table_ubs.tex}
    124120\end {description}
    125121
    … …  
    160156
    161157%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
    162 \subsection{Partner 6: \altera}
     158\subsection{Partner 6: \xilinx}
     159\ressourcehelp
     160\begin{figure}\leavevmode\center
     161\input{table_xilinx_full.tex}
     162\caption{\label{ress-detail-xilinx}Man power in $mm$ for the delivrables of \xilinx.}
     163\end{figure}
     164\begin{description}
     165\item[Equipment]
     166    No specific equipment acquisition is required for this project.
     167\item[Personnel costs]
     168    \xilinx employees involved in the project are permanent Software Engineers.
     169    The detail by delivrables is given in figure~\ref{ress-detail-xilinx} and
     170    summarizes by task in the following table.
     171    \begin{center}\input{table_xilinx_short.tex}\end{center}
     172\item[Subcontracting]
     173    No subcontracting costs.
     174\item[Travel]
     175    The travel costs are associated to project meeting as well as participation to
     176    conferences. The travel costs are estimated to
     177    \mustbecompleted{FIXME:\xilinx: XX\%} of the total requested ANR funding.
     178\item[Expenses for inward billing] none
     179\item[Other working costs] none
     180\end{description}
     181
     182%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
     183\subsection{Partner 7: \bull}
    163184\ressourcehelp
    164185
    165186%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
    166 \subsection{Partner 7: \xilinx}
     187\subsection{Partner 8: \thales}
    167188\ressourcehelp
    168189
    169190%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
    170 \subsection{Partner 8: \bull}
     191\subsection{Partner 9: \zied}
    171192\ressourcehelp
    172193
    173194%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
    174 \subsection{Partner 9: \thales}
     195\subsection{Partner 10: \navtel}
    175196\ressourcehelp
    176197
    177 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
    178 \subsection{Partner 10: \zied}
    179 \ressourcehelp
    180 
    181 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
    182 \subsection{Partner 11: \navtel}
    183 \ressourcehelp
    184 

  • anr/task-7.tex

    r78 r99  
    3838      \CoutHorsD{6}{36}{\Stima}{dissemination}{0:2:2}
    3939    \end{livrable}
    40 \item This \ST consists of making a COACH tutorial and to publish it on the public WEB
     40\item
     41    \label{subtask-tutorial}
     42    This \ST consists of making a COACH tutorial and to publish it on the public WEB
    4143    site. The tutorial example will also be used as reference demonstrator of the
    4244    framework.
Note: See TracChangeset for help on using the changeset viewer.