[56] | 1 | % vim:set spell: |
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| 2 | % vim:spell spelllang=en: |
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| 3 | |
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[23] | 4 | \begin{taskinfo} |
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[126] | 5 | \let\BULL\leader |
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| 6 | \let\UPMC\enable |
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[23] | 7 | \let\TIMA\enable |
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[126] | 8 | \let\THALES\enable |
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[113] | 9 | \let\XILINX\enable |
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[23] | 10 | \end{taskinfo} |
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| 11 | % |
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| 12 | \begin{objectif} |
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| 13 | This task pools the features dedicated to HPC system design. It is described on |
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| 14 | figures~\ref{coach-flow} and \ref{archi-hpc}. It consists in |
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| 15 | \begin{itemize} |
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[111] | 16 | \item Providing a software tool that helps the HPC designer to find a good partition of the initial application |
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[56] | 17 | (figure~\ref{archi-hpc}). |
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[126] | 18 | \item specification of the communication schemes between the software part running on the PC and the |
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| 19 | FPGA-SoC. |
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[38] | 20 | \item Implementing the communication scheme at all levels: partition help, software |
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[23] | 21 | implementation both on the PC and in the operating system of the FPGA-SoC, hardware. |
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[63] | 22 | \item Providing support for dynamic partial reconfiguration of \xilinx FPGA in order |
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| 23 | to optimize FPGA ressource usage. |
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[23] | 24 | \end{itemize} |
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[56] | 25 | |
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[23] | 26 | The low level hardware transmission support will be the PCI/X bus which allows high bit-rate |
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[134] | 27 | transfers. The reasons of this choices are that both \altera and \xilinx provide PCI/X IP for |
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[23] | 28 | their FPGA and that GPU HPC softwares use also it. |
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[111] | 29 | %This will allow us at least to be inspired by GPU communication schemes and may be to reuse |
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| 30 | %parts of the GPU softwares. |
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[56] | 31 | |
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[23] | 32 | \end{objectif} |
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| 33 | % |
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[112] | 34 | \mustbecompleted { FIXME :: Ne doit onpas fusionner les taches ST6-1, ST6-2, ST6-3 et pourquoi pas ST6-4 ???} |
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[52] | 35 | \begin{workpackage} |
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[123] | 36 | \subtask This \ST is the definition of the communication schemes as a software API |
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[23] | 37 | (Application Programing Interface) between the application part running on the PC and |
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| 38 | the application part running on the FPGA-SoC. |
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| 39 | \begin{livrable} |
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[126] | 40 | \itemL{0}{6}{d}{\Sbull}{HPC communication API}{1.0:0:0} |
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[52] | 41 | \setMacroInAuxFile{hpcCommApi} |
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[111] | 42 | Specification describing the API. |
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[23] | 43 | \end{livrable} |
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[123] | 44 | \subtask This \ST consists in helping to partition applications. |
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[36] | 45 | It is a library implementing the communication API with features to profile |
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[40] | 46 | the partitioned application. |
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[56] | 47 | %FIXME (Olivier) pour moi, on veut un outil de profiling pour partitionner l'application. |
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| 48 | % It is a profiling (or simulation) library implementing the communication API |
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| 49 | |
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[23] | 50 | \begin{livrable} |
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[52] | 51 | \itemL{6}{12}{x}{\Supmc}{HPC partionning helper}{1:0:0} |
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| 52 | A library implementing the communication API defined in the {\hpcCommApi} delivrable. |
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[23] | 53 | \end{livrable} |
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[123] | 54 | \subtask This \ST deals with the implementation of the communication API on the both sides (PC |
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[23] | 55 | part and FPGA-SoC). |
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| 56 | \begin{livrable} |
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[52] | 57 | \itemL{12}{21}{x}{\Supmc}{HPC API for Linux PC}{0:3:0} |
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| 58 | The PC part of the HPC communication API that comminicates with the FPGA-SOC, a |
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| 59 | library and probably a LINUX module. |
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[134] | 60 | \itemL{12}{21}{x}{\Supmc}{HPC API for MUTEKH OS}{0:3:0} |
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[52] | 61 | \setMacroInAuxFile{hpcMutekDriver} |
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| 62 | The FPGA-SoC part of the communication API, a driver. |
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[57] | 63 | \itemL{21}{24}{x}{\Stima}{HPC API for DNA OS}{0:3:0} |
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[52] | 64 | Port of the {\hpcMutekDriver} driver on the DNA OS. |
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| 65 | \itemL{24}{33}{x}{\Supmc}{HPC API}{0:0:1} |
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[134] | 66 | Maintenance work of HPC API for both Linux PC and MUTEKH OS. |
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[23] | 67 | \end{livrable} |
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[123] | 68 | \subtask This \ST deals with the implementation of hardware and SystemC modules |
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[134] | 69 | required by the neutral architectural template for using the PCI/X IP of \altera and \xilinx. |
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[23] | 70 | \begin{livrable} |
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[57] | 71 | \itemL{9}{18}{h}{\Stima}{HPC hardware \xilinx}{3:9:0} |
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[36] | 72 | \setMacroInAuxFile{hpcPlbBridge} |
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| 73 | The synthesizable VHDL description of a PLB/VCI bridge and its corresponding SystemC model. |
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[113] | 74 | \itemL{9}{18}{h}{\Supmc}{HPC hardware \altera}{1:2:0} |
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[36] | 75 | \setMacroInAuxFile{hpcAvalonBridge} |
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[40] | 76 | The synthesizable VHDL description of an AVALON/VCI bridge and its corresponding SystemC model. |
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[59] | 77 | \itemL{9}{24}{h}{\Supmc}{PCI/X traffic generator}{1:1:0} |
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| 78 | The SystemC description of a component that generates PCI/X traffic. It is |
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| 79 | required to prototype FPGA-SoC dedicated to HPC. |
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[23] | 80 | \end{livrable} |
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[59] | 81 | |
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[123] | 82 | \subtask This \ST consists in integrating dynamic partial reconfiguration of \xilinx FPGA in the CSG design flow. |
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[56] | 83 | It also includes appropriate SoC-FPGA OS drivers and a modification of the profiling library. |
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[23] | 84 | \begin{livrable} |
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[113] | 85 | \itemL{24}{36}{x}{\Supmc}{CSG support for \ganttlf reconfiguration}{0:0:2} |
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[63] | 86 | Modification of CSG software to support statically reconfigurable task. |
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[130] | 87 | \itemL{18}{36}{x}{\Stima}{CSG module for \ganttlf dynamic reconfiguration}{0:4:12} |
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[63] | 88 | This livrable is a CSG module allowing to partition the task graph on |
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| 89 | the dynamic partial reconfiguration regions. The resulting task-region assignement |
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| 90 | is directly used for generation of bitstreams. The module also produces reconfiguration |
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| 91 | management software to be run on the SoC-FPGA. |
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| 92 | \itemL{18}{30}{x}{\Stima}{dynamic reconfiguration \ganttlf DNA drivers}{0:3:3} |
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[52] | 93 | \setMacroInAuxFile{hpcDynconfDriver} |
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[59] | 94 | The drivers required by the DNA OS in order to manage dynamic partial |
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| 95 | reconfiguration inside the SoC-FPGA. |
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[134] | 96 | \itemL{30}{36}{x}{\Supmc}{dynamic reconfiguration \ganttlf MUTEKH drivers}{0:0:1} |
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| 97 | Port of the {\hpcDynconfDriver} drivers on the MUTEKH OS. |
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[63] | 98 | \itemL{24}{36}{x}{\Stima}{Profiler for \ganttlf dynamic reconfiguration}{0:0:6} |
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[59] | 99 | Extension of the HPC partionning helper in order to integrate dynamic partial |
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| 100 | reconfiguration dedicated features (reconfiguration time of regions, variable |
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| 101 | number of coprocessors). |
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[113] | 102 | \itemL{24}{36}{d}{\Sxilinx}{optimisation for \ganttlf \xilinx dynamic reconfiguration}{0:0:1} |
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| 103 | \xilinx will work with \tima in order to better take into account during |
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| 104 | partitioning decisions specific constraints due to partial reconfiguration process. |
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| 105 | The delivrable is a document describing the \xilinx specific constraints. |
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[59] | 106 | \end{livrable} |
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[113] | 107 | %\item This \ST is the delivery of 2 PCI/X \mustbecompleted{FIXME: Stratix4} FPGA board |
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| 108 | % with its PCI/X IP. These boards are dedicated to the COACH HPC development. |
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| 109 | % They are based on \mustbecompleted{FIXME:stratix4} FPGA device of 400,000 LUT. |
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| 110 | % \begin{livrable} |
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| 111 | % \itemL{0}{6}{m}{\Saltera}{HPC development boards}{0:0:0} Two PCI/X FPGA boards. |
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| 112 | % \end{livrable} |
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[23] | 113 | \end{workpackage} |
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