Changeset 123 for trunk/IPs/systemC

trunk/IPs/systemC/Environment/Data/src/Segment_init.cpp

-                      r88
+                      r123
     int    size   = this->size;
     int    offset = 0;
     loadexec(&ptab,&size,&offset,filename,sections);
 //     std::cout << "    - size         : " << size         << std::endl;
 //     std::cout << "    - offset       : " << offset       << std::endl;

trunk/IPs/systemC/Environment/src/Environment.cpp

-                      r112
+                      r123
     component_cache       = new cache::Cache     ("cache", param->param_cache);
     component_tty         = new tty::TTY * [param->nb_component_tty];
     for (uint32_t i=0; i<param->nb_component_tty; i++)
     component_tty     [i] = new tty::TTY         ("tty_"+i    ,param->param_tty     [i]);
     component_ramlock     = new ramlock::RamLock * [param->nb_component_ramlock];
     for (uint32_t i=0; i<param->nb_component_ramlock; i++)
     component_ramlock [i] = new ramlock::RamLock ("ramlock_"+i,param->param_ramlock [i]);
     component_sim2os      = new sim2os::Sim2OS   ("sim2os" ,param->param_sim2os );
     component_data        = new data::Data       ("data"   ,param->param_data   );
     component_buffer_irsp = new queue::Sort_Queue<irsp_t*> * [param->nb_entity];
     component_buffer_drsp = new queue::Sort_Queue<drsp_t*> * [param->nb_entity];
 …
         entity.segment->define_target(data::TYPE_TARGET_SIM2OS,0);
+      }
     for (uint32_t i=0; i<param->nb_entity; i++)
 …
         dcache_rsp_val [i] = new Tcontrol_t [param->dcache_dedicated_nb_port[i]];
+      }
     // *****[ Definition of method ]*****
     SC_METHOD (transition);
 …
     dont_initialize ();
     sensitive << (*(CLOCK)).neg();
+  }

trunk/IPs/systemC/Environment/src/Environment_transition.cpp

-                      r117
+                      r123
                     _cout(ENVIRONMENT,"     * Rdata : ");
                     for (uint32_t i=0; i<nb_bytes; i++)
                       __cout(ENVIRONMENT,"%.2x",0xff&static_cast<uint32_t>(read_dram[0][i]));
+                    for (uint32_t x=0; x<nb_bytes; x++)
+                      __cout(ENVIRONMENT,"%.2x",0xff&static_cast<uint32_t>(read_dram[0][x]));
                     _cout(ENVIRONMENT,".\n");

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue.cpp

-                      r122
+                      r123
     usage_environment(_usage);
 #if DEBUG_Core_Glue == true
     log_printf(INFO,Core_Glue,FUNCTION,_("<%s> Parameters"),_name.c_str());
     std::cout << *param << std::endl;
 #endif
+// #if DEBUG_Core_Glue == true
+//     log_printf(INFO,Core_Glue,FUNCTION,_("<%s> Parameters"),_name.c_str());
+//     std::cout << *param << std::endl;
+// #endif
     log_printf(INFO,Core_Glue,FUNCTION,_("<%s> : Allocation"),_name.c_str());

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_genMealy_branch_complete.cpp

-                      r98
+                      r123
         BRANCH_COMPLETE_OOO_ENGINE_ACK [i][j] = 0;
+    if (PORT_READ(in_NRESET))
+      {
     for (uint32_t i=0; i<_param->_nb_ooo_engine; ++i)
       for (uint32_t j=0; j<_param->_ooo_engine_nb_inst_branch_complete[i]; ++j)
 …
           PORT_WRITE(out_BRANCH_COMPLETE_OOO_ENGINE_MISS_PREDICTION [i][j], PORT_READ(in_BRANCH_COMPLETE_FRONT_END_MISS_PREDICTION [num_front_end][j]));
+        }
+      }
     for (uint32_t i=0; i<_param->_nb_front_end; ++i)

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_genMealy_commit_event.cpp

-                      r105
+                      r123
       COMMIT_EVENT_OOO_ENGINE_ACK [i] = 0;
+    if (PORT_READ(in_NRESET))
+      {
      for (uint32_t i=0; i<_param->_nb_ooo_engine; ++i)
+       {
 …
+       }
+      }
     for (uint32_t i=0; i<_param->_nb_front_end; ++i)
       PORT_WRITE(out_COMMIT_EVENT_FRONT_END_VAL [i], COMMIT_EVENT_FRONT_END_VAL [i]);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_genMealy_execute.cpp

-                      r88
+                      r123
         EXECUTE_EXECUTE_LOOP_ACK [i][j] = 0;
+    if (PORT_READ(in_NRESET))
+      {
     for (uint32_t i=0; i<_param->_nb_execute_loop; ++i)
 …
           PORT_WRITE(out_EXECUTE_OOO_ENGINE_DATA         [num_ooo_engine][num_execute_loop][j], PORT_READ(in_EXECUTE_EXECUTE_LOOP_DATA         [i][j]));
+        }
+      }
     for (uint32_t i=0; i<_param->_nb_ooo_engine; ++i)

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_genMealy_insert.cpp

-                      r109
+                      r123
     log_function(Core_Glue,FUNCTION,_name.c_str());
+    if (PORT_READ(in_NRESET))
+      {
     for (uint32_t i=0; i<_param->_nb_execute_loop; ++i)
       for (uint32_t j=0; j<_param->_execute_loop_nb_ooo_engine[i]; ++j)
 …
+            }
+        }
+      }
+    else
+      {
+        for (uint32_t i=0; i<_param->_nb_execute_loop; ++i)
+          for (uint32_t j=0; j<_param->_execute_loop_nb_ooo_engine[i]; ++j)
+            {
+              Tcontext_t num_ooo_engine   = _param->_translate_execute_loop_num_ooo_engine [i][j];
+              for (uint32_t k=0; k<_param->_execute_loop_nb_inst_insert[i][j]; ++k)
+                {
+                  PORT_WRITE(out_INSERT_OOO_ENGINE_ACK  [num_ooo_engine][k],0);
+                 PORT_WRITE(out_INSERT_EXECUTE_LOOP_VAL [i][j][k],0);
+                }
+            }
+      }
     log_end(Core_Glue,FUNCTION);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_genMealy_issue.cpp

-                      r122
+                      r123
     Tcontrol_t ISSUE_OOO_ENGINE_ACK   [_param->_nb_ooo_engine  ][_param->_max_nb_inst_issue_queue];
     Tcontrol_t ISSUE_EXECUTE_LOOP_VAL [_param->_nb_execute_loop][_param->_max_nb_read_unit];
+    for (uint32_t i=0; i<_param->_nb_ooo_engine; ++i)
+      for (uint32_t j=0; j<_param->_nb_inst_issue_queue[i]; ++j)
+        ISSUE_OOO_ENGINE_ACK [i][j] = 0;
+    for (uint32_t i=0; i<_param->_nb_execute_loop; ++i)
+      for (uint32_t j=0; j<_param->_nb_read_unit[i]; ++j)
+        ISSUE_EXECUTE_LOOP_VAL [i][j] = 0;
+    if (PORT_READ(in_NRESET))
+      {
     Tcontrol_t READ_UNIT_ENABLE       [_param->_nb_execute_loop][_param->_max_nb_read_unit];
     Tcontrol_t SLOT_ENABLE            [_param->_nb_ooo_engine  ][_param->_max_nb_inst_issue_slot];
 …
     // Init -> all at 0
     for (uint32_t i=0; i<_param->_nb_ooo_engine; ++i)
+      {
+        for (uint32_t j=0; j<_param->_nb_inst_issue_queue[i]; ++j)
+          ISSUE_OOO_ENGINE_ACK [i][j] = 0;
+        for (uint32_t j=0; j<_param->_nb_inst_issue_slot[i]; ++j)
+          SLOT_ENABLE [i][j] = 1;
+      }
+      for (uint32_t j=0; j<_param->_nb_inst_issue_slot[i]; ++j)
+        SLOT_ENABLE [i][j] = 1;
     for (uint32_t i=0; i<_param->_nb_execute_loop; ++i)
       for (uint32_t j=0; j<_param->_nb_read_unit[i]; ++j)
+        {
-          ISSUE_EXECUTE_LOOP_VAL [i][j] = 0;
           // Read unit is enable is signal ack is set
           READ_UNIT_ENABLE       [i][j] = (PORT_READ(in_ISSUE_EXECUTE_LOOP_ACK [i][j]) == 1);
 …
+      }
+      }
     // Write output
     for (uint32_t i=0; i<_param->_nb_ooo_engine; ++i)

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/src/Dcache_Access.cpp

-                      r88
+                      r123
     usage_environment(_usage);
 #if DEBUG_Dcache_Access == true
     log_printf(INFO,Dcache_Access,FUNCTION,_("<%s> Parameters"),_name.c_str());
+// #if DEBUG_Dcache_Access == true
+//     log_printf(INFO,Dcache_Access,FUNCTION,_("<%s> Parameters"),_name.c_str());
     std::cout << *param << std::endl;
 #endif
+//     std::cout << *param << std::endl;
+// #endif
     log_printf(INFO,Dcache_Access,FUNCTION,_("<%s> : Allocation"),_name.c_str());

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/src/Dcache_Access_genMealy_req.cpp

-                      r117
+                      r123
     log_begin(Dcache_Access,FUNCTION);
+    if (PORT_READ(in_NRESET))
+      {
     Tcontrol_t dcache_req_val [_param->_nb_dcache_port];
     for (uint32_t i=0; i<_param->_nb_dcache_port; ++i)
 …
         for (uint32_t k=0; k<_param->_nb_cache_access [i][j]; ++k)
           PORT_WRITE(out_LSQ_REQ_ACK [i][j][k], lsq_req_ack [i][j][k]);
+      }
+    else
+      {
+        for (uint32_t i=0; i<_param->_nb_dcache_port; ++i)
+          PORT_WRITE(out_DCACHE_REQ_VAL [i], 0);
+        for (uint32_t i=0; i<_param->_nb_execute_loop; ++i)
+          for (uint32_t j=0; j<_param->_nb_load_store_unit[i]; ++j)
+            for (uint32_t k=0; k<_param->_nb_cache_access [i][j]; ++k)
+              PORT_WRITE(out_LSQ_REQ_ACK [i][j][k], 0);
+      }
     log_end(Dcache_Access,FUNCTION);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/src/Dcache_Access_genMealy_rsp.cpp

-                      r94
+                      r123
     log_begin(Dcache_Access,FUNCTION);
+    if (PORT_READ(in_NRESET))
+      {
     Tcontrol_t lsq_rsp_val [_param->_nb_execute_loop][_param->_max_nb_load_store_unit][_param->_max_nb_cache_access];
     for (uint32_t i=0; i<_param->_nb_execute_loop; ++i)
 …
         for (uint32_t k=0; k<_param->_nb_cache_access [i][j]; ++k)
           PORT_WRITE(out_LSQ_RSP_VAL [i][j][k], lsq_rsp_val [i][j][k]);
+      }
+    else
+      {
+        for (uint32_t i=0; i<_param->_nb_dcache_port; ++i)
+          PORT_WRITE(out_DCACHE_RSP_ACK [i],0);
+        for (uint32_t i=0; i<_param->_nb_execute_loop; ++i)
+          for (uint32_t j=0; j<_param->_nb_load_store_unit[i]; ++j)
+            for (uint32_t k=0; k<_param->_nb_cache_access [i][j]; ++k)
+              PORT_WRITE(out_LSQ_RSP_VAL [i][j][k], 0);
+      }
     log_end(Dcache_Access,FUNCTION);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/src/Icache_Access.cpp

-                      r88
+                      r123
     usage_environment(_usage);
 #if DEBUG_Core == true
     log_printf(INFO,Core,FUNCTION,_("<%s> Parameters"),_name.c_str());
     std::cout << *param << std::endl;
 #endif
+// #if DEBUG_Core == true
+//     log_printf(INFO,Core,FUNCTION,_("<%s> Parameters"),_name.c_str());
+//     std::cout << *param << std::endl;
+// #endif
     log_printf(INFO,Icache_Access,FUNCTION,_("<%s> : Allocation"),_name.c_str());

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/src/Icache_Access_genMealy_req.cpp

-                      r119
+                      r123
     Tcontrol_t icache_req_val [_param->_nb_icache_port];
     for (uint32_t i=0; i<_param->_nb_icache_port; ++i)
+      icache_req_val [i] = 0;
+    Tcontrol_t context_req_ack [_param->_nb_front_end][_param->_max_nb_context];
+    for (uint32_t i=0; i<_param->_nb_front_end; ++i)
+      for (uint32_t j=0; j<_param->_nb_context[i]; ++j)
+        context_req_ack [i][j] = 0;
+    if (PORT_READ(in_NRESET))
+      {
+        icache_req_val [i] = 0;
+    for (uint32_t i=0; i<_param->_nb_icache_port; ++i)
+      {
 #ifdef STATISTICS
         _internal_ICACHE_REQ_NB_ACCESS         [i] = 0;
 …
+      }
-    Tcontrol_t context_req_ack [_param->_nb_front_end][_param->_max_nb_context];
-    for (uint32_t i=0; i<_param->_nb_front_end; ++i)
-      for (uint32_t j=0; j<_param->_nb_context[i]; ++j)
-        context_req_ack [i][j] = 0;
     std::list<generic::priority::select_t> * select = _priority ->select();
     for (std::list<generic::priority::select_t>::iterator it=select ->begin();
 …
+          }
+      }
+      }
     for (uint32_t i=0; i<_param->_nb_icache_port; ++i)

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/src/Icache_Access_genMealy_rsp.cpp

-                      r88
+                      r123
         context_rsp_val [i][j] = 0;
+    if (PORT_READ(in_NRESET))
+      {
     for (uint32_t i=0; i<_param->_nb_icache_port; ++i)
+      {
 …
+      }
+      }
+    else
+      for (uint32_t i=0; i<_param->_nb_icache_port; ++i)
+        PORT_WRITE(out_ICACHE_RSP_ACK [i],0);
     for (uint32_t i=0; i<_param->_nb_front_end; ++i)
       for (uint32_t j=0; j<_param->_nb_context[i]; ++j)

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/src/Execute_loop_Glue.cpp

-                      r88
+                      r123
     usage_environment(_usage);
 #if DEBUG_Execute_loop_Glue == true
     log_printf(INFO,Execute_loop_Glue,FUNCTION,_("<%s> Parameters"),_name.c_str());
+// #if DEBUG_Execute_loop_Glue == true
+//     log_printf(INFO,Execute_loop_Glue,FUNCTION,_("<%s> Parameters"),_name.c_str());
     std::cout << *param << std::endl;
 #endif
+//     std::cout << *param << std::endl;
+// #endif
     log_printf(INFO,Execute_loop_Glue,FUNCTION,_("<%s> : Allocation"),_name.c_str());

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/src/Execute_loop_Glue_genMealy_gpr_write.cpp

-                      r88
+                      r123
     log_begin(Execute_loop_Glue,FUNCTION);
+    if (PORT_READ(in_NRESET))
+      {
     for (uint32_t i=0; i<_param->_nb_gpr_write; i++)
+      {
 …
         PORT_WRITE(out_GPR_WRITE_READ_UNIT_DATA               [i],data         );
+      }
+      }
+    else
+      {
+        for (uint32_t i=0; i<_param->_nb_gpr_write; i++)
+          {
+            PORT_WRITE(out_GPR_WRITE_WRITE_UNIT_ACK               [i],0);
+            PORT_WRITE(out_GPR_WRITE_REGISTER_FILE_VAL            [i],0);
+            PORT_WRITE(out_GPR_WRITE_READ_UNIT_VAL                [i],0);
+          }
+      }
     log_end(Execute_loop_Glue,FUNCTION);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/src/Execute_loop_Glue_genMealy_spr_write.cpp

-                      r88
+                      r123
     log_begin(Execute_loop_Glue,FUNCTION);
+    if (PORT_READ(in_NRESET))
+      {
     for (uint32_t i=0; i<_param->_nb_spr_write; i++)
+      {
 …
         PORT_WRITE(out_SPR_WRITE_READ_UNIT_DATA               [i],data         );
+      }
+      }
+    else
+      {
+        for (uint32_t i=0; i<_param->_nb_spr_write; i++)
+          {
+            PORT_WRITE(out_SPR_WRITE_WRITE_UNIT_ACK               [i],0);
+            PORT_WRITE(out_SPR_WRITE_REGISTER_FILE_VAL            [i],0);
+            PORT_WRITE(out_SPR_WRITE_READ_UNIT_VAL                [i],0);
+          }
+      }
     log_end(Execute_loop_Glue,FUNCTION);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit.cpp

-                      r116
+                      r123
     allocation ();
 #if DEBUG_Functionnal_unit == true
     log_printf(INFO,Functionnal_unit,FUNCTION,_("<%s> Parameters"),_name.c_str());
+// #if DEBUG_Functionnal_unit == true
+//     log_printf(INFO,Functionnal_unit,FUNCTION,_("<%s> Parameters"),_name.c_str());
     std::cout << *param << std::endl;
 #endif
+//     std::cout << *param << std::endl;
+// #endif
 #ifdef STATISTICS

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_genMealy.cpp

-                      r118
+                      r123
           // Can out if : have an instruction and is finish (latence == 0)
           internal_EXECUTE_OUT_VAL = (reg_BUSY_OUT and (_execute_operation_out->_timing._latence == 0));
-          PORT_WRITE(out_EXECUTE_OUT_VAL, internal_EXECUTE_OUT_VAL);
+        }
 …
                                      (internal_EXECUTE_OUT_VAL and PORT_READ(in_EXECUTE_OUT_ACK)));
+            }
-          PORT_WRITE(out_EXECUTE_IN_ACK , internal_EXECUTE_IN_ACK);
+        }
+      }
+    else
+      {
+        // RESET
+        internal_EXECUTE_IN_ACK = 0;
+        internal_EXECUTE_OUT_VAL = 0;
+      }
+    // Write Output
+    PORT_WRITE(out_EXECUTE_IN_ACK , internal_EXECUTE_IN_ACK);
+    PORT_WRITE(out_EXECUTE_OUT_VAL, internal_EXECUTE_OUT_VAL);
     log_end(Functionnal_unit,FUNCTION);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_genMoore.cpp

r116	r123
26	26	log_function(Functionnal_unit,FUNCTION,_name.c_str());
27	27
	28	if (PORT_READ(in_NRESET))
28	29	{
29	30	if (_param->_have_port_context_id)

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit.cpp

-                      r111
+                      r123
     log_printf(FUNC,Load_store_unit,FUNCTION,"Begin");
 #if DEBUG_Load_store_unit == true
     log_printf(INFO,Load_store_unit,FUNCTION,_("<%s> Parameters"),_name.c_str());
     std::cout << *param << std::endl;
 #endif
+// #if DEBUG_Load_store_unit == true
+//     log_printf(INFO,Load_store_unit,FUNCTION,_("<%s> Parameters"),_name.c_str());
+//     std::cout << *param << std::endl;
+// #endif
 #ifdef SYSTEMC

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMealy_insert.cpp

-                      r101
+                      r123
       ack [i] = 0;
+    if (PORT_READ(in_NRESET))
+      {
     // find first valid entry
     // store queue is never full (pointer is manage by rename stage)
 …
+            }
+        }
+      }
+    else
+      {
+        internal_MEMORY_IN_ACK = 0;
+//         internal_MEMORY_IN_PORT = i;
+      }
     for (uint32_t i=0; i<_param->_nb_inst_memory; i++)

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMoore.cpp

-                      r122
+                      r123
     log_function(Load_store_unit,FUNCTION,_name.c_str());
+    if (PORT_READ(in_NRESET))
+      {
     // ~~~~~[ Interface "memory_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 …
     // write output
-    PORT_WRITE(out_MEMORY_OUT_VAL          [0], internal_MEMORY_OUT_VAL);
     if (_param->_have_port_context_id)
     PORT_WRITE(out_MEMORY_OUT_CONTEXT_ID   [0], memory_out_context_id   );
 …
     // ~~~~~[ Interface "dache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     Tcontext_t        dcache_req_context_id;
     Tpacket_t         dcache_req_packet_id ;
     Tdcache_address_t dcache_req_address   ;
     Tdcache_type_t    dcache_req_type      ;
     Tdcache_data_t    dcache_req_wdata     ;
+    Tcontext_t        dcache_req_context_id = 0;
+    Tpacket_t         dcache_req_packet_id  = 0;
+    Tdcache_address_t dcache_req_address    = 0;
+    Tdcache_type_t    dcache_req_type       = 0;
+    Tdcache_data_t    dcache_req_wdata      = 0;
     log_printf(TRACE,Load_store_unit,FUNCTION,"  * Test DCACHE_REQ");
 …
+      }
-    PORT_WRITE(out_DCACHE_REQ_VAL       [0], internal_DCACHE_REQ_VAL);
     if (_param->_have_port_dcache_context_id)
     PORT_WRITE(out_DCACHE_REQ_CONTEXT_ID[0], dcache_req_context_id);
 …
     PORT_WRITE(out_DCACHE_REQ_TYPE      [0], dcache_req_type      );
     PORT_WRITE(out_DCACHE_REQ_WDATA     [0], dcache_req_wdata     );
+      }
+    else
+      {
+        // Reset
+    internal_MEMORY_OUT_VAL = 0;
+//  internal_MEMORY_OUT_PTR =0
+//  internal_MEMORY_OUT_SELECT_QUEUE = SELECT_STORE_QUEUE;
+    internal_DCACHE_REQ_VAL = 0;
+    internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ = 0;
+//  internal_DCACHE_REQ_SELECT_QUEUE = SELECT_LOAD_QUEUE_SPECULATIVE;
+      }
+    // Write output
+    PORT_WRITE(out_MEMORY_OUT_VAL [0], internal_MEMORY_OUT_VAL);
+    PORT_WRITE(out_DCACHE_REQ_VAL [0], internal_DCACHE_REQ_VAL);
     log_end(Load_store_unit,FUNCTION);
   };

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_genMoore.cpp

r81	r123
26	26	log_printf(FUNC,Load_store_unit,FUNCTION,"Begin");
27	27
	28	// if (PORT_READ(in_NRESET))
28	29	(this->*function_genMoore) ();
29	30

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue.cpp

-                      r88
+                      r123
     log_printf(FUNC,Read_queue,"Read_queue","Begin");
 #if DEBUG_Read_queue == true
     log_printf(INFO,Read_queue,FUNCTION,_("<%s> Parameters"),_name.c_str());
     std::cout << *param << std::endl;
 #endif
+// #if DEBUG_Read_queue == true
+//     log_printf(INFO,Read_queue,FUNCTION,_("<%s> Parameters"),_name.c_str());
+//     std::cout << *param << std::endl;
+// #endif
 #ifdef SYSTEMC

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_genMealy_read_queue_out_gpr.cpp

-                      r88
+                      r123
     log_function(Read_queue,FUNCTION,_name.c_str());
+    if (PORT_READ(in_NRESET))
+      {
     internal_READ_QUEUE_OUT_DATA_RA_VAL = (// Previous value
                                            _queue_head->_data_ra_val or
 …
     // Affectation out port
+    PORT_WRITE(out_READ_QUEUE_OUT_DATA_RA    ,internal_READ_QUEUE_OUT_DATA_RA    );
+    PORT_WRITE(out_READ_QUEUE_OUT_DATA_RB    ,internal_READ_QUEUE_OUT_DATA_RB    );
+      }
+    else
+      {
+        internal_READ_QUEUE_OUT_DATA_RA_VAL = 0;
+        internal_READ_QUEUE_OUT_DATA_RB_VAL = 0;
+//         internal_READ_QUEUE_OUT_DATA_RA = 0;
+//         internal_READ_QUEUE_OUT_DATA_RB = 0;
+      }
     PORT_WRITE(out_READ_QUEUE_OUT_DATA_RA_VAL,internal_READ_QUEUE_OUT_DATA_RA_VAL);
     PORT_WRITE(out_READ_QUEUE_OUT_DATA_RB_VAL,internal_READ_QUEUE_OUT_DATA_RB_VAL);
-    PORT_WRITE(out_READ_QUEUE_OUT_DATA_RA    ,internal_READ_QUEUE_OUT_DATA_RA    );
-    PORT_WRITE(out_READ_QUEUE_OUT_DATA_RB    ,internal_READ_QUEUE_OUT_DATA_RB    );
     log_end(Read_queue,FUNCTION);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_genMealy_read_queue_out_spr.cpp

-                      r88
+                      r123
     log_function(Read_queue,FUNCTION,_name.c_str());
+    if (PORT_READ(in_NRESET))
+      {
     internal_READ_QUEUE_OUT_DATA_RC_VAL = (// Previous value
                                            _queue_head->_data_rc_val or
 …
     // Affectation out port
+    PORT_WRITE(out_READ_QUEUE_OUT_DATA_RC    ,internal_READ_QUEUE_OUT_DATA_RC    );
+      }
+    else
+      {
+        internal_READ_QUEUE_OUT_DATA_RC_VAL = 0;
+//         internal_READ_QUEUE_OUT_DATA_RC
+      }
     PORT_WRITE(out_READ_QUEUE_OUT_DATA_RC_VAL,internal_READ_QUEUE_OUT_DATA_RC_VAL);
-    PORT_WRITE(out_READ_QUEUE_OUT_DATA_RC    ,internal_READ_QUEUE_OUT_DATA_RC    );
     log_end(Read_queue,FUNCTION);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_genMealy_read_queue_out_val.cpp

-                      r88
+                      r123
     log_function(Read_queue,FUNCTION,_name.c_str());
+    if (PORT_READ(in_NRESET))
+      {
     internal_READ_QUEUE_OUT_READ_RA_VAL = (// Previous value
                                            _queue_head->_read_ra_val  and
 …
-    PORT_WRITE(out_READ_QUEUE_OUT_VAL, internal_READ_QUEUE_OUT_VAL);
     log_printf(TRACE,Read_queue,FUNCTION,"  * internal_READ_QUEUE_OUT_VAL           : %d",internal_READ_QUEUE_OUT_VAL);
     log_printf(TRACE,Read_queue,FUNCTION,"    * _queue->empty()                     : %d",_queue->empty());
 …
     log_printf(TRACE,Read_queue,FUNCTION,"      * _queue_head->_read_rc_val         : %d",_queue_head->_read_rc_val);
     log_printf(TRACE,Read_queue,FUNCTION,"      * in_SPR_READ_ACK      [0]          : %d",PORT_READ(in_SPR_READ_ACK      [0]));
+      }
+    else
+      {
+        internal_READ_QUEUE_OUT_VAL = 0;
+      }
+    PORT_WRITE(out_READ_QUEUE_OUT_VAL, internal_READ_QUEUE_OUT_VAL);
     log_end(Read_queue,FUNCTION);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_genMoore.cpp

-                      r122
+                      r123
     log_function(Read_queue,FUNCTION,_name.c_str());
+    if (PORT_READ(in_NRESET))
+      {
     bool not_full  = _queue->size() < _param->_size_queue;
     bool not_empty = not _queue->empty();
 …
     PORT_WRITE (out_SPR_READ_OOO_ENGINE_ID [0],               _queue_head->_ooo_engine_id);
     PORT_WRITE (out_SPR_READ_NUM_REG       [0],               _queue_head->_num_reg_rc);
+      }
+    else
+      {
+        // Reset
+    PORT_WRITE (out_READ_QUEUE_IN_ACK , 0);
+    PORT_WRITE (out_GPR_READ_VAL   [0], 0);
+    PORT_WRITE (out_GPR_READ_VAL   [1], 0);
+    PORT_WRITE (out_SPR_READ_VAL   [0], 0);
+      }
     log_end(Read_queue,FUNCTION);
   };

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_transition.cpp

-                      r122
+                      r123
         // Init, else error in registerfile
         _queue_head->_ooo_engine_id = 0;
+        // not necessary
+        _queue_head->_read_ra_val = false;
+        _queue_head->_read_rb_val = false;
+        _queue_head->_read_rc_val = false;
+        _queue_head->_data_ra_val = false;
+        _queue_head->_data_rb_val = false;
+        _queue_head->_data_rc_val = false;
+        _queue_head->_num_reg_ra  = 0;
+        _queue_head->_num_reg_rb  = 0;
+        _queue_head->_num_reg_rc  = 0;
+      }
     else

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/src/Reservation_station.cpp

-                      r88
+                      r123
     log_printf(FUNC,Reservation_station,FUNCTION,"Begin");
 #if DEBUG_Reservation_station == true
     log_printf(INFO,Reservation_station,FUNCTION,_("<%s> Parameters"),_name.c_str());
+// #if DEBUG_Reservation_station == true
+//     log_printf(INFO,Reservation_station,FUNCTION,_("<%s> Parameters"),_name.c_str());
     std::cout << *param << std::endl;
 #endif
+//     std::cout << *param << std::endl;
+// #endif
 #ifdef SYSTEMC

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/src/Reservation_station_genMoore.cpp

-                      r122
+                      r123
     log_function(Reservation_station,FUNCTION,_name.c_str());
+    if (PORT_READ(in_NRESET))
+      {
     // ~~~~~[ Interface "insert" ]~~~~~~~~~~~~~~~~~~~~~~~~
 …
     internal_INSERT_ACK = not _queue_control->full();
 #endif
-    PORT_WRITE(out_INSERT_ACK, internal_INSERT_ACK);
     // ~~~~~[ Interface "retire" ]~~~~~~~~~~~~~~~~~~~~~~~
 …
         internal_RETIRE_VAL [i] = val;
-        PORT_WRITE(out_RETIRE_VAL [i], val);
         if (val)
 …
+          }
+      }
+      }
+    else
+      {
+        // Reset
+        internal_INSERT_ACK = 0;
+        // internal_INSERT_SLOT
+        for (uint32_t i=0; i<_param->_nb_inst_retire; i++)
+          {
+            internal_RETIRE_VAL [i] = 0;
+            // internal_RETIRE_SLOT [i];
+          }
+      }
+    // Write Output
+    PORT_WRITE(out_INSERT_ACK    , internal_INSERT_ACK);
+    for (uint32_t i=0; i<_param->_nb_inst_retire; i++)
+    PORT_WRITE(out_RETIRE_VAL [i], internal_RETIRE_VAL [i]);
     log_end(Reservation_station,FUNCTION);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/src/Read_unit.cpp

-                      r88
+                      r123
     log_printf(FUNC,Read_unit,FUNCTION,"Begin");
 #if DEBUG_Read_unit == true
     log_printf(INFO,Read_unit,FUNCTION,_("<%s> Parameters"),_name.c_str());
+// #if DEBUG_Read_unit == true
+//     log_printf(INFO,Read_unit,FUNCTION,_("<%s> Parameters"),_name.c_str());
     std::cout << *param << std::endl;
 #endif
+//     std::cout << *param << std::endl;
+// #endif
     log_printf(INFO,Read_unit,FUNCTION,"Allocation");

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/src/Execute_queue_genMoore.cpp

-                      r101
+                      r123
     log_function(Execute_queue,FUNCTION,_name.c_str());
+    if (PORT_READ(in_NRESET))
+      {
     // -----[ Interface "execute_queue_in" ]--------------------------------
+    {
       internal_EXECUTE_QUEUE_IN_ACK = _queue->size() < _param->_size_queue;
-      PORT_WRITE(out_EXECUTE_QUEUE_IN_ACK, internal_EXECUTE_QUEUE_IN_ACK);
+    }
     // -----[ Interface "execute_queue_out" ]--------------------------------
+    {
-      // TODO : make a genMealy version
       internal_EXECUTE_QUEUE_OUT_VAL = (not _queue->empty());
-      PORT_WRITE(out_EXECUTE_QUEUE_OUT_VAL, internal_EXECUTE_QUEUE_OUT_VAL);
       if (internal_EXECUTE_QUEUE_OUT_VAL)
+        {
 …
+        }
+    }
+      }
+    else
+      {
+        // Reset
+      internal_EXECUTE_QUEUE_IN_ACK  = 0;
+      internal_EXECUTE_QUEUE_OUT_VAL = 0;
+      }
+    // Write output
+    PORT_WRITE(out_EXECUTE_QUEUE_IN_ACK , internal_EXECUTE_QUEUE_IN_ACK);
+    PORT_WRITE(out_EXECUTE_QUEUE_OUT_VAL, internal_EXECUTE_QUEUE_OUT_VAL);
     log_end(Execute_queue,FUNCTION);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue_genMealy_bypass.cpp

-                      r118
+                      r123
     log_function(Write_queue,FUNCTION,_name.c_str());
+    if (PORT_READ(in_NRESET))
+      {
     Tcontrol_t val = PORT_READ(in_WRITE_QUEUE_IN_VAL);
 …
     PORT_WRITE(out_BYPASS_WRITE_SPR_NUM_REG   [0], PORT_READ(in_WRITE_QUEUE_IN_NUM_REG_RE   )); // RE
     PORT_WRITE(out_BYPASS_WRITE_SPR_DATA      [0], PORT_READ(in_WRITE_QUEUE_IN_DATA_RE      ));
+    // -----[ Interface "bypass_write" ]----------------------------------
+      }
+    else
+      {
+    PORT_WRITE(out_BYPASS_WRITE_GPR_VAL       [0], 0);
+    PORT_WRITE(out_BYPASS_WRITE_SPR_VAL       [0], 0);
+      }
     log_end(Write_queue,FUNCTION);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue_genMealy_write.cpp

-                      r118
+                      r123
     log_function(Write_queue,FUNCTION,_name.c_str());
+    if (PORT_READ(in_NRESET))
+      {
     // -----[ Interface "bypass_write" ]----------------------------------
     // in genMoore
 …
+        }
+    }
+      }
+    else
+      {
+        internal_WRITE_QUEUE_OUT_VAL = 0;
+      }
+    PORT_WRITE(out_WRITE_QUEUE_OUT_VAL, internal_WRITE_QUEUE_OUT_VAL);
     log_end(Write_queue,FUNCTION);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue_genMoore.cpp

-                      r118
+                      r123
     log_function(Write_queue,FUNCTION,_name.c_str());
+    if (PORT_READ(in_NRESET))
+      {
     // -----[ Interface "bypass_write" ]----------------------------------
+    {
 …
+    {
       internal_WRITE_QUEUE_IN_ACK = _queue->size() < _param->_size_queue;
-      PORT_WRITE(out_WRITE_QUEUE_IN_ACK, internal_WRITE_QUEUE_IN_ACK);
+    }
 …
       internal_SPR_WRITE_VAL = val and _queue->front()->_write_re;
-      PORT_WRITE(out_GPR_WRITE_VAL [0], internal_GPR_WRITE_VAL);
-      PORT_WRITE(out_SPR_WRITE_VAL [0], internal_SPR_WRITE_VAL);
       if (val)
+        {
 …
                                       );
-      PORT_WRITE(out_WRITE_QUEUE_OUT_VAL, internal_WRITE_QUEUE_OUT_VAL);
       if (internal_WRITE_QUEUE_OUT_VAL)
+        {
 …
       } // end WRITE_QUEUE_SCHEME_MOORE
+      }
+    else
+      {
+        // Reset
+        internal_WRITE_QUEUE_IN_ACK  = 0;
+        internal_WRITE_QUEUE_OUT_VAL = 0;
+        internal_GPR_WRITE_VAL = 0;
+        internal_SPR_WRITE_VAL = 0;
+      }
+    // Write output
+    PORT_WRITE(out_WRITE_QUEUE_IN_ACK , internal_WRITE_QUEUE_IN_ACK);
+    PORT_WRITE(out_WRITE_QUEUE_OUT_VAL, internal_WRITE_QUEUE_OUT_VAL);
+    PORT_WRITE(out_GPR_WRITE_VAL [0]  , internal_GPR_WRITE_VAL);
+    PORT_WRITE(out_SPR_WRITE_VAL [0]  , internal_SPR_WRITE_VAL);
     log_end(Write_queue,FUNCTION);
   };

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/src/Execution_unit_to_Write_unit.cpp

-                      r88
+                      r123
     log_printf(FUNC,Execution_unit_to_Write_unit,FUNCTION,"Begin");
 #if DEBUG_Execution_unit_to_Write_unit == true
     log_printf(INFO,Execution_unit_to_Write_unit,FUNCTION,_("<%s> Parameters"),_name.c_str());
     std::cout << *param << std::endl;
 #endif
+// #if DEBUG_Execution_unit_to_Write_unit == true
+//     log_printf(INFO,Execution_unit_to_Write_unit,FUNCTION,_("<%s> Parameters"),_name.c_str());
+//     std::cout << *param << std::endl;
+// #endif
     log_printf(INFO,Execution_unit_to_Write_unit,FUNCTION,"Allocation");

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/src/Execution_unit_to_Write_unit_genMealy.cpp

-                      r97
+                      r123
     log_printf(FUNC,Execution_unit_to_Write_unit,FUNCTION,"Begin");
+    if (PORT_READ(in_NRESET))
+      {
     bool write_unit_use [_param->_nb_write_unit];
 …
         PORT_WRITE(out_WRITE_UNIT_IN_VAL[i], write_unit_use[i]);
+      }
+      }
+    else
+      {
+        for (uint32_t i=0; i<_param->_nb_execute_unit; i++)
+          for (uint32_t j=0; j<_param->_nb_execute_unit_port[i]; j++)
+            PORT_WRITE(out_EXECUTE_UNIT_OUT_ACK [i][j], 0);
+        for (uint32_t i=0; i<_param->_nb_write_unit; i++)
+          PORT_WRITE(out_WRITE_UNIT_IN_VAL[i], 0);
+      }
     log_printf(FUNC,Execution_unit_to_Write_unit,FUNCTION,"End");

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/src/Read_unit_to_Execution_unit.cpp

-                      r88
+                      r123
     log_printf(FUNC,Read_unit_to_Execution_unit,FUNCTION,"Begin");
 #if DEBUG_Read_unit_to_Execution_unit == true
     log_printf(INFO,Read_unit_to_Execution_unit,FUNCTION,_("<%s> Parameters"),_name.c_str());
     std::cout << *param << std::endl;
 #endif
+// #if DEBUG_Read_unit_to_Execution_unit == true
+//     log_printf(INFO,Read_unit_to_Execution_unit,FUNCTION,_("<%s> Parameters"),_name.c_str());
+//     std::cout << *param << std::endl;
+// #endif
     log_printf(INFO,Read_unit_to_Execution_unit,FUNCTION,"Allocation");

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/src/Read_unit_to_Execution_unit_genMealy.cpp

-                      r122
+                      r123
     log_function(Read_unit_to_Execution_unit,FUNCTION,_name.c_str());
+    if (PORT_READ(in_NRESET))
+      {
     bool execute_unit_use [_param->_nb_execute_unit][_param->_max_nb_execute_unit_port];
 …
       for (uint32_t j=0; j<_param->_nb_execute_unit_port[i]; j++)
         PORT_WRITE(out_EXECUTE_UNIT_IN_VAL[i][j], execute_unit_use[i][j]);
+      }
+    else
+      {
+        for (uint32_t i=0; i<_param->_nb_read_unit; i++)
+          for (uint32_t j=0; j<_param->_nb_read_unit_port[i]; j++)
+            PORT_WRITE(out_READ_UNIT_OUT_ACK [i][j], 0);
+        for (uint32_t i=0; i<_param->_nb_execute_unit; i++)
+          for (uint32_t j=0; j<_param->_nb_execute_unit_port[i]; j++)
+            PORT_WRITE(out_EXECUTE_UNIT_IN_VAL[i][j], 0);
+      }
     log_end(Read_unit_to_Execution_unit,FUNCTION);
   };

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue.cpp

-                      r88
+                      r123
     log_printf(FUNC,Register_unit_Glue,FUNCTION,"Begin");
 #if DEBUG_Register_unit_Glue == true
     log_printf(INFO,Register_unit_Glue,FUNCTION,_("<%s> Parameters"),_name.c_str());
     std::cout << *param << std::endl;
 #endif
+// #if DEBUG_Register_unit_Glue == true
+//     log_printf(INFO,Register_unit_Glue,FUNCTION,_("<%s> Parameters"),_name.c_str());
+//     std::cout << *param << std::endl;
+// #endif
     log_printf(INFO,Register_unit_Glue,FUNCTION,"Allocation");

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_genMealy_gpr_read.cpp

-                      r88
+                      r123
     log_function(Register_unit_Glue,FUNCTION,_name.c_str());
+//     if (not PORT_READ(in_NRESET))
+//       {
+//      for (uint32_t j=0; j<_param->_nb_gpr_read; j++)
+//        PORT_WRITE(out_GPR_READ_ACK      [j], 0);
+//       }
+//     else
+    if (PORT_READ(in_NRESET))
+      {
         for (uint32_t j=0; j<_param->_nb_gpr_read; j++)
 …
             PORT_WRITE(out_GPR_READ_DATA_VAL [j], PORT_READ(in_GPR_READ_STATUS_DATA_VAL  [ooo_engine_id][j]));
+          }
+      }
+    else
+      {
+        for (uint32_t j=0; j<_param->_nb_gpr_read; j++)
+          PORT_WRITE(out_GPR_READ_ACK      [j], 0);
+      }

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_genMealy_gpr_read_registerfile.cpp

-                      r88
+                      r123
     log_function(Register_unit_Glue,FUNCTION,_name.c_str());
+//     if (not PORT_READ(in_NRESET))
+//       {
+//      for (uint32_t j=0; j<_param->_nb_gpr_read; j++)
+//        for (uint32_t i=0; i<_param->_nb_ooo_engine; i++)
+//          PORT_WRITE(out_GPR_READ_REGISTERFILE_VAL [i][j],0);
+//       }
+//     else
+    if (PORT_READ(in_NRESET))
+      {
         for (uint32_t j=0; j<_param->_nb_gpr_read; j++)
 …
+          }
+      }
+    else
+      {
+        for (uint32_t j=0; j<_param->_nb_gpr_read; j++)
+          for (uint32_t i=0; i<_param->_nb_ooo_engine; i++)
+            PORT_WRITE(out_GPR_READ_REGISTERFILE_VAL [i][j],0);
+      }
     log_end(Register_unit_Glue,FUNCTION);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_genMealy_gpr_read_status.cpp

-                      r88
+                      r123
     log_function(Register_unit_Glue,FUNCTION,_name.c_str());
+//     if (not PORT_READ(in_NRESET))
+//       {
+//      for (uint32_t j=0; j<_param->_nb_gpr_read; j++)
+//        for (uint32_t i=0; i<_param->_nb_ooo_engine; i++)
+//          PORT_WRITE(out_GPR_READ_STATUS_VAL       [i][j], 0);
+//       }
+//     else
+    if (PORT_READ(in_NRESET))
+      {
         for (uint32_t j=0; j<_param->_nb_gpr_read; j++)
 …
+          }
+      }
+    else
+      {
+        for (uint32_t j=0; j<_param->_nb_gpr_read; j++)
+          for (uint32_t i=0; i<_param->_nb_ooo_engine; i++)
+            PORT_WRITE(out_GPR_READ_STATUS_VAL       [i][j], 0);
+      }
     log_end(Register_unit_Glue,FUNCTION);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_genMealy_gpr_registerfile.cpp

-                      r88
+                      r123
     log_function(Register_unit_Glue,FUNCTION,_name.c_str());
+//     if (not PORT_READ(in_NRESET))
+//       {
+//      for (uint32_t j=0; j<_param->_nb_gpr_write; j++)
+//        for (uint32_t i=0; i<_param->_nb_ooo_engine; i++)
+//          PORT_WRITE(out_GPR_WRITE_REGISTERFILE_VAL [i][j], 0);
+//       }
+//     else
+    if (PORT_READ(in_NRESET))
+      {
         for (uint32_t j=0; j<_param->_nb_gpr_write; j++)
 …
+          }
+      }
+    else
+      {
+        for (uint32_t j=0; j<_param->_nb_gpr_write; j++)
+          for (uint32_t i=0; i<_param->_nb_ooo_engine; i++)
+            PORT_WRITE(out_GPR_WRITE_REGISTERFILE_VAL [i][j], 0);
+      }
     log_end(Register_unit_Glue,FUNCTION);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_genMealy_gpr_write.cpp

-                      r88
+                      r123
     log_begin(Register_unit_Glue,FUNCTION);
     log_function(Register_unit_Glue,FUNCTION,_name.c_str());
+//     if (not PORT_READ(in_NRESET))
+//       {
+//      for (uint32_t j=0; j<_param->_nb_gpr_write; j++)
+//        for (uint32_t i=0; i<_param->_nb_ooo_engine; i++)
+//          PORT_WRITE(out_GPR_WRITE_ACK [j], 0);
+//       }
+//     else
+    if (PORT_READ(in_NRESET))
+      {
         for (uint32_t j=0; j<_param->_nb_gpr_write; j++)
 …
             PORT_WRITE(out_GPR_WRITE_ACK [j],registerfile_ack and status_ack);
+          }
+      }
+    else
+      {
+        for (uint32_t j=0; j<_param->_nb_gpr_write; j++)
+          for (uint32_t i=0; i<_param->_nb_ooo_engine; i++)
+            PORT_WRITE(out_GPR_WRITE_ACK [j], 0);
+      }

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_genMealy_gpr_write_status.cpp

-                      r88
+                      r123
     log_function(Register_unit_Glue,FUNCTION,_name.c_str());
+//     if (not PORT_READ(in_NRESET))
+//       {
+//      for (uint32_t j=0; j<_param->_nb_gpr_write; j++)
+//        for (uint32_t i=0; i<_param->_nb_ooo_engine; i++)
+//          PORT_WRITE(out_GPR_WRITE_STATUS_VAL       [i][j], 0);
+//       }
+//     else
+    if (PORT_READ(in_NRESET))
+      {
         for (uint32_t j=0; j<_param->_nb_gpr_write; j++)
 …
+          }
+      }
+    else
+      {
+        for (uint32_t j=0; j<_param->_nb_gpr_write; j++)
+          for (uint32_t i=0; i<_param->_nb_ooo_engine; i++)
+            PORT_WRITE(out_GPR_WRITE_STATUS_VAL       [i][j], 0);
+      }
     log_end(Register_unit_Glue,FUNCTION);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_genMealy_insert.cpp

-                      r88
+                      r123
     log_function(Register_unit_Glue,FUNCTION,_name.c_str());
+    if (PORT_READ(in_NRESET))
+      {
     for (uint32_t i=0; i<_param->_nb_ooo_engine; i++)
       for (uint32_t j=0; j<_param->_nb_inst_insert_rob [i]; j++)
 …
+        }
+      }
+    else
+      {
+        for (uint32_t i=0; i<_param->_nb_ooo_engine; i++)
+          for (uint32_t j=0; j<_param->_nb_inst_insert_rob [i]; j++)
+            {
+              PORT_WRITE(out_INSERT_ROB_ACK            [i][j], 0);
+              PORT_WRITE(out_INSERT_ROB_GPR_STATUS_VAL [i][j], 0);
+              PORT_WRITE(out_INSERT_ROB_SPR_STATUS_VAL [i][j], 0);
+            }
+      }
     log_end(Register_unit_Glue,FUNCTION);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_genMealy_retire.cpp

r88	r123
27	27	log_function(Register_unit_Glue,FUNCTION,_name.c_str());
28	28
	29	if (PORT_READ(in_NRESET))
	30	{
29	31	for (uint32_t i=0; i<_param->_nb_ooo_engine; i++)
30	32	{
…	…
58	60	}
59	61	}
60
	62	}
61	63	log_end(Register_unit_Glue,FUNCTION);
62	64	};

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_genMealy_spr_read.cpp

-                      r88
+                      r123
     log_function(Register_unit_Glue,FUNCTION,_name.c_str());
+//     if (not PORT_READ(in_NRESET))
+//       {
+//      for (uint32_t j=0; j<_param->_nb_spr_read; j++)
+//        PORT_WRITE(out_SPR_READ_ACK      [j], 0);
+//       }
+//     else
+    if (PORT_READ(in_NRESET))
+      {
         for (uint32_t j=0; j<_param->_nb_spr_read; j++)
 …
             PORT_WRITE(out_SPR_READ_DATA_VAL [j], PORT_READ(in_SPR_READ_STATUS_DATA_VAL  [ooo_engine_id][j]));
+          }
+      }
+    else
+      {
+        for (uint32_t j=0; j<_param->_nb_spr_read; j++)
+          PORT_WRITE(out_SPR_READ_ACK      [j], 0);
+      }

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_genMealy_spr_read_registerfile.cpp

-                      r88
+                      r123
     log_function(Register_unit_Glue,FUNCTION,_name.c_str());
+//     if (not PORT_READ(in_NRESET))
+//       {
+//      for (uint32_t j=0; j<_param->_nb_spr_read; j++)
+//        for (uint32_t i=0; i<_param->_nb_ooo_engine; i++)
+//          PORT_WRITE(out_SPR_READ_REGISTERFILE_VAL [i][j],0);
+//       }
+//     else
+    if (PORT_READ(in_NRESET))
+      {
         for (uint32_t j=0; j<_param->_nb_spr_read; j++)
 …
+          }
+      }
+    else
+      {
+        for (uint32_t j=0; j<_param->_nb_spr_read; j++)
+          for (uint32_t i=0; i<_param->_nb_ooo_engine; i++)
+            PORT_WRITE(out_SPR_READ_REGISTERFILE_VAL [i][j],0);
+      }
     log_end(Register_unit_Glue,FUNCTION);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_genMealy_spr_read_status.cpp

-                      r88
+                      r123
     log_function(Register_unit_Glue,FUNCTION,_name.c_str());
+//     if (not PORT_READ(in_NRESET))
+//       {
+//      for (uint32_t j=0; j<_param->_nb_spr_read; j++)
+//        for (uint32_t i=0; i<_param->_nb_ooo_engine; i++)
+//          PORT_WRITE(out_SPR_READ_STATUS_VAL       [i][j], 0);
+//       }
+//     else
+    if (PORT_READ(in_NRESET))
+      {
         for (uint32_t j=0; j<_param->_nb_spr_read; j++)
 …
+          }
+      }
+    else
+      {
+        for (uint32_t j=0; j<_param->_nb_spr_read; j++)
+          for (uint32_t i=0; i<_param->_nb_ooo_engine; i++)
+            PORT_WRITE(out_SPR_READ_STATUS_VAL       [i][j], 0);
+      }
     log_end(Register_unit_Glue,FUNCTION);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_genMealy_spr_registerfile.cpp

-                      r88
+                      r123
     log_function(Register_unit_Glue,FUNCTION,_name.c_str());
+//     if (not PORT_READ(in_NRESET))
+//       {
+//      for (uint32_t j=0; j<_param->_nb_spr_write; j++)
+//        for (uint32_t i=0; i<_param->_nb_ooo_engine; i++)
+//          PORT_WRITE(out_SPR_WRITE_REGISTERFILE_VAL [i][j], 0);
+//       }
+//     else
+    if (PORT_READ(in_NRESET))
+      {
         for (uint32_t j=0; j<_param->_nb_spr_write; j++)
 …
+          }
+      }
+    else
+      {
+        for (uint32_t j=0; j<_param->_nb_spr_write; j++)
+          for (uint32_t i=0; i<_param->_nb_ooo_engine; i++)
+            PORT_WRITE(out_SPR_WRITE_REGISTERFILE_VAL [i][j], 0);
+      }
     log_end(Register_unit_Glue,FUNCTION);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_genMealy_spr_write.cpp

-                      r88
+                      r123
     log_function(Register_unit_Glue,FUNCTION,_name.c_str());
+//     if (not PORT_READ(in_NRESET))
+//       {
+//      for (uint32_t j=0; j<_param->_nb_spr_write; j++)
+//        for (uint32_t i=0; i<_param->_nb_ooo_engine; i++)
+//          PORT_WRITE(out_SPR_WRITE_ACK [j], 0);
+//       }
+//     else
+    if (PORT_READ(in_NRESET))
+      {
         for (uint32_t j=0; j<_param->_nb_spr_write; j++)
 …
             PORT_WRITE(out_SPR_WRITE_ACK [j],registerfile_ack and status_ack);
+          }
+      }
+    else
+      {
+        for (uint32_t j=0; j<_param->_nb_spr_write; j++)
+          for (uint32_t i=0; i<_param->_nb_ooo_engine; i++)
+            PORT_WRITE(out_SPR_WRITE_ACK [j], 0);
+      }

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_genMealy_spr_write_status.cpp

-                      r88
+                      r123
     log_function(Register_unit_Glue,FUNCTION,_name.c_str());
+//     if (not PORT_READ(in_NRESET))
+//       {
+//      for (uint32_t j=0; j<_param->_nb_spr_write; j++)
+//        for (uint32_t i=0; i<_param->_nb_ooo_engine; i++)
+//          PORT_WRITE(out_SPR_WRITE_STATUS_VAL       [i][j], 0);
+//       }
+//     else
+    if (PORT_READ(in_NRESET))
+      {
         for (uint32_t j=0; j<_param->_nb_spr_write; j++)
 …
+          }
+      }
+    else
+      {
+        for (uint32_t j=0; j<_param->_nb_spr_write; j++)
+          for (uint32_t i=0; i<_param->_nb_ooo_engine; i++)
+            PORT_WRITE(out_SPR_WRITE_STATUS_VAL       [i][j], 0);
+      }
     log_end(Register_unit_Glue,FUNCTION);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/src/Register_unit.cpp

-                      r88
+                      r123
     log_printf(FUNC,Register_unit,FUNCTION,"Begin");
 #if DEBUG_Register_unit == true
     log_printf(INFO,Register_unit,FUNCTION,_("<%s> Parameters"),_name.c_str());
+// #if DEBUG_Register_unit == true
+//     log_printf(INFO,Register_unit,FUNCTION,_("<%s> Parameters"),_name.c_str());
     std::cout << *param << std::endl;
 #endif
+//     std::cout << *param << std::endl;
+// #endif
     log_printf(INFO,Register_unit,FUNCTION,"Allocation");

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/src/Execute_loop.cpp

-                      r88
+                      r123
     log_printf(FUNC,Execute_loop,FUNCTION,"Begin");
 #if DEBUG_Execute_loop == true
     log_printf(INFO,Execute_loop,FUNCTION,_("<%s> Parameters"),_name.c_str());
+// #if DEBUG_Execute_loop == true
+//     log_printf(INFO,Execute_loop,FUNCTION,_("<%s> Parameters"),_name.c_str());
     std::cout << *param << std::endl;
 #endif
+//     std::cout << *param << std::endl;
+// #endif
     log_printf(INFO,Execute_loop,FUNCTION,"Allocation");

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/src/Parameters_msg_error.cpp

-                      r88
+                      r123
 #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/include/Parameters.h"
 #include <sstream>
+#include <set>
 namespace morpheo                    {
 …
         test.error(toString(_("Functionnal_unit [%d] must treat once instruction.\n"),i));
+    std::set<uint32_t> link_load_store_unit_and_write_unit [_nb_load_store_unit];
+    for (uint32_t i=0; i<_nb_load_store_unit; ++i)
+      link_load_store_unit_and_write_unit[i].clear();
+    for (uint32_t i=0; i<_nb_execute_unit; i++)
+      if (_is_load_store_unit [i])
+        {
+          uint32_t lsq = _translate_num_execute_unit[i];
+          for (uint32_t j=0; j<_nb_execute_unit_port[i]; j++)
+            for (uint32_t k=0; k<_nb_write_unit; k++)
+              if (_execution_unit_to_write_unit_table_routing [i][j][k])
+                {
+                  if (link_load_store_unit_and_write_unit[lsq].find(k) != link_load_store_unit_and_write_unit[lsq].end())
+                    {
+                      if (link_load_store_unit_and_write_unit[lsq].size() != 0)
+                        test.error(toString(_("Can't connect Load Store Unit [%d] (port %d) with Write unit [%d], because it's already connected with Write unit [%d]"),lsq,j,k,*(link_load_store_unit_and_write_unit[lsq].begin())));
+                      link_load_store_unit_and_write_unit[lsq].insert(link_load_store_unit_and_write_unit[lsq].end(),k);
+                    }
+                }
+        }
     log_printf(FUNC,Execute_loop,FUNCTION,"End");

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Context_State.h

-                      r120
+                      r123
     // ~~~~~[ Interface : "context" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   public    : SC_OUT(Tcontrol_t         )  ** out_CONTEXT_DECOD_ENABLE               ;//[nb_context]
+  public    : SC_OUT(Tcontrol_t         )  ** out_CONTEXT_EVENT                      ;//[nb_context]
     // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 …
   public  : void        genMoore                  (void);
   public  : void        genMealy_decod_event      (void);
+  public  : void        genMealy_context_event    (void);
 #endif

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State.cpp

-                      r101
+                      r123
     usage_environment(_usage);
 #if DEBUG_Context_State == true
     log_printf(INFO,Context_State,FUNCTION,_("<%s> Parameters"),_name.c_str());
+// #if DEBUG_Context_State == true
+//     log_printf(INFO,Context_State,FUNCTION,_("<%s> Parameters"),_name.c_str());
     std::cout << *param << std::endl;
 #endif
+//     std::cout << *param << std::endl;
+// #endif
     log_printf(INFO,Context_State,FUNCTION,_("Allocation"));
 …
         // List dependency information
 # endif
+        log_printf(INFO,Context_State,FUNCTION,_("Method - genMealy_context_event"));
+        SC_METHOD (genMealy_context_event);
+        dont_initialize ();
+//      sensitive << (*(in_CLOCK)).neg(); // use internal register
+        sensitive << (*(in_COMMIT_EVENT_VAL             ));
+        if (_param->_have_port_context_id)
+        sensitive << (*(in_COMMIT_EVENT_CONTEXT_ID      ));
+        for (uint32_t i=0; i<_param->_nb_inst_branch_complete; ++i)
+          {
+            sensitive << (*(in_BRANCH_COMPLETE_VAL             [i]))
+                      << (*(in_BRANCH_COMPLETE_MISS_PREDICTION [i]));
+            if (_param->_have_port_context_id)
+            sensitive << (*(in_BRANCH_COMPLETE_CONTEXT_ID      [i]));
+          }
+# ifdef SYSTEMCASS_SPECIFIC
+        // List dependency information
+# endif
 #endif

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_allocation.cpp

r119	r123
172	172
173	173	ALLOC1_SIGNAL_OUT(out_CONTEXT_DECOD_ENABLE ,"decod_enable",Tcontrol_t,1);
	174	ALLOC1_SIGNAL_OUT(out_CONTEXT_EVENT ,"event" ,Tcontrol_t,1);
174	175
175	176	ALLOC1_INTERFACE_END(_param->_nb_context);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_deallocation.cpp

r119	r123
91	91
92	92	DELETE1_SIGNAL(out_CONTEXT_DECOD_ENABLE ,_param->_nb_context,1);
	93	DELETE1_SIGNAL(out_CONTEXT_EVENT ,_param->_nb_context,1);
93	94
94	95	DELETE1_SIGNAL( in_DEPTH_MIN ,_param->_nb_context,_param->_size_depth);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_genMealy_decod_event.cpp

-                      r102
+                      r123
     log_function(Context_State,FUNCTION,_name.c_str());
+    if (PORT_READ(in_NRESET))
+      {
     for (uint32_t i=0; i<_param->_nb_decod_unit; i++)
+      {
 …
         internal_DECOD_EVENT_ACK [i] = ack;
-        PORT_WRITE(out_DECOD_EVENT_ACK [i], internal_DECOD_EVENT_ACK [i]);
+      }
+      }
+    else
+      {
+        for (uint32_t i=0; i<_param->_nb_decod_unit; i++)
+          internal_DECOD_EVENT_ACK [i] = 0;
+      }
+    for (uint32_t i=0; i<_param->_nb_decod_unit; i++)
+      PORT_WRITE(out_DECOD_EVENT_ACK [i], internal_DECOD_EVENT_ACK [i]);
     log_end(Context_State,FUNCTION);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_genMoore.cpp

-                      r119
+                      r123
     log_function(Context_State,FUNCTION,_name.c_str());
+    if (PORT_READ(in_NRESET))
+      {
     // -------------------------------------------------------------------
     // -----[ EVENT ]-----------------------------------------------------
 …
         internal_EVENT_VAL [i] = val;
-        PORT_WRITE(out_EVENT_VAL              [i], val);
         PORT_WRITE(out_EVENT_ADDRESS          [i], address);
         PORT_WRITE(out_EVENT_ADDRESS_NEXT     [i], address_next);
 …
         internal_SPR_EVENT_VAL [i] = (state == CONTEXT_STATE_KO_EXCEP_SPR  );
-        PORT_WRITE(out_SPR_EVENT_VAL       [i], internal_SPR_EVENT_VAL     [i]);
         PORT_WRITE(out_SPR_EVENT_EPCR      [i], reg_EVENT_ADDRESS_EPCR     [i]);
         PORT_WRITE(out_SPR_EVENT_EEAR      [i], reg_EVENT_ADDRESS_EEAR     [i]);
 …
         PORT_WRITE(out_CONTEXT_DECOD_ENABLE [i], (state==CONTEXT_STATE_OK));
+      }
+      }
+    else
+      {
+        for (uint32_t i=0; i<_param->_nb_context; i++)
+          {
+            internal_EVENT_VAL     [i] = 0;
+            internal_SPR_EVENT_VAL [i] = 0;
+            PORT_WRITE(out_CONTEXT_DECOD_ENABLE [i], 0);
+          }
+      }
+    // Write output
+    for (uint32_t i=0; i<_param->_nb_context; i++)
+      {
+        PORT_WRITE(out_EVENT_VAL     [i], internal_EVENT_VAL     [i]);
+        PORT_WRITE(out_SPR_EVENT_VAL [i], internal_SPR_EVENT_VAL [i]);
+      }
     log_end(Context_State,FUNCTION);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_transition.cpp

-                      r122
+                      r123
 namespace context_state {
+#define MISS_FAST
+// #define MANAGE_EVENT MANAGE_EVENT_WAIT_ALL
+// #define MANAGE_EVENT MANAGE_EVENT_WAIT_DECODE
+#define MANAGE_EVENT MANAGE_EVENT_NO_WAIT
 #define get_priority(x) \
   (((state == CONTEXT_STATE_KO_MISS_LOAD_ADDR                  ) or  \
+    (state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND               ) or  \
     (state == CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR       ) or  \
-    (state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND               ) or  \
     (state == CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAITEND    ) or  \
     (state == CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAIT_UPDATE))?3: \
 …
             reg_STATE            [i] = CONTEXT_STATE_OK;
             reg_INTERRUPT_ENABLE [i] = 0;
+            reg_EVENT_DEPTH      [i] = 0; // unacessary
+          }
+      }
 …
             Tcounter_t inst_all        = inst_commit_all + inst_decod_all;
 //          Tcounter_t inst_mem        = inst_commit_mem + inst_decod_all;
+            bool       condition       = ( (MANAGE_EVENT == MANAGE_EVENT_WAIT_ALL   )?(inst_all       == 0):
+                                          ((MANAGE_EVENT == MANAGE_EVENT_WAIT_DECODE)?(inst_decod_all == 0):
+                                            true));
             context_state_t state = reg_STATE [i];
 …
               case CONTEXT_STATE_KO_MISS_BRANCH_WAITEND :
+                {
+                  // Wait end of all instruction
+//                if (inst_all == 0)
+                  if (
+#ifdef  MISS_FAST
+                      inst_decod_all ==
+#else
+                      inst_all ==
+#endif
+)
+                  if (condition)
 //                  state = CONTEXT_STATE_OK;
                     state = CONTEXT_STATE_KO_MISS_BRANCH_ADDR;
 …
+                {
                   // Wait end of all instruction
+//                if (inst_all == 0)
+                  if (
+#ifdef  MISS_FAST
+                      inst_decod_all ==
+#else
+                      inst_all ==
+#endif
+)
+                  if (condition)
                     state = CONTEXT_STATE_KO_MISS_LOAD_ADDR;
 …
+                {
                   // Wait end of all instruction
+//                if (inst_all == 0)
+                  if (
+#ifdef  MISS_FAST
+                      inst_decod_all ==
+#else
+                      inst_all ==
+#endif
+)
+                  if (condition)
 //                  state = CONTEXT_STATE_OK; // @@@ TODO : make MISS fast (miss decod)
                     state = CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR;
 …
 #endif
+              log_printf(TRACE,Context_State,FUNCTION,"    * state     : %s",toString(state).c_str());
               log_printf(TRACE,Context_State,FUNCTION,"    * depth     : %d",depth     );
               log_printf(TRACE,Context_State,FUNCTION,"    * depth_cur : %d",depth_cur );
 …
+                          }
+                        }
+                      depth = (depth+1)%_param->_nb_inst_branch_speculated[context];
                       break;
+                    }

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod.cpp

-                      r101
+                      r123
     log_printf(FUNC,Decod,FUNCTION,"Begin");
 #if DEBUG_Decod == true
     log_printf(INFO,Decod,FUNCTION,_("<%s> Parameters"),_name.c_str());
     std::cout << *param << std::endl;
 #endif
+// #if DEBUG_Decod == true
+//     log_printf(INFO,Decod,FUNCTION,_("<%s> Parameters"),_name.c_str());
+//     std::cout << *param << std::endl;
+// #endif
     log_printf(INFO,Decod,FUNCTION,"Allocation");

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_genMealy.cpp

-                      r120
+                      r123
     log_function(Decod,FUNCTION,_name.c_str());
+    if (PORT_READ(in_NRESET))
+      {
     //-----------------------------------
     // Initialization
 …
 #endif
+      }
+      }
+    else
+      {
+    for (uint32_t i=0; i<_param->_nb_context; i++)
+      {
+        internal_CONTEXT_HAVE_TRANSACTION [i] = false;
+//      internal_CONTEXT_ADDRESS_PREVIOUS [i] = reg_CONTEXT_ADDRESS_PREVIOUS [i];
+//      internal_CONTEXT_IS_DELAY_SLOT    [i] = reg_CONTEXT_IS_DELAY_SLOT    [i];
+      for (uint32_t j=0; j<_param->_nb_inst_fetch[i]; j++)
+        PORT_WRITE(out_IFETCH_ACK [i][j], 0);
+      }
+    PORT_WRITE(out_CONTEXT_EVENT_VAL, 0);
+    for (uint32_t i=0; i<_param->_nb_inst_decod; i++)
+      {
+        PORT_WRITE(out_PREDICT_VAL [i], 0);
+        PORT_WRITE(out_DECOD_VAL   [i], 0);
+#ifdef STATISTICS
+        internal_DECOD_VAL [i] = 0;
+#endif
+      }
+      }
     log_end(Decod,FUNCTION);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/include/Decod_queue.h

-                      r111
+                      r123
   public    : SC_OUT(Toperation_t       )  ** out_DECOD_OUT_OPERATION     ;//[nb_inst_decod]
   public    : SC_OUT(Tcontrol_t         )  ** out_DECOD_OUT_NO_EXECUTE    ;//[nb_inst_decod]
+//public    : SC_OUT(Tcontrol_t         )  ** out_DECOD_OUT_HAVE_EVENT    ;//[nb_inst_decod]
+  public    : SC_OUT(Tcontrol_t         )  ** out_DECOD_OUT_LAST_EVENT    ;//[nb_inst_decod]
   public    : SC_OUT(Tcontrol_t         )  ** out_DECOD_OUT_IS_DELAY_SLOT ;//[nb_inst_decod]
 #ifdef DEBUG
 …
   public    : SC_OUT(Tcounter_t         )  ** out_NB_INST_ALL             ;//[nb_context]
+    // ~~~~~[ Interface : "context" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+  public    : SC_IN (Tcontrol_t         )  **  in_CONTEXT_EVENT           ;//[nb_context]
     // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 …
   private   : std::list<decod_queue_entry_t*> * reg_QUEUE                  ;
   private   : uint32_t                        * reg_NB_INST                ;//[nb_context]
+  private   : uint32_t                        * reg_NB_INST_EVENT          ;//[nb_context]
     // implementation : one_fifo only
   private   : uint32_t                          reg_LAST_SLOT              ;

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue.cpp

-                      r111
+                      r123
     usage_environment(_usage);
 #if DEBUG_Decod_queue == true
     log_printf(INFO,Decod_queue,FUNCTION,_("<%s> Parameters"),_name.c_str());
+// #if DEBUG_Decod_queue == true
+//     log_printf(INFO,Decod_queue,FUNCTION,_("<%s> Parameters"),_name.c_str());
     std::cout << *param << std::endl;
 #endif
+//     std::cout << *param << std::endl;
+// #endif
     log_printf(INFO,Decod_queue,FUNCTION,_("Allocation"));
 …
         for (uint32_t i=0; i<_param->_nb_inst_decod; i++)
           sensitive << (*(in_DECOD_OUT_ACK [i]));
           for (uint32_t i=0; i<_param->_nb_context; i++)
+            {
               if (_param->_have_port_depth)
+                {
               sensitive << (*(in_DEPTH_MIN [i]));
               sensitive << (*(in_DEPTH_MAX [i]));
+                }
               sensitive << (*(in_DEPTH_FULL[i]));
+            }
+//         for (uint32_t i=0; i<_param->_nb_context; i++)
+//           {
+//             if (_param->_have_port_depth)
+//               {
+//                 sensitive << (*(in_DEPTH_MIN [i]));
+//                 sensitive << (*(in_DEPTH_MAX [i]));
+//               }
+//             sensitive << (*(in_DEPTH_FULL[i]));
+//           }
 # ifdef SYSTEMCASS_SPECIFIC
         // List dependency information
         for (uint32_t i=0; i<_param->_nb_inst_decod; i++)
+          {
             (*(out_DECOD_OUT_VAL [i])) (*(in_DECOD_OUT_ACK [i]));
             for (uint32_t j=0; j<_param->_nb_context; j++)
+              {
                 if (_param->_have_port_depth)
+                  {
                 (*(out_DECOD_OUT_VAL [i])) (*(in_DEPTH_MIN [j]));
                 (*(out_DECOD_OUT_VAL [i])) (*(in_DEPTH_MAX [j]));
+                  }
+              }
+          }
+//      // List dependency information
+//      for (uint32_t i=0; i<_param->_nb_inst_decod; i++)
+//        {
+//          (*(out_DECOD_OUT_VAL [i])) (*(in_DECOD_OUT_ACK [i]));
+//             for (uint32_t j=0; j<_param->_nb_context; j++)
+//               {
+//                 if (_param->_have_port_depth)
+//                   {
+//                 (*(out_DECOD_OUT_VAL [i])) (*(in_DEPTH_MIN [j]));
+//                 (*(out_DECOD_OUT_VAL [i])) (*(in_DEPTH_MAX [j]));
+//                   }
+//               }
+//        }
 # endif

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_allocation.cpp

-                      r118
+                      r123
       ALLOC1_SIGNAL_OUT(out_DECOD_OUT_OPERATION      ,"operation"    ,Toperation_t       ,_param->_size_operation             );
       ALLOC1_SIGNAL_OUT(out_DECOD_OUT_NO_EXECUTE     ,"no_execute"   ,Tcontrol_t         ,1                                   );
+//    ALLOC1_SIGNAL_OUT(out_DECOD_OUT_HAVE_EVENT     ,"have_event"   ,Tcontrol_t         ,1                                   );
+      ALLOC1_SIGNAL_OUT(out_DECOD_OUT_LAST_EVENT     ,"last_event"   ,Tcontrol_t         ,1                                   );
       ALLOC1_SIGNAL_OUT(out_DECOD_OUT_IS_DELAY_SLOT  ,"is_delay_slot",Tcontrol_t         ,1                                   );
 #ifdef DEBUG
 …
+    }
+    // ~~~~~[ Interface : "context" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+    {
+      ALLOC1_INTERFACE_BEGIN("context",IN ,NORTH,_("Context"), _param->_nb_context);
+      ALLOC1_SIGNAL_IN ( in_CONTEXT_EVENT  ,"event"    ,Tcontrol_t         ,1);
+      ALLOC1_INTERFACE_END(_param->_nb_context);
+    }
     if (usage_is_set(_usage,USE_SYSTEMC))
+      {
 …
+      }
+    ALLOC1(reg_NB_INST,uint32_t,_param->_nb_context);
+    ALLOC1(reg_NB_INST           ,uint32_t,_param->_nb_context);
+    ALLOC1(reg_NB_INST_EVENT     ,uint32_t,_param->_nb_context);
     // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_deallocation.cpp

-                      r115
+                      r123
         DELETE1_SIGNAL(out_DECOD_OUT_TYPE          ,_param->_nb_inst_decod,_param->_size_type                  );
         DELETE1_SIGNAL(out_DECOD_OUT_OPERATION     ,_param->_nb_inst_decod,_param->_size_operation             );
+        DELETE1_SIGNAL(out_DECOD_OUT_NO_EXECUTE    ,_param->_nb_inst_decod,1                                   );
+        DELETE1_SIGNAL(out_DECOD_OUT_NO_EXECUTE    ,_param->_nb_inst_decod,1                                   );
+//      DELETE1_SIGNAL(out_DECOD_OUT_HAVE_EVENT    ,_param->_nb_inst_decod,1                                   );
+        DELETE1_SIGNAL(out_DECOD_OUT_LAST_EVENT    ,_param->_nb_inst_decod,1                                   );
         DELETE1_SIGNAL(out_DECOD_OUT_IS_DELAY_SLOT ,_param->_nb_inst_decod,1                                   );
 #ifdef DEBUG
 …
         DELETE1_SIGNAL(out_NB_INST_ALL             ,_param->_nb_context,_param->_size_nb_inst_decod);
+        DELETE1_SIGNAL( in_CONTEXT_EVENT           ,_param->_nb_context,1);
         // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 …
+          }
+        DELETE1(reg_NB_INST ,_param->_nb_context);
+        DELETE1(reg_NB_INST           ,_param->_nb_context);
+        DELETE1(reg_NB_INST_EVENT     ,_param->_nb_context);
         // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_function_multi_fifo_genMealy_decod_out.cpp

-                      r115
+                      r123
     log_begin(Decod_queue,FUNCTION);
     log_function(Decod_queue,FUNCTION,_name.c_str());
+    Tcontrol_t val [_param->_nb_inst_decod];
+    if (PORT_READ(in_NRESET))
+      {
+    bool       context_val   [_param->_nb_context];
+    uint32_t   nb_inst_event [_param->_nb_context];
+    for (uint32_t i=0; i<_param->_nb_context; i++)
+      {
+        context_val   [i] = true;
+        nb_inst_event [i] = reg_NB_INST_EVENT [i];
+      }
+    Tcontrol_t val         [_param->_nb_inst_decod];
     for (uint32_t i=0; i<_param->_nb_inst_decod; i++)
+      {
 …
             Tcontext_t context         = reg_QUEUE[num_bank].front()->_context_id    [0];
-            Tdepth_t   depth           = reg_QUEUE[num_bank].front()->_depth         [0];
-            Tdepth_t   depth_min       = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN [context]):0;
-            Tdepth_t   depth_max       = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MAX [context]):0;
-            Tcontrol_t depth_full      = PORT_READ(in_DEPTH_FULL[context]);
+            // is a valid instruction ?
+            // If DEPTH_CURRENT :
+            // equal at     DEPTH_MIN            -> not speculative
+            // not include ]DEPTH_MIN:DEPTH_MAX] -> previous branch miss
+            //     include ]DEPTH_MIN:DEPTH_MAX] -> speculative
+            // All case
+            // ....... min ...X... max ....... OK
+            // ....... min ....... max ...X... KO
+            // ...X... min ....... max ....... KO
+            // ....... max ....... min ...X... OK
+            // ...X... max ....... min ....... OK
+            // ....... max ...X... min ....... KO
+            Tcontrol_t is_valid = true;
+            log_printf(TRACE,Decod_queue,FUNCTION,"      * context      : %d",context);
+//             Tcontrol_t   is_valid      = ((depth == depth_min) or
+//                                           depth_full or
+//                                           ((depth_min <= depth_max)?
+//                                            ((depth >= depth_min) and (depth <=depth_max)):
+//                                            ((depth >= depth_min) or  (depth <=depth_max))));
+            //Tcontrol_t is_valid        = ((depth == depth_min) or
+            //                              ((depth_min < depth_max)?
+            //                               (depth<=depth_max):
+            //                               ((depth > depth_min) or (depth <= depth_max))));
+            //Tcontrol_t is_valid        = depth <= depth_max;
+            log_printf(TRACE,Decod_queue,FUNCTION,"    * is_valid : %d",is_valid);
+            log_printf(TRACE,Decod_queue,FUNCTION,"      * context      : %d",context);
+            log_printf(TRACE,Decod_queue,FUNCTION,"      * depth        : %d",depth);
+            log_printf(TRACE,Decod_queue,FUNCTION,"      * depth_min    : %d",depth_min);
+            log_printf(TRACE,Decod_queue,FUNCTION,"      * depth_max    : %d",depth_max);
+            log_printf(TRACE,Decod_queue,FUNCTION,"      * depth_full   : %d",depth_full);
+#ifdef DEBUG
+            log_printf(TRACE,Decod_queue,FUNCTION,"      * address      : 0x%x (0x%x)",reg_QUEUE[num_bank].front()->_address     [0],reg_QUEUE[num_bank].front()->_address     [0]<<2);
+#endif
+            log_printf(TRACE,Decod_queue,FUNCTION,"      * address_next : 0x%x (0x%x)",reg_QUEUE[num_bank].front()->_address_next[0],reg_QUEUE[num_bank].front()->_address_next[0]<<2);
+            if (context_val [context])
+              {
+            internal_DECOD_OUT_VAL [i] = 1; // in all case, val is set (entry is not empty, and instruction is valid)
+            if (is_valid)
+              {
+                val                    [i] = 1;
+                internal_DECOD_OUT_ACK [i] = PORT_READ(in_DECOD_OUT_ACK [i]);
+              }
+            else
+              {
+                // Consume the instruction (to erase)
+                internal_DECOD_OUT_ACK [i] = 1;
+//                 Tdepth_t   depth           = reg_QUEUE[num_bank].front()->_depth         [0];
+//                 Tdepth_t   depth_min       = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN [context]):0;
+//                 Tdepth_t   depth_max       = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MAX [context]):0;
+//                 Tcontrol_t depth_full      = PORT_READ(in_DEPTH_FULL[context]);
+                    // is a valid instruction ?
+                // If DEPTH_CURRENT :
+                // equal at     DEPTH_MIN            -> not speculative
+                // not include ]DEPTH_MIN:DEPTH_MAX] -> previous branch miss
+                //     include ]DEPTH_MIN:DEPTH_MAX] -> speculative
+                // All case
+                // ....... min ...X... max ....... OK
+                // ....... min ....... max ...X... KO
+                // ...X... min ....... max ....... KO
+                // ....... max ....... min ...X... OK
+                // ...X... max ....... min ....... OK
+                // ....... max ...X... min ....... KO
+                Tcontrol_t is_valid = (nb_inst_event [context] == 0);
+//                 Tcontrol_t   is_valid      = ((depth == depth_min) or
+//                                               depth_full or
+//                                               ((depth_min <= depth_max)?
+//                                                ((depth >= depth_min) and (depth <=depth_max)):
+//                                                ((depth >= depth_min) or  (depth <=depth_max))));
+                log_printf(TRACE,Decod_queue,FUNCTION,"    * is_valid : %d",is_valid);
+                log_printf(TRACE,Decod_queue,FUNCTION,"      * context_val  : %d",context_val   [context]);
+                log_printf(TRACE,Decod_queue,FUNCTION,"      * nb_inst_event: %d",nb_inst_event [context]);
+//              log_printf(TRACE,Decod_queue,FUNCTION,"      * depth        : %d",depth);
+//              log_printf(TRACE,Decod_queue,FUNCTION,"      * depth_min    : %d",depth_min);
+//              log_printf(TRACE,Decod_queue,FUNCTION,"      * depth_max    : %d",depth_max);
+//              log_printf(TRACE,Decod_queue,FUNCTION,"      * depth_full   : %d",depth_full);
+#ifdef DEBUG
+                log_printf(TRACE,Decod_queue,FUNCTION,"      * address      : 0x%x (0x%x)",reg_QUEUE[num_bank].front()->_address     [0],reg_QUEUE[num_bank].front()->_address     [0]<<2);
+#endif
+                log_printf(TRACE,Decod_queue,FUNCTION,"      * address_next : 0x%x (0x%x)",reg_QUEUE[num_bank].front()->_address_next[0],reg_QUEUE[num_bank].front()->_address_next[0]<<2);
+                internal_DECOD_OUT_VAL [i] = 1; // in all case, val is set (entry is not empty, and instruction is valid)
+                if (is_valid)
+                  {
+                    val                    [i] = 1;
+                    internal_DECOD_OUT_ACK [i] = PORT_READ(in_DECOD_OUT_ACK [i]);
+                  }
+                else
+                  {
+                    // Consume the instruction (to erase)
+                    internal_DECOD_OUT_ACK [i] = 1;
+                    // Have event ?
+                    if (nb_inst_event [context] > 0)
+                      {
+                        nb_inst_event [context] --;
+                        // Last event ?
+                        if (nb_inst_event [context] == 0)
+                          {
+                            context_val [context] = false;
+                          }
+                      }
+                  }
+              }
+          }
 …
         PORT_WRITE(out_DECOD_OUT_VAL [i],val [i]);
+      }
+      }
+    else
+      {
+        // Reset
+        for (uint32_t i=0; i<_param->_nb_inst_decod; i++)
+          {
+            internal_DECOD_OUT_VAL [i] = 0;
+            internal_DECOD_OUT_ACK [i] = 0;
+            PORT_WRITE(out_DECOD_OUT_VAL [i],0);
+          }
+      }

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_function_multi_fifo_genMoore.cpp

-                      r111
+                      r123
     log_function(Decod_queue,FUNCTION,_name.c_str());
+    if (PORT_READ(in_NRESET))
+      {
     //--------------------------------------------------------------------
     //-----[ DECOD_IN ]---------------------------------------------------
 …
+        {
           internal_DECOD_IN_ACK [i] = (reg_QUEUE[num_bank].size() < _param->_size_queue);
-          PORT_WRITE(out_DECOD_IN_ACK [i],internal_DECOD_IN_ACK [i]);
           num_bank = (num_bank+1)%_param->_nb_bank;
 …
                 PORT_WRITE(out_DECOD_OUT_OPERATION     [i],reg_QUEUE[num_bank].front()->_operation     [0]);
                 PORT_WRITE(out_DECOD_OUT_NO_EXECUTE    [i],reg_QUEUE[num_bank].front()->_no_execute    [0]);
+//              PORT_WRITE(out_DECOD_OUT_HAVE_EVENT    [i],0);
+                PORT_WRITE(out_DECOD_OUT_LAST_EVENT    [i],0);
                 PORT_WRITE(out_DECOD_OUT_IS_DELAY_SLOT [i],reg_QUEUE[num_bank].front()->_is_delay_slot [0]);
 #ifdef DEBUG
 …
     for (uint32_t i=0; i<_param->_nb_context; i++)
       PORT_WRITE(out_NB_INST_ALL [i], reg_NB_INST [i]);
+      }
+    else
+      {
+        for (uint32_t i=0; i<_param->_nb_inst_decod; i++)
+          {
+            internal_DECOD_IN_ACK [i] = 0;
+          }
+        for (uint32_t i=0; i<_param->_nb_context; i++)
+          PORT_WRITE(out_NB_INST_ALL [i], 0);
+      }
+    // Write output
+    for (uint32_t i=0; i<_param->_nb_inst_decod; i++)
+      {
+        PORT_WRITE(out_DECOD_IN_ACK [i],internal_DECOD_IN_ACK [i]);
+      }
     log_end(Decod_queue,FUNCTION);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_function_multi_fifo_transition.cpp

-                      r112
+                      r123
         for (uint32_t i=0; i<_param->_nb_context; i++)
+          reg_NB_INST [i]=0;
+          {
+            reg_NB_INST       [i]=0;
+            reg_NB_INST_EVENT [i]=0;
+          }
         reg_NUM_BANK_HEAD = 0;
 …
                 // Update pointer
                 reg_NUM_BANK_HEAD = (reg_NUM_BANK_HEAD+1)%_param->_nb_bank;
+                reg_NB_INST [context] --;
+                reg_NB_INST       [context] --;
+                if (reg_NB_INST_EVENT [context] > 0)
+                reg_NB_INST_EVENT [context] --;
+              }
+        }
         //--------------------------------------------------------------------
+        //-----[ CONTEXT_EVENT ]----------------------------------------------
+        //--------------------------------------------------------------------
+        for (uint32_t i=0; i<_param->_nb_context; i++)
+          if (PORT_READ(in_CONTEXT_EVENT [i]))
+            reg_NB_INST_EVENT [i] = reg_NB_INST [i];
+        //--------------------------------------------------------------------
         //-----[ OTHERS ]-----------------------------------------------------
         //--------------------------------------------------------------------
 …
 #if defined(DEBUG) and defined(DEBUG_Decod_queue) and (DEBUG >= DEBUG_TRACE)
     log_printf(TRACE,Decod_queue,FUNCTION,"  * Dump decod_queue");
     log_printf(TRACE,Decod_queue,FUNCTION,"    * reg_NUM_BANK_HEAD : %d",reg_NUM_BANK_HEAD);
     log_printf(TRACE,Decod_queue,FUNCTION,"    * reg_NUM_BANK_TAIL : %d",reg_NUM_BANK_TAIL);
+    log_printf(TRACE,Decod_queue,FUNCTION,"    * reg_NUM_BANK_HEAD     : %d",reg_NUM_BANK_HEAD);
+    log_printf(TRACE,Decod_queue,FUNCTION,"    * reg_NUM_BANK_TAIL     : %d",reg_NUM_BANK_TAIL);
     for (uint32_t i=0; i<_param->_nb_context; i++)
+      log_printf(TRACE,Decod_queue,FUNCTION,"    * reg_NB_INST [%d] : %d",i,reg_NB_INST [i]);
+      {
+    log_printf(TRACE,Decod_queue,FUNCTION,"    * reg_NB_INST       [%d] : %d",i,reg_NB_INST [i]);
+    log_printf(TRACE,Decod_queue,FUNCTION,"    * reg_NB_INST_EVENT [%d] : %d",i,reg_NB_INST_EVENT [i]);
+      }
     for (uint32_t i=0; i<_param->_nb_bank; ++i)
+      {

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_function_one_fifo_genMealy_decod_out.cpp

-                      r115
+                      r123
     log_function(Decod_queue,FUNCTION,_name.c_str());
+    if (PORT_READ(in_NRESET))
+      {
+    bool       context_val   [_param->_nb_context];
+    uint32_t   nb_inst_event [_param->_nb_context];
+    for (uint32_t i=0; i<_param->_nb_context; i++)
+      {
+        context_val   [i] = true;
+        nb_inst_event [i] = reg_NB_INST_EVENT [i];
+      }
     Tcontrol_t val [_param->_nb_inst_decod];
     for (uint32_t i=0; i<_param->_nb_inst_decod; i++)
 …
               Tcontext_t context         = reg_QUEUE->front()->_context_id    [index];
-              Tdepth_t   depth           = reg_QUEUE->front()->_depth         [index];
-              Tdepth_t   depth_min       = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN [context]):0;
-              Tdepth_t   depth_max       = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MAX [context]):0;
-              Tcontrol_t depth_full      = PORT_READ(in_DEPTH_FULL[context]);
+              // is a valid instruction ?
+              // If DEPTH_CURRENT :
+              // equal at     DEPTH_MIN            -> not speculative
+              // not include ]DEPTH_MIN:DEPTH_MAX] -> previous branch miss
+              //     include ]DEPTH_MIN:DEPTH_MAX] -> speculative
+              // All case
+              // ....... min ...X... max ....... OK
+              // ....... min ....... max ...X... KO
+              // ...X... min ....... max ....... KO
+              // ....... max ....... min ...X... OK
+              // ...X... max ....... min ....... OK
+              // ....... max ...X... min ....... KO
+              Tcontrol_t is_valid = true;
+//               Tcontrol_t   is_valid      = ((depth == depth_min) or
+//                                             depth_full or
+//                                             ((depth_min <= depth_max)?
+//                                              ((depth >= depth_min) and (depth <=depth_max)):
+//                                              ((depth >= depth_min) or  (depth <=depth_max))));
+              //Tcontrol_t is_valid        = ((depth == depth_min) or
+              //                              ((depth_min < depth_max)?
+              //                               (depth<=depth_max):
+              //                               ((depth > depth_min) or (depth <= depth_max))));
+              //Tcontrol_t is_valid        = depth <= depth_max;
+              log_printf(TRACE,Decod_queue,FUNCTION,"      * context      : %d",context);
+              log_printf(TRACE,Decod_queue,FUNCTION,"    * is_valid : %d",is_valid);
+              log_printf(TRACE,Decod_queue,FUNCTION,"      * context      : %d",context);
+              log_printf(TRACE,Decod_queue,FUNCTION,"      * depth        : %d",depth);
+              log_printf(TRACE,Decod_queue,FUNCTION,"      * depth_min    : %d",depth_min);
+              log_printf(TRACE,Decod_queue,FUNCTION,"      * depth_max    : %d",depth_max);
+              log_printf(TRACE,Decod_queue,FUNCTION,"      * depth_full   : %d",depth_full);
+#ifdef DEBUG
+              log_printf(TRACE,Decod_queue,FUNCTION,"      * address      : 0x%x (0x%x)",reg_QUEUE->front()->_address     [index],reg_QUEUE->front()->_address     [index]<<2);
+#endif
+              log_printf(TRACE,Decod_queue,FUNCTION,"      * address_next : 0x%x (0x%x)",reg_QUEUE->front()->_address_next[index],reg_QUEUE->front()->_address_next[index]<<2);
+              internal_DECOD_OUT_VAL [index] = 1; // in all case, val is set (entry is not empty, and instruction is valid)
+              if (is_valid)
+              if (context_val [context])
+                {
+                  val                    [i]     = 1;
+                  internal_DECOD_OUT_ACK [index] = PORT_READ(in_DECOD_OUT_ACK [i]);
+                }
+              else
+                {
+                  // Consume the instruction (to erase)
+                  internal_DECOD_OUT_ACK [index] = 1;
+//               Tdepth_t   depth           = reg_QUEUE->front()->_depth         [index];
+//               Tdepth_t   depth_min       = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN [context]):0;
+//               Tdepth_t   depth_max       = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MAX [context]):0;
+//               Tcontrol_t depth_full      = PORT_READ(in_DEPTH_FULL[context]);
+                  // is a valid instruction ?
+                  // If DEPTH_CURRENT :
+                  // equal at     DEPTH_MIN            -> not speculative
+                  // not include ]DEPTH_MIN:DEPTH_MAX] -> previous branch miss
+                  //     include ]DEPTH_MIN:DEPTH_MAX] -> speculative
+                  // All case
+                  // ....... min ...X... max ....... OK
+                  // ....... min ....... max ...X... KO
+                  // ...X... min ....... max ....... KO
+                  // ....... max ....... min ...X... OK
+                  // ...X... max ....... min ....... OK
+                  // ....... max ...X... min ....... KO
+                  Tcontrol_t is_valid = (nb_inst_event [context] == 0);
+//                   Tcontrol_t   is_valid      = ((depth == depth_min) or
+//                                                 depth_full or
+//                                                 ((depth_min <= depth_max)?
+//                                                  ((depth >= depth_min) and (depth <=depth_max)):
+//                                                  ((depth >= depth_min) or  (depth <=depth_max))));
+                  log_printf(TRACE,Decod_queue,FUNCTION,"    * is_valid : %d",is_valid);
+                  log_printf(TRACE,Decod_queue,FUNCTION,"      * context_val  : %d",context_val   [context]);
+                  log_printf(TRACE,Decod_queue,FUNCTION,"      * nb_inst_event: %d",nb_inst_event [context]);
+//                   log_printf(TRACE,Decod_queue,FUNCTION,"      * depth        : %d",depth);
+//                   log_printf(TRACE,Decod_queue,FUNCTION,"      * depth_min    : %d",depth_min);
+//                   log_printf(TRACE,Decod_queue,FUNCTION,"      * depth_max    : %d",depth_max);
+//                   log_printf(TRACE,Decod_queue,FUNCTION,"      * depth_full   : %d",depth_full);
+#ifdef DEBUG
+                  log_printf(TRACE,Decod_queue,FUNCTION,"      * address      : 0x%x (0x%x)",reg_QUEUE->front()->_address     [index],reg_QUEUE->front()->_address     [index]<<2);
+#endif
+                  log_printf(TRACE,Decod_queue,FUNCTION,"      * address_next : 0x%x (0x%x)",reg_QUEUE->front()->_address_next[index],reg_QUEUE->front()->_address_next[index]<<2);
+                  internal_DECOD_OUT_VAL [index] = 1; // in all case, val is set (entry is not empty, and instruction is valid)
+                  if (is_valid)
+                    {
+                      val                    [i]     = 1;
+                      internal_DECOD_OUT_ACK [index] = PORT_READ(in_DECOD_OUT_ACK [i]);
+                    }
+                  else
+                    {
+                      // Consume the instruction (to erase)
+                      internal_DECOD_OUT_ACK [index] = 1;
+                      // Have event ?
+                      if (nb_inst_event [context] > 0)
+                        {
+                          nb_inst_event [context] --;
+                          // Last event ?
+                          if (nb_inst_event [context] == 0)
+                            {
+                              context_val [context] = false;
+                            }
+                        }
+                    }
+                }
+            }
 …
         PORT_WRITE(out_DECOD_OUT_VAL [i],val [i]);
+      }
+      }
+    else
+      {
+        // Reset
+        for (uint32_t i=0; i<_param->_nb_inst_decod; i++)
+          {
+            internal_DECOD_OUT_VAL [i] = 0;
+            internal_DECOD_OUT_ACK [i] = 0;
+            PORT_WRITE(out_DECOD_OUT_VAL [i],0);
+          }
+      }

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_function_one_fifo_genMoore.cpp

-                      r111
+                      r123
     log_function(Decod_queue,FUNCTION,_name.c_str());
+    if (PORT_READ(in_NRESET))
+      {
     //--------------------------------------------------------------------
     //-----[ DECOD_IN ]---------------------------------------------------
 …
+        {
           internal_DECOD_IN_ACK [i] = ack;
-          PORT_WRITE(out_DECOD_IN_ACK [i],ack);
+        }
+    }
 …
           PORT_WRITE(out_DECOD_OUT_OPERATION     [i],reg_QUEUE->front()->_operation     [index]);
           PORT_WRITE(out_DECOD_OUT_NO_EXECUTE    [i],reg_QUEUE->front()->_no_execute    [index]);
+//        PORT_WRITE(out_DECOD_OUT_HAVE_EVENT    [i],0);
+          PORT_WRITE(out_DECOD_OUT_LAST_EVENT    [i],0);
           PORT_WRITE(out_DECOD_OUT_IS_DELAY_SLOT [i],reg_QUEUE->front()->_is_delay_slot [index]);
 #ifdef DEBUG
 …
     for (uint32_t i=0; i<_param->_nb_context; i++)
       PORT_WRITE(out_NB_INST_ALL [i], reg_NB_INST [i]);
+      }
+    else
+      {
+        for (uint32_t i=0; i<_param->_nb_inst_decod; i++)
+          {
+            internal_DECOD_IN_ACK [i] = 0;
+          }
+        for (uint32_t i=0; i<_param->_nb_context; i++)
+          PORT_WRITE(out_NB_INST_ALL [i], 0);
+      }
+    // Write output
+    for (uint32_t i=0; i<_param->_nb_inst_decod; i++)
+      {
+        PORT_WRITE(out_DECOD_IN_ACK [i],internal_DECOD_IN_ACK [i]);
+      }
     log_end(Decod_queue,FUNCTION);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_function_one_fifo_transition.cpp

-                      r112
+                      r123
         for (uint32_t i=0; i<_param->_nb_context; i++)
+          reg_NB_INST [i]=0;
+          {
+            reg_NB_INST       [i]=0;
+            reg_NB_INST_EVENT [i]=0;
+          }
         reg_LAST_SLOT = 0;
 …
                     log_printf(TRACE,Decod_queue,FUNCTION,_("    * context : %d"),context);
+                    reg_NB_INST [context] --;
+                    reg_NB_INST       [context] --;
+                    if (reg_NB_INST_EVENT [context] > 0)
+                    reg_NB_INST_EVENT [context] --;
                     log_printf(TRACE,Decod_queue,FUNCTION,_("    * nb_inst : %d"),reg_NB_INST [context]);
+                  }
 …
+              }
+          }
+        //--------------------------------------------------------------------
+        //-----[ CONTEXT_EVENT ]----------------------------------------------
+        //--------------------------------------------------------------------
+        for (uint32_t i=0; i<_param->_nb_context; i++)
+          if (PORT_READ(in_CONTEXT_EVENT [i]))
+            reg_NB_INST_EVENT [i] = reg_NB_INST [i];
+      }

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_genMealy_decod_out.cpp

r111	r123
25	25	log_function(Decod_queue,FUNCTION,_name.c_str());
26	26
	27	// if (PORT_READ(in_NRESET))
27	28	(this->*function_genMealy_decod_out) ();
28	29

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/include/Decod_unit.h

-                      r118
+                      r123
   public    : SC_OUT(Toperation_t       )  ** out_DECOD_OPERATION                    ;//[nb_inst_decod]
   public    : SC_OUT(Tcontrol_t         )  ** out_DECOD_NO_EXECUTE                   ;//[nb_inst_decod]
+//public    : SC_OUT(Tcontrol_t         )  ** out_DECOD_HAVE_EVENT                   ;//[nb_inst_decod]
+  public    : SC_OUT(Tcontrol_t         )  ** out_DECOD_LAST_EVENT                   ;//[nb_inst_decod]
   public    : SC_OUT(Tcontrol_t         )  ** out_DECOD_IS_DELAY_SLOT                ;//[nb_inst_decod]
 #ifdef DEBUG
 …
     // ~~~~~[ Interface : "context" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   public    : SC_IN (Tcontrol_t         )  **  in_CONTEXT_DECOD_ENABLE               ;//[nb_context]
+  public    : SC_IN (Tcontrol_t         )  **  in_CONTEXT_EVENT                      ;//[nb_context]
   public    : SC_IN (Tcontrol_t         )  **  in_CONTEXT_DEPTH_VAL                  ;//[nb_context]
   public    : SC_IN (Tdepth_t           )  **  in_CONTEXT_DEPTH                      ;//[nb_context]

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/src/Decod_unit.cpp

-                      r88
+                      r123
     usage_environment(_usage);
 #if DEBUG_Decod_unit == true
     log_printf(INFO,Decod_unit,FUNCTION,_("<%s> Parameters"),_name.c_str());
+// #if DEBUG_Decod_unit == true
+//     log_printf(INFO,Decod_unit,FUNCTION,_("<%s> Parameters"),_name.c_str());
     std::cout << *param << std::endl;
 #endif
+//     std::cout << *param << std::endl;
+// #endif
     log_printf(INFO,Decod_unit,FUNCTION,_("Allocation"));

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/src/Decod_unit_allocation.cpp

-                      r118
+                      r123
       ALLOC1_SIGNAL_OUT(out_DECOD_OPERATION    ,"operation"    ,Toperation_t      ,_param->_size_operation             );
       ALLOC1_SIGNAL_OUT(out_DECOD_NO_EXECUTE   ,"no_execute"   ,Tcontrol_t        ,1                                   );
+//    ALLOC1_SIGNAL_OUT(out_DECOD_HAVE_EVENT   ,"have_event"   ,Tcontrol_t        ,1                                   );
+      ALLOC1_SIGNAL_OUT(out_DECOD_LAST_EVENT   ,"last_event"   ,Tcontrol_t        ,1                                   );
       ALLOC1_SIGNAL_OUT(out_DECOD_IS_DELAY_SLOT,"is_delay_slot",Tcontrol_t        ,1                                   );
 #ifdef DEBUG
 …
       ALLOC1_SIGNAL_IN (in_CONTEXT_DECOD_ENABLE,"decod_enable",Tcontrol_t,1);
+      ALLOC1_SIGNAL_IN (in_CONTEXT_EVENT       ,"event"       ,Tcontrol_t,1);
       ALLOC1_SIGNAL_IN (in_CONTEXT_DEPTH_VAL   ,"depth_val"   ,Tcontrol_t,1);
       ALLOC1_SIGNAL_IN (in_CONTEXT_DEPTH       ,"depth"       ,Tdepth_t  ,_param->_size_depth);
 …
           PORT_MAP(_component,src ,"out_DECOD_OUT_"+toString(i)+"_NO_EXECUTE"   ,
                               dest,"out_DECOD_"    +toString(i)+"_NO_EXECUTE"   );
+//        PORT_MAP(_component,src ,"out_DECOD_OUT_"+toString(i)+"_HAVE_EVENT"   ,
+//                            dest,"out_DECOD_"    +toString(i)+"_HAVE_EVENT"   );
+          PORT_MAP(_component,src ,"out_DECOD_OUT_"+toString(i)+"_LAST_EVENT"   ,
+                              dest,"out_DECOD_"    +toString(i)+"_LAST_EVENT"   );
           PORT_MAP(_component,src ,"out_DECOD_OUT_"+toString(i)+"_IS_DELAY_SLOT",
                               dest,"out_DECOD_"    +toString(i)+"_IS_DELAY_SLOT");
 …
                               dest,"out_NB_INST_"+toString(i)+"_DECOD_ALL");
+        }
+      for (uint32_t i=0; i<_param->_nb_context; i++)
+        {
+          dest = _name;
+#ifdef POSITION
+          _component->interface_map (src ,"context_"+toString(i),
+                                     dest,"context_"+toString(i));
+#endif
+          PORT_MAP(_component,src , "in_CONTEXT_"+toString(i)+"_EVENT"       ,
+                              dest, "in_CONTEXT_"+toString(i)+"_EVENT"       );
+        }
+    }
     // ~~~~~[ Others ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/src/Decod_unit_deallocation.cpp

-                      r112
+                      r123
         DELETE1_SIGNAL(out_DECOD_OPERATION                    ,_param->_nb_inst_decod,_param->_size_operation             );
         DELETE1_SIGNAL(out_DECOD_NO_EXECUTE                   ,_param->_nb_inst_decod,1                                   );
+//      DELETE1_SIGNAL(out_DECOD_HAVE_EVENT                   ,_param->_nb_inst_decod,1                                   );
+        DELETE1_SIGNAL(out_DECOD_LAST_EVENT                   ,_param->_nb_inst_decod,1                                   );
         DELETE1_SIGNAL(out_DECOD_IS_DELAY_SLOT                ,_param->_nb_inst_decod,1                                   );
 #ifdef DEBUG
 …
         DELETE1_SIGNAL(in_CONTEXT_DECOD_ENABLE                ,_param->_nb_context,1);
+        DELETE1_SIGNAL(in_CONTEXT_EVENT                       ,_param->_nb_context,1);
         DELETE1_SIGNAL(in_CONTEXT_DEPTH                       ,_param->_nb_context,_param->_size_depth);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue.cpp

-                      r119
+                      r123
     usage_environment(_usage);
 #if DEBUG_Front_end_Glue == true
     log_printf(INFO,Front_end_Glue,FUNCTION,_("<%s> Parameters"),_name.c_str());
     std::cout << *param << std::endl;
 #endif
+// #if DEBUG_Front_end_Glue == true
+//     log_printf(INFO,Front_end_Glue,FUNCTION,_("<%s> Parameters"),_name.c_str());
+//     std::cout << *param << std::endl;
+// #endif
     log_printf(INFO,Front_end_Glue,FUNCTION,_("<%s> : Allocation"),_name.c_str());

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_genMealy_branch_complete.cpp

-                      r88
+                      r123
     log_begin(Front_end_Glue,FUNCTION);
+    if (PORT_READ(in_NRESET))
+      {
     for (uint32_t i=0; i<_param->_nb_inst_branch_complete; ++i)
+      {
 …
         PORT_WRITE(out_BRANCH_COMPLETE_ACK [i],ack);
+      }
+      }
+    else
+      {
+        // RESET
+        for (uint32_t i=0; i<_param->_nb_inst_branch_complete; ++i)
+          {
+            PORT_WRITE(out_BRANCH_COMPLETE_PREDICTION_UNIT_VAL [i],0);
+            PORT_WRITE(out_BRANCH_COMPLETE_CONTEXT_STATE_VAL   [i],0);
+            PORT_WRITE(out_BRANCH_COMPLETE_ACK                 [i],0);
+          }
+      }
     log_end(Front_end_Glue,FUNCTION);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_genMealy_decod.cpp

-                      r88
+                      r123
     // Warning : this function is an sc_method if _have_port_context_id
+    if (PORT_READ(in_NRESET))
+      {
     for (uint32_t i=0; i<_param->_nb_decod_unit; ++i)
       for (uint32_t j=0; j<_param->_nb_inst_decod[i]; ++j)
         PORT_WRITE(out_DECOD_CONTEXT_ID [i][j],_param->_translate_context_id_from_decod_unit[i][PORT_READ(in_DECOD_DECOD_UNIT_CONTEXT_ID [i][j])]);
+      }
     log_end(Front_end_Glue,FUNCTION);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_genMealy_depth.cpp

-                      r101
+                      r123
     log_begin(Front_end_Glue,FUNCTION);
+    if (PORT_READ(in_NRESET))
+      {
     for (uint32_t i=0; i<_param->_nb_context; ++i)
+      {
 …
           PORT_WRITE(out_DEPTH_DECOD_UNIT_FULL        [i][j], PORT_READ(in_DEPTH_PREDICTION_UNIT_FULL    [num_context]));
+        }
+      }
     log_end(Front_end_Glue,FUNCTION);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_genMealy_event.cpp

-                      r119
+                      r123
     log_function(Front_end_Glue,FUNCTION,_name.c_str());
+    if (PORT_READ(in_NRESET))
+      {
     for (uint32_t i=0; i<_param->_nb_context; ++i)
+      {
 …
 #endif
+      }
+      }
+    else
+      {
+        // Reset
+        for (uint32_t i=0; i<_param->_nb_context; ++i)
+          {
+            PORT_WRITE(out_EVENT_VAL                 [i], 0);
+            PORT_WRITE(out_EVENT_IFETCH_UNIT_VAL     [i], 0);
+            PORT_WRITE(out_EVENT_PREDICTION_UNIT_VAL [i], 0);
+            PORT_WRITE(out_EVENT_CONTEXT_STATE_ACK   [i], 0);
+          }
+      }
     log_end(Front_end_Glue,FUNCTION);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_genMealy_nb_inst.cpp

-                      r108
+                      r123
     log_begin(Front_end_Glue,FUNCTION);
+    if (PORT_READ(in_NRESET))
+      {
     for (uint32_t i=0; i<_param->_nb_context; ++i)
+      {
 …
         PORT_WRITE(out_NB_INST_DECOD_ALL               [i], nb_inst);
         PORT_WRITE(out_NB_INST_CONTEXT_STATE_DECOD_ALL [i], nb_inst);
+      }
+      }

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management.cpp

-                      r88
+                      r123
     log_printf(FUNC,Address_management,FUNCTION,"Begin");
 #if DEBUG_Address_management == true
     log_printf(INFO,Address_management,FUNCTION,_("<%s> Parameters"),_name.c_str());
+// #if DEBUG_Address_management == true
+//     log_printf(INFO,Address_management,FUNCTION,_("<%s> Parameters"),_name.c_str());
     std::cout << *param << std::endl;
 #endif
+//     std::cout << *param << std::endl;
+// #endif
     log_printf(INFO,Address_management,FUNCTION,"Allocation");

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_genMoore.cpp

-                      r107
+                      r123
     log_printf(FUNC,Address_management,FUNCTION,"Begin");
+    if (PORT_READ(in_NRESET))
+      {
     // =========================================
     // ===== ADDRESS ===========================
 …
     internal_ADDRESS_VAL = reg_PC_ACCESS_VAL;
-    PORT_WRITE(out_ADDRESS_VAL                        ,internal_ADDRESS_VAL                     );
     // Align pc on instruction packet address.
     PORT_WRITE(out_ADDRESS_INSTRUCTION_ADDRESS        ,reg_PC_ACCESS - (reg_PC_ACCESS%_param->_nb_instruction));
 …
     internal_PREDICT_VAL = not reg_PC_NEXT_NEXT_VAL;
-    PORT_WRITE(out_PREDICT_VAL                  ,internal_PREDICT_VAL);
     PORT_WRITE(out_PREDICT_PC_PREVIOUS          ,reg_PC_CURRENT        );
     PORT_WRITE(out_PREDICT_PC_CURRENT           ,reg_PC_NEXT           );
     PORT_WRITE(out_PREDICT_PC_CURRENT_IS_DS_TAKE,reg_PC_NEXT_IS_DS_TAKE);
+      }
+    else
+      {
+    internal_ADDRESS_VAL = 0;
+    internal_PREDICT_VAL = 0;
+      }
+    PORT_WRITE(out_ADDRESS_VAL,internal_ADDRESS_VAL);
+    PORT_WRITE(out_PREDICT_VAL,internal_PREDICT_VAL);
     log_printf(FUNC,Address_management,FUNCTION,"End");
   };

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_transition.cpp

-                      r119
+                      r123
       std::string instruction_enable;
       for (uint32_t i=0; i<_param->_nb_instruction; ++i)
         instruction_enable += toString(reg_PC_ACCESS_INSTRUCTION_ENABLE [i])+ " ";
+        instruction_enable += ((reg_PC_ACCESS_VAL)?(toString(reg_PC_ACCESS_INSTRUCTION_ENABLE [i])):"X") + " ";
       log_printf(TRACE,Address_management,FUNCTION,"    * Access    : %d %d 0x%.8x (%.8x) - %.2d %.2d %.2d - %s",
 …
       std::string instruction_enable;
       for (uint32_t i=0; i<_param->_nb_instruction; ++i)
         instruction_enable += toString(reg_PC_CURRENT_INSTRUCTION_ENABLE [i])+ " ";
+        instruction_enable += ((reg_PC_CURRENT_VAL)?(toString(reg_PC_CURRENT_INSTRUCTION_ENABLE [i])):"X") + " ";
       log_printf(TRACE,Address_management,FUNCTION,"    * Current   : %d %d 0x%.8x (%.8x) - %.2d %.2d %.2d - %s",
 …
       std::string instruction_enable;
       for (uint32_t i=0; i<_param->_nb_instruction; ++i)
         instruction_enable += toString(reg_PC_NEXT_INSTRUCTION_ENABLE [i])+ " ";
+        instruction_enable += ((reg_PC_NEXT_VAL)?(toString(reg_PC_NEXT_INSTRUCTION_ENABLE [i])):"X") + " ";
       log_printf(TRACE,Address_management,FUNCTION,"    * Next      : %d %d 0x%.8x (%.8x) - %.2d %.2d %.2d - %s",

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue.cpp

-                      r88
+                      r123
     log_printf(FUNC,Ifetch_queue,FUNCTION,"Begin");
 #if DEBUG_Ifetch_queue == true
     log_printf(INFO,Ifetch_queue,FUNCTION,_("<%s> Parameters"),_name.c_str());
+// #if DEBUG_Ifetch_queue == true
+//     log_printf(INFO,Ifetch_queue,FUNCTION,_("<%s> Parameters"),_name.c_str());
     std::cout << *param << std::endl;
 #endif
+//     std::cout << *param << std::endl;
+// #endif
     log_printf(INFO,Ifetch_queue,FUNCTION,_("<%s> Allocation"),_name.c_str());

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_deallocation.cpp

-                      r112
+                      r123
         DELETE0_SIGNAL( in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID,_param->_size_depth          );
         DELETE0_SIGNAL(out_ADDRESS_IFETCH_QUEUE_ID            ,_param->_size_ifetch_queue_ptr);
         DELETE1_SIGNAL( in_ADDRESS_INSTRUCTION_ENABLE         ,1,_param->_nb_instruction);
+        DELETE1_SIGNAL( in_ADDRESS_INSTRUCTION_ENABLE         ,_param->_nb_instruction,1);
         DELETE1_SIGNAL(out_DECOD_VAL                        ,1,_param->_nb_instruction);
         DELETE1_SIGNAL( in_DECOD_ACK                        ,1,_param->_nb_instruction);
         DELETE1_SIGNAL(out_DECOD_INSTRUCTION                ,_param->_size_instruction,_param->_nb_instruction);
+        DELETE1_SIGNAL(out_DECOD_VAL                        ,_param->_nb_instruction,1);
+        DELETE1_SIGNAL( in_DECOD_ACK                        ,_param->_nb_instruction,1);
+        DELETE1_SIGNAL(out_DECOD_INSTRUCTION                ,_param->_nb_instruction,_param->_size_instruction);
         DELETE0_SIGNAL(out_DECOD_ADDRESS                    ,_param->_size_instruction_address);
         DELETE0_SIGNAL(out_DECOD_INST_IFETCH_PTR            ,_param->_size_inst_ifetch_ptr );
 …
         DELETE0_SIGNAL( in_ICACHE_RSP_PACKET_ID  ,_param->_size_ifetch_queue_ptr);
         DELETE0_SIGNAL( in_ICACHE_RSP_ERROR      ,_param->_size_icache_error);
         DELETE1_SIGNAL( in_ICACHE_RSP_INSTRUCTION,_param->_size_instruction,_param->_nb_instruction);
+        DELETE1_SIGNAL( in_ICACHE_RSP_INSTRUCTION,_param->_nb_instruction,_param->_size_instruction);
         DELETE0_SIGNAL( in_EVENT_RESET_VAL,1);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_genMoore.cpp

-                      r119
+                      r123
     log_printf(FUNC,Ifetch_queue,FUNCTION,"Begin");
+    if (PORT_READ(in_NRESET))
+      {
     // ==========================================================
     // =====[ ADDRESS ]==========================================
 …
       internal_ADDRESS_ACK = (_queue[reg_PTR_WRITE]->_state == IFETCH_QUEUE_STATE_EMPTY);
-      PORT_WRITE(out_ADDRESS_ACK            , internal_ADDRESS_ACK);
       if (_param->_have_port_ifetch_queue_ptr)
       PORT_WRITE(out_ADDRESS_IFETCH_QUEUE_ID, reg_PTR_WRITE);
 …
+        {
           internal_DECOD_VAL [i] = ack and _queue[reg_PTR_READ]->_instruction_enable [i];
-          PORT_WRITE(out_DECOD_VAL         [i], internal_DECOD_VAL [i]);
           PORT_WRITE(out_DECOD_INSTRUCTION [i],         _queue[reg_PTR_READ]->_instruction        [i]);
+        }
 …
       PORT_WRITE(out_DECOD_EXCEPTION                  , _queue[reg_PTR_READ]->_exception                  );
+    }
+      }
+    else
+      {
+        // Reset
+        internal_ADDRESS_ACK = 0;
+        for (uint32_t i=0; i<_param->_nb_instruction; i++)
+          internal_DECOD_VAL [i] = 0;
+      }
+    // Write Output
+    PORT_WRITE(out_ADDRESS_ACK  , internal_ADDRESS_ACK);
+    for (uint32_t i=0; i<_param->_nb_instruction; i++)
+    PORT_WRITE(out_DECOD_VAL [i], internal_DECOD_VAL [i]);
     log_printf(FUNC,Ifetch_queue,FUNCTION,"End");

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/src/Ifetch_unit_Glue.cpp

-                      r88
+                      r123
     log_printf(FUNC,Ifetch_unit_Glue,FUNCTION,"Begin");
 #if DEBUG_Ifetch_unit_Glue == true
     log_printf(INFO,Ifetch_unit_Glue,FUNCTION,_("<%s> Parameters"),_name.c_str());
+// #if DEBUG_Ifetch_unit_Glue == true
+//     log_printf(INFO,Ifetch_unit_Glue,FUNCTION,_("<%s> Parameters"),_name.c_str());
     std::cout << *param << std::endl;
 #endif
+//     std::cout << *param << std::endl;
+// #endif
     log_printf(INFO,Ifetch_unit_Glue,FUNCTION,"Allocation");

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/src/Ifetch_unit_Glue_genMealy_event.cpp

-                      r81
+                      r123
     log_printf(FUNC,Ifetch_unit_Glue,FUNCTION,"Begin");
+    if (PORT_READ(in_NRESET))
+      {
     Tcontrol_t address_ack = PORT_READ(in_EVENT_ADDRESS_ACK);
     Tcontrol_t queue_ack   = PORT_READ(in_EVENT_QUEUE_ACK  );
 …
     PORT_WRITE(out_EVENT_ADDRESS_VAL, val         and queue_ack);
     PORT_WRITE(out_EVENT_QUEUE_VAL  , address_ack and val);
+      }
+    else
+      {
+    PORT_WRITE(out_EVENT_ACK        , 0);
+    PORT_WRITE(out_EVENT_ADDRESS_VAL, 0);
+    PORT_WRITE(out_EVENT_QUEUE_VAL  , 0);
+      }
     log_printf(FUNC,Ifetch_unit_Glue,FUNCTION,"End");
   };

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/src/Ifetch_unit_Glue_genMealy_icache_req.cpp

-                      r85
+                      r123
     log_printf(FUNC,Ifetch_unit_Glue,FUNCTION,"Begin");
+    if (PORT_READ(in_NRESET))
+      {
     Tcontrol_t address_val = PORT_READ(in_ICACHE_REQ_ADDRESS_VAL);
     Tcontrol_t queue_ack   = PORT_READ(in_ICACHE_REQ_QUEUE_ACK  );
 …
     PORT_WRITE(out_ICACHE_REQ_ADDRESS      ,address);
     PORT_WRITE(out_ICACHE_REQ_QUEUE_ADDRESS,address);
+      }
+    else
+      {
+        // RESET
+        PORT_WRITE(out_ICACHE_REQ_VAL        , 0);
+        PORT_WRITE(out_ICACHE_REQ_ADDRESS_ACK, 0);
+        PORT_WRITE(out_ICACHE_REQ_QUEUE_VAL  , 0);
+      }
     log_printf(FUNC,Ifetch_unit_Glue,FUNCTION,"End");

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/src/Ifetch_unit.cpp

-                      r88
+                      r123
     log_printf(FUNC,Ifetch_unit,FUNCTION,"Begin");
 #if DEBUG_Ifetch_unit == true
     log_printf(INFO,Ifetch_unit,FUNCTION,_("<%s> Parameters"),_name.c_str());
+// #if DEBUG_Ifetch_unit == true
+//     log_printf(INFO,Ifetch_unit,FUNCTION,_("<%s> Parameters"),_name.c_str());
     std::cout << *param << std::endl;
 #endif
+//     std::cout << *param << std::endl;
+// #endif
     log_printf(INFO,Ifetch_unit,FUNCTION,"Allocation");

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/src/Ifetch_unit_deallocation.cpp

-                      r112
+                      r123
         DELETE0_SIGNAL( in_ICACHE_RSP_PACKET_ID  ,_param->_size_ifetch_queue_ptr   );
         DELETE0_SIGNAL( in_ICACHE_RSP_ERROR      ,_param->_size_icache_error);
         DELETE1_SIGNAL( in_ICACHE_RSP_INSTRUCTION,_param->_size_instruction,_param->_nb_instruction);
+        DELETE1_SIGNAL( in_ICACHE_RSP_INSTRUCTION,_param->_nb_instruction, _param->_size_instruction);
         DELETE0_SIGNAL(out_PREDICT_VAL                        ,1);
 …
         DELETE0_SIGNAL( in_PREDICT_BRANCH_STATE               ,_param->_size_branch_state);
         DELETE0_SIGNAL( in_PREDICT_BRANCH_UPDATE_PREDICTION_ID,_param->_size_depth);
         DELETE1_SIGNAL( in_PREDICT_INSTRUCTION_ENABLE         ,1,_param->_nb_instruction);
+        DELETE1_SIGNAL( in_PREDICT_INSTRUCTION_ENABLE         ,_param->_nb_instruction,1);
     //  DELETE0_SIGNAL(out_DECOD_CONTEXT_ID                 ,_param->_size_context_id);
 …
         DELETE1_SIGNAL(out_DECOD_VAL                        ,1,_param->_nb_instruction);
         DELETE1_SIGNAL( in_DECOD_ACK                        ,1,_param->_nb_instruction);
         DELETE1_SIGNAL(out_DECOD_INSTRUCTION                ,_param->_size_instruction,_param->_nb_instruction);
+        DELETE1_SIGNAL(out_DECOD_INSTRUCTION                ,_param->_nb_instruction,_param->_size_instruction);
         DELETE0_SIGNAL( in_EVENT_VAL              ,1);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/src/Branch_Target_Buffer_Glue.cpp

-                      r88
+                      r123
     log_printf(FUNC,Branch_Target_Buffer_Glue,FUNCTION,"Begin");
 #if DEBUG_Branch_Target_Buffer_Glue == true
     log_printf(INFO,Branch_Target_Buffer_Glue,FUNCTION,_("<%s> Parameters"),_name.c_str());
     std::cout << *param << std::endl;
 #endif
+// #if DEBUG_Branch_Target_Buffer_Glue == true
+//     log_printf(INFO,Branch_Target_Buffer_Glue,FUNCTION,_("<%s> Parameters"),_name.c_str());
+//     std::cout << *param << std::endl;
+// #endif
     log_printf(INFO,Branch_Target_Buffer_Glue,FUNCTION,"Allocation");

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/src/Branch_Target_Buffer_Glue_genMealy_decod.cpp

-                      r98
+                      r123
     log_function(Branch_Target_Buffer_Glue,FUNCTION,_name.c_str());
+    if (PORT_READ(in_NRESET))
+      {
     for (uint32_t i=0; i<_param->_nb_inst_decod; i++)
+      {
 …
+          }
+      }
+      }
+    else
+      {
+        for (uint32_t i=0; i<_param->_nb_inst_decod; i++)
+          {
+            PORT_WRITE(out_DECOD_ACK            [i], 0);
+            PORT_WRITE(out_DECOD_REGISTER_VAL   [i], 0);
+            if (_param->_have_port_victim)
+            PORT_WRITE(out_DECOD_VICTIM_VAL     [i], 0);
+          }
+      }
     log_end(Branch_Target_Buffer_Glue,FUNCTION);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/src/Branch_Target_Buffer_Glue_genMealy_predict.cpp

-                      r108
+                      r123
     log_function(Branch_Target_Buffer_Glue,FUNCTION,_name.c_str());
+    if (PORT_READ(in_NRESET))
+      {
     for (uint32_t i=0; i<_param->_nb_inst_predict; i++)
+      {
 …
+          }
+      }
+      }
+    else
+      {
+        for (uint32_t i=0; i<_param->_nb_inst_predict; i++)
+          {
+            PORT_WRITE(out_PREDICT_ACK            [i], 0);
+            PORT_WRITE(out_PREDICT_REGISTER_VAL   [i], 0);
+            if (_param->_have_port_victim)
+            PORT_WRITE(out_PREDICT_VICTIM_VAL     [i], 0);
+          }
+      }
     log_end(Branch_Target_Buffer_Glue,FUNCTION);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/src/Branch_Target_Buffer_Glue_genMealy_update.cpp

-                      r98
+                      r123
     log_function(Branch_Target_Buffer_Glue,FUNCTION,_name.c_str());
+    if (PORT_READ(in_NRESET))
+      {
     for (uint32_t i=0; i<_param->_nb_inst_update; i++)
+      {
 …
+          }
+      }
+      }
+    else
+      {
+        for (uint32_t i=0; i<_param->_nb_inst_update; i++)
+          {
+            PORT_WRITE(out_UPDATE_ACK            [i], 0);
+            PORT_WRITE(out_UPDATE_REGISTER_VAL   [i], 0);
+            if (_param->_have_port_victim)
+            PORT_WRITE(out_UPDATE_VICTIM_VAL     [i], 0);
+          }
+      }
     log_end(Branch_Target_Buffer_Glue,FUNCTION);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register.cpp

-                      r113
+                      r123
     log_printf(FUNC,Branch_Target_Buffer_Register,FUNCTION,"Begin");
 #if DEBUG_Branch_Target_Buffer_Register == true
     log_printf(INFO,Branch_Target_Buffer_Register,FUNCTION,_("<%s> Parameters"),_name.c_str());
     std::cout << *param << std::endl;
 #endif
+// #if DEBUG_Branch_Target_Buffer_Register == true
+//     log_printf(INFO,Branch_Target_Buffer_Register,FUNCTION,_("<%s> Parameters"),_name.c_str());
+//     std::cout << *param << std::endl;
+// #endif
     log_printf(INFO,Branch_Target_Buffer_Register,FUNCTION,"Allocation");

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_genMealy_decod.cpp

-                      r88
+                      r123
     log_function(Branch_Target_Buffer_Register,FUNCTION,_name.c_str());
+    if (PORT_READ(in_NRESET))
+      {
     for (uint32_t i=0; i<_param->_nb_inst_decod; i++)
+      {
 …
+          }
+      }
+      }
+    else
+      {
+//      internal_DECOD_HIT       [i] = hit      ;
+//      internal_DECOD_NUM_BANK  [i] = num_bank ;
+//      internal_DECOD_NUM_ENTRY [i] = num_entry;
+      }
     log_end(Branch_Target_Buffer_Register,FUNCTION);
   };

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_genMealy_predict.cpp

r108	r123
25	25	log_function(Branch_Target_Buffer_Register,FUNCTION,_name.c_str());
26	26
	27	if (PORT_READ(in_NRESET))
	28	{
27	29	for (uint32_t i=0; i<_param->_nb_inst_predict; i++)
28	30	{
…	…
64	66	}
65	67	}
	68	}
	69	// else
	70	// {
	71	// }
66	72
67	73	log_end(Branch_Target_Buffer_Register,FUNCTION);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_genMealy_update.cpp

-                      r88
+                      r123
     log_function(Branch_Target_Buffer_Register,FUNCTION,_name.c_str());
+    if (PORT_READ(in_NRESET))
+      {
     for (uint32_t i=0; i<_param->_nb_inst_update; i++)
+      {
 …
+          }
+      }
+      }
+//     else
+//       {
+//      internal_UPDATE_HIT       [i] = hit      ;
+//      internal_UPDATE_NUM_BANK  [i] = num_bank ;
+//      internal_UPDATE_NUM_ENTRY [i] = num_entry;
+//       }
     log_end(Branch_Target_Buffer_Register,FUNCTION);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/src/Branch_Target_Buffer.cpp

-                      r88
+                      r123
     log_printf(INFO,Branch_Target_Buffer,FUNCTION,"Allocation");
 #if DEBUG_Branch_Target_Buffer == true
     log_printf(INFO,Branch_Target_Buffer,FUNCTION,_("<%s> Parameters"),_name.c_str());
+// #if DEBUG_Branch_Target_Buffer == true
+//     log_printf(INFO,Branch_Target_Buffer,FUNCTION,_("<%s> Parameters"),_name.c_str());
     std::cout << *param << std::endl;
 #endif
+//     std::cout << *param << std::endl;
+// #endif
     allocation (

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Direction_Glue/src/Direction_Glue.cpp

-                      r112
+                      r123
 #if DEBUG_Direction_Glue == true
     log_printf(INFO,Direction_Glue,FUNCTION,_("<%s> Parameters"),_name.c_str());
     std::cout << *param << std::endl;
 #endif
+// #if DEBUG_Direction_Glue == true
+//     log_printf(INFO,Direction_Glue,FUNCTION,_("<%s> Parameters"),_name.c_str());
+//     std::cout << *param << std::endl;
+// #endif
     log_printf(INFO,Direction_Glue,FUNCTION,"Allocation");

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Direction_Glue/src/Direction_Glue_genMealy_predict.cpp

-                      r107
+                      r123
     log_function(Direction_Glue,FUNCTION,_name.c_str());
+    if (PORT_READ(in_NRESET))
+      {
+//         std::cout << "Kane (before) " << std::endl;
+//         std::cout << _param << std::endl;
+//         std::cout << _param->_nb_inst_update << std::endl;
+//         std::cout << _param->_nb_inst_predict<< std::endl;
+//         std::cout << "Kane (end) " << std::endl;
     // constant direction : never / always
     for (uint32_t i=0; i<_param->_nb_inst_predict; i++)
 …
         log_printf(TRACE,Direction_Glue,FUNCTION,"  * PREDICT [%d]",i);
         Tcontrol_t direction;
+        Tcontrol_t direction = false;
         switch (_param->_predictor_scheme)
 …
         PORT_WRITE(out_PREDICT_DIRECTION   [i], direction);
+      }
+      }
+    else
+      {
+        //RESET
+        for (uint32_t i=0; i<_param->_nb_inst_predict; i++)
+          {
+            if (_param->_have_component_meta_predictor)
+              {
+            PORT_WRITE(out_PREDICT_PREDICTOR_VAL [i], 0);
+            PORT_WRITE(out_PREDICT_ACK           [i], 0);
+              }
+          }
+      }
     log_end(Direction_Glue,FUNCTION);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Direction_Glue/src/Direction_Glue_genMealy_update.cpp

-                      r112
+                      r123
     log_function(Direction_Glue,FUNCTION,_name.c_str());
+    if (PORT_READ(in_NRESET))
+      {
     for (uint32_t i=0; i<_param->_nb_inst_update; i++)
+      {
 …
         PORT_WRITE(out_UPDATE_PREDICTOR_PREDICTION_IFETCH [i], PORT_READ(in_UPDATE_PREDICTION_IFETCH [i]));
+      }
+      }
+    else
+      {
+        // RESET
+        for (uint32_t i=0; i<_param->_nb_inst_update; i++)
+          {
+            PORT_WRITE(out_UPDATE_PREDICTOR_VAL [i], 0);
+            PORT_WRITE(out_UPDATE_ACK           [i], 0);
+          }
+      }
     log_end(Direction_Glue,FUNCTION);
   };

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Meta_Predictor_Glue/src/Meta_Predictor_Glue_genMealy_predict.cpp

-                      r111
+                      r123
     log_function(Meta_Predictor_Glue,FUNCTION,_name.c_str());
+    if (PORT_READ(in_NRESET))
+      {
     for (uint32_t i=0; i<_param->_nb_inst_predict; ++i)
+      {
 …
         PORT_WRITE(out_PREDICT_DIRECTION [i],direction);
+      }
+      }
+//     else
+//       {
+//       }
     log_end(Meta_Predictor_Glue,FUNCTION);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Meta_Predictor_Glue/src/Meta_Predictor_Glue_genMealy_predict_valack.cpp

-                      r111
+                      r123
     log_function(Meta_Predictor_Glue,FUNCTION,_name.c_str());
+    if (PORT_READ(in_NRESET))
+      {
     for (uint32_t i=0; i<_param->_nb_inst_predict; ++i)
+      {
 …
         PORT_WRITE(out_PREDICT_ACK [i],ack);
+      }
+      }
+    else
+      {
+        // Reset
+        for (uint32_t i=0; i<_param->_nb_inst_predict; ++i)
+          {
+            for (uint32_t j=0; j<_param->_nb_predictor; ++j)
+              PORT_WRITE(out_PREDICT_PREDICTOR_VAL [j][i],0);
+            PORT_WRITE(out_PREDICT_ACK [i],0);
+          }
+      }

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Meta_Predictor_Glue/src/Meta_Predictor_Glue_genMealy_update.cpp

-                      r112
+                      r123
     log_function(Meta_Predictor_Glue,FUNCTION,_name.c_str());
+    if (PORT_READ(in_NRESET))
+      {
     for (uint32_t i=0; i<_param->_nb_inst_update; ++i)
+      {
 …
+          }
+      }
+      }
+//     else
+//       {
+//         // RESET
+//       }
     log_end(Meta_Predictor_Glue,FUNCTION);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Meta_Predictor_Glue/src/Meta_Predictor_Glue_genMealy_update_valack.cpp

-                      r111
+                      r123
     log_function(Meta_Predictor_Glue,FUNCTION,_name.c_str());
+    if (PORT_READ(in_NRESET))
+      {
     for (uint32_t i=0; i<_param->_nb_inst_update; ++i)
+      {
 …
         PORT_WRITE(out_UPDATE_ACK [i],ack);
+      }
+      }
+    else
+      {
+        // RESET
+        for (uint32_t i=0; i<_param->_nb_inst_update; ++i)
+          {
+            for (uint32_t j=0; j<_param->_nb_predictor; ++j)
+              PORT_WRITE(out_UPDATE_PREDICTOR_VAL [j][i],0);
+            PORT_WRITE(out_UPDATE_ACK [i],0);
+          }
+      }

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_genMealy_predict.cpp

-                      r119
+                      r123
     log_function(Two_Level_Branch_Predictor,FUNCTION,_name.c_str());
+    if (PORT_READ(in_NRESET))
+      {
     // ===================================================================
     // =====[ PREDICT ]===================================================
 …
           PORT_WRITE(out_PREDICT_HISTORY   [i],history  );
+        }
+      }
     log_end(Two_Level_Branch_Predictor,FUNCTION);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Direction.cpp

-                      r88
+                      r123
     log_printf(FUNC,Direction,FUNCTION,"Begin");
 #if DEBUG_Direction == true
     log_printf(INFO,Direction,FUNCTION,_("<%s> Parameters"),_name.c_str());
+// #if DEBUG_Direction == true
+//     log_printf(INFO,Direction,FUNCTION,_("<%s> Parameters"),_name.c_str());
     std::cout << *param << std::endl;
 #endif
+//     std::cout << *param << std::endl;
+// #endif
     log_printf(INFO,Direction,FUNCTION,"Allocation");

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/src/Prediction_unit_Glue.cpp

-                      r110
+                      r123
     usage_environment(_usage);
 #if DEBUG_Prediction_unit_Glue == true
     log_printf(INFO,Prediction_unit_Glue,FUNCTION,_("<%s> Parameters"),_name.c_str());
     std::cout << *param << std::endl;
 #endif
+// #if DEBUG_Prediction_unit_Glue == true
+//     log_printf(INFO,Prediction_unit_Glue,FUNCTION,_("<%s> Parameters"),_name.c_str());
+//     std::cout << *param << std::endl;
+// #endif
     log_printf(INFO,Prediction_unit_Glue,FUNCTION,"Allocation");

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/src/Prediction_unit_Glue_genMealy_decod.cpp

-                      r110
+                      r123
           PORT_WRITE(out_DECOD_ACK [i][j], ack[j]);
+      }
+    else
+      {
+        // Reset
+        for (uint32_t i=0; i<_param->_nb_inst_branch_decod; i++)
+          {
+            PORT_WRITE(out_DECOD_BTB_VAL [i], 0);
+            PORT_WRITE(out_DECOD_RAS_VAL [i], 0);
+            PORT_WRITE(out_DECOD_UPT_VAL [i], 0);
+          }
+        for (uint32_t i=0; i<_param->_nb_decod_unit; i++)
+          for (uint32_t j=0; j<_param->_nb_inst_decod[i]; j++)
+            PORT_WRITE(out_DECOD_ACK [i][j], 0);
+      }
     log_end(Prediction_unit_Glue,FUNCTION);
   };

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/src/Prediction_unit_Glue_genMealy_predict.cpp

-                      r111
+                      r123
       PORT_WRITE(out_PREDICT_ACK[i],ack[i]);
+      }
+    else
+      {
+        // RESET
+        for (uint32_t i=0; i<_param->_nb_inst_branch_predict; i++)
+          {
+            PORT_WRITE(out_PREDICT_BTB_VAL [i], 0);
+            PORT_WRITE(out_PREDICT_DIR_VAL [i], 0);
+            PORT_WRITE(out_PREDICT_RAS_VAL [i], 0);
+            PORT_WRITE(out_PREDICT_UPT_VAL [i], 0);
+          }
+        for (uint32_t i=0; i<_param->_nb_context; i++)
+          PORT_WRITE(out_PREDICT_ACK[i],0);
+      }
     log_end(Prediction_unit_Glue,FUNCTION);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/src/Prediction_unit_Glue_genMealy_update.cpp

-                      r98
+                      r123
     log_function(Prediction_unit_Glue,FUNCTION,_name.c_str());
+    if (PORT_READ(in_NRESET))
+      {
     for (uint32_t i=0; i<_param->_nb_inst_branch_update; i++)
+      {
 …
         PORT_WRITE(out_UPDATE_UPT_ACK [i], upt_ack);
+      }
+      }
+    else
+      {
+        // RESET
+        for (uint32_t i=0; i<_param->_nb_inst_branch_update; i++)
+          {
+            PORT_WRITE(out_UPDATE_BTB_VAL [i], 0);
+            PORT_WRITE(out_UPDATE_DIR_VAL [i], 0);
+            PORT_WRITE(out_UPDATE_RAS_VAL [i], 0);
+            PORT_WRITE(out_UPDATE_UPT_ACK [i], 0);
+          }
+      }
     log_end(Prediction_unit_Glue,FUNCTION);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Return_Address_Stack.cpp

-                      r88
+                      r123
     log_printf(FUNC,Return_Address_Stack,FUNCTION,"Begin");
 #if DEBUG_Return_Address_Stac == true
     log_printf(INFO,Return_Address_Stac,FUNCTION,_("<%s> Parameters"),_name.c_str());
+// #if DEBUG_Return_Address_Stac == true
+//     log_printf(INFO,Return_Address_Stac,FUNCTION,_("<%s> Parameters"),_name.c_str());
     std::cout << *param << std::endl;
 #endif
+//     std::cout << *param << std::endl;
+// #endif
     log_printf(INFO,Return_Address_Stack,FUNCTION,"Allocation");

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Return_Address_Stack_genMealy_decod.cpp

r118	r123
66	66	}
67	67	}
	68	else
	69	{
	70	// internal_DECOD_HIT [i] = (push or (reg_NB_ELT[context]>0));
	71	}
	72
68	73	log_end(Return_Address_Stack,FUNCTION);
69	74	};

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Return_Address_Stack_genMealy_predict.cpp

-                      r118
+                      r123
     log_function(Return_Address_Stack,FUNCTION,_name.c_str());
     if (PORT_READ(in_NRESET) == 1)
+    if (PORT_READ(in_NRESET))
+      {
 #ifdef DEBUG_TEST
 …
+      }
+      }
+    else
+      {
+//     for (uint32_t i=0; i<_param->_nb_inst_predict; i++)
+//      internal_PREDICT_HIT [i] = (push or (reg_PREDICT_NB_ELT[context]>0));
+      }
     log_end(Return_Address_Stack,FUNCTION);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Types.h

-                      r122
+                      r123
       UPT_EVENT_STATE_KO_DECODE_WAIT_END_EVENT        , // prediction unit is ok, wait the end of event (send by Context State)
       UPT_EVENT_STATE_KO_COMMIT_UPDATE_CONTEXT        , // prediction unit is update, send signal to context manager
+      UPT_EVENT_STATE_KO_COMMIT_WAIT_END_EVENT          // prediction unit is ok, wait the end of event (send by Context State)
+      UPT_EVENT_STATE_KO_COMMIT_WAIT_END_EVENT        , // prediction unit is ok, wait the end of event (send by Context State)
+      UPT_EVENT_STATE_KO_COMMIT_WAIT_END_UPDATE         // prediction unit is ok, wait the end of event (send by Context State)
     } upt_event_state_t;
 …
       case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::UPT_EVENT_STATE_KO_COMMIT_UPDATE_CONTEXT  : return "UPT_EVENT_STATE_KO_COMMIT_UPDATE_CONTEXT"  ; break;
       case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::UPT_EVENT_STATE_KO_COMMIT_WAIT_END_EVENT  : return "UPT_EVENT_STATE_KO_COMMIT_WAIT_END_EVENT"  ; break;
+      case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::UPT_EVENT_STATE_KO_COMMIT_WAIT_END_UPDATE : return "UPT_EVENT_STATE_KO_COMMIT_WAIT_END_UPDATE" ; break;
       default    : return ""; break;
+      }

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table.cpp

-                      r111
+                      r123
     usage_environment(_usage);
 #if DEBUG_Update_Prediction_Table == true
     log_printf(INFO,Update_Prediction_Table,FUNCTION,_("<%s> Parameters"),_name.c_str());
     std::cout << *param << std::endl;
 #endif
+// #if DEBUG_Update_Prediction_Table == true
+//     log_printf(INFO,Update_Prediction_Table,FUNCTION,_("<%s> Parameters"),_name.c_str());
+//     std::cout << *param << std::endl;
+// #endif
     log_printf(INFO,Update_Prediction_Table,FUNCTION,"Allocation");

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_genMealy_branch_complete.cpp

-                      r122
+                      r123
     log_begin(Update_Prediction_Table,FUNCTION);
     log_function(Update_Prediction_Table,FUNCTION,_name.c_str());
+    if (PORT_READ(in_NRESET))
+      {
     for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++)
 #ifdef DEBUG_TEST
 …
 //      PORT_WRITE(out_BRANCH_COMPLETE_ADDRESS_DEST    [i], internal_BRANCH_COMPLETE_ADDRESS_DEST    [i]);
+      }
+      }
     log_end(Update_Prediction_Table,FUNCTION);
   };

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_genMealy_decod.cpp

-                      r122
+                      r123
+      }
+      }
+    else
+      {
+        // RESET
+        for (uint32_t i=0; i<_param->_nb_inst_decod; i++)
+          PORT_WRITE(out_DECOD_ACK          [i], 0);
+      }
     log_end(Update_Prediction_Table,FUNCTION);
   };

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_genMealy_predict.cpp

-                      r122
+                      r123
         log_printf(TRACE,Update_Prediction_Table,FUNCTION,"  * ACK         : %d",internal_PREDICT_ACK [i]);
-        PORT_WRITE(out_PREDICT_ACK                  [i], internal_PREDICT_ACK                  [i]);
         if (_param->_have_port_depth)
         PORT_WRITE(out_PREDICT_UPDATE_PREDICTION_ID [i], internal_PREDICT_UPDATE_PREDICTION_ID [i]);
 …
       }//don't reset
+    else
+      {
+        for (uint32_t i=0; i<_param->_nb_inst_predict; i++)
+          {
+            internal_PREDICT_ACK [i] = 0;
+//          internal_PREDICT_UPDATE_PREDICTION_ID [i] = top;
+          }
+      }
+    for (uint32_t i=0; i<_param->_nb_inst_predict; i++)
+      PORT_WRITE(out_PREDICT_ACK [i], internal_PREDICT_ACK [i]);
     log_end(Update_Prediction_Table,FUNCTION);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_genMoore.cpp

-                      r122
+                      r123
         internal_UPDATE_CONTEXT_ID      [i] = context;
-        PORT_WRITE(out_UPDATE_VAL                   [i],internal_UPDATE_VAL [i]);
         if (val)
+          {
 …
         Tcontrol_t val = ((reg_UPT_EVENT_STATE [i] == UPT_EVENT_STATE_KO_DECODE_UPDATE_CONTEXT) or
                           (reg_UPT_EVENT_STATE [i] == UPT_EVENT_STATE_KO_COMMIT_UPDATE_CONTEXT));
-        PORT_WRITE(out_BRANCH_EVENT_VAL              [i],val);
         if (_param->_have_port_depth)
         PORT_WRITE(out_BRANCH_EVENT_DEPTH            [i],reg_EVENT_DEPTH            [i]);
 …
             internal_UPDATE_VAL             [i] = 0;
             internal_UPDATE_VAL_WITHOUT_ACK [i] = 0;
+            internal_UPDATE_CONTEXT_ID      [i] = 0;
+          }
         for (uint32_t i=0; i<_param->_nb_context; i++)
 …
+      }
+    // Write output
+    for (uint32_t i=0; i<_param->_nb_inst_update; i++)
+      PORT_WRITE(out_UPDATE_VAL       [i],internal_UPDATE_VAL [i]);
+    for (uint32_t i=0; i<_param->_nb_context; i++)
+      PORT_WRITE(out_BRANCH_EVENT_VAL [i],internal_BRANCH_EVENT_VAL [i]);
     log_end(Update_Prediction_Table,FUNCTION);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_transition.cpp

-                      r122
+                      r123
+                        }
+                      // Test if freeing the branch with no accurate ?
+                      if ((reg_UPDATE_PREDICTION_TABLE [context][depth]._is_accurate == false) and not ko)
+                        reg_IS_ACCURATE [context] = true;
                       // Update pointer
                       //  * if update RAS : update pointer is decreaste until it equal at top pointer
 …
+                                }
-                              reg_UPT_EVENT_STATE [context] = upt_event_state;
+                            }
                           else
 …
+                        }
+                      // Test if freeing the branch with no accurate ?
+                      if ((reg_UPDATE_PREDICTION_TABLE [context][depth]._is_accurate == false) and not ko)
+                        reg_IS_ACCURATE [context] = true;
+                      // special case :
+                      if ((upt_event_state == UPT_EVENT_STATE_KO_COMMIT_WAIT_END_UPDATE) and
+                          (reg_UPT_UPDATE [context] == reg_EVENT_UPT_PTR [context]))
+                        {
+                          reg_UPT_TOP     [context] = reg_UPT_TOP_EVENT [context];
+                          reg_UPT_UPDATE  [context] = reg_UPT_TOP_EVENT [context];
+                          reg_IS_ACCURATE [context] = true;
+                          upt_event_state = UPT_EVENT_STATE_OK;
+                        }
+                      reg_UPT_EVENT_STATE [context] = upt_event_state;
                       log_printf(TRACE,Update_Prediction_Table,FUNCTION,"      * reg_UPT_UPDATE (after ) : %d",reg_UPT_UPDATE[context]);
 …
                         Taddress_t        address_src         = reg_UPDATE_PREDICTION_TABLE [context][depth]._address_src;
                         upt_state_t       event_top           = reg_UPDATE_PREDICTION_TABLE [context][top]._state;
+                        upt_state_t       top_state           = reg_UPDATE_PREDICTION_TABLE [context][top]._state;
                         log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * upt_event_state     : %s",toString(upt_event_state).c_str());
                         log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * event_top           : %s",toString(event_top).c_str());
+                        log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * top_state           : %s",toString(top_state).c_str());
                         bool              previous_ufpt_event = (reg_UFPT_EVENT_STATE [i] == UFPT_EVENT_STATE_KO_FLUSH);
 …
                                                                  or (upt_event_state == UPT_EVENT_STATE_KO_EVENT_WAIT_UFPT)
                                                                  or (upt_event_state == UPT_EVENT_STATE_KO_EVENT_FLUSH_UPT)
+                                                                 or (event_top       == UPDATE_PREDICTION_STATE_END_KO    )
+                                                                 or (event_top       == UPDATE_PREDICTION_STATE_KO        )
+                                                                 or (upt_event_state == UPT_EVENT_STATE_KO_COMMIT_WAIT_END_UPDATE)
+                                                                 or (top_state       == UPDATE_PREDICTION_STATE_END_KO    )
+                                                                 or (top_state       == UPDATE_PREDICTION_STATE_KO        )
                                                                  );
 …
                                 reg_UPDATE_PREDICTION_TABLE [context][top]._retire_ok = false;
                                 switch (event_top)
+                                switch (top_state)
+                                  {
                                   case UPDATE_PREDICTION_STATE_END_KO :
+                                  case UPDATE_PREDICTION_STATE_END    :
+                                    {
                                       // Have already update predictor
 …
                       case UPT_EVENT_STATE_KO_COMMIT_WAIT_END_EVENT :
+                        {
+                          Tdepth_t depth = reg_EVENT_UPT_PTR [i];
+                          Tdepth_t depth  = reg_EVENT_UPT_PTR [i];
+                          Tdepth_t update = reg_UPT_UPDATE    [i];
                           log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * depth : %d",depth);
 …
+                            }
+                            reg_UPT_TOP    [i] = reg_UPT_TOP_EVENT [i];
+                            reg_UPT_UPDATE [i] = reg_UPT_TOP_EVENT [i];
+                          // break; continue
+                          // Special case : branch_complete a speculative branch and the context_state signal the end of this event before the complete of previous branch
+                          if (depth != update)
+                            {
+                              log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * EVENT [%d] <- EVENT_STATE_COMMIT_WAIT_END_UPDATE (event)",i);
+                              upt_event_state = UPT_EVENT_STATE_KO_COMMIT_WAIT_END_UPDATE;
+                              break; // stop here
+                             }
+                          reg_UPT_TOP    [i] = reg_UPT_TOP_EVENT [i];
+                          reg_UPT_UPDATE [i] = reg_UPT_TOP_EVENT [i];
+//                             break; continue
+                        }
                       case UPT_EVENT_STATE_KO_DECODE_WAIT_END_EVENT :
 …
                     // Flush UPFT
                     flush_UFPT [i] = true;
+                    if (upt_event_state == UPT_EVENT_STATE_KO_COMMIT_WAIT_END_UPDATE)
+                      {
+                        reg_UPT_TOP     [i] = reg_UPT_TOP_EVENT [i];
+                        reg_UPT_UPDATE  [i] = reg_UPT_TOP_EVENT [i];
+                        reg_IS_ACCURATE [i] = true;
+                        upt_event_state = UPT_EVENT_STATE_OK;
+                      }
                     // Flush UPT
 …
                     reg_EVENT_UPT_PTR         [i] = top;
                     reg_EVENT_UPT_FULL        [i] = (not empty and (bottom == reg_UPT_TOP [i]));
+//                  reg_EVENT_DEPTH           [i] = PORT_READ(in_EVENT_DEPTH [i]);//(top+1)%_param->_size_upt_queue[i];
                     reg_EVENT_DEPTH           [i] = top;
 //                  reg_EVENT_ADDRESS_SRC     [i] = address_src; // delay_slot is compute in I_State
 //                  reg_EVENT_ADDRESS_DEST_VAL[i] = good_take;

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/src/Prediction_unit.cpp

-                      r88
+                      r123
     log_printf(FUNC,Prediction_unit,FUNCTION,"Begin");
 #if DEBUG_Prediction_unit == true
     log_printf(INFO,Prediction_unit,FUNCTION,_("<%s> Parameters"),_name.c_str());
+// #if DEBUG_Prediction_unit == true
+//     log_printf(INFO,Prediction_unit,FUNCTION,_("<%s> Parameters"),_name.c_str());
     std::cout << *param << std::endl;
 #endif
+//     std::cout << *param << std::endl;
+// #endif
     log_printf(INFO,Prediction_unit,FUNCTION,"Allocation");

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/include/Front_end.h

r108	r123
93	93	public : SC_OUT(Toperation_t ) ** out_DECOD_OPERATION ;//[sum_inst_decod]
94	94	public : SC_OUT(Tcontrol_t ) ** out_DECOD_NO_EXECUTE ;//[sum_inst_decod]
	95	//public : SC_OUT(Tcontrol_t ) ** out_DECOD_HAVE_EVENT ;//[sum_inst_decod]
	96	public : SC_OUT(Tcontrol_t ) ** out_DECOD_LAST_EVENT ;//[sum_inst_decod]
95	97	public : SC_OUT(Tcontrol_t ) ** out_DECOD_IS_DELAY_SLOT ;//[sum_inst_decod]
96	98	#ifdef DEBUG

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Front_end.cpp

-                      r88
+                      r123
     usage_environment(_usage);
 #if DEBUG_Core == true
     log_printf(INFO,Core,FUNCTION,_("<%s> Parameters"),_name.c_str());
+// #if DEBUG_Core == true
+//     log_printf(INFO,Core,FUNCTION,_("<%s> Parameters"),_name.c_str());
     std::cout << *param << std::endl;
 #endif
+//     std::cout << *param << std::endl;
+// #endif
     log_printf(INFO,Front_end,FUNCTION,_("<%s> : Allocation"),_name.c_str());

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Front_end_allocation.cpp

-                      r119
+                      r123
       ALLOC1_SIGNAL_OUT (out_DECOD_OPERATION                  ,"OPERATION"        ,Toperation_t         ,_param->_size_operation             );
       ALLOC1_SIGNAL_OUT (out_DECOD_NO_EXECUTE                 ,"NO_EXECUTE"       ,Tcontrol_t           ,1                                   );
+//    ALLOC1_SIGNAL_OUT (out_DECOD_HAVE_EVENT                 ,"HAVE_EVENT"       ,Tcontrol_t           ,1                                   );
+      ALLOC1_SIGNAL_OUT (out_DECOD_LAST_EVENT                 ,"LAST_EVENT"       ,Tcontrol_t           ,1                                   );
       ALLOC1_SIGNAL_OUT (out_DECOD_IS_DELAY_SLOT              ,"IS_DELAY_SLOT"    ,Tcontrol_t           ,1                                   );
 #ifdef DEBUG
 …
           PORT_MAP(_component,src ,"out_DECOD_"+toString(j)+"_NO_EXECUTE"   ,
                               dest,"out_DECOD_"+toString(x)+"_NO_EXECUTE"   );
+//           PORT_MAP(_component,src ,"out_DECOD_"+toString(j)+"_HAVE_EVENT"   ,
+//                               dest,"out_DECOD_"+toString(x)+"_HAVE_EVENT"   );
+          PORT_MAP(_component,src ,"out_DECOD_"+toString(j)+"_LAST_EVENT"   ,
+                              dest,"out_DECOD_"+toString(x)+"_LAST_EVENT"   );
           PORT_MAP(_component,src ,"out_DECOD_"+toString(j)+"_IS_DELAY_SLOT",
                               dest,"out_DECOD_"+toString(x)+"_IS_DELAY_SLOT");
 …
           COMPONENT_MAP(_component,src , "in_CONTEXT_"+toString(j)+"_DECOD_ENABLE",
                                    dest,"out_CONTEXT_"+toString(y)+"_DECOD_ENABLE");
+          COMPONENT_MAP(_component,src , "in_CONTEXT_"+toString(j)+"_EVENT",
+                                   dest,"out_CONTEXT_"+toString(y)+"_EVENT");
           dest = _name+"_glue";

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Front_end_deallocation.cpp

-                      r122
+                      r123
         DELETE1_SIGNAL(out_DECOD_TYPE                       ,_param->_sum_inst_decod,_param->_size_type                  );
         DELETE1_SIGNAL(out_DECOD_OPERATION                  ,_param->_sum_inst_decod,_param->_size_operation             );
+        DELETE1_SIGNAL(out_DECOD_NO_EXECUTE                 ,_param->_sum_inst_decod,1                                   );
+        DELETE1_SIGNAL(out_DECOD_NO_EXECUTE                 ,_param->_sum_inst_decod,1                                   );
+//      DELETE1_SIGNAL(out_DECOD_HAVE_EVENT                 ,_param->_sum_inst_decod,1                                   );
+        DELETE1_SIGNAL(out_DECOD_LAST_EVENT                 ,_param->_sum_inst_decod,1                                   );
         DELETE1_SIGNAL(out_DECOD_IS_DELAY_SLOT              ,_param->_sum_inst_decod,1                                   );
 #ifdef DEBUG

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h

-                      r122
+                      r123
   public    : SC_IN (Toperation_t       ) ***  in_INSERT_OPERATION                 ;//[nb_rename_unit][nb_inst_insert]
   public    : SC_IN (Tcontrol_t         ) ***  in_INSERT_NO_EXECUTE                ;//[nb_rename_unit][nb_inst_insert]
+  public    : SC_IN (Tcontrol_t         ) ***  in_INSERT_LAST_EVENT                ;//[nb_rename_unit][nb_inst_insert]
   public    : SC_IN (Tcontrol_t         ) ***  in_INSERT_IS_DELAY_SLOT             ;//[nb_rename_unit][nb_inst_insert]
 #ifdef DEBUG
 …
   public    : SC_IN (Tcontrol_t         ) ***  in_RETIRE_EVENT_ACK                 ;//[nb_front_end][nb_context]
   public    : SC_OUT(Tevent_state_t     ) *** out_RETIRE_EVENT_STATE               ;//[nb_front_end][nb_context]
   public    : SC_OUT(Tcontrol_t         ) *** out_RETIRE_EVENT_FLUSH               ;//[nb_front_end][nb_context]
+//public    : SC_OUT(Tcontrol_t         ) *** out_RETIRE_EVENT_FLUSH               ;//[nb_front_end][nb_context]
   public    : SC_OUT(Tcontrol_t         ) *** out_RETIRE_EVENT_STOP                ;//[nb_front_end][nb_context]
 …
   public    : SC_OUT(Tcontrol_t         ) *** out_SPR_WRITE_SR_OV                  ;//[nb_front_end][nb_context]
+    // ~~~~~[ interface : "info" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+#ifdef DEBUG_TEST
+  public    : SC_OUT(bool               )   * out_INFO_ROB_EMPTY                   ;
+#endif
     // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   private   : generic::priority::Priority   * _priority_insert                     ;
 …
   private   : Tcommit_event_state_t        ** reg_EVENT_STATE                      ;//[nb_front_end][nb_context]
 //private   : bool                         ** reg_EVENT_FLUSH                      ;//[nb_front_end][nb_context]
   private   : bool                         ** reg_EVENT_STOP                       ;//[nb_front_end][nb_context]
+//private   : bool                         ** reg_EVENT_STOP                       ;//[nb_front_end][nb_context]
   private   : uint32_t                     ** reg_EVENT_NUM_BANK                   ;//[nb_front_end][nb_context]
   private   : uint32_t                     ** reg_EVENT_NUM_PTR                    ;//[nb_front_end][nb_context]
   private   : bool                         ** reg_EVENT_CAN_RESTART                ;//[nb_front_end][nb_context]
+//private   : bool                         ** reg_EVENT_CAN_RESTART                ;//[nb_front_end][nb_context]
   private   : uint32_t                     ** reg_EVENT_PACKET                     ;//[nb_front_end][nb_context]
   private   : bool                         ** reg_EVENT_LAST                       ;//[nb_front_end][nb_context]
   private   : uint32_t                     ** reg_EVENT_LAST_NUM_BANK              ;//[nb_front_end][nb_context]
   private   : uint32_t                     ** reg_EVENT_LAST_NUM_PTR               ;//[nb_front_end][nb_context]
+  private   : bool                         ** reg_EVENT_NEXT_STOP                  ;//[nb_front_end][nb_context]
+  private   : uint32_t                     ** reg_EVENT_NEXT_PACKET                ;//[nb_front_end][nb_context]
 //private   : Taddress_t                   ** reg_PC_PREVIOUS                      ;//[nb_front_end][nb_context]

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Types.h

-                      r122
+                      r123
   typedef enum
+    {
+      COMMIT_EVENT_STATE_NO_EVENT  ,
+      COMMIT_EVENT_STATE_EVENT     ,
+      COMMIT_EVENT_STATE_WAIT_DECOD,
+      COMMIT_EVENT_STATE_WAIT_END  ,
+      COMMIT_EVENT_STATE_NO_EVENT     ,
+      COMMIT_EVENT_STATE_NOT_YET_EVENT,
+      COMMIT_EVENT_STATE_EVENT        ,
+//    COMMIT_EVENT_STATE_WAIT_DECOD   ,
+      COMMIT_EVENT_STATE_WAIT_END     ,
       COMMIT_EVENT_STATE_END
     } Tcommit_event_state_t;
+#define commit_event_state_to_event_state(x) ((x==COMMIT_EVENT_STATE_EVENT)?EVENT_STATE_EVENT:((x==COMMIT_EVENT_STATE_WAIT_DECOD)?EVENT_STATE_WAITEND:((x==COMMIT_EVENT_STATE_WAIT_END)?EVENT_STATE_WAITEND:((x==COMMIT_EVENT_STATE_END)?EVENT_STATE_END:EVENT_STATE_NO_EVENT))))
+#define commit_event_state_to_event_state(x) ((x==COMMIT_EVENT_STATE_EVENT)?EVENT_STATE_EVENT:((x==COMMIT_EVENT_STATE_WAIT_END)?EVENT_STATE_WAITEND:((x==COMMIT_EVENT_STATE_END)?EVENT_STATE_END:EVENT_STATE_NO_EVENT)))
+// #define commit_event_state_to_event_state(x) ((x==COMMIT_EVENT_STATE_EVENT)?EVENT_STATE_EVENT:((x==COMMIT_EVENT_STATE_WAIT_DECOD)?EVENT_STATE_WAITEND:((x==COMMIT_EVENT_STATE_WAIT_END)?EVENT_STATE_WAITEND:((x==COMMIT_EVENT_STATE_END)?EVENT_STATE_END:EVENT_STATE_NO_EVENT))))
 …
       case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_STORE_OK_WAIT_END          : return "ROB_STORE_OK_WAIT_END"           ; break;
       case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_STORE_KO_WAIT_END          : return "ROB_STORE_KO_WAIT_END"           ; break;
+      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_STORE_EVENT                : return "ROB_STORE_EVENT"                 ; break;
       case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_OTHER_WAIT_END             : return "ROB_OTHER_WAIT_END"              ; break;
       case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_EVENT_WAIT_END             : return "ROB_EVENT_WAIT_END"              ; break;

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit.cpp

-                      r121
+                      r123
     usage_environment(_usage);
 #if DEBUG_Commit_unit == true
     log_printf(TRACE,Commit_unit,FUNCTION,_("<%s> Parameters"),_name.c_str());
     std::cout << *param << std::endl;
 #endif
+// #if DEBUG_Commit_unit == true
+//     log_printf(TRACE,Commit_unit,FUNCTION,_("<%s> Parameters"),_name.c_str());
+//     std::cout << *param << std::endl;
+// #endif
     log_printf(INFO,Commit_unit,FUNCTION,_("<%s> Allocation"),_name.c_str());

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_allocation.cpp

-                      r122
+                      r123
       _ALLOC2_SIGNAL_IN ( in_INSERT_OPERATION               ,"operation"            ,Toperation_t      ,_param->_size_operation             ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
       _ALLOC2_SIGNAL_IN ( in_INSERT_NO_EXECUTE              ,"no_execute"           ,Tcontrol_t        ,1                                   ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
+      _ALLOC2_SIGNAL_IN ( in_INSERT_LAST_EVENT              ,"last_event"           ,Tcontrol_t        ,1                                   ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
       _ALLOC2_SIGNAL_IN ( in_INSERT_IS_DELAY_SLOT           ,"is_delay_slot"        ,Tcontrol_t        ,1                                   ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);
 #ifdef DEBUG
 …
       _ALLOC2_VALACK_IN ( in_RETIRE_EVENT_ACK               ,ACK,_param->_nb_front_end,_param->_nb_context[it1]);
       _ALLOC2_SIGNAL_OUT(out_RETIRE_EVENT_STATE             ,"state"                ,Tevent_state_t    ,_param->_size_event_state           ,_param->_nb_front_end,_param->_nb_context[it1]);
       _ALLOC2_SIGNAL_OUT(out_RETIRE_EVENT_FLUSH             ,"flush"                ,Tcontrol_t        ,1                                   ,_param->_nb_front_end,_param->_nb_context[it1]);
+//    _ALLOC2_SIGNAL_OUT(out_RETIRE_EVENT_FLUSH             ,"flush"                ,Tcontrol_t        ,1                                   ,_param->_nb_front_end,_param->_nb_context[it1]);
       _ALLOC2_SIGNAL_OUT(out_RETIRE_EVENT_STOP              ,"stop"                 ,Tcontrol_t        ,1                                   ,_param->_nb_front_end,_param->_nb_context[it1]);
 …
+    }
+#ifdef DEBUG_TEST
+    {
+      ALLOC0_INTERFACE_BEGIN("info",OUT,EAST,_("Information."));
+      ALLOC0_SIGNAL_OUT(out_INFO_ROB_EMPTY                   ,"rob_empty"   ,bool               ,1);
+      ALLOC0_INTERFACE_END();
+    }
+#endif
     if (usage_is_set(_usage,USE_SYSTEMC))
+      {
 …
     ALLOC2(reg_EVENT_STATE          ,Tcommit_event_state_t,_param->_nb_front_end,_param->_nb_context [it1]);
 //  ALLOC2(reg_EVENT_FLUSH          ,bool                 ,_param->_nb_front_end,_param->_nb_context [it1]);
     ALLOC2(reg_EVENT_STOP           ,bool                 ,_param->_nb_front_end,_param->_nb_context [it1]);
+//  ALLOC2(reg_EVENT_STOP           ,bool                 ,_param->_nb_front_end,_param->_nb_context [it1]);
     ALLOC2(reg_EVENT_NUM_BANK       ,uint32_t             ,_param->_nb_front_end,_param->_nb_context [it1]);
     ALLOC2(reg_EVENT_NUM_PTR        ,uint32_t             ,_param->_nb_front_end,_param->_nb_context [it1]);
     ALLOC2(reg_EVENT_CAN_RESTART    ,bool                 ,_param->_nb_front_end,_param->_nb_context [it1]);
+//  ALLOC2(reg_EVENT_CAN_RESTART    ,bool                 ,_param->_nb_front_end,_param->_nb_context [it1]);
     ALLOC2(reg_EVENT_PACKET         ,uint32_t             ,_param->_nb_front_end,_param->_nb_context [it1]);
     ALLOC2(reg_EVENT_LAST           ,bool                 ,_param->_nb_front_end,_param->_nb_context [it1]);
     ALLOC2(reg_EVENT_LAST_NUM_BANK  ,uint32_t             ,_param->_nb_front_end,_param->_nb_context [it1]);
     ALLOC2(reg_EVENT_LAST_NUM_PTR   ,uint32_t             ,_param->_nb_front_end,_param->_nb_context [it1]);
+    ALLOC2(reg_EVENT_NEXT_STOP      ,bool                 ,_param->_nb_front_end,_param->_nb_context [it1]);
+    ALLOC2(reg_EVENT_NEXT_PACKET    ,uint32_t             ,_param->_nb_front_end,_param->_nb_context [it1]);
 //  ALLOC2(reg_PC_PREVIOUS          ,Taddress_t           ,_param->_nb_front_end,_param->_nb_context [it1]);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_deallocation.cpp

-                      r122
+                      r123
         DELETE2_SIGNAL( in_INSERT_OPERATION               ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_operation             );
         DELETE2_SIGNAL( in_INSERT_NO_EXECUTE              ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1                                   );
+        DELETE2_SIGNAL( in_INSERT_LAST_EVENT              ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1                                   );
         DELETE2_SIGNAL( in_INSERT_IS_DELAY_SLOT           ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1                                   );
 #ifdef DEBUG
 …
         DELETE2_SIGNAL( in_RETIRE_EVENT_ACK               ,_param->_nb_front_end,_param->_nb_context[it1],1);
         DELETE2_SIGNAL(out_RETIRE_EVENT_STATE             ,_param->_nb_front_end,_param->_nb_context[it1],_param->_size_event_state);
         DELETE2_SIGNAL(out_RETIRE_EVENT_FLUSH             ,_param->_nb_front_end,_param->_nb_context[it1],1);
+//      DELETE2_SIGNAL(out_RETIRE_EVENT_FLUSH             ,_param->_nb_front_end,_param->_nb_context[it1],1);
         DELETE2_SIGNAL(out_RETIRE_EVENT_STOP              ,_param->_nb_front_end,_param->_nb_context[it1],1);
 …
         DELETE2_SIGNAL(out_SPR_WRITE_SR_OV                ,_param->_nb_front_end, _param->_nb_context[it1],1);
+        DELETE0_SIGNAL(out_INFO_ROB_EMPTY                 ,1);
         // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
         DELETE1(internal_BANK_INSERT_VAL             ,_param->_nb_bank);
 …
         DELETE2(reg_EVENT_STATE          ,_param->_nb_front_end,_param->_nb_context [it1]);
 //      DELETE2(reg_EVENT_FLUSH          ,_param->_nb_front_end,_param->_nb_context [it1]);
         DELETE2(reg_EVENT_STOP           ,_param->_nb_front_end,_param->_nb_context [it1]);
+//      DELETE2(reg_EVENT_STOP           ,_param->_nb_front_end,_param->_nb_context [it1]);
         DELETE2(reg_EVENT_NUM_BANK       ,_param->_nb_front_end,_param->_nb_context [it1]);
         DELETE2(reg_EVENT_NUM_PTR        ,_param->_nb_front_end,_param->_nb_context [it1]);
         DELETE2(reg_EVENT_CAN_RESTART    ,_param->_nb_front_end,_param->_nb_context [it1]);
+//         DELETE2(reg_EVENT_CAN_RESTART    ,_param->_nb_front_end,_param->_nb_context [it1]);
         DELETE2(reg_EVENT_PACKET         ,_param->_nb_front_end,_param->_nb_context [it1]);
         DELETE2(reg_EVENT_LAST           ,_param->_nb_front_end,_param->_nb_context [it1]);
         DELETE2(reg_EVENT_LAST_NUM_BANK  ,_param->_nb_front_end,_param->_nb_context [it1]);
         DELETE2(reg_EVENT_LAST_NUM_PTR   ,_param->_nb_front_end,_param->_nb_context [it1]);
+        DELETE2(reg_EVENT_NEXT_STOP      ,_param->_nb_front_end,_param->_nb_context [it1]);
+        DELETE2(reg_EVENT_NEXT_PACKET    ,_param->_nb_front_end,_param->_nb_context [it1]);
 //      DELETE2(reg_PC_PREVIOUS          ,_param->_nb_front_end,_param->_nb_context [it1]);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_commit.cpp

-                      r119
+                      r123
     log_begin(Commit_unit,FUNCTION);
     log_function(Commit_unit,FUNCTION,_name.c_str());
+    if (PORT_READ(in_NRESET))
+      {
 #ifdef STATISTICS
 …
     for (uint32_t i=0; i<_param->_nb_inst_commit; i++)
       PORT_WRITE(out_COMMIT_ACK [i],commit_ack [i]);
+      }
+    else
+      {
+        for (uint32_t i=0; i<_param->_nb_inst_commit; i++)
+          PORT_WRITE(out_COMMIT_ACK [i],0);
+      }
     log_end(Commit_unit,FUNCTION);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_insert.cpp

-                      r122
+                      r123
     log_function(Commit_unit,FUNCTION,_name.c_str());
+    if (PORT_READ(in_NRESET))
+      {
     Tcontrol_t bank_full         [_param->_nb_bank];
     Tcontrol_t insert_ack        [_param->_nb_rename_unit][_param->_max_nb_inst_insert];
 …
 #endif
+        }
+      }
+    else
+      {
+        for (uint32_t i=0; i<_param->_nb_bank; i++)
+          internal_BANK_INSERT_VAL  [i] = false;
+        for (uint32_t i=0; i<_param->_nb_rename_unit; i++)
+          for (uint32_t j=0; j<_param->_nb_inst_insert[i]; j++)
+            PORT_WRITE(out_INSERT_ACK       [i][j],0);
+      }
     log_end(Commit_unit,FUNCTION);
   };

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_retire.cpp

-                      r122
+                      r123
     log_function(Commit_unit,FUNCTION,_name.c_str());
+    if (PORT_READ(in_NRESET))
+      {
     Tcontrol_t retire_val          [_param->_nb_rename_unit][_param->_max_nb_inst_retire];
     uint32_t   num_inst_retire     [_param->_nb_rename_unit];
 …
                   // if future event, don't update after this event
                   if (reg_EVENT_STOP [front_end_id][context_id] and
                       (reg_EVENT_PACKET [entry->front_end_id][entry->context_id]  == packet))
+                  if ((reg_EVENT_STATE  [entry->front_end_id][entry->context_id] == COMMIT_EVENT_STATE_NOT_YET_EVENT) and
+                      (reg_EVENT_PACKET [entry->front_end_id][entry->context_id] == packet))
                     bypass = false;
+              }
 …
           PORT_WRITE(out_SPR_WRITE_SR_OV     [i][j], spr_write_sr_ov     [i][j]);
+        }
+      }
+    else
+      {
+        for (uint32_t i=0; i<_param->_nb_rename_unit; i++)
+          for (uint32_t j=0; j<_param->_nb_inst_retire[i]; j++)
+            PORT_WRITE(out_RETIRE_VAL [i][j],0);
+      }
     log_end(Commit_unit,FUNCTION);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMoore.cpp

-                      r122
+                      r123
     log_function(Commit_unit,FUNCTION,_name.c_str());
+    if (PORT_READ(in_NRESET))
+      {
     // ===================================================================
     // =====[ REEXECUTE ]=================================================
 …
           internal_REEXECUTE_VAL      [i] = val;
-          PORT_WRITE(out_REEXECUTE_VAL[i], internal_REEXECUTE_VAL [i]);
+        }
+    }
 …
                   // don't complete a branch when rob manage an present event
+                  if ((reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_NO_EVENT) and
+                  if (((reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_NO_EVENT) or
+                       (reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_NOT_YET_EVENT)) and
                       (state == ROB_BRANCH_COMPLETE))
+                    {
 …
                       // test if have a future event (stop is set)
                       log_printf(TRACE,Commit_unit,FUNCTION,"      * reg_EVENT_STOP   : %d",reg_EVENT_STOP [front_end_id][context_id]);
                       if (reg_EVENT_STOP [front_end_id][context_id])
+//                       log_printf(TRACE,Commit_unit,FUNCTION,"      * reg_EVENT_STOP   : %d",reg_EVENT_STOP [front_end_id][context_id]);
+                      if (reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_NOT_YET_EVENT)
+                        {
                           // Have future event, can complete the branch if the event is most speculative than this branchement
 …
           internal_BRANCH_COMPLETE_VAL [i] = val;
-          PORT_WRITE(out_BRANCH_COMPLETE_VAL [i], internal_BRANCH_COMPLETE_VAL [i]);
+        }
+    }
 …
+        }
-      PORT_WRITE(out_UPDATE_VAL, internal_UPDATE_VAL);
       log_printf(TRACE,Commit_unit,FUNCTION,"  * UPDATE (end)");
+    }
 …
     // =====[ NB_INST ]===================================================
     // ===================================================================
+    for (uint32_t i=0; i<_param->_nb_front_end; i++)
+      for (uint32_t j=0; j<_param->_nb_context [i]; j++)
+        {
+          PORT_WRITE(out_NB_INST_COMMIT_ALL [i][j], reg_NB_INST_COMMIT_ALL [i][j]);
+          PORT_WRITE(out_NB_INST_COMMIT_MEM [i][j], reg_NB_INST_COMMIT_MEM [i][j]);
+        }
+    {
+#ifdef DEBUG_TEST
+      bool empty = true;
+#endif
+      for (uint32_t i=0; i<_param->_nb_front_end; i++)
+        for (uint32_t j=0; j<_param->_nb_context [i]; j++)
+          {
+#ifdef DEBUG_TEST
+            empty &= (reg_NB_INST_COMMIT_ALL [i][j] == 0);
+#endif
+            PORT_WRITE(out_NB_INST_COMMIT_ALL [i][j], reg_NB_INST_COMMIT_ALL [i][j]);
+            PORT_WRITE(out_NB_INST_COMMIT_MEM [i][j], reg_NB_INST_COMMIT_MEM [i][j]);
+          }
+#ifdef DEBUG_TEST
+      PORT_WRITE(out_INFO_ROB_EMPTY,empty);
+#endif
+    }
     // ===================================================================
 …
       for (uint32_t j=0; j<_param->_nb_context [i]; j++)
+        {
+//        bool flush = reg_EVENT_FLUSH [i][j];
+          bool flush = (((reg_EVENT_STATE [i][j] == COMMIT_EVENT_STATE_EVENT) or
+                         (reg_EVENT_STATE [i][j] == COMMIT_EVENT_STATE_WAIT_DECOD)) and
+                        not reg_EVENT_CAN_RESTART[i][j]);
+//           bool flush = (((reg_EVENT_STATE [i][j] == COMMIT_EVENT_STATE_EVENT) or
+//                          (reg_EVENT_STATE [i][j] == COMMIT_EVENT_STATE_WAIT_DECOD)) and
+//                         not reg_EVENT_CAN_RESTART[i][j]);
           PORT_WRITE(out_RETIRE_EVENT_STATE [i][j], commit_event_state_to_event_state(reg_EVENT_STATE[i][j]));
+          PORT_WRITE(out_RETIRE_EVENT_FLUSH [i][j], flush);
+          PORT_WRITE(out_RETIRE_EVENT_STOP  [i][j], reg_EVENT_STOP [i][j]);
+//        PORT_WRITE(out_RETIRE_EVENT_FLUSH [i][j], flush);
+//        PORT_WRITE(out_RETIRE_EVENT_STOP  [i][j], reg_EVENT_STOP [i][j]);
+          PORT_WRITE(out_RETIRE_EVENT_STOP  [i][j], ((reg_EVENT_STATE [i][j] == COMMIT_EVENT_STATE_NOT_YET_EVENT) or
+                                                     reg_EVENT_NEXT_STOP [i][j]));
+        }
+      }
+    else
+      {
+        for (uint32_t i=0; i<_param->_nb_inst_reexecute; ++i)
+          {
+            internal_REEXECUTE_VAL      [i] = 0;
+//             internal_REEXECUTE_NUM_BANK [i] = num_bank;
+          }
+        for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++)
+          {
+            internal_BRANCH_COMPLETE_VAL [i] = 0;
+//             internal_BRANCH_COMPLETE_NUM_BANK           [i] = num_bank;
+          }
+        internal_UPDATE_VAL = 0;
+//       internal_UPDATE_NUM_BANK = reg_NUM_BANK_HEAD;
+        for (uint32_t i=0; i<_param->_nb_front_end; i++)
+          for (uint32_t j=0; j<_param->_nb_context [i]; j++)
+            {
+              PORT_WRITE(out_RETIRE_EVENT_STATE [i][j], commit_event_state_to_event_state(COMMIT_EVENT_STATE_NO_EVENT));
+//            PORT_WRITE(out_RETIRE_EVENT_FLUSH [i][j], flush);
+//            PORT_WRITE(out_RETIRE_EVENT_STOP  [i][j], reg_EVENT_STOP [i][j]);
+              PORT_WRITE(out_RETIRE_EVENT_STOP  [i][j], true);
+            }
+      }
+      for (uint32_t i=0; i<_param->_nb_inst_reexecute; ++i)
+        PORT_WRITE(out_REEXECUTE_VAL[i], internal_REEXECUTE_VAL [i]);
+      for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++)
+        PORT_WRITE(out_BRANCH_COMPLETE_VAL [i], internal_BRANCH_COMPLETE_VAL [i]);
+      PORT_WRITE(out_UPDATE_VAL, internal_UPDATE_VAL);
     log_end(Commit_unit,FUNCTION);
   };

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp

-                      r122
+                      r123
               reg_EVENT_STATE           [i][j] = COMMIT_EVENT_STATE_NO_EVENT;
 //            reg_EVENT_FLUSH           [i][j] = false;
               reg_EVENT_STOP            [i][j] = false;
+//            reg_EVENT_STOP            [i][j] = false;
               reg_EVENT_LAST            [i][j] = false;
+              reg_EVENT_NEXT_STOP       [i][j] = false;
 //            reg_PC_PREVIOUS           [i][j] = (0x100-4)>>2;
 …
               //   * and decod_queue is empty
               //   * and have an event or have a futur event
               if (not reg_EVENT_CAN_RESTART [i][j] and
                    (PORT_READ(in_NB_INST_DECOD_ALL [i][j]) == 0) and
                    (reg_EVENT_STOP [i][j] or (reg_EVENT_STATE [i][j] != COMMIT_EVENT_STATE_NO_EVENT)))
                 reg_EVENT_CAN_RESTART [i][j] = true;
+//               if (not reg_EVENT_CAN_RESTART [i][j] and
+//                    (PORT_READ(in_NB_INST_DECOD_ALL [i][j]) == 0) and
+//                    (reg_EVENT_STOP [i][j] or (reg_EVENT_STATE [i][j] != COMMIT_EVENT_STATE_NO_EVENT)))
+//                 reg_EVENT_CAN_RESTART [i][j] = true;
               // Test event state
 …
+                      {
                         // A minor optimisation : test if wait_decod is previously empty.
                         if (not reg_EVENT_CAN_RESTART [i][j])
                           reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_WAIT_DECOD;
                         else
+//                         if (not reg_EVENT_CAN_RESTART [i][j])
+//                           reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_WAIT_DECOD;
+//                         else
                           reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_WAIT_END;
+                      }
 …
                     break;
+                  }
                 case COMMIT_EVENT_STATE_WAIT_DECOD :
+                  {
                     // Wait flush of decod_queue.
                     // Test if can restart now
                     if (reg_EVENT_CAN_RESTART [i][j])
+                      {
                         //reg_EVENT_FLUSH [i][j] = false;
                         // A minor optimisation : test if the last element is already retire
                         if (not reg_EVENT_LAST [i][j])
                           reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_WAIT_END;
                         else
                           reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_END;
+                      }
                     break;
+                  }
+//                 case COMMIT_EVENT_STATE_WAIT_DECOD :
+//                   {
+//                     // Wait flush of decod_queue.
+//                     // Test if can restart now
+//                     if (reg_EVENT_CAN_RESTART [i][j])
+//                       {
+//                         //reg_EVENT_FLUSH [i][j] = false;
+//                         // A minor optimisation : test if the last element is already retire
+//                         if (not reg_EVENT_LAST [i][j])
+//                           reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_WAIT_END;
+//                         else
+//                           reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_END;
+//                       }
+//                     break;
+//                   }
                 case COMMIT_EVENT_STATE_WAIT_END :
+                  {
 …
                     // flush of re order buffer is finish
-                    reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_NO_EVENT;
                     reg_EVENT_LAST  [i][j] = false;
+                    if (not reg_EVENT_NEXT_STOP [i][j])
+                      reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_NO_EVENT;
+                    else
+                      {
+                        reg_EVENT_NEXT_STOP [i][j] = false;
+                        reg_EVENT_PACKET [i][j] = reg_EVENT_NEXT_PACKET [i][j];
+                        reg_EVENT_STATE         [i][j] = COMMIT_EVENT_STATE_NOT_YET_EVENT;
+//                      reg_EVENT_STOP          [i][j] = true;
+                        reg_EVENT_LAST_NUM_BANK [i][j] = ((reg_NUM_BANK_TAIL==0)?_param->_nb_bank:reg_NUM_BANK_TAIL)-1;
+                        reg_EVENT_LAST_NUM_PTR  [i][j] = reg_NUM_PTR_TAIL;
+                      }
                     break;
+                  }
                   //case COMMIT_EVENT_STATE_NO_EVENT :
+                  //case COMMIT_EVENT_STATE_NOT_YET_EVENT :
                 default : break;
+                }
 …
                       //     * or present_event
                       //   * and not can_restart (previous empty decod queue), because between the event_stop (branch_complete) and the state event (miss in head), many cycle is occured.
+                      bool flush = ((// present event
+                                     ((reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_EVENT) or
+                                      (reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_WAIT_DECOD)) or
+                                     // futur event
+                                     reg_EVENT_STOP [front_end_id][context_id])
+                                    // can't restart
+                                    and not reg_EVENT_CAN_RESTART[front_end_id][context_id]
+                                    );
+                      if (flush)
+                        {
+                          // A new invalid instruction is push in rob -> new last instruction
+                          reg_EVENT_LAST          [front_end_id][context_id] = false;
+                          reg_EVENT_LAST_NUM_BANK [front_end_id][context_id] = num_bank;
+                          reg_EVENT_LAST_NUM_PTR  [front_end_id][context_id] = ptr;
+                        }
+//                       bool flush = ((// present event
+//                                      ((reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_EVENT) or
+//                                       (reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_WAIT_DECOD)
+//                                       ) or
+//                                      futur event
+//                                      reg_EVENT_STOP [front_end_id][context_id])
+//                                     // can't restart
+//                                     and not reg_EVENT_CAN_RESTART[front_end_id][context_id]
+//                                     );
+//                       if (flush)
+//                         {
+//                           // A new invalid instruction is push in rob -> new last instruction
+//                           reg_EVENT_LAST          [front_end_id][context_id] = false;
+//                           reg_EVENT_LAST_NUM_BANK [front_end_id][context_id] = num_bank;
+//                           reg_EVENT_LAST_NUM_PTR  [front_end_id][context_id] = ptr;
+//                         }
                       // Update pointer
 …
                     // find the good entry !!!
                     entry_t *       entry        = internal_BANK_COMMIT_ENTRY [i][j];
+                    log_printf(TRACE,Commit_unit,FUNCTION,"    * ptr        : %d",entry->ptr);
                   //Toperation_t    operation    = PORT_READ(in_COMMIT_OPERATION   [x]);
 …
                     // Commit an instruction ...
+                    // Test if have an event (miss_speculation or exception) and not manage a previous event
+                    // if yes, this instruction would modify state machine. Also stop Re Order Buffer
+//                  bool flush = reg_EVENT_FLUSH [entry->front_end_id][entry->context_id];
+                    bool flush = ((reg_EVENT_STATE [entry->front_end_id][entry->context_id] == COMMIT_EVENT_STATE_EVENT) or
+                                  (reg_EVENT_STATE [entry->front_end_id][entry->context_id] == COMMIT_EVENT_STATE_WAIT_DECOD) or
+                                  (reg_EVENT_STATE [entry->front_end_id][entry->context_id] == COMMIT_EVENT_STATE_WAIT_END));
+                    if ((have_exception or have_miss_speculation) and (not flush))
+                    // Test if have an event (miss_speculation or exception)
+                    if (have_exception or have_miss_speculation)
+                      {
+                        // Two case :
+                        // if no previous manage event -> generate an event
+                        // if    previous manage event -> next generate an event
+//                      bool flush = reg_EVENT_FLUSH [front_end_id][context_id];
+                        bool flush = ((reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_EVENT) or
+//                                    (reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_WAIT_DECOD) or
+                                      (reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_WAIT_END) or
+                                      (reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_END)
+                                      );
                         uint32_t packet = ((entry->ptr << _param->_shift_num_slot) | i);
+                        // test have a previous event detected (event_stop = 1)
+                        // if yes, test if the actual event if "before (in order)" that the previous event
+                        if (reg_EVENT_STOP [entry->front_end_id][entry->context_id])
+                        uint32_t _top   = ((_rob[ reg_NUM_BANK_HEAD].front()->ptr << _param->_shift_num_slot) | reg_NUM_BANK_HEAD);
+                        if (not flush)
+                          {
+                            // Compare packet_id (by construction instruction is insert in order by increase packet_id)
+                            uint32_t _top = ((_rob[ reg_NUM_BANK_HEAD].front()->ptr << _param->_shift_num_slot) | reg_NUM_BANK_HEAD);
+                            uint32_t _old = reg_EVENT_PACKET [entry->front_end_id][entry->context_id];
+                            uint32_t _new = packet;
+                            if (_old < _top) _old = _old+_param->_size_queue;
+                            if (_new < _top) _new = _new+_param->_size_queue;
+                            if (_new < _old) reg_EVENT_PACKET [entry->front_end_id][entry->context_id] = packet;
+                            bool     can    = true;
+                            // test have a previous event detected (event_stop = 1)
+                            // if yes, test if the actual event if "before (in order)" that the previous event
+                            if (reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_NOT_YET_EVENT)
+                              {
+                                // Compare packet_id (by construction instruction is insert in order by increase packet_id)
+                                uint32_t _old = reg_EVENT_PACKET [front_end_id][context_id];
+                                uint32_t _new = packet;
+                                if (_old < _top) _old = _old+_param->_size_queue;
+                                if (_new < _top) _new = _new+_param->_size_queue;
+                                if (_new < _old) reg_EVENT_PACKET [front_end_id][context_id] = packet;
+                                else can = false;
+                              }
+                            else
+                              reg_EVENT_PACKET [front_end_id][context_id] = packet;
+                            if (can)
+                              {
+                                // have an error, stop issue instruction
+                                reg_EVENT_STATE         [front_end_id][context_id] = COMMIT_EVENT_STATE_NOT_YET_EVENT;
+                                //                      reg_EVENT_STOP          [front_end_id][context_id] = true;
+                                reg_EVENT_LAST_NUM_BANK [front_end_id][context_id] = ((reg_NUM_BANK_TAIL==0)?_param->_nb_bank:reg_NUM_BANK_TAIL)-1;
+                                reg_EVENT_LAST_NUM_PTR  [front_end_id][context_id] = reg_NUM_PTR_TAIL;
+                              }
+                          }
                         else
+                          reg_EVENT_PACKET [entry->front_end_id][entry->context_id] = packet;
+                        // have an error, stop issue instruction
+                        reg_EVENT_STOP          [entry->front_end_id][entry->context_id] = true;
+//                         reg_EVENT_NUM_BANK      [entry->front_end_id][entry->context_id] = i;
+//                         reg_EVENT_NUM_PTR       [entry->front_end_id][entry->context_id] = entry->ptr;
+//                      reg_EVENT_CAN_RESTART   [entry->front_end_id][entry->context_id] = false;
+                        reg_EVENT_LAST_NUM_BANK [entry->front_end_id][entry->context_id] = ((reg_NUM_BANK_TAIL==0)?_param->_nb_bank:reg_NUM_BANK_TAIL)-1;
+                        reg_EVENT_LAST_NUM_PTR  [entry->front_end_id][entry->context_id] = reg_NUM_PTR_TAIL;
+                          {
+                            bool find = true;
+                            // already manage an event.
+                            if (reg_EVENT_NEXT_STOP [front_end_id][context_id])
+                              {
+                                // after last ?
+                                uint32_t _old = reg_EVENT_NEXT_PACKET [front_end_id][context_id];
+                                uint32_t _new = packet;
+                                if (_old < _top) _old = _old+_param->_size_queue;
+                                if (_new < _top) _new = _new+_param->_size_queue;
+                                if (_new > _old) reg_EVENT_NEXT_PACKET [front_end_id][context_id] = packet;
+                                find = false;
+                              }
+                            else
+                              {
+                                // after last ?
+                                uint32_t _old = ((reg_EVENT_LAST_NUM_PTR [front_end_id][context_id] << _param->_shift_num_slot) | reg_EVENT_LAST_NUM_BANK [front_end_id][context_id]);
+                                uint32_t _new = packet;
+                                if (_old < _top) _old = _old+_param->_size_queue;
+                                if (_new < _top) _new = _new+_param->_size_queue;
+                                if (_new > _old) reg_EVENT_NEXT_PACKET [front_end_id][context_id] = packet;
+                                find = false;
+                              }
+                            if (find)
+                            reg_EVENT_NEXT_STOP [front_end_id][context_id] = true; // in all case : need stop
+                          }
+                      }
                     // Update Re Order Buffer
                     entry->state        = state;
 …
+                      {
                           reg_EVENT_STATE         [front_end_id][context_id] = COMMIT_EVENT_STATE_EVENT;
+//                        reg_EVENT_FLUSH         [front_end_id][context_id] = true;
+                          reg_EVENT_STOP          [front_end_id][context_id] = false; // instruction flow can continue
+//                        reg_EVENT_CAN_RESTART   [front_end_id][context_id] = false;
+//                        reg_EVENT_STOP          [front_end_id][context_id] = false; // instruction flow can continue
                           reg_EVENT_LAST          [front_end_id][context_id] = false;
                           // it the head !
                           reg_EVENT_PACKET        [front_end_id][context_id] = packet_id;
                           // If event is an load_miss, many instruction can be inserted.
                           // -> new last instruction
                           if (state == ROB_END_LOAD_MISS)
+                            {
                             reg_EVENT_CAN_RESTART   [front_end_id][context_id] = false;
+//                           // If event is an load_miss, many instruction can be inserted.
+//                           // -> new last instruction
+//                           if (state == ROB_END_LOAD_MISS)
+//                             {
+// //                             reg_EVENT_CAN_RESTART   [front_end_id][context_id] = false;
                             reg_EVENT_LAST_NUM_BANK [front_end_id][context_id] = ((reg_NUM_BANK_TAIL==0)?_param->_nb_bank:reg_NUM_BANK_TAIL)-1;
                             reg_EVENT_LAST_NUM_PTR  [front_end_id][context_id] = reg_NUM_PTR_TAIL;
+                            }
+//                             reg_EVENT_LAST_NUM_BANK [front_end_id][context_id] = ((reg_NUM_BANK_TAIL==0)?_param->_nb_bank:reg_NUM_BANK_TAIL)-1;
+//                             reg_EVENT_LAST_NUM_PTR  [front_end_id][context_id] = reg_NUM_PTR_TAIL;
+//                             }
+                        }
 …
                     //   * need event
                     //   * packet id = last packet id
+                    if ((reg_EVENT_STATE         [front_end_id][context_id] != COMMIT_EVENT_STATE_NO_EVENT) and
+                    if (((reg_EVENT_STATE         [front_end_id][context_id] != COMMIT_EVENT_STATE_NO_EVENT     ) and
+                         (reg_EVENT_STATE         [front_end_id][context_id] != COMMIT_EVENT_STATE_NOT_YET_EVENT)) and
                         (reg_EVENT_LAST_NUM_BANK [front_end_id][context_id] == num_bank            ) and
                         (reg_EVENT_LAST_NUM_PTR  [front_end_id][context_id] == entry->ptr          ))
 …
                     // Update pointer
                     reg_NUM_BANK_HEAD = (num_bank+1)%_param->_nb_bank;
-                    // Remove entry
-                    delete entry;
-                    _rob [num_bank].pop_front();
                     // Reset watch dog timer because have transaction on retire interface
 …
+                    }
 #endif
+                    // Remove entry
+                    delete entry;
+                    _rob [num_bank].pop_front();
+                  }
+              }
 …
               if (miss)
+                {
+                  bool     can    = true;
                   uint32_t packet = ((entry->ptr << _param->_shift_num_slot) | num_bank);
                   // test if this packet is before previous event
                   if (reg_EVENT_STOP [entry->front_end_id][entry->context_id])
+                  if (reg_EVENT_STATE [entry->front_end_id][entry->context_id] == COMMIT_EVENT_STATE_NOT_YET_EVENT)
+                    {
                       uint32_t _top = ((_rob[ reg_NUM_BANK_HEAD].front()->ptr << _param->_shift_num_slot) | reg_NUM_BANK_HEAD);
 …
                       if (_new < _top) _new = _new+_param->_size_queue;
                       if (_new < _old) reg_EVENT_PACKET [entry->front_end_id][entry->context_id] = packet;
+                      else can = false;
+                    }
                   else
                     reg_EVENT_PACKET [entry->front_end_id][entry->context_id] = packet;
+                  // In all case, stop instruction flow
+                  reg_EVENT_STOP          [entry->front_end_id][entry->context_id] = true;
+//                   reg_EVENT_NUM_BANK      [entry->front_end_id][entry->context_id] = num_bank;
+//                   reg_EVENT_NUM_PTR       [entry->front_end_id][entry->context_id] = entry->ptr;
+                  reg_EVENT_CAN_RESTART   [entry->front_end_id][entry->context_id] = false;
+                  reg_EVENT_LAST_NUM_BANK [entry->front_end_id][entry->context_id] = ((reg_NUM_BANK_TAIL==0)?_param->_nb_bank:reg_NUM_BANK_TAIL)-1;
+                  reg_EVENT_LAST_NUM_PTR  [entry->front_end_id][entry->context_id] = reg_NUM_PTR_TAIL;
+                  if (can)
+                    {
+                      // In all case, stop instruction flow
+                      reg_EVENT_STATE         [entry->front_end_id][entry->context_id] = COMMIT_EVENT_STATE_NOT_YET_EVENT;
+//                    reg_EVENT_STOP          [entry->front_end_id][entry->context_id] = true;
+//                    reg_EVENT_CAN_RESTART   [entry->front_end_id][entry->context_id] = false;
+                      reg_EVENT_LAST_NUM_BANK [entry->front_end_id][entry->context_id] = ((reg_NUM_BANK_TAIL==0)?_param->_nb_bank:reg_NUM_BANK_TAIL)-1;
+                      reg_EVENT_LAST_NUM_PTR  [entry->front_end_id][entry->context_id] = reg_NUM_PTR_TAIL;
+                    }
+                }
+            }
 …
                       bool         flush         = ((reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_EVENT) or
                                                     (reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_WAIT_DECOD) or
+//                                                  (reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_WAIT_DECOD) or
                                                     (reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_WAIT_END));
                       bool         speculative   = entry->speculative and not (depth == depth_min);
 …
                       // Test if this instruction is the last of event
+                      if ((reg_EVENT_STATE         [front_end_id][context_id] != COMMIT_EVENT_STATE_NO_EVENT) and
+                      if (((reg_EVENT_STATE         [front_end_id][context_id] != COMMIT_EVENT_STATE_NO_EVENT) and
+                           (reg_EVENT_STATE         [front_end_id][context_id] != COMMIT_EVENT_STATE_NOT_YET_EVENT)) and
                           (reg_EVENT_LAST_NUM_BANK [front_end_id][context_id] == num_bank            ) and
                           (reg_EVENT_LAST_NUM_PTR  [front_end_id][context_id] == entry->ptr          ))
 …
             log_printf(TRACE,Commit_unit,FUNCTION,"      * EVENT_STATE       : %s - %s",toString(reg_EVENT_STATE [i][j]).c_str(),toString(commit_event_state_to_event_state(reg_EVENT_STATE [i][j])).c_str());
 //          log_printf(TRACE,Commit_unit,FUNCTION,"      * EVENT_FLUSH       : %d",reg_EVENT_FLUSH [i][j]);
             log_printf(TRACE,Commit_unit,FUNCTION,"      * EVENT_STOP        : %d",reg_EVENT_STOP  [i][j]);
 //             log_printf(TRACE,Commit_unit,FUNCTION,"      * EVENT             : %d (bank %d, ptr %d)",((reg_EVENT_NUM_PTR [i][j] << _param->_shift_num_slot) | reg_EVENT_NUM_BANK [i][j]), reg_EVENT_NUM_BANK [i][j],reg_EVENT_NUM_PTR [i][j]);
             log_printf(TRACE,Commit_unit,FUNCTION,"      * EVENT_CAN_RESTART : %d",reg_EVENT_CAN_RESTART [i][j]);
+//          log_printf(TRACE,Commit_unit,FUNCTION,"      * EVENT_STOP        : %d",reg_EVENT_STOP  [i][j]);
+//          log_printf(TRACE,Commit_unit,FUNCTION,"      * EVENT             : %d (bank %d, ptr %d)",((reg_EVENT_NUM_PTR [i][j] << _param->_shift_num_slot) | reg_EVENT_NUM_BANK [i][j]), reg_EVENT_NUM_BANK [i][j],reg_EVENT_NUM_PTR [i][j]);
+//          log_printf(TRACE,Commit_unit,FUNCTION,"      * EVENT_CAN_RESTART : %d",reg_EVENT_CAN_RESTART [i][j]);
             log_printf(TRACE,Commit_unit,FUNCTION,"      * EVENT_PACKET      : %d",reg_EVENT_PACKET[i][j]);
             log_printf(TRACE,Commit_unit,FUNCTION,"      * EVENT_LAST        : %d",reg_EVENT_LAST [i][j]);
             log_printf(TRACE,Commit_unit,FUNCTION,"      * EVENT_LAST        : %d (bank %d, ptr %d)",((reg_EVENT_LAST_NUM_PTR [i][j] << _param->_shift_num_slot) | reg_EVENT_LAST_NUM_BANK [i][j]), reg_EVENT_LAST_NUM_BANK [i][j],reg_EVENT_LAST_NUM_PTR [i][j]);
+            log_printf(TRACE,Commit_unit,FUNCTION,"      * EVENT_NEXT_STOP   : %d",reg_EVENT_NEXT_STOP  [i][j]);
+            log_printf(TRACE,Commit_unit,FUNCTION,"      * EVENT_NEXT_PACKET : %d",reg_EVENT_NEXT_PACKET[i][j]);
             log_printf(TRACE,Commit_unit,FUNCTION,"      * NB_INST_ALL       : %d",reg_NB_INST_COMMIT_ALL[i][j]);
             log_printf(TRACE,Commit_unit,FUNCTION,"      * NB_INST_MEM       : %d",reg_NB_INST_COMMIT_MEM[i][j]);
 …
+        }
+      bool all_empty = false;
+      bool     all_empty   = false;
+      uint32_t nb_write_rd = 0;
+      uint32_t nb_write_re = 0;
       while (not all_empty)
+        {
 …
+                {
                   all_empty = false;
+                  nb_write_rd += ((*it)->write_rd)?1:0;
+                  nb_write_re += ((*it)->write_re)?1:0;
                   log_printf(TRACE,Commit_unit,FUNCTION,"        [%.4d][%.4d] (%.4d) %.4d %.4d %.4d %.4d, %.3d %.3d, %.1d, %.1d %.4d, %.1d %.4d, %s",
 …
+            }
+        }
+      log_printf(TRACE,Commit_unit,FUNCTION,"    * nb_write_rd   : %d",nb_write_rd);
+      log_printf(TRACE,Commit_unit,FUNCTION,"    * nb_write_re   : %d",nb_write_re);
+    }
 #endif

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue.cpp

-                      r111
+                      r123
     usage_environment(_usage);
 #if DEBUG_Issue_queue == true
     log_printf(INFO,Issue_queue,FUNCTION,_("<%s> Parameters"),_name.c_str());
+// #if DEBUG_Issue_queue == true
+//     log_printf(INFO,Issue_queue,FUNCTION,_("<%s> Parameters"),_name.c_str());
     std::cout << *param << std::endl;
 #endif
+//     std::cout << *param << std::endl;
+// #endif
     log_printf(INFO,Issue_queue,FUNCTION,_("<%s> : Allocation"),_name.c_str());

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_function_in_order_genMealy_issue_out.cpp

-                      r122
+                      r123
     log_function(Issue_queue,FUNCTION,_name.c_str());
+    if (PORT_READ(in_NRESET))
     // ===================================================================
     // =====[ ISSUE_OUT ]=================================================
     // ===================================================================
+    {
+      {
       Tcontrol_t val [_param->_nb_inst_issue];
 …
+        }
+    }
+    else
+      {
+      for (uint32_t i=0; i<_param->_nb_inst_issue; i++)
+        internal_ISSUE_OUT_VAL [i] = 0;
+      }
+    for (uint32_t i=0; i<_param->_nb_inst_issue; i++)
+      PORT_WRITE(out_ISSUE_OUT_VAL [i], internal_ISSUE_OUT_VAL [i]);
     log_end(Issue_queue,FUNCTION);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_function_in_order_genMoore.cpp

-                      r111
+                      r123
           internal_ISSUE_IN_ACK [i][j] = false;
+      if (PORT_READ(in_NRESET))
+        {
       std::list<generic::priority::select_t> * select_in = _priority_in ->select(); // same select for all issue
       std::list<generic::priority::select_t>::iterator it=select_in ->begin();
 …
           nb_insert ++;
+        }
+        }
       for (uint32_t i=0; i<_param->_nb_rename_unit; i++)
         for (uint32_t j=0; j<_param->_nb_inst_rename[i]; j++)

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_function_out_of_order_genMoore.cpp

-                      r122
+                      r123
     log_function(Issue_queue,FUNCTION,_name.c_str());
+    if (PORT_READ(in_NRESET))
+      {
     // ===================================================================
     // =====[ REEXECUTE_UNIT ]============================================
 …
+        {
           internal_ISSUE_OUT_VAL [i] = val [i];
+        }
+    }
+      }
+    else
+      {
+        // Reset
+        for (uint32_t i=0; i<_param->_nb_bank; i++)
+          {
+            internal_BANK_IN_ACK  [i] = 0;
+//             internal_BANK_IN_NUM_RENAME_UNIT [num_bank] = num_rename_unit;
+//             internal_BANK_IN_NUM_INST        [num_bank] = num_inst_rename;
+          }
+        for (uint32_t i=0; i<_param->_nb_rename_unit; i++)
+          for (uint32_t j=0; j<_param->_nb_inst_rename[i]; j++)
+            PORT_WRITE(out_ISSUE_IN_ACK [i][j],0);
+          for (uint32_t i=0; i<_param->_nb_inst_issue; i++)
+            {
+              internal_ISSUE_OUT_VAL [i] = 0;
+//            internal_ISSUE_OUT_FROM_REEXECUTE [i] = true;
+//            internal_ISSUE_OUT_NUM_BANK       [i] = num_bank;
+//            internal_ISSUE_OUT_ENTRY          [i] = entry;
+            }
+      }
+    // Write output
+      for (uint32_t i=0; i<_param->_nb_inst_issue; i++)
+        {
           PORT_WRITE(out_ISSUE_OUT_VAL [i], internal_ISSUE_OUT_VAL [i]);
+        }
+    }
     log_end(Issue_queue,FUNCTION);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_genMoore.cpp

-                      r111
+                      r123
     log_function(Issue_queue,FUNCTION,_name.c_str());
+    if (PORT_READ(in_NRESET))
+      {
     // ===================================================================
     // =====[ REEXECUTE_UNIT ]============================================
 …
         log_printf(TRACE,Issue_queue,FUNCTION,"    * ACK : %d",internal_REEXECUTE_ACK [i]);
+      }
-        PORT_WRITE(out_REEXECUTE_ACK [i], internal_REEXECUTE_ACK [i]);
+      }
+    else
+      {
+        // Reset
+        for (uint32_t i=0; i<_param->_nb_inst_reexecute; ++i)
+          internal_REEXECUTE_ACK [i] = 0;
+      }
+    // Write Output
+    for (uint32_t i=0; i<_param->_nb_inst_reexecute; ++i)
+      PORT_WRITE(out_REEXECUTE_ACK [i], internal_REEXECUTE_ACK [i]);
     (this->*function_genMoore) ();

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue.cpp

-                      r122
+                      r123
     usage_environment(_usage);
 #if DEBUG_OOO_Engine_Glue == true
     log_printf(INFO,OOO_Engine_Glue,FUNCTION,_("<%s> Parameters"),_name.c_str());
     std::cout << *param << std::endl;
 #endif
+// #if DEBUG_OOO_Engine_Glue == true
+//     log_printf(INFO,OOO_Engine_Glue,FUNCTION,_("<%s> Parameters"),_name.c_str());
+//     std::cout << *param << std::endl;
+// #endif
     log_printf(INFO,OOO_Engine_Glue,FUNCTION,_("<%s> : Allocation"),_name.c_str());

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue_genMealy_insert.cpp

-                      r122
+                      r123
     log_function(OOO_Engine_Glue,FUNCTION,_name.c_str());
+    if (PORT_READ(in_NRESET))
+      {
     uint32_t x=0;
     for (uint32_t i=0; i<_param->_nb_rename_unit; ++i)
 …
           x ++;
+        }
+      }
+//     else
+//       {
+//       }
     log_end(OOO_Engine_Glue,FUNCTION);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue_genMealy_insert_valack.cpp

-                      r110
+                      r123
     log_function(OOO_Engine_Glue,FUNCTION,_name.c_str());
+    if (PORT_READ(in_NRESET))
+      {
     uint32_t x=0;
     for (uint32_t i=0; i<_param->_nb_rename_unit; ++i)
 …
+          }
+      }
+      }
+    else
+      {
+        uint32_t x=0;
+        for (uint32_t i=0; i<_param->_nb_rename_unit; ++i)
+          for (uint32_t j=0; j<_param->_nb_inst_insert[i]; ++j)
+            {
+              PORT_WRITE(out_INSERT_VAL             [x]   ,0);
+              PORT_WRITE(out_INSERT_RENAME_UNIT_ACK [i][j],0);
+              PORT_WRITE(out_INSERT_COMMIT_UNIT_VAL [i][j],0);
+              PORT_WRITE(out_INSERT_ISSUE_QUEUE_VAL [i][j],0);
+              x ++;
+            }
+      }
     log_end(OOO_Engine_Glue,FUNCTION);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue_genMealy_rename.cpp

-                      r120
+                      r123
     log_function(OOO_Engine_Glue,FUNCTION,_name.c_str());
+    if (PORT_READ(in_NRESET))
+      {
     for (uint32_t i=0; i<_param->_nb_front_end; ++i)
       for (uint32_t j=0; j<_param->_nb_inst_decod[i]; ++j)
 …
           PORT_WRITE(out_RENAME_RENAME_UNIT_FRONT_END_ID [i][j],_param->_translate_front_end_id_to_rename_unit [PORT_READ(in_RENAME_FRONT_END_ID [i][j])]);
+        }
+      }
     log_end(OOO_Engine_Glue,FUNCTION);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue_genMealy_retire.cpp

-                      r88
+                      r123
     log_function(OOO_Engine_Glue,FUNCTION,_name.c_str());
+    if (PORT_READ(in_NRESET))
+      {
     uint32_t x=0;
     for (uint32_t i=0; i<_param->_nb_rename_unit; ++i)
 …
           x ++;
+        }
+}
     log_end(OOO_Engine_Glue,FUNCTION);
   };

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue_genMealy_retire_valack.cpp

-                      r88
+                      r123
     log_function(OOO_Engine_Glue,FUNCTION,_name.c_str());
+    if (PORT_READ(in_NRESET))
+      {
     uint32_t x=0;
     for (uint32_t i=0; i<_param->_nb_rename_unit; ++i)
 …
           x ++;
+        }
+}
     log_end(OOO_Engine_Glue,FUNCTION);
   };

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue_genMealy_spr.cpp

-                      r88
+                      r123
     log_begin(OOO_Engine_Glue,FUNCTION);
+//     if (PORT_READ(in_NRESET))
+      {
     for (uint32_t i=0; i<_param->_nb_front_end; ++i)
       for (uint32_t j=0; j<_param->_nb_context[i]; ++j)
 …
           delete sr;
+        }
+      }
     log_end(OOO_Engine_Glue,FUNCTION);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit.cpp

-                      r88
+                      r123
     usage_environment(_usage);
 #if DEBUG_Reexecute_unit == true
     log_printf(INFO,Reexecute_unit,FUNCTION,_("<%s> Parameters"),_name.c_str());
+// #if DEBUG_Reexecute_unit == true
+//     log_printf(INFO,Reexecute_unit,FUNCTION,_("<%s> Parameters"),_name.c_str());
     std::cout << *param << std::endl;
 #endif
+//     std::cout << *param << std::endl;
+// #endif
     log_printf(INFO,Reexecute_unit,FUNCTION,_("<%s> : Allocation"),_name.c_str());

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_genMealy_commit.cpp

-                      r117
+                      r123
     log_function(Reexecute_unit,FUNCTION,_name.c_str());
+    if (PORT_READ(in_NRESET))
+      {
     // Initialisation
     Tcontrol_t execute_loop_ack [_param->_nb_execute_loop][_param->_max_nb_inst_execute];
 …
       for (uint32_t j=0; j<_param->_nb_inst_execute [i]; ++j)
         PORT_WRITE(out_EXECUTE_LOOP_ACK [i][j], execute_loop_ack [i][j]);
+      }
+    else
+      {
+#ifdef STATISTICS
+        for (uint32_t i=0; i<_param->_nb_inst_commit; ++i)
+          internal_COMMIT_VAL [i] = 0;
+#endif
+        for (uint32_t i=0; i<_param->_nb_execute_loop; ++i)
+          for (uint32_t j=0; j<_param->_nb_inst_execute [i]; ++j)
+            PORT_WRITE(out_EXECUTE_LOOP_ACK [i][j], 0);
+      }
     log_end(Reexecute_unit,FUNCTION);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_genMealy_reexecute.cpp

-                      r122
+                      r123
     log_function(Reexecute_unit,FUNCTION,_name.c_str());
+    if (PORT_READ(in_NRESET))
+      {
     // ===================================================================
     // =====[ REEXECUTE ]=================================================
 …
         internal_REEXECUTE_VAL     [i] = val;
         internal_REEXECUTE_ROB_ACK [i] = ack;
+      }
+      }
+    else
+      {
+        for (uint32_t i=0; i<_param->_nb_inst_reexecute; i++)
+          {
+            internal_REEXECUTE_VAL     [i] = 0;
+            internal_REEXECUTE_ROB_ACK [i] = 0;
+          }
+      }
+    for (uint32_t i=0; i<_param->_nb_inst_reexecute; i++)
+      {
         PORT_WRITE(out_REEXECUTE_VAL     [i], internal_REEXECUTE_VAL     [i]);
         PORT_WRITE(out_REEXECUTE_ROB_ACK [i], internal_REEXECUTE_ROB_ACK [i]);
+      }
     log_end(Reexecute_unit,FUNCTION);
   };

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_genMoore.cpp

-                      r98
+                      r123
     log_function(Reexecute_unit,FUNCTION,_name.c_str());
+    if (PORT_READ(in_NRESET))
+      {
     // ===================================================================
     // =====[ SPR ]=======================================================
 …
         internal_SPR_VAL [i] = val;
+      }
+      }
+    else
+      {
+        //Reset
+        for (uint32_t i=0; i<_param->_nb_inst_reexecute; i++)
+          internal_SPR_VAL [i] = 0;
+      }
+    // Write output
+    for (uint32_t i=0; i<_param->_nb_inst_reexecute; i++)
+      {
         PORT_WRITE(out_SPR_VAL [i], internal_SPR_VAL [i]);
+      }

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/src/Load_Store_pointer_unit.cpp

-                      r122
+                      r123
     log_printf(FUNC,Load_Store_pointer_unit,FUNCTION,"Begin");
 #if DEBUG_Load_Store_pointer_unit == true
     log_printf(INFO,Load_Store_pointer_unit,FUNCTION,_("<%s> Parameters"),_name.c_str());
     std::cout << *param << std::endl;
 #endif
+// #if DEBUG_Load_Store_pointer_unit == true
+//     log_printf(INFO,Load_Store_pointer_unit,FUNCTION,_("<%s> Parameters"),_name.c_str());
+//     std::cout << *param << std::endl;
+// #endif
     log_printf(INFO,Load_Store_pointer_unit,FUNCTION,"Allocation");

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/src/Load_Store_pointer_unit_genMealy_insert.cpp

-                      r122
+                      r123
     log_function(Load_Store_pointer_unit,FUNCTION,_name.c_str());
+    if (PORT_READ(in_NRESET))
+      {
     // TODO : limité à nb_inst_memory le nombre d'accès par lsq !!!
 …
         // Write output
         internal_INSERT_ACK [i] = ack;
-        PORT_WRITE(out_INSERT_ACK                   [i], ack);
+      }
+      }
+    else
+      {
+        for (uint32_t i=0; i<_param->_nb_inst_insert; i++)
+          internal_INSERT_ACK [i] = 0;
+      }
+    for (uint32_t i=0; i<_param->_nb_inst_insert; i++)
+      PORT_WRITE(out_INSERT_ACK [i], internal_INSERT_ACK [i]);
     log_end(Load_Store_pointer_unit,FUNCTION);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/src/Load_Store_pointer_unit_genMealy_retire.cpp

-                      r110
+                      r123
     log_printf(FUNC,Load_Store_pointer_unit,FUNCTION,"Begin");
+    if (PORT_READ(in_NRESET))
+      {
 //     bool use_lsq [_param->_nb_load_store_queue];
 //     for (uint32_t i=0; i<_param->_nb_load_store_queue; i++)
 …
         // Write output
         internal_RETIRE_ACK [i] = ack;
-        PORT_WRITE(out_RETIRE_ACK                   [i], ack);
+      }
+      }
+    else
+      {
+        for (uint32_t i=0; i<_param->_nb_inst_retire; i++)
+          internal_RETIRE_ACK [i] = 0;
+      }
+    for (uint32_t i=0; i<_param->_nb_inst_retire; i++)
+      PORT_WRITE(out_RETIRE_ACK [i], internal_RETIRE_ACK [i]);
     log_printf(FUNC,Load_Store_pointer_unit,FUNCTION,"End");

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Dependency_checking_unit/src/Dependency_checking_unit.cpp

-                      r121
+                      r123
     log_printf(FUNC,Dependency_checking_unit,FUNCTION,"Begin");
 #if DEBUG_Dependency_checking_unit == true
     log_printf(INFO,Dependency_checking_unit,FUNCTION,_("<%s> Parameters"),_name.c_str());
     std::cout << *param << std::endl;
 #endif
+// #if DEBUG_Dependency_checking_unit == true
+//     log_printf(INFO,Dependency_checking_unit,FUNCTION,_("<%s> Parameters"),_name.c_str());
+//     std::cout << *param << std::endl;
+// #endif
     log_printf(INFO,Dependency_checking_unit,FUNCTION,"Allocation");

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Dependency_checking_unit/src/Dependency_checking_unit_genMealy.cpp

-                      r121
+                      r123
     log_function(Dependency_checking_unit,FUNCTION,_name.c_str());
+    if (PORT_READ(in_NRESET))
+      {
 //     Tcontrol_t         val                [_param->_nb_inst_insert];
 //     Tcontrol_t         ack                [_param->_nb_inst_insert];
 …
         PORT_WRITE(out_RENAME_OUT_NUM_REG_RE_PHY_NEW [i], num_reg_re_phy_new [i]);
+      }
+      }
     log_end(Dependency_checking_unit,FUNCTION);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/include/Free_List_unit.h

-                      r110
+                      r123
   public    : SC_IN (Tspecial_address_t)   **  in_PUSH_SPR_NUM_REG;
+    // ~~~~~[ interface : "info" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+#ifdef DEBUG_TEST
+  public    : SC_OUT(uint32_t  )            * out_INFO_NB_GPR_FREE;
+  public    : SC_OUT(uint32_t  )            * out_INFO_NB_SPR_FREE;
+#endif
     // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   private   : generic::priority::Priority   * _priority_gpr;
 …
 #ifdef SYSTEMC
   public  : void        transition                (void);
+#ifdef DEBUG_TEST
+  public  : void        genMoore                  (void);
+#endif
   public  : void        genMealy_pop              (void);
   public  : void        genMealy_push_gpr         (void);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Free_List_unit.cpp

-                      r110
+                      r123
     log_printf(FUNC,Free_List_unit,FUNCTION,"Begin");
 #if DEBUG_Free_List_unit == true
     log_printf(INFO,Free_List_unit,FUNCTION,_("<%s> Parameters"),_name.c_str());
+// #if DEBUG_Free_List_unit == true
+//     log_printf(INFO,Free_List_unit,FUNCTION,_("<%s> Parameters"),_name.c_str());
     std::cout << *param << std::endl;
 #endif
+//     std::cout << *param << std::endl;
+// #endif
     log_printf(INFO,Free_List_unit,FUNCTION,"Allocation");
 …
 # endif
+#ifdef DEBUG_TEST
+        log_printf(INFO,Free_List_unit,FUNCTION,"Method - genMoore");
+        SC_METHOD (genMoore);
+        dont_initialize ();
+        sensitive << (*(in_CLOCK)).neg();
+# ifdef SYSTEMCASS_SPECIFIC
+        // List dependency information
+# endif
+#endif
         log_printf(INFO,Free_List_unit,FUNCTION,"Method - genMealy_pop");

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Free_List_unit_allocation.cpp

-                      r112
+                      r123
+     }
+    // ~~~~~[ interface : "info" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+#ifdef DEBUG_TEST
+     {
+       ALLOC0_INTERFACE_BEGIN("info",OUT, NORTH, _("Information"));
+       ALLOC0_SIGNAL_OUT(out_INFO_NB_GPR_FREE,"nb_gpr_free",uint32_t,_param->_size_general_register+1);
+       ALLOC0_SIGNAL_OUT(out_INFO_NB_SPR_FREE,"nb_spr_free",uint32_t,_param->_size_special_register+1);
+       ALLOC0_INTERFACE_END();
+     }
+#endif
      if (usage_is_set(_usage,USE_SYSTEMC))
+       {

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Free_List_unit_deallocation.cpp

-                      r112
+                      r123
         DELETE1_SIGNAL( in_PUSH_SPR_NUM_REG,_param->_nb_push,_param->_size_special_register);
+#ifdef DEBUG_TEST
+        DELETE0_SIGNAL(out_INFO_NB_GPR_FREE,_param->_size_general_register+1);
+        DELETE0_SIGNAL(out_INFO_NB_SPR_FREE,_param->_size_special_register+1);
+#endif
         DELETE1(_gpr_list             ,_param->_nb_bank);
         DELETE1(_spr_list             ,_param->_nb_bank);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Free_List_unit_genMealy_pop.cpp

-                      r109
+                      r123
     log_function(Free_List_unit,FUNCTION,_name.c_str());
+    if (PORT_READ(in_NRESET))
+      {
     std::list<generic::priority::select_t> * select_gpr = _priority_gpr->select();
     std::list<generic::priority::select_t>::iterator it_gpr=select_gpr->begin();
 …
     std::list<generic::priority::select_t>::iterator it_spr=select_spr->begin();
     for (uint32_t i=0; i<_param->_nb_pop; i++)
+     for (uint32_t i=0; i<_param->_nb_pop; i++)
+      {
         log_printf(TRACE,Free_List_unit,FUNCTION,"  * POP [%d]",i);
 …
         internal_POP_ACK [i] = gpr_ack and spr_ack;
-        PORT_WRITE(out_POP_ACK [i], internal_POP_ACK [i]);
+      }
 …
 //      PORT_WRITE(out_POP_ACK [i], internal_POP_ACK [i]);
 //       }
+      }
+    else
+      {
+        for (uint32_t i=0; i<_param->_nb_pop; i++)
+          internal_POP_ACK [i] = 0;
+      }
+    for (uint32_t i=0; i<_param->_nb_pop; i++)
+      PORT_WRITE(out_POP_ACK [i], internal_POP_ACK [i]);
     log_end(Free_List_unit,FUNCTION);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Free_List_unit_genMealy_push_gpr.cpp

-                      r108
+                      r123
     log_function(Free_List_unit,FUNCTION,_name.c_str());
+    if (PORT_READ(in_NRESET))
+      {
     // bank conflit
     bool bank_use [_param->_nb_bank];
 …
         internal_PUSH_GPR_ACK [i] = gpr_ack;
-        PORT_WRITE(out_PUSH_GPR_ACK [i], internal_PUSH_GPR_ACK [i]);
+      }
+      }
+    else
+      {
+        for (uint32_t i=0; i<_param->_nb_push; i++)
+          internal_PUSH_GPR_ACK [i] = 0;
+      }
+    for (uint32_t i=0; i<_param->_nb_push; i++)
+      PORT_WRITE(out_PUSH_GPR_ACK [i], internal_PUSH_GPR_ACK [i]);
     log_end(Free_List_unit,FUNCTION);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Free_List_unit_genMealy_push_spr.cpp

-                      r108
+                      r123
     log_function(Free_List_unit,FUNCTION,_name.c_str());
+    if (PORT_READ(in_NRESET))
+      {
     bool bank_use [_param->_nb_bank];
     for (uint32_t i=0; i<_param->_nb_bank; i++)
 …
         internal_PUSH_SPR_ACK [i] = spr_ack;
-        PORT_WRITE(out_PUSH_SPR_ACK [i], internal_PUSH_SPR_ACK [i]);
+      }
+      }
+    else
+      {
+        for (uint32_t i=0; i<_param->_nb_push; i++)
+          internal_PUSH_SPR_ACK [i] = 0;
+      }
+    for (uint32_t i=0; i<_param->_nb_push; i++)
+      PORT_WRITE(out_PUSH_SPR_ACK [i], internal_PUSH_SPR_ACK [i]);
     log_end(Free_List_unit,FUNCTION);
   };

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit.cpp

-                      r122
+                      r123
     log_printf(FUNC,Register_Address_Translation_unit,FUNCTION,"Begin");
 #if DEBUG_Register_Address_Translation_unit == true
     log_printf(INFO,Register_Address_Translation_unit,FUNCTION,_("<%s> Parameters"),_name.c_str());
     std::cout << *param << std::endl;
 #endif
+// #if DEBUG_Register_Address_Translation_unit == true
+//     log_printf(INFO,Register_Address_Translation_unit,FUNCTION,_("<%s> Parameters"),_name.c_str());
+//     std::cout << *param << std::endl;
+// #endif
     log_printf(INFO,Register_Address_Translation_unit,FUNCTION,"Allocation");

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_genMealy_rename.cpp

r122	r123
29	29	for (uint32_t i=0; i<_param->_nb_inst_insert; i++)
30	30	if (PORT_READ(in_RENAME_VAL [i])) // not in sensitive list : it's to have valide value to array access
31		{
	31	{
32	32	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * RENAME [%d]",i);
33	33

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_transition.cpp

r122	r123
40	40	{
41	41	rat_gpr_not_speculative [i][j][k] = gpr++;
42		~~// rat_gpr_speculative [i][j][k] = gpr++;~~
43	42	rat_gpr_speculative_valid [i][j][k] = false;
44		// rat_gpr_update_table [i][j][k] = false;
	43	rat_gpr_speculative [i][j][k] = 0 ; // not necessary
	44	rat_gpr_update_table [i][j][k] = false; // not necessary
45	45	}
46	46	for (uint32_t k=0; k<_param->_nb_special_register_logic; k++)
47	47	{
48	48	rat_spr_not_speculative [i][j][k] = spr++;
49		~~// rat_spr_speculative [i][j][k] = spr++;~~
50	49	rat_spr_speculative_valid [i][j][k] = false;
51		// rat_spr_update_table [i][j][k] = false;
	50	rat_spr_speculative [i][j][k] = 0 ; // not necessary
	51	rat_spr_update_table [i][j][k] = false; // not necessary
52	52	}
53	53	}

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/src/Register_translation_unit_Glue.cpp

-                      r110
+                      r123
     log_printf(FUNC,Register_translation_unit_Glue,FUNCTION,"Begin");
 #if DEBUG_Register_translation_unit_Glue == true
     log_printf(INFO,Register_translation_unit_Glue,FUNCTION,_("<%s> Parameters"),_name.c_str());
     std::cout << *param << std::endl;
 #endif
+// #if DEBUG_Register_translation_unit_Glue == true
+//     log_printf(INFO,Register_translation_unit_Glue,FUNCTION,_("<%s> Parameters"),_name.c_str());
+//     std::cout << *param << std::endl;
+// #endif
     log_printf(INFO,Register_translation_unit_Glue,FUNCTION,"Allocation");

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/src/Register_translation_unit_Glue_genMealy_insert.cpp

-                      r117
+                      r123
     log_function(Register_translation_unit_Glue,FUNCTION,_name.c_str());
+    if (PORT_READ(in_NRESET))
+      {
     for (uint32_t i=0; i<_param->_nb_inst_insert; i++)
+      {
 …
         PORT_WRITE(out_INSERT_NUM_REG_RE_PHY_NEW           [i], NUM_REG_RE_PHY_NEW);
+      }
+      }
+//     else
+//       {
+//       }
     log_end(Register_translation_unit_Glue,FUNCTION);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/src/Register_translation_unit_Glue_genMealy_insert_valack.cpp

-                      r110
+                      r123
     log_begin(Register_translation_unit_Glue,FUNCTION);
     log_function(Register_translation_unit_Glue,FUNCTION,_name.c_str());
+    if (PORT_READ(in_NRESET))
+      {
     for (uint32_t i=0; i<_param->_nb_inst_insert; i++)
+      {
 …
+      }
+      }
+    else
+      {
+        for (uint32_t i=0; i<_param->_nb_inst_insert; i++)
+          {
+#ifdef STATISTICS
+            internal_INSERT_RENAME_ACK [i] = 0;
+#endif
+            PORT_WRITE(out_INSERT_RENAME_ACK     [i], 0);
+            PORT_WRITE(out_INSERT_INSERT_VAL     [i], 0);
+            PORT_WRITE(out_INSERT_RAT_INSERT_VAL [i], 0);
+            PORT_WRITE(out_INSERT_FREE_LIST_VAL  [i], 0);
+            PORT_WRITE(out_INSERT_STAT_LIST_VAL  [i], 0);
+          }
+      }
     log_end(Register_translation_unit_Glue,FUNCTION);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/src/Register_translation_unit_Glue_genMealy_retire.cpp

-                      r110
+                      r123
     log_function(Register_translation_unit_Glue,FUNCTION,_name.c_str());
+    if (PORT_READ(in_NRESET))
+      {
     for (uint32_t i=0; i<_param->_nb_inst_retire; i++)
+      {
 …
         log_printf(TRACE,Register_translation_unit_Glue,FUNCTION,"    * stat_list_ack  (r): %d",stat_list_ack );
+      }
+      }
+    else
+      {
+        for (uint32_t i=0; i<_param->_nb_inst_retire; i++)
+          {
+            PORT_WRITE(out_RETIRE_ACK           [i], 0);
+            PORT_WRITE(out_RETIRE_RAT_VAL       [i], 0);
+            PORT_WRITE(out_RETIRE_STAT_LIST_VAL [i], 0);
+          }
+      }
     log_end(Register_translation_unit_Glue,FUNCTION);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/include/Stat_List_unit.h

-                      r121
+                      r123
   public    : SC_OUT(Tcontrol_t        )   ** out_RETIRE_ACK               ;//[nb_inst_retire]
   public    : SC_IN (Tcontrol_t        )   **  in_RETIRE_RESTORE           ;//[nb_inst_retire]
 //   public    : SC_IN (Tcontrol_t        )   **  in_RETIRE_READ_RA           ;//[nb_inst_retire]
 //   public    : SC_IN (Tgeneral_address_t)   **  in_RETIRE_NUM_REG_RA_PHY    ;//[nb_inst_retire]
 //   public    : SC_IN (Tcontrol_t        )   **  in_RETIRE_READ_RB           ;//[nb_inst_retire]
 //   public    : SC_IN (Tgeneral_address_t)   **  in_RETIRE_NUM_REG_RB_PHY    ;//[nb_inst_retire]
 //   public    : SC_IN (Tcontrol_t        )   **  in_RETIRE_READ_RC           ;//[nb_inst_retire]
 //   public    : SC_IN (Tspecial_address_t)   **  in_RETIRE_NUM_REG_RC_PHY    ;//[nb_inst_retire]
+//public    : SC_IN (Tcontrol_t        )   **  in_RETIRE_READ_RA           ;//[nb_inst_retire]
+//public    : SC_IN (Tgeneral_address_t)   **  in_RETIRE_NUM_REG_RA_PHY    ;//[nb_inst_retire]
+//public    : SC_IN (Tcontrol_t        )   **  in_RETIRE_READ_RB           ;//[nb_inst_retire]
+//public    : SC_IN (Tgeneral_address_t)   **  in_RETIRE_NUM_REG_RB_PHY    ;//[nb_inst_retire]
+//public    : SC_IN (Tcontrol_t        )   **  in_RETIRE_READ_RC           ;//[nb_inst_retire]
+//public    : SC_IN (Tspecial_address_t)   **  in_RETIRE_NUM_REG_RC_PHY    ;//[nb_inst_retire]
   public    : SC_IN (Tcontrol_t        )   **  in_RETIRE_WRITE_RD          ;//[nb_inst_retire]
   public    : SC_IN (Tcontrol_t        )   **  in_RETIRE_RESTORE_RD_PHY_OLD;//[nb_inst_retire]
 …
   public    : SC_IN (Tcontrol_t)           **  in_PUSH_SPR_ACK             ;//[nb_reg_free]
   public    : SC_OUT(Tspecial_address_t)   ** out_PUSH_SPR_NUM_REG         ;//[nb_reg_free]
+    // ~~~~~[ interface : "info" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+#ifdef DEBUG_TEST
+  public    : SC_IN (bool      )            *  in_INFO_ROB_EMPTY  ;
+  public    : SC_IN (uint32_t  )            *  in_INFO_NB_GPR_FREE;
+  public    : SC_IN (uint32_t  )            *  in_INFO_NB_SPR_FREE;
+#endif
     // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/include/Types.h

r117	r123
66	66	else
67	67	{
68		// _is_link = 0; // already unset
	68	_is_link = 0;
69	69	_is_use = 0;
70	70	}

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/src/Stat_List_unit.cpp

-                      r112
+                      r123
     log_printf(FUNC,Stat_List_unit,FUNCTION,"Begin");
 #if DEBUG_Stat_List_unit == true
     log_printf(INFO,Stat_List_unit,FUNCTION,_("<%s> Parameters"),_name.c_str());
+// #if DEBUG_Stat_List_unit == true
+//     log_printf(INFO,Stat_List_unit,FUNCTION,_("<%s> Parameters"),_name.c_str());
     std::cout << *param << std::endl;
 #endif
+//     std::cout << *param << std::endl;
+// #endif
     log_printf(INFO,Stat_List_unit,FUNCTION,"Allocation");

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/src/Stat_List_unit_allocation.cpp

-                      r121
+                      r123
+     }
+    // ~~~~~[ interface : "info" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+#ifdef DEBUG_TEST
+     {
+       ALLOC0_INTERFACE_BEGIN("info",IN, NORTH, _("Information"));
+       ALLOC0_SIGNAL_IN ( in_INFO_ROB_EMPTY  ,"rob_empty"  ,bool    ,1);
+       ALLOC0_SIGNAL_IN ( in_INFO_NB_GPR_FREE,"nb_gpr_free",uint32_t,_param->_size_general_register+1);
+       ALLOC0_SIGNAL_IN ( in_INFO_NB_SPR_FREE,"nb_spr_free",uint32_t,_param->_size_special_register+1);
+       ALLOC0_INTERFACE_END();
+     }
+#endif
     // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     if (usage_is_set(_usage,USE_SYSTEMC))

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/src/Stat_List_unit_deallocation.cpp

-                      r121
+                      r123
         DELETE1_SIGNAL(out_PUSH_SPR_NUM_REG,_param->_nb_reg_free,_param->_size_special_register);
+#ifdef DEBUG_TEST
+        DELETE0_SIGNAL( in_INFO_ROB_EMPTY  ,1);
+        DELETE0_SIGNAL( in_INFO_NB_GPR_FREE,_param->_size_general_register+1);
+        DELETE0_SIGNAL( in_INFO_NB_SPR_FREE,_param->_size_special_register+1);
+#endif
         DELETE2(gpr_stat_list             ,_param->_nb_bank,_param->_nb_general_register_by_bank);
         DELETE2(spr_stat_list             ,_param->_nb_bank,_param->_nb_special_register_by_bank);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/src/Stat_List_unit_genMoore.cpp

-                      r118
+                      r123
     log_function(Stat_List_unit,FUNCTION,_name.c_str());
+    if (PORT_READ(in_NRESET))
+      {
     uint32_t  gpr_ptr = reg_GPR_PTR_FREE;
     uint32_t  spr_ptr = reg_SPR_PTR_FREE;
 …
           internal_PUSH_GPR_NUM_REG  [i] = gpr_ptr ;
-          PORT_WRITE(out_PUSH_GPR_VAL [i], val);
           if (val)
             PORT_WRITE(out_PUSH_GPR_NUM_REG[i], ((bank_gpr<<_param->_shift_gpr) | gpr_ptr));
 …
           internal_PUSH_SPR_NUM_REG  [i] = spr_ptr ;
-          PORT_WRITE(out_PUSH_SPR_VAL [i], val);
           if (val)
             PORT_WRITE(out_PUSH_SPR_NUM_REG[i], ((bank_spr<<_param->_shift_spr) | spr_ptr));
 …
+      }
+      }
+    else
+      {
+        for (uint32_t i=0; i<_param->_nb_reg_free; i++)
+          {
+            internal_PUSH_GPR_VAL      [i] = 0;
+//          internal_PUSH_GPR_NUM_BANK [i] = bank_gpr;
+//          internal_PUSH_GPR_NUM_REG  [i] = gpr_ptr ;
+            internal_PUSH_SPR_VAL      [i] = 0;
+//          internal_PUSH_SPR_NUM_BANK [i] = bank_spr;
+//          internal_PUSH_SPR_NUM_REG  [i] = spr_ptr ;
+          }
+      }
+    for (uint32_t i=0; i<_param->_nb_reg_free; i++)
+      {
+        PORT_WRITE(out_PUSH_GPR_VAL [i], internal_PUSH_GPR_VAL      [i]);
+        PORT_WRITE(out_PUSH_SPR_VAL [i], internal_PUSH_SPR_VAL      [i]);
+      }
     log_end(Stat_List_unit,FUNCTION);
   };

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/src/Stat_List_unit_transition.cpp

-                      r118
+                      r123
     else
+      {
+#ifdef DEBUG_TEST
+        {
+          uint32_t free_list_nb_gpr_free     = PORT_READ(in_INFO_NB_GPR_FREE);
+          uint32_t free_list_nb_spr_free     = PORT_READ(in_INFO_NB_SPR_FREE);
+          uint32_t stat_list_nb_gpr_free     = 0;
+          uint32_t stat_list_nb_spr_free     = 0;
+          uint32_t stat_list_nb_gpr_can_free = 0;
+          uint32_t stat_list_nb_spr_can_free = 0;
+          uint32_t stat_list_nb_gpr_link     = 0;
+          uint32_t stat_list_nb_spr_link     = 0;
+          uint32_t stat_list_nb_gpr_use      = 0;
+          uint32_t stat_list_nb_spr_use      = 0;
+          for (uint32_t i=0; i<_param->_nb_bank; i++)
+            {
+              for (uint32_t j=0; j<_param->_nb_general_register_by_bank; j++)
+                {
+                  if (gpr_stat_list [i][j]._is_free)
+                    stat_list_nb_gpr_free ++;
+                  if (gpr_stat_list [i][j]._is_link)
+                    stat_list_nb_gpr_link ++;
+                  if (gpr_stat_list [i][j]._is_use)
+                    stat_list_nb_gpr_use ++;
+                  if (gpr_stat_list [i][j].can_free())
+                    stat_list_nb_gpr_can_free ++;
+                }
+              for (uint32_t j=0; j<_param->_nb_special_register_by_bank; j++)
+                {
+                  if (spr_stat_list [i][j]._is_free)
+                    stat_list_nb_spr_free ++;
+                  if (spr_stat_list [i][j]._is_link)
+                    stat_list_nb_spr_link ++;
+                  if (spr_stat_list [i][j]._is_use)
+                    stat_list_nb_spr_use ++;
+                  if (spr_stat_list [i][j].can_free())
+                    stat_list_nb_spr_can_free ++;
+                }
+            }
+          uint32_t  nb_gpr_free = stat_list_nb_gpr_free+stat_list_nb_gpr_can_free;
+          uint32_t  nb_spr_free = stat_list_nb_spr_free+stat_list_nb_spr_can_free;
+          uint32_t _nb_gpr_free = (_param->_nb_general_register - _param->_nb_gpr_use_init);
+          uint32_t _nb_spr_free = (_param->_nb_special_register - _param->_nb_spr_use_init);
+          uint32_t  nb_gpr_link = stat_list_nb_gpr_link - _param->_nb_gpr_use_init;
+          uint32_t  nb_spr_link = stat_list_nb_spr_link - _param->_nb_spr_use_init;
+          uint32_t  nb_gpr_use  = stat_list_nb_gpr_use - _param->_nb_gpr_use_init;
+          uint32_t  nb_spr_use  = stat_list_nb_spr_use - _param->_nb_spr_use_init;
+          log_printf(TRACE,Stat_List_unit,FUNCTION,"  * nb_gpr_free : stat_list %d - free_list %d - free %d, link %d (%d), use %d (%d)",stat_list_nb_gpr_free,free_list_nb_gpr_free,nb_gpr_free,nb_gpr_link,stat_list_nb_gpr_link,nb_gpr_use,stat_list_nb_gpr_use);
+          log_printf(TRACE,Stat_List_unit,FUNCTION,"  * nb_spr_free : stat_list %d - free_list %d - free %d, link %d (%d), use %d (%d)",stat_list_nb_spr_free,free_list_nb_spr_free,nb_spr_free,nb_spr_link,stat_list_nb_spr_link,nb_spr_use,stat_list_nb_spr_use);
+          if (free_list_nb_gpr_free != stat_list_nb_gpr_free)
+            throw ERRORMORPHEO(FUNCTION,toString(_("Number of free general register is not valid. %d in Stat_List and %d in Free_list.\n"),stat_list_nb_gpr_free,free_list_nb_gpr_free));
+          if (free_list_nb_spr_free != stat_list_nb_spr_free)
+            throw ERRORMORPHEO(FUNCTION,toString(_("Number of free general register is not valid. %d in Stat_List and %d in Free_list.\n"),stat_list_nb_spr_free,free_list_nb_spr_free));
+          if (PORT_READ(in_INFO_ROB_EMPTY) and (nb_gpr_free != _nb_gpr_free))
+            throw ERRORMORPHEO(FUNCTION,toString(_("Rob is empty but they have %d general registers free or can_free and must be %d registers."),nb_gpr_free,_nb_gpr_free));
+          if (PORT_READ(in_INFO_ROB_EMPTY) and (nb_spr_free != _nb_spr_free))
+            throw ERRORMORPHEO(FUNCTION,toString(_("Rob is empty but they have %d special registers free or can_free and must be %d registers."),nb_spr_free,_nb_spr_free));
+        }
+#endif
         // =====================================================
         // =====[ INSERT ]======================================
 …
       for (uint32_t i=0; i<_param->_nb_bank; i++)
         for (uint32_t j=0; j<_param->_nb_general_register_by_bank; j++)
           log_printf(TRACE,Stat_List_unit,FUNCTION,"    * GPR[%.4d][%.5d] (%.5d) - free %.1d, link %.1d",
+          log_printf(TRACE,Stat_List_unit,FUNCTION,"    * GPR[%.4d][%.5d] (%.5d) - free %.1d, link %.1d, use %.1d",
                      i,
                      j,
                      (i<<_param->_shift_gpr)|j,
                      gpr_stat_list[i][j]._is_free,
+                     gpr_stat_list[i][j]._is_link// ,
+                     gpr_stat_list[i][j]._is_link,
+                     gpr_stat_list[i][j]._is_use// ,
 //                      gpr_stat_list[i][j]._is_valid,
 //                      gpr_stat_list[i][j]._counter
 …
       for (uint32_t i=0; i<_param->_nb_bank; i++)
         for (uint32_t j=0; j<_param->_nb_special_register_by_bank; j++)
           log_printf(TRACE,Stat_List_unit,FUNCTION,"    * SPR[%.4d][%.5d] (%.5d) - free %.1d, link %.1d",
+          log_printf(TRACE,Stat_List_unit,FUNCTION,"    * SPR[%.4d][%.5d] (%.5d) - free %.1d, link %.1d, use %.1d",
                      i,
                      j,
                      (i<<_param->_shift_spr)|j,
                      spr_stat_list[i][j]._is_free,
+                     spr_stat_list[i][j]._is_link// ,
+                     spr_stat_list[i][j]._is_link,
+                     spr_stat_list[i][j]._is_use// ,
 //                      spr_stat_list[i][j]._is_valid,
 //                      spr_stat_list[i][j]._counter

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/include/Register_translation_unit.h

-                      r121
+                      r123
   public    : SC_IN (Tevent_state_t    )  ***  in_RETIRE_EVENT_STATE       ;//[nb_front_end][nb_context]
+    // ~~~~~[ interface : "info" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+#ifdef DEBUG_TEST
+  public    : SC_IN (bool      )            *  in_INFO_ROB_EMPTY  ;
+#endif
     // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   public : morpheo::behavioural::core::multi_ooo_engine::ooo_engine::rename_unit::register_translation_unit::dependency_checking_unit::Dependency_checking_unit                   * _component_dependency_checking_unit;

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/src/Register_translation_unit.cpp

-                      r88
+                      r123
     log_printf(FUNC,Register_translation_unit,FUNCTION,"Begin");
 #if DEBUG_Register_translation_unit == true
     log_printf(INFO,Register_translation_unit,FUNCTION,_("<%s> Parameters"),_name.c_str());
+// #if DEBUG_Register_translation_unit == true
+//     log_printf(INFO,Register_translation_unit,FUNCTION,_("<%s> Parameters"),_name.c_str());
     std::cout << *param << std::endl;
 #endif
+//     std::cout << *param << std::endl;
+// #endif
     log_printf(INFO,Register_translation_unit,FUNCTION,"Allocation");

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/src/Register_translation_unit_allocation.cpp

-                      r122
+                      r123
       ALLOC2_INTERFACE_END(_param->_nb_front_end, _param->_nb_context[it1]);
+    }
+    // ~~~~~[ interface : "info" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+#ifdef DEBUG_TEST
+     {
+       ALLOC0_INTERFACE_BEGIN("info",IN, NORTH, _("Information"));
+       ALLOC0_SIGNAL_IN ( in_INFO_ROB_EMPTY  ,"rob_empty"  ,bool    ,1);
+       ALLOC0_INTERFACE_END();
+     }
+#endif
     // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 …
                                    dest,"out_PUSH_SPR_"+toString(i)+"_NUM_REG");
+        }
+    // ~~~~~[ interface : "info" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+#ifdef DEBUG_TEST
+      {
+        dest = _name+"_stat_list_unit";
+#ifdef POSITION
+        _component->interface_map (src ,"info"
+                                   dest,"info");
+#endif
+        COMPONENT_MAP(_component,src ,"out_INFO_NB_GPR_FREE",
+                                 dest, "in_INFO_NB_GPR_FREE");
+        COMPONENT_MAP(_component,src ,"out_INFO_NB_SPR_FREE",
+                                 dest, "in_INFO_NB_SPR_FREE");
+      }
+#endif
+    }
     // ===================================================================
 …
           //out_PUSH_SPR_NUM_REG - free_list_unit
+        }
+#ifdef DEBUG_TEST
+      {
+        dest = _name;
+#ifdef POSITION
+        _component->interface_map (src ,"info"
+                                   dest,"info");
+#endif
+        PORT_MAP(_component,src , "in_INFO_ROB_EMPTY",
+                            dest, "in_INFO_ROB_EMPTY");
+      }
+#endif
+    }

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/src/Register_translation_unit_deallocation.cpp

-                      r121
+                      r123
         DELETE2_SIGNAL(out_RETIRE_EVENT_ACK            ,_param->_nb_front_end, _param->_nb_context[it1],1);
         DELETE2_SIGNAL( in_RETIRE_EVENT_STATE          ,_param->_nb_front_end, _param->_nb_context[it1],_param->_size_event_state);
+#ifdef DEBUG_TEST
+        DELETE0_SIGNAL( in_INFO_ROB_EMPTY  ,1);
+#endif
+      }

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/include/Rename_select.h

-                      r122
+                      r123
   public    : SC_IN (Toperation_t      )  ***  in_RENAME_IN_OPERATION     ;//[nb_front_end][nb_inst_decod]
   public    : SC_IN (Tcontrol_t        )  ***  in_RENAME_IN_NO_EXECUTE    ;//[nb_front_end][nb_inst_decod]
+//public    : SC_IN (Tcontrol_t        )  ***  in_RENAME_IN_HAVE_EVENT    ;//[nb_front_end][nb_inst_decod]
+  public    : SC_IN (Tcontrol_t        )  ***  in_RENAME_IN_LAST_EVENT    ;//[nb_front_end][nb_inst_decod]
   public    : SC_IN (Tcontrol_t        )  ***  in_RENAME_IN_IS_DELAY_SLOT ;//[nb_front_end][nb_inst_decod]
 #ifdef DEBUG
 …
   public    : SC_OUT(Toperation_t      )   ** out_RENAME_OUT_OPERATION    ;//[nb_inst_rename]
   public    : SC_OUT(Tcontrol_t        )   ** out_RENAME_OUT_NO_EXECUTE   ;//[nb_inst_rename]
+  public    : SC_OUT(Tcontrol_t        )   ** out_RENAME_OUT_LAST_EVENT   ;//[nb_inst_rename]
   public    : SC_OUT(Tcontrol_t        )   ** out_RENAME_OUT_IS_DELAY_SLOT;//[nb_inst_rename]
 #ifdef DEBUG
 …
     // ~~~~~[ Interface "retire_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   public    : SC_IN (Tcontrol_t        )  ***  in_RETIRE_EVENT_FLUSH      ;//[nb_front_end][nb_context]
+//   public    : SC_IN (Tcontrol_t        )  ***  in_RETIRE_EVENT_FLUSH      ;//[nb_front_end][nb_context]
   public    : SC_IN (Tcontrol_t        )  ***  in_RETIRE_EVENT_STOP       ;//[nb_front_end][nb_context]

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/src/Rename_select.cpp

-                      r122
+                      r123
     log_printf(FUNC,Rename_select,FUNCTION,"Begin");
 #if DEBUG_Core == true
     log_printf(INFO,Core,FUNCTION,_("<%s> Parameters"),_name.c_str());
     std::cout << *param << std::endl;
 #endif
+// #if DEBUG_Core == true
+//     log_printf(INFO,Core,FUNCTION,_("<%s> Parameters"),_name.c_str());
+//     std::cout << *param << std::endl;
+// #endif
     log_printf(INFO,Rename_select,FUNCTION,"Allocation");
 …
                         << (*(in_RENAME_IN_OPERATION     [i][j]))
                         << (*(in_RENAME_IN_NO_EXECUTE    [i][j]))
+//                      << (*(in_RENAME_IN_HAVE_EVENT    [i][j]))
+                        << (*(in_RENAME_IN_LAST_EVENT    [i][j]))
                         << (*(in_RENAME_IN_IS_DELAY_SLOT [i][j]))
 #ifdef DEBUG
 …
         for (uint32_t i=0; i<_param->_nb_front_end; i++)
           for (uint32_t j=0; j<_param->_nb_context [i]; j++)
             sensitive << (*(in_RETIRE_EVENT_FLUSH [i][j]))
+            sensitive // << (*(in_RETIRE_EVENT_FLUSH [i][j]))
                       << (*(in_RETIRE_EVENT_STOP  [i][j]));

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/src/Rename_select_allocation.cpp

-                      r122
+                      r123
       _ALLOC2_SIGNAL_IN ( in_RENAME_IN_OPERATION     ,"operation"    ,Toperation_t      ,_param->_size_operation             , _param->_nb_front_end, _param->_nb_inst_decod[it1]);
       _ALLOC2_SIGNAL_IN ( in_RENAME_IN_NO_EXECUTE    ,"no_execute"   ,Tcontrol_t        ,1                                   , _param->_nb_front_end, _param->_nb_inst_decod[it1]);
+//    _ALLOC2_SIGNAL_IN ( in_RENAME_IN_HAVE_EVENT    ,"have_event"   ,Tcontrol_t        ,1                                   , _param->_nb_front_end, _param->_nb_inst_decod[it1]);
+      _ALLOC2_SIGNAL_IN ( in_RENAME_IN_LAST_EVENT    ,"last_event"   ,Tcontrol_t        ,1                                   , _param->_nb_front_end, _param->_nb_inst_decod[it1]);
       _ALLOC2_SIGNAL_IN ( in_RENAME_IN_IS_DELAY_SLOT ,"is_delay_slot",Tcontrol_t        ,1                                   , _param->_nb_front_end, _param->_nb_inst_decod[it1]);
 #ifdef DEBUG
 …
       ALLOC1_SIGNAL_OUT(out_RENAME_OUT_OPERATION     ,"operation"    ,Toperation_t      ,_param->_size_operation             );
       ALLOC1_SIGNAL_OUT(out_RENAME_OUT_NO_EXECUTE    ,"no_execute"   ,Tcontrol_t        ,1                                   );
+      ALLOC1_SIGNAL_OUT(out_RENAME_OUT_LAST_EVENT    ,"last_event"   ,Tcontrol_t        ,1                                   );
       ALLOC1_SIGNAL_OUT(out_RENAME_OUT_IS_DELAY_SLOT ,"is_delay_slot",Tcontrol_t        ,1                                   );
 #ifdef DEBUG
 …
       ALLOC2_INTERFACE_BEGIN("retire_event", IN,NORTH, _("Retire event"), _param->_nb_front_end, _param->_nb_context[it1]);
       _ALLOC2_SIGNAL_IN ( in_RETIRE_EVENT_FLUSH         ,"flush"                ,Tcontrol_t        ,1                        , _param->_nb_front_end, _param->_nb_context[it1]);
+//       _ALLOC2_SIGNAL_IN ( in_RETIRE_EVENT_FLUSH         ,"flush"                ,Tcontrol_t        ,1                        , _param->_nb_front_end, _param->_nb_context[it1]);
       _ALLOC2_SIGNAL_IN ( in_RETIRE_EVENT_STOP          ,"stop"                 ,Tcontrol_t        ,1                        , _param->_nb_front_end, _param->_nb_context[it1]);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/src/Rename_select_deallocation.cpp

-                      r122
+                      r123
         DELETE2_SIGNAL( in_RENAME_IN_OPERATION     ,_param->_nb_front_end, _param->_nb_inst_decod[it1],_param->_size_operation             );
         DELETE2_SIGNAL( in_RENAME_IN_NO_EXECUTE    ,_param->_nb_front_end, _param->_nb_inst_decod[it1],1                                   );
+//      DELETE2_SIGNAL( in_RENAME_IN_HAVE_EVENT    ,_param->_nb_front_end, _param->_nb_inst_decod[it1],1                                   );
+        DELETE2_SIGNAL( in_RENAME_IN_LAST_EVENT    ,_param->_nb_front_end, _param->_nb_inst_decod[it1],1                                   );
         DELETE2_SIGNAL( in_RENAME_IN_IS_DELAY_SLOT ,_param->_nb_front_end, _param->_nb_inst_decod[it1],1                                   );
 #ifdef DEBUG
 …
         DELETE1_SIGNAL(out_RENAME_OUT_OPERATION     ,_param->_nb_inst_rename,_param->_size_operation             );
         DELETE1_SIGNAL(out_RENAME_OUT_NO_EXECUTE    ,_param->_nb_inst_rename,1                                   );
+        DELETE1_SIGNAL(out_RENAME_OUT_LAST_EVENT    ,_param->_nb_inst_rename,1                                   );
         DELETE1_SIGNAL(out_RENAME_OUT_IS_DELAY_SLOT ,_param->_nb_inst_rename,1                                   );
 #ifdef DEBUG
 …
         DELETE1_SIGNAL(out_RENAME_OUT_EXCEPTION     ,_param->_nb_inst_rename,_param->_size_exception             );
         DELETE2_SIGNAL( in_RETIRE_EVENT_FLUSH       ,_param->_nb_front_end, _param->_nb_context[it1],1);
+//         DELETE2_SIGNAL( in_RETIRE_EVENT_FLUSH       ,_param->_nb_front_end, _param->_nb_context[it1],1);
         DELETE2_SIGNAL( in_RETIRE_EVENT_STOP        ,_param->_nb_front_end, _param->_nb_context[it1],1);
+      }

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/src/Rename_select_genMealy.cpp

-                      r122
+                      r123
 namespace rename_select {
-// #define CONTINUE_ON_EVENT_STOP
 #undef  FUNCTION
 #define FUNCTION "Rename_select::genMealy"
 …
     Tcontrol_t val                  [_param->_nb_inst_rename];
     Tcontrol_t ack                  [_param->_nb_front_end][_param->_max_nb_inst_decod];
-    Tcontrol_t previous_transaction [_param->_nb_front_end];
     for (uint32_t i=0; i<_param->_nb_inst_rename; ++i)
       val [i] = false;
     for (uint32_t i=0; i<_param->_nb_front_end; i++)
+      for (uint32_t j=0; j<_param->_nb_inst_decod[i]; j++)
+        ack [i][j] = false;
+    if (PORT_READ(in_NRESET))
+      {
+        previous_transaction [i] = true;
+        for (uint32_t j=0; j<_param->_nb_inst_decod[i]; j++)
+          ack [i][j] = false;
+      }
+        Tcontrol_t previous_transaction [_param->_nb_front_end];
+        for (uint32_t i=0; i<_param->_nb_front_end; i++)
+          previous_transaction [i] = true;
     std::list<generic::priority::select_t> * select = _priority->select();
 …
                 // Test if ROB is Flushed
-#ifndef CONTINUE_ON_EVENT_STOP
                 if (not stop)
-#endif
+                  {
                     // Find !!!
 …
                     ack [x][y] = PORT_READ(in_RENAME_OUT_ACK [i]);
+                    Tcontrol_t     have_event          = (PORT_READ(in_RETIRE_EVENT_FLUSH [x][context_id])
+#ifdef CONTINUE_ON_EVENT_STOP
+                                                          or stop
+#endif
                                                           );
                     Tcontrol_t     can_register_access = not have_event;
                     Tcontrol_t     no_execute          = (PORT_READ(in_RENAME_IN_NO_EXECUTE [x][y]) or have_event);
                     Tcontrol_t     read_ra             = (PORT_READ(in_RENAME_IN_READ_RA    [x][y]) and can_register_access);
                     Tcontrol_t     read_rb             = (PORT_READ(in_RENAME_IN_READ_RB    [x][y]) and can_register_access);
                     Tcontrol_t     read_rc             = (PORT_READ(in_RENAME_IN_READ_RC    [x][y]) and can_register_access);
                     Tcontrol_t     write_rd            = (PORT_READ(in_RENAME_IN_WRITE_RD   [x][y]) and can_register_access);
                     Tcontrol_t     write_re            = (PORT_READ(in_RENAME_IN_WRITE_RE   [x][y]) and can_register_access);
 //                  Tcontrol_t     read_ra             = (PORT_READ(in_RENAME_IN_READ_RA    [x][y]));
 //                  Tcontrol_t     read_rb             = (PORT_READ(in_RENAME_IN_READ_RB    [x][y]));
 //                  Tcontrol_t     read_rc             = (PORT_READ(in_RENAME_IN_READ_RC    [x][y]));
 //                  Tcontrol_t     write_rd            = (PORT_READ(in_RENAME_IN_WRITE_RD   [x][y]));
 //                  Tcontrol_t     write_re            = (PORT_READ(in_RENAME_IN_WRITE_RE   [x][y]));
+//                  Tcontrol_t     have_event          = (PORT_READ(in_RETIRE_EVENT_FLUSH [x][context_id]) // or
+//                                                           );
+//                  log_printf(TRACE,Rename_select,FUNCTION,"      * have_event           : %d",have_event);
+//                  Tcontrol_t     can_register_access = not have_event;
+//                  Tcontrol_t     no_execute          = (PORT_READ(in_RENAME_IN_NO_EXECUTE [x][y]) or have_event);
+//                  Tcontrol_t     read_ra             = (PORT_READ(in_RENAME_IN_READ_RA    [x][y]) and can_register_access);
+//                  Tcontrol_t     read_rb             = (PORT_READ(in_RENAME_IN_READ_RB    [x][y]) and can_register_access);
+//                  Tcontrol_t     read_rc             = (PORT_READ(in_RENAME_IN_READ_RC    [x][y]) and can_register_access);
+//                  Tcontrol_t     write_rd            = (PORT_READ(in_RENAME_IN_WRITE_RD   [x][y]) and can_register_access);
+//                  Tcontrol_t     write_re            = (PORT_READ(in_RENAME_IN_WRITE_RE   [x][y]) and can_register_access);
+                    Tcontrol_t     no_execute          = (PORT_READ(in_RENAME_IN_NO_EXECUTE [x][y]));
+                    Tcontrol_t     read_ra             = (PORT_READ(in_RENAME_IN_READ_RA    [x][y]));
+                    Tcontrol_t     read_rb             = (PORT_READ(in_RENAME_IN_READ_RB    [x][y]));
+                    Tcontrol_t     read_rc             = (PORT_READ(in_RENAME_IN_READ_RC    [x][y]));
+                    Tcontrol_t     write_rd            = (PORT_READ(in_RENAME_IN_WRITE_RD   [x][y]));
+                    Tcontrol_t     write_re            = (PORT_READ(in_RENAME_IN_WRITE_RE   [x][y]));
+                    log_printf(TRACE,Rename_select,FUNCTION,"      * have_event           : %d",have_event);
+                    log_printf(TRACE,Rename_select,FUNCTION,"      * no_execute (before)  : %d",PORT_READ(in_RENAME_IN_NO_EXECUTE [x][y]));
+                    log_printf(TRACE,Rename_select,FUNCTION,"      * no_execute (after)   : %d",no_execute);
+                    log_printf(TRACE,Rename_select,FUNCTION,"      * no_execute           : %d",no_execute);
                     if (_param->_have_port_front_end_id)
 …
                     PORT_WRITE(out_RENAME_OUT_OPERATION    [i],PORT_READ(in_RENAME_IN_OPERATION     [x][y]));
                     PORT_WRITE(out_RENAME_OUT_NO_EXECUTE   [i],no_execute);
+                    PORT_WRITE(out_RENAME_OUT_LAST_EVENT   [i],PORT_READ(in_RENAME_IN_LAST_EVENT    [x][y]));
                     PORT_WRITE(out_RENAME_OUT_IS_DELAY_SLOT[i],PORT_READ(in_RENAME_IN_IS_DELAY_SLOT [x][y]));
 #ifdef DEBUG
 …
+      }
+      }
+//     else
+//       {
+//       }
     for (uint32_t i=0; i<_param->_nb_inst_rename; ++i)
       PORT_WRITE(out_RENAME_OUT_VAL [i], val [i]);
 …
       for (uint32_t j=0; j<_param->_nb_inst_decod[i]; j++)
         PORT_WRITE(out_RENAME_IN_ACK [i][j], ack [i][j]);
     log_end(Rename_select,FUNCTION);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Rename_unit_Glue.cpp

-                      r122
+                      r123
     usage_environment(_usage);
 #if DEBUG_Rename_unit_Glue == true
     log_printf(INFO,Rename_unit_Glue,FUNCTION,_("<%s> Parameters"),_name.c_str());
     std::cout << *param << std::endl;
 #endif
+// #if DEBUG_Rename_unit_Glue == true
+//     log_printf(INFO,Rename_unit_Glue,FUNCTION,_("<%s> Parameters"),_name.c_str());
+//     std::cout << *param << std::endl;
+// #endif
     log_printf(INFO,Rename_unit_Glue,FUNCTION,_("<%s> : Allocation"),_name.c_str());

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Rename_unit_Glue_genMealy_insert.cpp

-                      r88
+                      r123
     log_function(Rename_unit_Glue,FUNCTION,_name.c_str());
+    if (PORT_READ(in_NRESET))
+      {
     for (uint32_t i=0; i<_param->_nb_inst_insert; i++)
+      {
 …
         PORT_WRITE(out_INSERT_LOAD_STORE_QUEUE_POINTER_OPERATION    [i],OPERATION         );
+      }
+      }
     log_end(Rename_unit_Glue,FUNCTION);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Rename_unit_Glue_genMealy_insert_valack.cpp

-                      r115
+                      r123
     log_function(Rename_unit_Glue,FUNCTION,_name.c_str());
+    if (PORT_READ(in_NRESET))
+      {
 //     // Transaction must be in-order - made in rename_select
 //     Tcontrol_t previous_transaction = true;
 …
 //      previous_transaction = RENAME_SELECT_VAL and RENAME_SELECT_ACK;
+      }
+      }
+    else
+      {
+        for (uint32_t i=0; i<_param->_nb_inst_insert; i++)
+          {
+//      PORT_WRITE(out_INSERT_VAL                          [i], 0);
+        PORT_WRITE(out_INSERT_RENAME_SELECT_ACK            [i], 0);
+        PORT_WRITE(out_INSERT_REGISTER_TRANSLATION_VAL     [i], 0);
+        PORT_WRITE(out_INSERT_LOAD_STORE_QUEUE_POINTER_VAL [i], 0);
+          }
+      }
     log_end(Rename_unit_Glue,FUNCTION);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Rename_unit_Glue_genMealy_retire_event_valack.cpp

-                      r122
+                      r123
     log_function(Rename_unit_Glue,FUNCTION,_name.c_str());
+    if (PORT_READ(in_NRESET))
+      {
     for (uint32_t i=0; i<_param->_nb_front_end; i++)
       for (uint32_t j=0; j<_param->_nb_context[i]; j++)
 …
           log_printf(TRACE,Rename_unit_Glue,FUNCTION,"    * load_store_queue_pointer_ack (r) : %d",LOAD_STORE_QUEUE_POINTER_ACK);
+        }
+      }
+    else
+      {
+        for (uint32_t i=0; i<_param->_nb_front_end; i++)
+          for (uint32_t j=0; j<_param->_nb_context[i]; j++)
+            {
+              PORT_WRITE(out_RETIRE_EVENT_ACK                          [i][j], 0);
+              PORT_WRITE(out_RETIRE_EVENT_LOAD_STORE_QUEUE_POINTER_VAL [i][j], 0);
+              PORT_WRITE(out_RETIRE_EVENT_REGISTER_TRANSLATION_VAL     [i][j], 0);
+            }
+      }
     log_end(Rename_unit_Glue,FUNCTION);
   };

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Rename_unit_Glue_genMealy_retire_valack.cpp

-                      r110
+                      r123
     log_function(Rename_unit_Glue,FUNCTION,_name.c_str());
+    if (PORT_READ(in_NRESET))
+      {
     // Transaction must be in-order - made in commit_unit
 //     Tcontrol_t previous_transaction = true;
 …
         log_printf(TRACE,Rename_unit_Glue,FUNCTION,"    * load_store_queue_pointer_ack (r) : %d",LOAD_STORE_QUEUE_POINTER_ACK);
+      }
+      }
+    else
+      {
+        for (uint32_t i=0; i<_param->_nb_inst_retire; i++)
+          {
+        PORT_WRITE(out_RETIRE_ACK                          [i], 0);
+        PORT_WRITE(out_RETIRE_LOAD_STORE_QUEUE_POINTER_VAL [i], 0);
+        PORT_WRITE(out_RETIRE_REGISTER_TRANSLATION_VAL     [i], 0);
+          }
+      }
     log_end(Rename_unit_Glue,FUNCTION);
   };

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/include/Rename_unit.h

-                      r122
+                      r123
   public    : SC_IN (Toperation_t      )  ***  in_RENAME_IN_OPERATION         ;//[nb_front_end][nb_inst_decod]
   public    : SC_IN (Tcontrol_t        )  ***  in_RENAME_IN_NO_EXECUTE        ;//[nb_front_end][nb_inst_decod]
+//public    : SC_IN (Tcontrol_t        )  ***  in_RENAME_IN_HAVE_EVENT        ;//[nb_front_end][nb_inst_decod]
+  public    : SC_IN (Tcontrol_t        )  ***  in_RENAME_IN_LAST_EVENT        ;//[nb_front_end][nb_inst_decod]
   public    : SC_IN (Tcontrol_t        )  ***  in_RENAME_IN_IS_DELAY_SLOT     ;//[nb_front_end][nb_inst_decod]
 #ifdef DEBUG
 …
   public    : SC_OUT(Toperation_t      )   ** out_INSERT_OPERATION            ;//[nb_inst_insert]
   public    : SC_OUT(Tcontrol_t        )   ** out_INSERT_NO_EXECUTE           ;//[nb_inst_insert]
+  public    : SC_OUT(Tcontrol_t        )   ** out_INSERT_LAST_EVENT           ;//[nb_inst_insert]
   public    : SC_OUT(Tcontrol_t        )   ** out_INSERT_IS_DELAY_SLOT        ;//[nb_inst_insert]
 #ifdef DEBUG
 …
   public    : SC_OUT(Tcontrol_t        )  *** out_RETIRE_EVENT_ACK            ;//[nb_front_end][nb_context]
   public    : SC_IN (Tevent_state_t    )  ***  in_RETIRE_EVENT_STATE          ;//[nb_front_end][nb_context]
   public    : SC_IN (Tcontrol_t        )  ***  in_RETIRE_EVENT_FLUSH          ;//[nb_front_end][nb_context]
+//public    : SC_IN (Tcontrol_t        )  ***  in_RETIRE_EVENT_FLUSH          ;//[nb_front_end][nb_context]
   public    : SC_IN (Tcontrol_t        )  ***  in_RETIRE_EVENT_STOP           ;//[nb_front_end][nb_context]
     // ~~~~~[ Interface : "spr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   public    : SC_IN (Tspr_t            )  ***  in_SPR_READ_SR                 ;//[nb_front_end][nb_context]
+    // ~~~~~[ interface : "info" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+#ifdef DEBUG_TEST
+  public    : SC_IN (bool      )            *  in_INFO_ROB_EMPTY  ;
+#endif
     // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Rename_unit.cpp

-                      r88
+                      r123
     usage_environment(_usage);
 #if DEBUG_Rename_unit == true
     log_printf(INFO,Rename_unit,FUNCTION,_("<%s> Parameters"),_name.c_str());
+// #if DEBUG_Rename_unit == true
+//     log_printf(INFO,Rename_unit,FUNCTION,_("<%s> Parameters"),_name.c_str());
     std::cout << *param << std::endl;
 #endif
+//     std::cout << *param << std::endl;
+// #endif
     log_printf(INFO,Rename_unit,FUNCTION,_("<%s> : Allocation"),_name.c_str());

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Rename_unit_allocation.cpp

-                      r122
+                      r123
       _ALLOC2_SIGNAL_IN ( in_RENAME_IN_OPERATION     ,"operation"    ,Toperation_t      ,_param->_size_operation             , _param->_nb_front_end, _param->_nb_inst_decod[it1]);
       _ALLOC2_SIGNAL_IN ( in_RENAME_IN_NO_EXECUTE    ,"no_execute"   ,Tcontrol_t        ,1                                   , _param->_nb_front_end, _param->_nb_inst_decod[it1]);
+//    _ALLOC2_SIGNAL_IN ( in_RENAME_IN_HAVE_EVENT    ,"have_event"   ,Tcontrol_t        ,1                                   , _param->_nb_front_end, _param->_nb_inst_decod[it1]);
+      _ALLOC2_SIGNAL_IN ( in_RENAME_IN_LAST_EVENT    ,"last_event"   ,Tcontrol_t        ,1                                   , _param->_nb_front_end, _param->_nb_inst_decod[it1]);
       _ALLOC2_SIGNAL_IN ( in_RENAME_IN_IS_DELAY_SLOT ,"is_delay_slot",Tcontrol_t        ,1                                   , _param->_nb_front_end, _param->_nb_inst_decod[it1]);
 #ifdef DEBUG
 …
       ALLOC1_SIGNAL_OUT(out_INSERT_OPERATION            ,"operation"            ,Toperation_t      ,_param->_size_operation             );
       ALLOC1_SIGNAL_OUT(out_INSERT_NO_EXECUTE           ,"no_execute"           ,Tcontrol_t        ,1                                   );
+      ALLOC1_SIGNAL_OUT(out_INSERT_LAST_EVENT           ,"last_event"           ,Tcontrol_t        ,1                                   );
       ALLOC1_SIGNAL_OUT(out_INSERT_IS_DELAY_SLOT        ,"is_delay_slot"        ,Tcontrol_t        ,1                                   );
 #ifdef DEBUG
 …
       _ALLOC2_VALACK_OUT(out_RETIRE_EVENT_ACK           ,ACK,_param->_nb_front_end, _param->_nb_context[it1]);
       _ALLOC2_SIGNAL_IN ( in_RETIRE_EVENT_STATE         ,"state"                ,Tevent_state_t    ,_param->_size_event_state, _param->_nb_front_end, _param->_nb_context[it1]);
       _ALLOC2_SIGNAL_IN ( in_RETIRE_EVENT_FLUSH         ,"flush"                ,Tcontrol_t        ,1                        , _param->_nb_front_end, _param->_nb_context[it1]);
+//       _ALLOC2_SIGNAL_IN ( in_RETIRE_EVENT_FLUSH         ,"flush"                ,Tcontrol_t        ,1                        , _param->_nb_front_end, _param->_nb_context[it1]);
       _ALLOC2_SIGNAL_IN ( in_RETIRE_EVENT_STOP          ,"stop"                 ,Tcontrol_t        ,1                        , _param->_nb_front_end, _param->_nb_context[it1]);
 …
       ALLOC2_INTERFACE_END(_param->_nb_front_end, _param->_nb_context[it1]);
+    }
+    // ~~~~~[ interface : "info" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+#ifdef DEBUG_TEST
+     {
+       ALLOC0_INTERFACE_BEGIN("info",IN, NORTH, _("Information"));
+       ALLOC0_SIGNAL_IN ( in_INFO_ROB_EMPTY  ,"rob_empty"  ,bool    ,1);
+       ALLOC0_INTERFACE_END();
+     }
+#endif
     // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 …
             PORT_MAP(_component,src , "in_RENAME_IN_"+toString(i)+"_"+toString(j)+"_NO_EXECUTE"   ,
                                 dest, "in_RENAME_IN_"+toString(i)+"_"+toString(j)+"_NO_EXECUTE"   );
+//          PORT_MAP(_component,src , "in_RENAME_IN_"+toString(i)+"_"+toString(j)+"_HAVE_EVENT"   ,
+//                              dest, "in_RENAME_IN_"+toString(i)+"_"+toString(j)+"_HAVE_EVENT"   );
+            PORT_MAP(_component,src , "in_RENAME_IN_"+toString(i)+"_"+toString(j)+"_LAST_EVENT"   ,
+                                dest, "in_RENAME_IN_"+toString(i)+"_"+toString(j)+"_LAST_EVENT"   );
             PORT_MAP(_component,src , "in_RENAME_IN_"+toString(i)+"_"+toString(j)+"_IS_DELAY_SLOT",
                                 dest, "in_RENAME_IN_"+toString(i)+"_"+toString(j)+"_IS_DELAY_SLOT");
 …
           PORT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+"_EXCEPTION_USE",
                               dest,"out_INSERT_"    +toString(i)+"_EXCEPTION_USE");
+          PORT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+"_LAST_EVENT",
+                              dest,"out_INSERT_"    +toString(i)+"_LAST_EVENT");
           dest = _name+"_register_translation_unit";
 …
                                        dest,"retire_event_"+toString(i)+"_"+toString(j));
 #endif
             PORT_MAP(_component,src , "in_RETIRE_EVENT_"+toString(i)+"_"+toString(j)+"_FLUSH",
                                 dest, "in_RETIRE_EVENT_"+toString(i)+"_"+toString(j)+"_FLUSH");
+//          PORT_MAP(_component,src , "in_RETIRE_EVENT_"+toString(i)+"_"+toString(j)+"_FLUSH",
+//                                 dest, "in_RETIRE_EVENT_"+toString(i)+"_"+toString(j)+"_FLUSH");
             PORT_MAP(_component,src , "in_RETIRE_EVENT_"+toString(i)+"_"+toString(j)+"_STOP",
                                 dest, "in_RETIRE_EVENT_"+toString(i)+"_"+toString(j)+"_STOP");
 …
                                 dest, "in_RETIRE_EVENT_"+toString(i)+"_"+toString(j)+"_STATE");
+          }
+#ifdef DEBUG_TEST
+      {
+        dest = _name;
+#ifdef POSITION
+        _component->interface_map (src ,"info"
+                                   dest,"info");
+#endif
+        PORT_MAP(_component,src , "in_INFO_ROB_EMPTY",
+                            dest, "in_INFO_ROB_EMPTY");
+      }
+#endif
+    }

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Rename_unit_deallocation.cpp

-                      r122
+                      r123
         DELETE2_SIGNAL( in_RENAME_IN_OPERATION         ,_param->_nb_front_end, _param->_nb_inst_decod[it1],_param->_size_operation             );
         DELETE2_SIGNAL( in_RENAME_IN_NO_EXECUTE        ,_param->_nb_front_end, _param->_nb_inst_decod[it1],1                                   );
+//      DELETE2_SIGNAL( in_RENAME_IN_HAVE_EVENT        ,_param->_nb_front_end, _param->_nb_inst_decod[it1],1                                   );
+        DELETE2_SIGNAL( in_RENAME_IN_LAST_EVENT        ,_param->_nb_front_end, _param->_nb_inst_decod[it1],1                                   );
         DELETE2_SIGNAL( in_RENAME_IN_IS_DELAY_SLOT     ,_param->_nb_front_end, _param->_nb_inst_decod[it1],1                                   );
 #ifdef DEBUG
 …
         DELETE1_SIGNAL(out_INSERT_OPERATION            ,_param->_nb_inst_insert,_param->_size_operation             );
         DELETE1_SIGNAL(out_INSERT_NO_EXECUTE           ,_param->_nb_inst_insert,1                                   );
+        DELETE1_SIGNAL(out_INSERT_LAST_EVENT           ,_param->_nb_inst_insert,1                                   );
         DELETE1_SIGNAL(out_INSERT_IS_DELAY_SLOT        ,_param->_nb_inst_insert,1                                   );
 #ifdef DEBUG
 …
         DELETE2_SIGNAL(out_RETIRE_EVENT_ACK            ,_param->_nb_front_end, _param->_nb_context[it1],1);
         DELETE2_SIGNAL( in_RETIRE_EVENT_STATE          ,_param->_nb_front_end, _param->_nb_context[it1],_param->_size_event_state);
         DELETE2_SIGNAL( in_RETIRE_EVENT_FLUSH          ,_param->_nb_front_end, _param->_nb_context[it1],1);
+//         DELETE2_SIGNAL( in_RETIRE_EVENT_FLUSH          ,_param->_nb_front_end, _param->_nb_context[it1],1);
         DELETE2_SIGNAL( in_RETIRE_EVENT_STOP           ,_param->_nb_front_end, _param->_nb_context[it1],1);
         DELETE2_SIGNAL(in_SPR_READ_SR                  ,_param->_nb_front_end, _param->_nb_context[it1],_param->_size_spr);
+#ifdef DEBUG_TEST
+        DELETE0_SIGNAL( in_INFO_ROB_EMPTY  ,1);
+#endif
+      }
     // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit.cpp

-                      r88
+                      r123
     usage_environment(_usage);
 #if DEBUG_Core == true
     log_printf(INFO,Core,FUNCTION,_("<%s> Parameters"),_name.c_str());
+// #if DEBUG_Core == true
+//     log_printf(INFO,Core,FUNCTION,_("<%s> Parameters"),_name.c_str());
     std::cout << *param << std::endl;
 #endif
+//     std::cout << *param << std::endl;
+// #endif
     log_printf(INFO,Special_Register_unit,FUNCTION,_("<%s> : Allocation"),_name.c_str());

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_genMealy_spr_access.cpp

-                      r98
+                      r123
     log_function(Special_Register_unit,FUNCTION,_name.c_str());
+    if (PORT_READ(in_NRESET))
+      {
     // ===================================================================
     // =====[ SPR_ACCESS ]================================================
 …
           PORT_WRITE(out_SPR_ACCESS_INVALID [i], not valid);
+        }
+      }
+//     else
+//       {
+//       }
     log_end(Special_Register_unit,FUNCTION);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_genMoore.cpp

-                      r98
+                      r123
     log_function(Special_Register_unit,FUNCTION,_name.c_str());
+//     if (PORT_READ(in_NRESET))
+      {
     // ===================================================================
     // =====[ SPR_READ ]==================================================
 …
 //        PORT_WRITE(out_SPR_READ_SR [i][j],sr->read());
 //      }
+      }
     log_end(Special_Register_unit,FUNCTION);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/include/OOO_Engine.h

r122	r123
76	76	public : SC_IN (Toperation_t ) *** in_RENAME_OPERATION ;//[nb_front_end][nb_inst_decod]
77	77	public : SC_IN (Tcontrol_t ) *** in_RENAME_NO_EXECUTE ;//[nb_front_end][nb_inst_decod]
	78	//public : SC_IN (Tcontrol_t ) *** in_RENAME_HAVE_EVENT ;//[nb_front_end][nb_inst_decod]
	79	public : SC_IN (Tcontrol_t ) *** in_RENAME_LAST_EVENT ;//[nb_front_end][nb_inst_decod]
78	80	public : SC_IN (Tcontrol_t ) *** in_RENAME_IS_DELAY_SLOT ;//[nb_front_end][nb_inst_decod]
79	81	#ifdef DEBUG

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine.cpp

-                      r88
+                      r123
     usage_environment(_usage);
 #if DEBUG_OOO_Engine == true
     log_printf(TRACE,OOO_Engine,FUNCTION,_("<%s> Parameters"),_name.c_str());
+// #if DEBUG_OOO_Engine == true
+//     log_printf(TRACE,OOO_Engine,FUNCTION,_("<%s> Parameters"),_name.c_str());
     std::cout << *param << std::endl;
 #endif
+//     std::cout << *param << std::endl;
+// #endif
     log_printf(INFO,OOO_Engine,FUNCTION,_("<%s> Allocation"),_name.c_str());

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_allocation.cpp

-                      r122
+                      r123
       _ALLOC2_SIGNAL_IN ( in_RENAME_OPERATION                 ,"OPERATION"                 ,Toperation_t      ,_param->_size_operation              ,_param->_nb_front_end,_param->_nb_inst_decod[it1]);
       _ALLOC2_SIGNAL_IN ( in_RENAME_NO_EXECUTE                ,"NO_EXECUTE"                ,Tcontrol_t        ,1                                    ,_param->_nb_front_end,_param->_nb_inst_decod[it1]);
+//    _ALLOC2_SIGNAL_IN ( in_RENAME_HAVE_EVENT                ,"HAVE_EVENT"                ,Tcontrol_t        ,1                                    ,_param->_nb_front_end,_param->_nb_inst_decod[it1]);
+      _ALLOC2_SIGNAL_IN ( in_RENAME_LAST_EVENT                ,"LAST_EVENT"                ,Tcontrol_t        ,1                                    ,_param->_nb_front_end,_param->_nb_inst_decod[it1]);
       _ALLOC2_SIGNAL_IN ( in_RENAME_IS_DELAY_SLOT             ,"IS_DELAY_SLOT"             ,Tcontrol_t        ,1                                    ,_param->_nb_front_end,_param->_nb_inst_decod[it1]);
 #ifdef DEBUG
 …
                     PORT_MAP(_component,src , "in_RENAME_IN_"+toString(x)+"_"+toString(k)+"_NO_EXECUTE"   ,
                                         dest, "in_RENAME_"   +toString(j)+"_"+toString(k)+"_NO_EXECUTE"   );
+//                     PORT_MAP(_component,src , "in_RENAME_IN_"+toString(x)+"_"+toString(k)+"_HAVE_EVENT"   ,
+//                                         dest, "in_RENAME_"   +toString(j)+"_"+toString(k)+"_HAVE_EVENT"   );
+                    PORT_MAP(_component,src , "in_RENAME_IN_"+toString(x)+"_"+toString(k)+"_LAST_EVENT"   ,
+                                        dest, "in_RENAME_"   +toString(j)+"_"+toString(k)+"_LAST_EVENT"   );
                     PORT_MAP(_component,src , "in_RENAME_IN_"+toString(x)+"_"+toString(k)+"_IS_DELAY_SLOT",
                                         dest, "in_RENAME_"   +toString(j)+"_"+toString(k)+"_IS_DELAY_SLOT");
 …
             COMPONENT_MAP(_component,src ,"out_INSERT_"+toString(j)                +"_IS_DELAY_SLOT" ,
                                      dest, "in_INSERT_"+toString(i)+"_"+toString(j)+"_IS_DELAY_SLOT" );
+//             COMPONENT_MAP(_component,src ,"out_INSERT_"+toString(j)                +"_HAVE_EVENT"    ,
+//                                      dest, "in_INSERT_"+toString(i)+"_"+toString(j)+"_HAVE_EVENT"    );
+            COMPONENT_MAP(_component,src ,"out_INSERT_"+toString(j)                +"_LAST_EVENT"    ,
+                                     dest, "in_INSERT_"+toString(i)+"_"+toString(j)+"_LAST_EVENT"    );
 #ifdef DEBUG
             COMPONENT_MAP(_component,src ,"out_INSERT_"+toString(j)                +"_ADDRESS"       ,
 …
                     COMPONENT_MAP(_component,src , "in_RETIRE_EVENT_"+toString(x)+"_"+toString(k)+"_STATE",
                                              dest,"out_RETIRE_EVENT_"+toString(j)+"_"+toString(k)+"_STATE");
                     COMPONENT_MAP(_component,src , "in_RETIRE_EVENT_"+toString(x)+"_"+toString(k)+"_FLUSH",
                                              dest,"out_RETIRE_EVENT_"+toString(j)+"_"+toString(k)+"_FLUSH");
+//                     COMPONENT_MAP(_component,src , "in_RETIRE_EVENT_"+toString(x)+"_"+toString(k)+"_FLUSH",
+//                                              dest,"out_RETIRE_EVENT_"+toString(j)+"_"+toString(k)+"_FLUSH");
                     COMPONENT_MAP(_component,src , "in_RETIRE_EVENT_"+toString(x)+"_"+toString(k)+"_STOP",
                                              dest,"out_RETIRE_EVENT_"+toString(j)+"_"+toString(k)+"_STOP");
 …
+              }
+        }
+        // ~~~~~[ Interface : "info" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+#ifdef DEBUG_TEST
+        {
+          dest = _name+"_commit_unit";
+#ifdef POSITION
+          _component->interface_map (src ,"info",
+                                     dest,"info");
+#endif
+          COMPONENT_MAP(_component,src , "in_INFO_ROB_EMPTY",
+                                   dest,"out_INFO_ROB_EMPTY");
+        }
+#endif
+      }

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_deallocation.cpp

r122	r123
35	35	DELETE2_SIGNAL( in_RENAME_OPERATION ,_param->_nb_front_end,_param->_nb_inst_decod[it1],_param->_size_operation );
36	36	DELETE2_SIGNAL( in_RENAME_NO_EXECUTE ,_param->_nb_front_end,_param->_nb_inst_decod[it1],1 );
	37	// DELETE2_SIGNAL( in_RENAME_HAVE_EVENT ,_param->_nb_front_end,_param->_nb_inst_decod[it1],1 );
	38	DELETE2_SIGNAL( in_RENAME_LAST_EVENT ,_param->_nb_front_end,_param->_nb_inst_decod[it1],1 );
37	39	DELETE2_SIGNAL( in_RENAME_IS_DELAY_SLOT ,_param->_nb_front_end,_param->_nb_inst_decod[it1],1 );
38	40	#ifdef DEBUG

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Core.cpp

-                      r88
+                      r123
     usage_environment(_usage);
 #if DEBUG_Core == true
     log_printf(INFO,Core,FUNCTION,_("<%s> Parameters"),_name.c_str());
+// #if DEBUG_Core == true
+//     log_printf(INFO,Core,FUNCTION,_("<%s> Parameters"),_name.c_str());
     std::cout << *param << std::endl;
 #endif
+//     std::cout << *param << std::endl;
+// #endif
     log_printf(INFO,Core,FUNCTION,_("<%s> Allocation"),_name.c_str());

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Core_allocation.cpp

-                      r122
+                      r123
               COMPONENT_MAP(_component,src , "in_RENAME_"+toString(j)+"_"+toString(k)+"_NO_EXECUTE"   ,
                                        dest,"out_DECOD_"                 +toString(k)+"_NO_EXECUTE"   );
+//               COMPONENT_MAP(_component,src , "in_RENAME_"+toString(j)+"_"+toString(k)+"_HAVE_EVENT"   ,
+//                                        dest,"out_DECOD_"                 +toString(k)+"_HAVE_EVENT"   );
+              COMPONENT_MAP(_component,src , "in_RENAME_"+toString(j)+"_"+toString(k)+"_LAST_EVENT"   ,
+                                       dest,"out_DECOD_"                 +toString(k)+"_LAST_EVENT"   );
               COMPONENT_MAP(_component,src , "in_RENAME_"+toString(j)+"_"+toString(k)+"_IS_DELAY_SLOT",
                                        dest,"out_DECOD_"                 +toString(k)+"_IS_DELAY_SLOT");

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Core_deallocation.cpp

-                      r122
+                      r123
     // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+    delete    _component_glue;
+    delete    _component_dcache_access;
+    delete    _component_icache_access;
+    for (uint32_t i=0; i<_param->_nb_execute_loop; ++i)
+    delete    _component_execute_loop [i];
+    delete [] _component_execute_loop;
+    for (uint32_t i=0; i<_param->_nb_ooo_engine; ++i)
+    delete    _component_ooo_engine [i];
+    delete [] _component_ooo_engine;
+    for (uint32_t i=0; i<_param->_nb_front_end; ++i)
+    delete    _component_front_end [i];
+    delete [] _component_front_end;
+    delete _component;
+    delete _component;
+//     delete    _component_glue;
+//     delete    _component_dcache_access;
+//     delete    _component_icache_access;
+//     for (uint32_t i=0; i<_param->_nb_execute_loop; ++i)
+//     delete    _component_execute_loop [i];
+//     delete [] _component_execute_loop;
+//     for (uint32_t i=0; i<_param->_nb_ooo_engine; ++i)
+//     delete    _component_ooo_engine [i];
+//     delete [] _component_ooo_engine;
+//     for (uint32_t i=0; i<_param->_nb_front_end; ++i)
+//     delete    _component_front_end [i];
+//     delete [] _component_front_end;
     log_end(Core,FUNCTION);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Parameters.cpp

-                      r122
+                      r123
     log_begin(Core,FUNCTION);
     for (uint32_t i=0; i<_nb_front_end; ++i)
     delete    _param_front_end [i];
     delete [] _param_front_end;
     for (uint32_t i=0; i<_nb_ooo_engine; ++i)
     delete    _param_ooo_engine [i];
     delete [] _param_ooo_engine;
     for (uint32_t i=0; i<_nb_execute_loop; ++i)
     delete    _param_execute_loop [i];
     delete [] _param_execute_loop;
     delete    _param_icache_access;
     delete    _param_dcache_access;
     delete    _param_glue;
+//     for (uint32_t i=0; i<_nb_front_end; ++i)
+//     delete    _param_front_end [i];
+//     delete [] _param_front_end;
+//     for (uint32_t i=0; i<_nb_ooo_engine; ++i)
+//     delete    _param_ooo_engine [i];
+//     delete [] _param_ooo_engine;
+//     for (uint32_t i=0; i<_nb_execute_loop; ++i)
+//     delete    _param_execute_loop [i];
+//     delete [] _param_execute_loop;
+//     delete    _param_icache_access;
+//     delete    _param_dcache_access;
+//     delete    _param_glue;
     DELETE3(_dcache_access_translate_load_store_unit_to_thread      ,_nb_execute_loop,_execute_loop_nb_load_store_unit[it1],_dcache_access_nb_context[it1]);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Comparator/src/Comparator_genMealy.cpp

-                      r113
+                      r123
     log_begin(Comparator,FUNCTION);
+    if (PORT_READ(in_NRESET))
+      {
     Tcontrol_t test;
     Tdata_t data_0 = PORT_READ(in_COMPARE_DATA_0);
 …
     PORT_WRITE(out_COMPARE_TEST,test);
+      }
     log_end(Comparator,FUNCTION);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Counter_genMealy.cpp

r113	r123
18	18	log_printf(FUNC,Counter,"genMealy","Begin");
19	19
	20	if (PORT_READ(in_NRESET))
20	21	for (uint32_t i=0; i<_param->_nb_port; i++)
21	22	{

trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/src/Queue_genMoore.cpp

-                      r101
+                      r123
     log_printf(FUNC,Queue,FUNCTION,"Begin");
+    if (PORT_READ(in_NRESET))
+      {
     //---------------------------------------------
     // Output
 …
     internal_RETIRE_VAL = not _queue_control->empty();
-    PORT_WRITE(out_INSERT_ACK , internal_INSERT_ACK);
-    PORT_WRITE(out_RETIRE_VAL , internal_RETIRE_VAL);
     PORT_WRITE(out_RETIRE_DATA,_queue_data[(*_queue_control)[0]]);
 …
     if (_param->_have_port_ptr_read )
     PORT_WRITE(out_PTR_READ , _queue_control->ptr_pop ());
+      }
+    else
+      {
+        // Reset
+        internal_INSERT_ACK = 0;
+        internal_RETIRE_VAL = 0;
+        for (uint32_t i=0; i<_param->_nb_port_slot; ++i)
+          PORT_WRITE(out_SLOT_VAL  [i], 0);
+      }
+    // Write output
+    PORT_WRITE(out_INSERT_ACK , internal_INSERT_ACK);
+    PORT_WRITE(out_RETIRE_VAL , internal_RETIRE_VAL);
     log_printf(FUNC,Queue,FUNCTION,"End");

trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic.cpp

-                      r98
+                      r123
     log_printf(FUNC,RegisterFile_Monolithic,"RegisterFile_Monolithic","Begin");
 #if DEBUG_RegisterFile_Monolithic == true
     log_printf(INFO,RegisterFile_Monolithic,FUNCTION,_("<%s> Parameters"),_name.c_str());
+// #if DEBUG_RegisterFile_Monolithic == true
+//     log_printf(INFO,RegisterFile_Monolithic,FUNCTION,_("<%s> Parameters"),_name.c_str());
     std::cout << *param << std::endl;
 #endif
+//     std::cout << *param << std::endl;
+// #endif
     log_printf(INFO,RegisterFile_Monolithic,"RegisterFile_Monolithic","Allocation");

trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_genMealy_read.cpp

-                      r106
+                      r123
     log_function(RegisterFile_Monolithic,FUNCTION,_name.c_str());
+    if (PORT_READ(in_NRESET))
+      {
     for (uint32_t i=0; i<_param->_nb_port_read; i++)
+      {
 …
         PORT_WRITE(out_READ_WRITE_RDATA[i],data);
+      }
+      }
     log_end(RegisterFile_Monolithic,FUNCTION);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked.cpp

-                      r88
+                      r123
     log_printf(FUNC,RegisterFile_Multi_Banked,FUNCTION,"Begin");
 #if DEBUG_RegisterFile_Multi_Banked == true
     log_printf(INFO,RegisterFile_Multi_Banked,FUNCTION,_("<%s> Parameters"),_name.c_str());
+// #if DEBUG_RegisterFile_Multi_Banked == true
+//     log_printf(INFO,RegisterFile_Multi_Banked,FUNCTION,_("<%s> Parameters"),_name.c_str());
     std::cout << *param << std::endl;
 #endif
+//     std::cout << *param << std::endl;
+// #endif
     log_printf(INFO,RegisterFile_Multi_Banked,FUNCTION,"Allocation");

trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_full_crossbar_genMealy_read.cpp

-                      r106
+                      r123
     log_begin(RegisterFile_Multi_Banked,FUNCTION);
     log_function(RegisterFile_Multi_Banked,FUNCTION,_name.c_str());
+    if (PORT_READ(in_NRESET))
+      {
     bool read_port_use [_param->_nb_bank][_param->_nb_port_read_by_bank];
 …
         PORT_WRITE(out_READ_ACK [i], ack);
+      }
+      }
+    else
+      for (uint32_t i=0; i<_param->_nb_port_read; i++)
+        PORT_WRITE(out_READ_ACK [i], false);
     log_end(RegisterFile_Multi_Banked,FUNCTION);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_full_crossbar_genMealy_write.cpp

-                      r106
+                      r123
     log_function(RegisterFile_Multi_Banked,FUNCTION,_name.c_str());
+    if (PORT_READ(in_NRESET))
+      {
     bool write_port_use [_param->_nb_bank][_param->_nb_port_write_by_bank];
 …
         PORT_WRITE(out_WRITE_ACK [i], ack);
+      }
+      }
+    else
+      {
+        for (uint32_t i=0; i<_param->_nb_port_write; i++)
+          {
+            internal_WRITE_VAL [i] = 0;
+            PORT_WRITE(out_WRITE_ACK [i], 0);
+          }
+      }
     log_end(RegisterFile_Multi_Banked,FUNCTION);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_partial_crossbar_genMealy_read.cpp

-                      r106
+                      r123
     log_function(RegisterFile_Multi_Banked,FUNCTION,_name.c_str());
+    if (PORT_READ(in_NRESET))
+      {
     bool read_port_use [_param->_nb_bank][_param->_nb_port_read_by_bank];
 …
         PORT_WRITE(out_READ_ACK [i], ack);
+      }
+      }
+    else
+      {
+        for (uint32_t i=0; i<_param->_nb_port_read; i++)
+          PORT_WRITE(out_READ_ACK [i],0);
+      }
     log_end(RegisterFile_Multi_Banked,FUNCTION);
   };

trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_partial_crossbar_genMealy_write.cpp

-                      r106
+                      r123
     log_function(RegisterFile_Multi_Banked,FUNCTION,_name.c_str());
+    if (PORT_READ(in_NRESET))
+      {
     bool write_port_use [_param->_nb_bank][_param->_nb_port_write_by_bank];
     for (uint32_t i=0; i<_param->_nb_bank; i++)
 …
         PORT_WRITE(out_WRITE_ACK [i], ack);
+      }
+      }
+    else
+      {
+        for (uint32_t i=0; i<_param->_nb_port_write; i++)
+          {
+            internal_WRITE_VAL [i] = 0;
+            PORT_WRITE(out_WRITE_ACK [i], 0);
+          }
+      }
     log_end(RegisterFile_Multi_Banked,FUNCTION);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Shifter.cpp

-                      r88
+                      r123
+  {
 #if DEBUG_Shifter == true
     log_printf(INFO,Shifter,FUNCTION,_("<%s> Parameters"),_name.c_str());
+// #if DEBUG_Shifter == true
+//     log_printf(INFO,Shifter,FUNCTION,_("<%s> Parameters"),_name.c_str());
     std::cout << *param << std::endl;
 #endif
+//     std::cout << *param << std::endl;
+// #endif
     allocation ();

trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Shifter_genMealy_shift.cpp

r82	r123
18	18	void Shifter::genMealy_shift (void)
19	19	{
	20	if (PORT_READ(in_NRESET))
20	21	for (uint32_t i=0; i<_param->_nb_port; i++)
21	22	{

trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Sort/src/Sort.cpp

-                      r88
+                      r123
     log_printf(FUNC,Sort,FUNCTION,"Begin");
 #if DEBUG_Sort == true
     log_printf(INFO,Sort,FUNCTION,_("<%s> Parameters"),_name.c_str());
+// #if DEBUG_Sort == true
+//     log_printf(INFO,Sort,FUNCTION,_("<%s> Parameters"),_name.c_str());
     std::cout << *param << std::endl;
 #endif
+//     std::cout << *param << std::endl;
+// #endif
     log_printf(INFO,Sort,FUNCTION,"Allocation");

trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Sort/src/Sort_genMealy.cpp

-                      r81
+                      r123
     log_printf(FUNC,Sort,FUNCTION,"Begin");
+    if (PORT_READ(in_NRESET))
+      {
     sort_t array [_param->_nb_input];
 …
         PORT_WRITE (out_OUTPUT_DATA  [i],array[i].data );
+      }
+      }
     log_printf(FUNC,Sort,FUNCTION,"End");

trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/src/Victim_Pseudo_LRU.cpp

-                      r88
+                      r123
     log_printf(FUNC,Victim_Pseudo_LRU,"Victim_Pseudo_LRU","Begin");
 #if DEBUG_Victim_Pseudo_LRU == true
     log_printf(INFO,Victim_Pseudo_LRU,FUNCTION,_("<%s> Parameters"),_name.c_str());
+// #if DEBUG_Victim_Pseudo_LRU == true
+//     log_printf(INFO,Victim_Pseudo_LRU,FUNCTION,_("<%s> Parameters"),_name.c_str());
     std::cout << *param << std::endl;
 #endif
+//     std::cout << *param << std::endl;
+// #endif
     log_printf(TRACE,Victim_Pseudo_LRU,"Victim_Pseudo_LRU","Allocation");

trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/src/Victim_Pseudo_LRU_genMealy.cpp

r88	r123
17	17	void Victim_Pseudo_LRU::genMealy (void)
18	18	{
	19	if (PORT_READ(in_NRESET))
19	20	for (uint32_t i=0; i<_param->_nb_access; i++)
20	21	{

trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/src/Victim_Pseudo_LRU_transition.cpp

r81	r123
22	22	{
23	23	Taddress_t address = (_param->_size_table>1)?PORT_READ(in_ACCESS_ADDRESS[i]):0;
24		Tentity_t entity;
	24	Tentity_t entity = 0;
25	25
26	26	if (PORT_READ(in_ACCESS_HIT [i]))

trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Types.h

-                      r118
+                      r123
       PREDICTOR_CUSTOM            // Not predefined scheme
     } Tpredictor_t;
+  typedef enum
+    {
+      MANAGE_EVENT_WAIT_ALL,
+      MANAGE_EVENT_WAIT_DECODE,
+      MANAGE_EVENT_NO_WAIT
+    } Tmanage_event_t;
   //--------------------------------------------------[ instruction ]-----

trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Version.h

-                      r122
+                      r123
 #define MORPHEO_MAJOR_VERSION "0"
 #define MORPHEO_MINOR_VERSION "2"
 #define MORPHEO_REVISION      "122"
+#define MORPHEO_REVISION      "123"
 #define MORPHEO_CODENAME      "Castor"
 #define MORPHEO_DATE_DAY      "03"
+#define MORPHEO_DATE_DAY      "08"
 #define MORPHEO_DATE_MONTH    "06"
 #define MORPHEO_DATE_YEAR     "2009"

trunk/IPs/systemC/processor/Morpheo/Files/Instance_x1_w1_1.cfg

r118	r123
80	80	<parameter name="nb_inst_branch_decod" value="1" />
81	81	<parameter name="nb_inst_branch_update" value="1" />
82		<parameter name="btb_size_queue" value="32"/>
	82	<parameter name="btb_size_queue" value="256"/>
83	83	<parameter name="btb_associativity" value="1" />
84	84	<parameter name="btb_size_counter" value="2" />

trunk/IPs/systemC/processor/Morpheo/Files/Instance_x1_w1_2.cfg

r120	r123
80	80	<parameter name="nb_inst_branch_decod" value="1" />
81	81	<parameter name="nb_inst_branch_update" value="1" />
82		<parameter name="btb_size_queue" value="32"/>
	82	<parameter name="btb_size_queue" value="256"/>
83	83	<parameter name="btb_associativity" value="1" />
84	84	<parameter name="btb_size_counter" value="2" />

trunk/IPs/systemC/processor/Morpheo/Files/Instance_x1_w1_3.cfg

-                      r120
+                      r123
     <parameter name="nb_inst_branch_decod"                  value="1" />
     <parameter name="nb_inst_branch_update"                 value="1" />
     <parameter name="btb_size_queue"                        value="32"/>
+    <parameter name="btb_size_queue"                        value="256"/>
     <parameter name="btb_associativity"                     value="1" />
     <parameter name="btb_size_counter"                      value="2" />
 …
   <link name="link_write_bloc_and_load_store_unit"     src="0.0"   dest="1"   />
   <link name="link_write_bloc_and_load_store_unit"     src="1.0"   dest="1"   />
+  <link name="link_write_bloc_and_load_store_unit"     src="1.0"   dest="0"   />
   <link name="link_write_bloc_and_functionnal_unit"    src="0.0"   dest="1"   />
   <link name="link_write_bloc_and_functionnal_unit"    src="1.0"   dest="1"   />

trunk/IPs/systemC/processor/Morpheo/Files/Instance_x1_w1_4.cfg

-                      r120
+                      r123
     <parameter name="nb_inst_branch_decod"                  value="1" />
     <parameter name="nb_inst_branch_update"                 value="1" />
     <parameter name="btb_size_queue"                        value="32"/>
+    <parameter name="btb_size_queue"                        value="256"/>
     <parameter name="btb_associativity"                     value="1" />
     <parameter name="btb_size_counter"                      value="2" />
 …
   <link name="link_write_bloc_and_load_store_unit"     src="0.0"   dest="1"   />
   <link name="link_write_bloc_and_load_store_unit"     src="1.0"   dest="1"   />
   <link name="link_write_bloc_and_load_store_unit"     src="2.0"   dest="1"   />
   <link name="link_write_bloc_and_functionnal_unit"    src="0.0"   dest="1"   />
   <link name="link_write_bloc_and_functionnal_unit"    src="0.1"   dest="1"   />
+  <link name="link_write_bloc_and_load_store_unit"     src="1.0"   dest="0"   />
+  <link name="link_write_bloc_and_load_store_unit"     src="2.0"   dest="0"   />
+  <link name="link_write_bloc_and_functionnal_unit"    src="0.0"   dest="0"   />
+  <link name="link_write_bloc_and_functionnal_unit"    src="0.1"   dest="0"   />
   <link name="link_write_bloc_and_functionnal_unit"    src="1.0"   dest="1"   />
   <link name="link_write_bloc_and_functionnal_unit"    src="1.1"   dest="1"   />

trunk/IPs/systemC/processor/Morpheo/Files/Instance_x1_w2_1.cfg

-                      r120
+                      r123
     <parameter name="nb_inst_branch_decod"                  value="1" />
     <parameter name="nb_inst_branch_update"                 value="1" />
     <parameter name="btb_size_queue"                        value="32"/>
+    <parameter name="btb_size_queue"                        value="512"/>
     <parameter name="btb_associativity"                     value="1" />
     <parameter name="btb_size_counter"                      value="2" />
 …
   <link name="link_write_bloc_and_load_store_unit"     src="0.0"   dest="1"   />
   <link name="link_write_bloc_and_load_store_unit"     src="1.0"   dest="1"   />
   <link name="link_write_bloc_and_functionnal_unit"    src="0.0"   dest="1"   />
+  <link name="link_write_bloc_and_load_store_unit"     src="1.0"   dest="0"   />
+  <link name="link_write_bloc_and_functionnal_unit"    src="0.0"   dest="0"   />
   <link name="link_write_bloc_and_functionnal_unit"    src="1.0"   dest="1"   />

trunk/IPs/systemC/processor/Morpheo/Files/Instance_x1_w2_2.cfg

-                      r120
+                      r123
     <parameter name="nb_inst_branch_decod"                  value="1" />
     <parameter name="nb_inst_branch_update"                 value="1" />
     <parameter name="btb_size_queue"                        value="64"/>
+    <parameter name="btb_size_queue"                        value="512"/>
     <parameter name="btb_associativity"                     value="2" />
     <parameter name="btb_size_counter"                      value="2" />
 …
   <link name="link_write_bloc_and_load_store_unit"     src="0.0"   dest="1"   />
   <link name="link_write_bloc_and_load_store_unit"     src="1.0"   dest="1"   />
   <link name="link_write_bloc_and_load_store_unit"     src="2.0"   dest="1"   />
   <link name="link_write_bloc_and_functionnal_unit"    src="0.0"   dest="1"   />
   <link name="link_write_bloc_and_functionnal_unit"    src="0.1"   dest="1"   />
+  <link name="link_write_bloc_and_load_store_unit"     src="1.0"   dest="0"   />
+  <link name="link_write_bloc_and_load_store_unit"     src="2.0"   dest="0"   />
+  <link name="link_write_bloc_and_functionnal_unit"    src="0.0"   dest="0"   />
+  <link name="link_write_bloc_and_functionnal_unit"    src="0.1"   dest="0"   />
   <link name="link_write_bloc_and_functionnal_unit"    src="1.0"   dest="1"   />
   <link name="link_write_bloc_and_functionnal_unit"    src="1.1"   dest="1"   />

trunk/IPs/systemC/processor/Morpheo/Files/Instance_x1_w2_3.cfg

-                      r120
+                      r123
     <parameter name="nb_inst_branch_decod"                  value="1" />
     <parameter name="nb_inst_branch_update"                 value="1" />
     <parameter name="btb_size_queue"                        value="64"/>
+    <parameter name="btb_size_queue"                        value="512"/>
     <parameter name="btb_associativity"                     value="2" />
     <parameter name="btb_size_counter"                      value="2" />
     <parameter name="btb_victim_scheme"                     value="3" />
     <parameter name="dir_predictor_scheme"                  value="2" />
+    <predictor id="0">
+      <parameter name="dir_have_bht"                        value="0"  />
+      <parameter name="dir_bht_size_shifter"                value="1"  />
+      <parameter name="dir_bht_nb_shifter"                  value="64" />
+      <parameter name="dir_have_pht"                        value="1"  />
+      <parameter name="dir_pht_size_counter"                value="2"  />
+      <parameter name="dir_pht_nb_counter"                  value="16" />
+      <parameter name="dir_pht_size_address_share"          value="0"  />
+    </predictor>
+    <predictor id="1">
+      <parameter name="dir_have_bht"                        value="1" />
+      <parameter name="dir_bht_size_shifter"                value="4" />
+      <parameter name="dir_bht_nb_shifter"                  value="1" />
+      <parameter name="dir_have_pht"                        value="1" />
+      <parameter name="dir_pht_size_counter"                value="2" />
+      <parameter name="dir_pht_nb_counter"                  value="64" />
+      <parameter name="dir_pht_size_address_share"          value="0" />
+    </predictor>
+    <predictor id="2">
+      <parameter name="dir_have_bht"                        value="0" />
+      <parameter name="dir_have_pht"                        value="1" />
+      <parameter name="dir_pht_size_counter"                value="2" />
+      <parameter name="dir_pht_nb_counter"                  value="128" />
+      <parameter name="dir_pht_size_address_share"          value="0" />
+    </predictor>
   </front_end>
 …
   <link name="link_write_bloc_and_load_store_unit"     src="0.0"   dest="1"   />
   <link name="link_write_bloc_and_load_store_unit"     src="1.0"   dest="1"   />
   <link name="link_write_bloc_and_load_store_unit"     src="2.0"   dest="1"   />
   <link name="link_write_bloc_and_functionnal_unit"    src="0.0"   dest="1"   />
   <link name="link_write_bloc_and_functionnal_unit"    src="0.1"   dest="1"   />
+  <link name="link_write_bloc_and_load_store_unit"     src="1.0"   dest="0"   />
+  <link name="link_write_bloc_and_load_store_unit"     src="2.0"   dest="0"   />
+  <link name="link_write_bloc_and_functionnal_unit"    src="0.0"   dest="0"   />
+  <link name="link_write_bloc_and_functionnal_unit"    src="0.1"   dest="0"   />
   <link name="link_write_bloc_and_functionnal_unit"    src="1.0"   dest="1"   />
   <link name="link_write_bloc_and_functionnal_unit"    src="1.1"   dest="1"   />

trunk/IPs/systemC/processor/Morpheo/Files/Instance_x1_w2_4.cfg

-                      r120
+                      r123
     <parameter name="nb_inst_branch_decod"                  value="1" />
     <parameter name="nb_inst_branch_update"                 value="1" />
     <parameter name="btb_size_queue"                        value="64"/>
+    <parameter name="btb_size_queue"                        value="512"/>
     <parameter name="btb_associativity"                     value="2" />
     <parameter name="btb_size_counter"                      value="2" />
 …
     <parameter name="nb_execute_loop_select"                value="1" />
     <parameter name="size_re_order_buffer"                  value="64"/>
     <parameter name="nb_re_order_buffer_bank"               value="32"/>
+    <parameter name="nb_re_order_buffer_bank"               value="16"/>
     <parameter name="commit_priority"                       value="1" />
     <parameter name="commit_load_balancing"                 value="1" />

trunk/IPs/systemC/processor/Morpheo/Files/Instance_x1_w4_1.cfg

r122	r123
85	85	<parameter name="nb_inst_branch_decod" value="1" />
86	86	<parameter name="nb_inst_branch_update" value="1" />
87		<parameter name="btb_size_queue" value="~~256~~" />
	87	<parameter name="btb_size_queue" value="1024" />
88	88	<parameter name="btb_associativity" value="8" />
89	89	<parameter name="btb_size_counter" value="2" />

trunk/IPs/systemC/processor/Morpheo/Files/Instance_x1_w4_2.cfg

r122	r123
85	85	<parameter name="nb_inst_branch_decod" value="1" />
86	86	<parameter name="nb_inst_branch_update" value="1" />
87		<parameter name="btb_size_queue" value="~~256~~" />
	87	<parameter name="btb_size_queue" value="1024" />
88	88	<parameter name="btb_associativity" value="8" />
89	89	<parameter name="btb_size_counter" value="2" />

trunk/IPs/systemC/processor/Morpheo/Files/Instance_x1_w4_3.cfg

r120	r123
85	85	<parameter name="nb_inst_branch_decod" value="1" />
86	86	<parameter name="nb_inst_branch_update" value="1" />
87		<parameter name="btb_size_queue" value="~~512~~" />
	87	<parameter name="btb_size_queue" value="1024" />
88	88	<parameter name="btb_associativity" value="8" />
89	89	<parameter name="btb_size_counter" value="2" />

trunk/IPs/systemC/processor/Morpheo/Files/Instance_x1_w8_1.cfg

r120	r123
91	91	<parameter name="nb_inst_branch_decod" value="1" />
92	92	<parameter name="nb_inst_branch_update" value="1" />
93		<parameter name="btb_size_queue" value="~~256~~" />
	93	<parameter name="btb_size_queue" value="1024" />
94	94	<parameter name="btb_associativity" value="8" />
95	95	<parameter name="btb_size_counter" value="2" />

trunk/IPs/systemC/processor/Morpheo/Files/Instance_x1_w8_2.cfg

r120	r123
91	91	<parameter name="nb_inst_branch_decod" value="1" />
92	92	<parameter name="nb_inst_branch_update" value="1" />
93		<parameter name="btb_size_queue" value="~~256~~" />
	93	<parameter name="btb_size_queue" value="1024" />
94	94	<parameter name="btb_associativity" value="8" />
95	95	<parameter name="btb_size_counter" value="2" />

trunk/IPs/systemC/processor/Morpheo/Files/Instance_x2_w1_3.cfg

-                      r118
+                      r123
   <link name="link_write_bloc_and_load_store_unit"     src="0.0"   dest="1"   />
   <link name="link_write_bloc_and_load_store_unit"     src="1.0"   dest="1"   />
   <link name="link_write_bloc_and_functionnal_unit"    src="0.0"   dest="1"   />
+  <link name="link_write_bloc_and_load_store_unit"     src="1.0"   dest="0"   />
+  <link name="link_write_bloc_and_functionnal_unit"    src="0.0"   dest="0"   />
   <link name="link_write_bloc_and_functionnal_unit"    src="1.0"   dest="1"   />

trunk/IPs/systemC/processor/Morpheo/Files/Instance_x2_w1_4.cfg

-                      r118
+                      r123
   <link name="link_write_bloc_and_load_store_unit"     src="0.0"   dest="1"   />
   <link name="link_write_bloc_and_load_store_unit"     src="1.0"   dest="1"   />
   <link name="link_write_bloc_and_load_store_unit"     src="2.0"   dest="1"   />
   <link name="link_write_bloc_and_functionnal_unit"    src="0.0"   dest="1"   />
   <link name="link_write_bloc_and_functionnal_unit"    src="0.1"   dest="1"   />
+  <link name="link_write_bloc_and_load_store_unit"     src="1.0"   dest="0"   />
+  <link name="link_write_bloc_and_load_store_unit"     src="2.0"   dest="0"   />
+  <link name="link_write_bloc_and_functionnal_unit"    src="0.0"   dest="0"   />
+  <link name="link_write_bloc_and_functionnal_unit"    src="0.1"   dest="0"   />
   <link name="link_write_bloc_and_functionnal_unit"    src="1.0"   dest="1"   />
   <link name="link_write_bloc_and_functionnal_unit"    src="1.1"   dest="1"   />

trunk/IPs/systemC/processor/Morpheo/Files/Instance_x2_w1_5.cfg

-                      r120
+                      r123
   <link name="link_write_bloc_and_load_store_unit"     src="0.0"   dest="1"   />
   <link name="link_write_bloc_and_load_store_unit"     src="1.0"   dest="1"   />
   <link name="link_write_bloc_and_load_store_unit"     src="2.0"   dest="1"   />
   <link name="link_write_bloc_and_functionnal_unit"    src="0.0"   dest="1"   />
   <link name="link_write_bloc_and_functionnal_unit"    src="0.1"   dest="1"   />
+  <link name="link_write_bloc_and_load_store_unit"     src="1.0"   dest="0"   />
+  <link name="link_write_bloc_and_load_store_unit"     src="2.0"   dest="0"   />
+  <link name="link_write_bloc_and_functionnal_unit"    src="0.0"   dest="0"   />
+  <link name="link_write_bloc_and_functionnal_unit"    src="0.1"   dest="0"   />
   <link name="link_write_bloc_and_functionnal_unit"    src="1.0"   dest="1"   />
   <link name="link_write_bloc_and_functionnal_unit"    src="1.1"   dest="1"   />

trunk/IPs/systemC/processor/Morpheo/Files/Instance_x2_w1_6.cfg

-                      r120
+                      r123
   <link name="link_write_bloc_and_load_store_unit"     src="0.0"   dest="1"   />
   <link name="link_write_bloc_and_load_store_unit"     src="1.0"   dest="1"   />
   <link name="link_write_bloc_and_load_store_unit"     src="2.0"   dest="1"   />
+  <link name="link_write_bloc_and_load_store_unit"     src="1.0"   dest="0"   />
+  <link name="link_write_bloc_and_load_store_unit"     src="2.0"   dest="0"   />
   <link name="link_write_bloc_and_load_store_unit"     src="0.1"   dest="1"   />
   <link name="link_write_bloc_and_load_store_unit"     src="1.1"   dest="1"   />
   <link name="link_write_bloc_and_load_store_unit"     src="2.1"   dest="1"   />
   <link name="link_write_bloc_and_functionnal_unit"    src="0.0"   dest="1"   />
+  <link name="link_write_bloc_and_load_store_unit"     src="1.1"   dest="0"   />
+  <link name="link_write_bloc_and_load_store_unit"     src="2.1"   dest="0"   />
+  <link name="link_write_bloc_and_functionnal_unit"    src="0.0"   dest="0"   />
   <link name="link_write_bloc_and_functionnal_unit"    src="1.0"   dest="1"   />
   <link name="link_write_bloc_and_functionnal_unit"    src="2.0"   dest="1"   />
   <link name="link_write_bloc_and_functionnal_unit"    src="0.1"   dest="1"   />
+  <link name="link_write_bloc_and_functionnal_unit"    src="0.1"   dest="0"   />
   <link name="link_write_bloc_and_functionnal_unit"    src="1.1"   dest="1"   />
   <link name="link_write_bloc_and_functionnal_unit"    src="2.1"   dest="1"   />

trunk/IPs/systemC/processor/Morpheo/Files/Morpheo.gen

-                      r120
+                      r123
   <parameter name="nb_inst_fetch"                         min="1"   max="16"   step="* 2" default="1"   level="..." description="..." />
   <parameter name="implement_group"                                                       default="0"   level="..." description="..." />
   <parameter name="ras_size_queue"                        min="2"   max="16"   step="* 2" default="2"   level="..." description="..." />
+  <parameter name="ras_size_queue"                        min="2"   max="32"   step="* 2" default="2"   level="..." description="..." />
   <parameter name="upt_size_queue"                        min="1"   max="32"   step="* 2" default="2"   level="..." description="..." />
   <parameter name="ufpt_size_queue"                       min="1"   max="16"   step="* 2" default="2"   level="..." description="..." />
 …
   <parameter name="nb_inst_branch_decod"                  min="1"   max="16"   step="* 2" default="1"   level="..." description="..." />
   <parameter name="nb_inst_branch_update"                 min="1"   max="16"   step="* 2" default="1"   level="..." description="..." />
   <parameter name="btb_size_queue"                        min="1"   max="512"  step="* 2" default="2"   level="..." description="..." />
+  <parameter name="btb_size_queue"                        min="1"   max="1024" step="* 2" default="2"   level="..." description="..." />
   <parameter name="btb_associativity"                     min="1"   max="16"   step="* 2" default="1"   level="..." description="..." />
   <parameter name="btb_size_counter"                      min="2"   max="16"   step="* 2" default="2"   level="..." description="..." />

trunk/IPs/systemC/processor/Morpheo/Files/Morpheo.sim

-                      r122
+                      r123
   <parameter  name="use_statistics"                         value="1"       />
   <parameter  name="use_information"                        value="0"       />
   <parameter  name="use_header"                             value="1"       />
+  <parameter  name="use_header"                             value="0"       />
   <parameter  name="directory_statistics"                   value="."       />
 …
   <parameter  name="statistics_period"                      value="0"       />
   <parameter  name="simulation_nb_cycle"                    value="1000000" />
+  <parameter  name="simulation_nb_cycle"                    value="10000000" />
   <parameter  name="simulation_nb_instruction"              value="0"       />
   <parameter  name="debug_level"                            value="0"       />
   <parameter  name="debug_cycle_start"                      value="4250"    />
   <parameter  name="debug_cycle_stop"                       value="4400"    />
+  <parameter  name="debug_cycle_start"                      value="0"       />
+  <parameter  name="debug_cycle_stop"                       value="2000000" />
   <parameter  name="debug_log_file_generate"                value="0"       />
   <parameter  name="debug_log_file_with_pid"                value="0"       />
   <parameter  name="debug_idle_cycle"                       value="1000"    />
   <parameter  name="debug_idle_time"                        value="10"      />
+  <parameter  name="debug_idle_time"                        value="3"       />
   <component  name="Comparator"                             model="systemc" debug="0" />

trunk/IPs/systemC/processor/Morpheo/Files/debug.cfg

-                      r120
+                      r123
 <?xml version="1.0" encoding="ISO-8859-1" ?>
 <core name="debug">
+<core name="Instance_x1_w4_1">
   <thread id="0">
 …
     <parameter name="nb_inst_fetch"                         value="8" />
     <parameter name="ras_size_queue"                        value="8" />
     <parameter name="upt_size_queue"                        value="32" />
+    <parameter name="upt_size_queue"                        value="16" />
     <parameter name="ufpt_size_queue"                       value="4" />
 …
   </rename_bloc>
   <read_bloc id="0,1,2,3,4,5">
+  <read_bloc id="0,1,2,3">
     <parameter name="size_read_queue"                       value="4" />
     <parameter name="size_reservation_station"              value="4" />
 …
   </read_bloc>
   <write_bloc id="0,1,2,3,4,5">
+  <write_bloc id="0,1,2,3">
     <parameter name="size_write_queue"                      value="4" />
     <parameter name="size_execute_queue"                    value="4" />
 …
   <load_store_unit id="0">
     <parameter name="size_store_queue"                      value="16" />
     <parameter name="size_load_queue"                       value="32" />
+    <parameter name="size_load_queue"                       value="16" />
     <parameter name="size_speculative_access_queue"         value="4" />
     <parameter name="nb_port_check"                         value="4" />
 …
   </load_store_unit>
+  <functionnal_unit id="0">
+    <parameter name="nb_inst_functionnal_unit" value="1" />
+    <timing type="8"  latence="1" delay="1" />
+    <timing type="10" latence="1" delay="1" />
+  </functionnal_unit>
+  <functionnal_unit id="1,2,3,4" >
+  <functionnal_unit id="0,1" >
     <parameter name="nb_inst_functionnal_unit" value="1" />
 …
   </functionnal_unit>
+  <functionnal_unit id="2">
+    <parameter name="nb_inst_functionnal_unit" value="1" />
+    <timing type="8"  latence="1" delay="1" />
+    <timing type="10" latence="1" delay="1" />
+  </functionnal_unit>
   <front_end id="0">
     <parameter name="nb_context"                            value="1" />
 …
     <parameter name="nb_inst_branch_decod"                  value="1" />
     <parameter name="nb_inst_branch_update"                 value="1" />
     <parameter name="btb_size_queue"                        value="256" />
+    <parameter name="btb_size_queue"                        value="1024" />
     <parameter name="btb_associativity"                     value="8" />
     <parameter name="btb_size_counter"                      value="2" />
     <parameter name="btb_victim_scheme"                     value="3" />
     <parameter name="dir_predictor_scheme"                  value="4" />
+    <parameter name="dir_predictor_scheme"                  value="2" />
     <predictor id="0">
       <parameter name="dir_have_bht"                        value="1"  />
       <parameter name="dir_bht_size_shifter"                value="4"  />
+      <parameter name="dir_have_bht"                        value="0"  />
+      <parameter name="dir_bht_size_shifter"                value="1"  />
       <parameter name="dir_bht_nb_shifter"                  value="64" />
       <parameter name="dir_have_pht"                        value="1"  />
       <parameter name="dir_pht_size_counter"                value="2"  />
       <parameter name="dir_pht_nb_counter"                  value="64" />
+      <parameter name="dir_pht_nb_counter"                  value="16" />
       <parameter name="dir_pht_size_address_share"          value="0"  />
     </predictor>
 …
       <parameter name="dir_have_pht"                        value="1" />
       <parameter name="dir_pht_size_counter"                value="2" />
       <parameter name="dir_pht_nb_counter"                  value="128" />
+      <parameter name="dir_pht_nb_counter"                  value="64" />
       <parameter name="dir_pht_size_address_share"          value="0" />
     </predictor>
 …
     <parameter name="nb_rename_unit_select"                 value="1" />
     <parameter name="nb_execute_loop_select"                value="1" />
     <parameter name="size_re_order_buffer"                  value="128"/>
     <parameter name="nb_re_order_buffer_bank"               value="64" />
+    <parameter name="size_re_order_buffer"                  value="64"/>
+    <parameter name="nb_re_order_buffer_bank"               value="16" />
     <parameter name="commit_priority"                       value="1" />
     <parameter name="commit_load_balancing"                 value="1" />
 …
   <execute_loop id="0">
     <parameter name="nb_read_unit"                          value="6" />
     <parameter name="nb_write_unit"                         value="6" />
     <parameter name="nb_execute_unit"                       value="6" />
+    <parameter name="nb_read_unit"                          value="4" />
+    <parameter name="nb_write_unit"                         value="4" />
+    <parameter name="nb_execute_unit"                       value="4" />
     <parameter name="nb_gpr_bank"                           value="1" />
     <parameter name="nb_gpr_port_read_by_bank"              value="12" />
     <parameter name="nb_gpr_port_write_by_bank"             value="6" />
+    <parameter name="nb_gpr_port_read_by_bank"              value="8" />
+    <parameter name="nb_gpr_port_write_by_bank"             value="4" />
     <parameter name="nb_spr_bank"                           value="1" />
     <parameter name="nb_spr_port_read_by_bank"              value="5" />
     <parameter name="nb_spr_port_write_by_bank"             value="5" />
+    <parameter name="nb_spr_port_read_by_bank"              value="4" />
+    <parameter name="nb_spr_port_write_by_bank"             value="4" />
     <parameter name="execution_unit_to_write_unit_priority" value="1" />
     <parameter name="read_unit_to_execution_unit_priority"  value="1" />
 …
   <link name="link_decod_unit_with_decod_bloc"         src="0"     dest="0.0" />
   <link name="link_rename_unit_with_rename_bloc"       src="0"     dest="0.0" />
   <link name="link_read_unit_with_read_bloc"           src="0"     dest="0.0" />
   <link name="link_read_unit_with_read_bloc"           src="1"     dest="0.1" />
   <link name="link_read_unit_with_read_bloc"           src="2"     dest="0.2" />
   <link name="link_read_unit_with_read_bloc"           src="3"     dest="0.3" />
-  <link name="link_read_unit_with_read_bloc"           src="4"     dest="0.4" />
-  <link name="link_read_unit_with_read_bloc"           src="5"     dest="0.5" />
   <link name="link_write_unit_with_write_bloc"         src="0"     dest="0.0" />
   <link name="link_write_unit_with_write_bloc"         src="1"     dest="0.1" />
   <link name="link_write_unit_with_write_bloc"         src="2"     dest="0.2" />
   <link name="link_write_unit_with_write_bloc"         src="3"     dest="0.3" />
-  <link name="link_write_unit_with_write_bloc"         src="4"     dest="0.4" />
-  <link name="link_write_unit_with_write_bloc"         src="5"     dest="0.5" />
   <link name="link_decod_bloc_with_thread"             src="0"     dest="0"   />
   <link name="link_rename_bloc_with_front_end"         src="0"     dest="0"   />
 …
   <link name="link_execute_unit_with_functionnal_unit" src="1"     dest="0.2"/>
   <link name="link_execute_unit_with_functionnal_unit" src="2"     dest="0.3"/>
-  <link name="link_execute_unit_with_functionnal_unit" src="3"     dest="0.4"/>
-  <link name="link_execute_unit_with_functionnal_unit" src="4"     dest="0.5"/>
   <link name="link_icache_port_with_thread"            src="0"     dest="0"   />
 …
   <link name="table_dispatch"                          src="0.0.0" dest="1"   />
   <link name="table_dispatch"                          src="0.1.0" dest="1"   />
   <link name="table_dispatch"                          src="0.2.0" dest="1"   />
   <link name="table_dispatch"                          src="0.3.0" dest="1"   />
   <link name="table_dispatch"                          src="0.0.1" dest="1"   />
+  <link name="table_dispatch"                          src="0.1.0" dest="0"   />
+  <link name="table_dispatch"                          src="0.2.0" dest="0"   />
+  <link name="table_dispatch"                          src="0.3.0" dest="0"   />
+  <link name="table_dispatch"                          src="0.0.1" dest="0"   />
   <link name="table_dispatch"                          src="0.1.1" dest="1"   />
   <link name="table_dispatch"                          src="0.2.1" dest="1"   />
   <link name="table_dispatch"                          src="0.3.1" dest="1"   />
   <link name="table_dispatch"                          src="0.0.2" dest="1"   />
   <link name="table_dispatch"                          src="0.1.2" dest="1"   />
+  <link name="table_dispatch"                          src="0.2.1" dest="0"   />
+  <link name="table_dispatch"                          src="0.3.1" dest="0"   />
+  <link name="table_dispatch"                          src="0.0.2" dest="0"   />
+  <link name="table_dispatch"                          src="0.1.2" dest="0"   />
   <link name="table_dispatch"                          src="0.2.2" dest="1"   />
   <link name="table_dispatch"                          src="0.3.2" dest="1"   />
   <link name="table_dispatch"                          src="0.0.3" dest="1"   />
   <link name="table_dispatch"                          src="0.1.3" dest="1"   />
   <link name="table_dispatch"                          src="0.2.3" dest="1"   />
+  <link name="table_dispatch"                          src="0.3.2" dest="0"   />
+  <link name="table_dispatch"                          src="0.0.3" dest="0"   />
+  <link name="table_dispatch"                          src="0.1.3" dest="0"   />
+  <link name="table_dispatch"                          src="0.2.3" dest="0"   />
   <link name="table_dispatch"                          src="0.3.3" dest="1"   />
-  <link name="table_dispatch"                          src="0.0.4" dest="1"   />
-  <link name="table_dispatch"                          src="0.1.4" dest="1"   />
-  <link name="table_dispatch"                          src="0.2.4" dest="1"   />
-  <link name="table_dispatch"                          src="0.3.4" dest="1"   />
-  <link name="table_dispatch"                          src="0.0.5" dest="1"   />
-  <link name="table_dispatch"                          src="0.1.5" dest="1"   />
-  <link name="table_dispatch"                          src="0.2.5" dest="1"   />
-  <link name="table_dispatch"                          src="0.3.5" dest="1"   />
   <link name="link_read_bloc_and_load_store_unit"      src="0.0"   dest="1"   />
 …
   <link name="link_read_bloc_and_load_store_unit"      src="2.0"   dest="0"   />
   <link name="link_read_bloc_and_load_store_unit"      src="3.0"   dest="0"   />
-  <link name="link_read_bloc_and_load_store_unit"      src="4.0"   dest="0"   />
-  <link name="link_read_bloc_and_load_store_unit"      src="5.0"   dest="0"   />
   <link name="link_read_bloc_and_functionnal_unit"     src="0.0"   dest="0"   />
   <link name="link_read_bloc_and_functionnal_unit"     src="1.0"   dest="1"   />
   <link name="link_read_bloc_and_functionnal_unit"     src="2.0"   dest="0"   />
+  <link name="link_read_bloc_and_functionnal_unit"     src="2.0"   dest="1"   />
   <link name="link_read_bloc_and_functionnal_unit"     src="3.0"   dest="0"   />
-  <link name="link_read_bloc_and_functionnal_unit"     src="4.0"   dest="0"   />
-  <link name="link_read_bloc_and_functionnal_unit"     src="5.0"   dest="0"   />
   <link name="link_read_bloc_and_functionnal_unit"     src="0.1"   dest="0"   />
   <link name="link_read_bloc_and_functionnal_unit"     src="1.1"   dest="0"   />
+  <link name="link_read_bloc_and_functionnal_unit"     src="1.1"   dest="1"   />
   <link name="link_read_bloc_and_functionnal_unit"     src="2.1"   dest="1"   />
+  <link name="link_read_bloc_and_functionnal_unit"     src="3.1"   dest="1"   />
+  <link name="link_read_bloc_and_functionnal_unit"     src="4.1"   dest="1"   />
+  <link name="link_read_bloc_and_functionnal_unit"     src="5.1"   dest="1"   />
+  <link name="link_read_bloc_and_functionnal_unit"     src="3.1"   dest="0"   />
   <link name="link_read_bloc_and_functionnal_unit"     src="0.2"   dest="0"   />
   <link name="link_read_bloc_and_functionnal_unit"     src="1.2"   dest="0"   />
   <link name="link_read_bloc_and_functionnal_unit"     src="2.2"   dest="1"   />
+  <link name="link_read_bloc_and_functionnal_unit"     src="2.2"   dest="0"   />
   <link name="link_read_bloc_and_functionnal_unit"     src="3.2"   dest="1"   />
-  <link name="link_read_bloc_and_functionnal_unit"     src="4.2"   dest="1"   />
-  <link name="link_read_bloc_and_functionnal_unit"     src="5.2"   dest="1"   />
-  <link name="link_read_bloc_and_functionnal_unit"     src="0.3"   dest="0"   />
-  <link name="link_read_bloc_and_functionnal_unit"     src="1.3"   dest="0"   />
-  <link name="link_read_bloc_and_functionnal_unit"     src="2.3"   dest="1"   />
-  <link name="link_read_bloc_and_functionnal_unit"     src="3.3"   dest="1"   />
-  <link name="link_read_bloc_and_functionnal_unit"     src="4.3"   dest="1"   />
-  <link name="link_read_bloc_and_functionnal_unit"     src="5.3"   dest="1"   />
-  <link name="link_read_bloc_and_functionnal_unit"     src="0.4"   dest="0"   />
-  <link name="link_read_bloc_and_functionnal_unit"     src="1.4"   dest="0"   />
-  <link name="link_read_bloc_and_functionnal_unit"     src="2.4"   dest="1"   />
-  <link name="link_read_bloc_and_functionnal_unit"     src="3.4"   dest="1"   />
-  <link name="link_read_bloc_and_functionnal_unit"     src="4.4"   dest="1"   />
-  <link name="link_read_bloc_and_functionnal_unit"     src="5.4"   dest="1"   />
   <link name="link_write_bloc_and_load_store_unit"     src="0.0"   dest="1"   />
 …
   <link name="link_write_bloc_and_load_store_unit"     src="2.0"   dest="0"   />
   <link name="link_write_bloc_and_load_store_unit"     src="3.0"   dest="0"   />
-  <link name="link_write_bloc_and_load_store_unit"     src="4.0"   dest="0"   />
-  <link name="link_write_bloc_and_load_store_unit"     src="5.0"   dest="0"   />
   <link name="link_write_bloc_and_functionnal_unit"    src="0.0"   dest="0"   />
   <link name="link_write_bloc_and_functionnal_unit"    src="1.0"   dest="1"   />
   <link name="link_write_bloc_and_functionnal_unit"    src="2.0"   dest="0"   />
+  <link name="link_write_bloc_and_functionnal_unit"    src="2.0"   dest="1"   />
   <link name="link_write_bloc_and_functionnal_unit"    src="3.0"   dest="0"   />
-  <link name="link_write_bloc_and_functionnal_unit"    src="4.0"   dest="0"   />
-  <link name="link_write_bloc_and_functionnal_unit"    src="5.0"   dest="0"   />
   <link name="link_write_bloc_and_functionnal_unit"    src="0.1"   dest="0"   />
   <link name="link_write_bloc_and_functionnal_unit"    src="1.1"   dest="0"   />
+  <link name="link_write_bloc_and_functionnal_unit"    src="1.1"   dest="1"   />
   <link name="link_write_bloc_and_functionnal_unit"    src="2.1"   dest="1"   />
+  <link name="link_write_bloc_and_functionnal_unit"    src="3.1"   dest="1"   />
+  <link name="link_write_bloc_and_functionnal_unit"    src="4.1"   dest="1"   />
+  <link name="link_write_bloc_and_functionnal_unit"    src="5.1"   dest="1"   />
+  <link name="link_write_bloc_and_functionnal_unit"    src="3.1"   dest="0"   />
   <link name="link_write_bloc_and_functionnal_unit"    src="0.2"   dest="0"   />
   <link name="link_write_bloc_and_functionnal_unit"    src="1.2"   dest="0"   />
   <link name="link_write_bloc_and_functionnal_unit"    src="2.2"   dest="1"   />
+  <link name="link_write_bloc_and_functionnal_unit"    src="2.2"   dest="0"   />
   <link name="link_write_bloc_and_functionnal_unit"    src="3.2"   dest="1"   />
-  <link name="link_write_bloc_and_functionnal_unit"    src="4.2"   dest="1"   />
-  <link name="link_write_bloc_and_functionnal_unit"    src="5.2"   dest="1"   />
-  <link name="link_write_bloc_and_functionnal_unit"    src="0.3"   dest="0"   />
-  <link name="link_write_bloc_and_functionnal_unit"    src="1.3"   dest="0"   />
-  <link name="link_write_bloc_and_functionnal_unit"    src="2.3"   dest="1"   />
-  <link name="link_write_bloc_and_functionnal_unit"    src="3.3"   dest="1"   />
-  <link name="link_write_bloc_and_functionnal_unit"    src="4.3"   dest="1"   />
-  <link name="link_write_bloc_and_functionnal_unit"    src="5.3"   dest="1"   />
-  <link name="link_write_bloc_and_functionnal_unit"    src="0.4"   dest="0"   />
-  <link name="link_write_bloc_and_functionnal_unit"    src="1.4"   dest="0"   />
-  <link name="link_write_bloc_and_functionnal_unit"    src="2.4"   dest="1"   />
-  <link name="link_write_bloc_and_functionnal_unit"    src="3.4"   dest="1"   />
-  <link name="link_write_bloc_and_functionnal_unit"    src="4.4"   dest="1"   />
-  <link name="link_write_bloc_and_functionnal_unit"    src="5.4"   dest="1"   />
   <link name="link_thread_and_functionnal_unit"        src="0.0"   dest="1"   />
   <link name="link_thread_and_functionnal_unit"        src="0.1"   dest="1"   />
   <link name="link_thread_and_functionnal_unit"        src="0.2"   dest="1"   />
-  <link name="link_thread_and_functionnal_unit"        src="0.3"   dest="1"   />
-  <link name="link_thread_and_functionnal_unit"        src="0.4"   dest="1"   />
 </core>

trunk/IPs/systemC/processor/Morpheo/Files/debug.sim

-                      r122
+                      r123
   <parameter  name="statistics_period"                      value="0"       />
   <parameter  name="simulation_nb_cycle"                    value="100"  />
+  <parameter  name="simulation_nb_cycle"                    value="500000"  />
   <parameter  name="simulation_nb_instruction"              value="0"       />
   <parameter  name="debug_level"                            value="0"       />
   <parameter  name="debug_cycle_start"                      value="8000"   />
   <parameter  name="debug_cycle_stop"                       value="9000"   />
+  <parameter  name="debug_cycle_start"                      value="0"       />
+  <parameter  name="debug_cycle_stop"                       value="20000"     />
   <parameter  name="debug_log_file_generate"                value="0"       />
 …
   <component  name="Context_State"                          model="systemc" debug="1" />
   <component  name="Decod"                                  model="systemc" debug="0" />
   <component  name="Decod_queue"                            model="systemc" debug="0" />
+  <component  name="Decod_queue"                            model="systemc" debug="1" />
   <component  name="Decod_unit"                             model="systemc" debug="0" />
   <component  name="Front_end_Glue"                         model="systemc" debug="0" />
   <component  name="Address_management"                     model="systemc" debug="0" />
   <component  name="Ifetch_queue"                           model="systemc" debug="0" />
+  <component  name="Address_management"                     model="systemc" debug="1" />
+  <component  name="Ifetch_queue"                           model="systemc" debug="1" />
   <component  name="Ifetch_unit_Glue"                       model="systemc" debug="0" />
   <component  name="Ifetch_unit"                            model="systemc" debug="0" />
 …
   <component  name="Branch_Target_Buffer_Register"          model="systemc" debug="0" />
   <component  name="Branch_Target_Buffer"                   model="systemc" debug="0" />
   <component  name="Direction_Glue"                         model="systemc" debug="0" />
+  <component  name="Direction_Glue"                         model="systemc" debug="1" />
   <component  name="Direction"                              model="systemc" debug="0" />
   <component  name="Two_Level_Branch_Predictor"             model="systemc" debug="0" />
   <component  name="Meta_Predictor_Glue"                    model="systemc" debug="0" />
+  <component  name="Two_Level_Branch_Predictor"             model="systemc" debug="1" />
+  <component  name="Meta_Predictor_Glue"                    model="systemc" debug="1" />
   <component  name="Meta_Predictor"                         model="systemc" debug="0" />
   <component  name="Prediction_unit_Glue"                   model="systemc" debug="0" />
   <component  name="Return_Address_Stack"                   model="systemc" debug="0" />
+  <component  name="Prediction_unit_Glue"                   model="systemc" debug="1" />
+  <component  name="Return_Address_Stack"                   model="systemc" debug="1" />
   <component  name="Update_Prediction_Table"                model="systemc" debug="1" />
   <component  name="Prediction_unit"                        model="systemc" debug="0" />

trunk/IPs/systemC/processor/Morpheo/TopLevel/src/Morpheo_deallocation.cpp

-                      r88
+                      r123
     // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+    delete _component_core;
     delete _component;
-    delete _component_core;
     log_end(Morpheo,FUNCTION);

trunk/IPs/systemC/shared/mapping_memory.h

r101	r123
6	6
7	7	# define DATA_CACHED_BASE 0x10000000
8		# define DATA_CACHED_SIZE 0x10000000
	8	# define DATA_CACHED_SIZE 0x05000000
9	9
10	10	# define DATA_STACK_BASE 0x40000000

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