Ignore:
Timestamp:
Nov 29, 2012, 6:14:01 PM (12 years ago)
Author:
rolagamo
Message:
 
Location:
PROJECT_CORE_MPI/CORE_MPI/TRUNK
Files:
104 deleted
4 edited

Legend:

Unmodified
Added
Removed

  • PROJECT_CORE_MPI/CORE_MPI/TRUNK/MPI_CORE_COMPONENTS.gise

    r15 r18  
    2323
    2424  <files xmlns="http://www.xilinx.com/XMLSchema">
    25     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="CORE_MPI.bld"/>
    26     <file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="CORE_MPI.cmd_log"/>
    27     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="CORE_MPI.lso"/>
    28     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="CORE_MPI.ncd" xil_pn:subbranch="Par"/>
    29     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="CORE_MPI.ngc"/>
    30     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="CORE_MPI.ngd"/>
    31     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="CORE_MPI.ngr"/>
    32     <file xil_pn:fileType="FILE_PAD_MISC" xil_pn:name="CORE_MPI.pad"/>
    33     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAR_REPORT" xil_pn:name="CORE_MPI.par" xil_pn:subbranch="Par"/>
    34     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PCF" xil_pn:name="CORE_MPI.pcf" xil_pn:subbranch="Map"/>
    35     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="CORE_MPI.prj"/>
    36     <file xil_pn:fileType="FILE_TRCE_MISC" xil_pn:name="CORE_MPI.ptwx"/>
    37     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="CORE_MPI.stx"/>
    38     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="CORE_MPI.syr"/>
    39     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="CORE_MPI.twr" xil_pn:subbranch="Par"/>
    40     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="CORE_MPI.twx" xil_pn:subbranch="Par"/>
    41     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_UNROUTES" xil_pn:name="CORE_MPI.unroutes" xil_pn:subbranch="Par"/>
    42     <file xil_pn:fileType="FILE_XPI" xil_pn:name="CORE_MPI.xpi"/>
    43     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="CORE_MPI.xst"/>
    44     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="CORE_MPI_beh.prj"/>
    45     <file xil_pn:fileType="FILE_HTML" xil_pn:name="CORE_MPI_envsettings.html"/>
    4625    <file xil_pn:fileType="FILE_NCD" xil_pn:name="CORE_MPI_guide.ncd" xil_pn:origination="imported"/>
    47     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="CORE_MPI_map.map" xil_pn:subbranch="Map"/>
    48     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="CORE_MPI_map.mrp" xil_pn:subbranch="Map"/>
    49     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="CORE_MPI_map.ncd" xil_pn:subbranch="Map"/>
    50     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="CORE_MPI_map.ngm" xil_pn:subbranch="Map"/>
    51     <file xil_pn:fileType="FILE_XRPT" xil_pn:name="CORE_MPI_map.xrpt"/>
    52     <file xil_pn:fileType="FILE_XRPT" xil_pn:name="CORE_MPI_ngdbuild.xrpt"/>
    53     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="CORE_MPI_pad.csv" xil_pn:subbranch="Par"/>
    54     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="CORE_MPI_pad.txt" xil_pn:subbranch="Par"/>
    55     <file xil_pn:fileType="FILE_XRPT" xil_pn:name="CORE_MPI_par.xrpt"/>
    56     <file xil_pn:fileType="FILE_HTML" xil_pn:name="CORE_MPI_summary.html"/>
    57     <file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="CORE_MPI_summary.xml"/>
    58     <file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="CORE_MPI_usage.xml"/>
    59     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="CORE_MPI_vhdl.prj"/>
    60     <file xil_pn:fileType="FILE_XRPT" xil_pn:name="CORE_MPI_xst.xrpt"/>
    6126    <file xil_pn:fileType="FILE_NCD" xil_pn:name="DMA_ARBITER_guide.ncd" xil_pn:origination="imported"/>
    6227    <file xil_pn:fileType="FILE_NCD" xil_pn:name="EX4_FSM_guide.ncd" xil_pn:origination="imported"/>
    63     <file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="MPICORETEST.cmd_log"/>
    64     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_MODELSIM_CMD" xil_pn:name="MPICORETEST.fdo"/>
    65     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="MPICORETEST.lso"/>
    66     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="MPICORETEST.prj"/>
    67     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="MPICORETEST.syr"/>
    68     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="MPICORETEST.xst"/>
    6928    <file xil_pn:fileType="FILE_NCD" xil_pn:name="MPICORETEST_guide.ncd" xil_pn:origination="imported"/>
    70     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="MPICORETEST_isim_beh.exe"/>
    71     <file xil_pn:fileType="FILE_HTML" xil_pn:name="MPICORETEST_summary.html"/>
    72     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="MPICORETEST_vhdl.prj"/>
    73     <file xil_pn:fileType="FILE_XRPT" xil_pn:name="MPICORETEST_xst.xrpt"/>
    74     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="MPI_NOC.bld"/>
    75     <file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="MPI_NOC.cmd_log"/>
    76     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="MPI_NOC.lso"/>
    77     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="MPI_NOC.ncd" xil_pn:subbranch="Par"/>
    78     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="MPI_NOC.ngc"/>
    79     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="MPI_NOC.ngd"/>
    80     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="MPI_NOC.ngr"/>
    81     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAR_REPORT" xil_pn:name="MPI_NOC.par" xil_pn:subbranch="Par"/>
    82     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PCF" xil_pn:name="MPI_NOC.pcf" xil_pn:subbranch="Map"/>
    83     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="MPI_NOC.prj"/>
    84     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="MPI_NOC.stx"/>
    8529    <file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="MPI_NOC.sym" xil_pn:origination="imported"/>
    86     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="MPI_NOC.syr"/>
    87     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="MPI_NOC.twr" xil_pn:subbranch="Par"/>
    88     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="MPI_NOC.twx" xil_pn:subbranch="Par"/>
    89     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_UNROUTES" xil_pn:name="MPI_NOC.unroutes" xil_pn:subbranch="Par"/>
    90     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="MPI_NOC.xst"/>
    9130    <file xil_pn:fileType="FILE_NCD" xil_pn:name="MPI_NOC_guide.ncd" xil_pn:origination="imported"/>
    92     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="MPI_NOC_isim_beh.exe"/>
    93     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="MPI_NOC_map.map" xil_pn:subbranch="Map"/>
    94     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="MPI_NOC_map.mrp" xil_pn:subbranch="Map"/>
    95     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="MPI_NOC_map.ncd" xil_pn:subbranch="Map"/>
    96     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="MPI_NOC_map.ngm" xil_pn:subbranch="Map"/>
    97     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="MPI_NOC_pad.csv" xil_pn:subbranch="Par"/>
    98     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="MPI_NOC_pad.txt" xil_pn:subbranch="Par"/>
    99     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="MPI_NOC_preroute.twr" xil_pn:subbranch="Map"/>
    100     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="MPI_NOC_preroute.twx" xil_pn:subbranch="Map"/>
    101     <file xil_pn:fileType="FILE_HTML" xil_pn:name="MPI_NOC_summary.html"/>
    102     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="MPI_NOC_vhdl.prj"/>
    103     <file xil_pn:fileType="FILE_XRPT" xil_pn:name="MPI_NOC_xst.xrpt"/>
    104     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="MultiMPITest.bld"/>
    105     <file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="MultiMPITest.cmd_log"/>
    106     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="MultiMPITest.lso"/>
    107     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="MultiMPITest.ncd" xil_pn:subbranch="Par"/>
    108     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="MultiMPITest.ngc"/>
    109     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="MultiMPITest.ngd"/>
    110     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="MultiMPITest.ngr"/>
    111     <file xil_pn:fileType="FILE_PAD_MISC" xil_pn:name="MultiMPITest.pad"/>
    112     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAR_REPORT" xil_pn:name="MultiMPITest.par" xil_pn:subbranch="Par"/>
    113     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PCF" xil_pn:name="MultiMPITest.pcf" xil_pn:subbranch="Map"/>
    114     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="MultiMPITest.prj"/>
    115     <file xil_pn:fileType="FILE_TRCE_MISC" xil_pn:name="MultiMPITest.ptwx"/>
    116     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="MultiMPITest.stx"/>
    117     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="MultiMPITest.syr"/>
    118     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="MultiMPITest.twr" xil_pn:subbranch="Par"/>
    119     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="MultiMPITest.twx" xil_pn:subbranch="Par"/>
    120     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_UNROUTES" xil_pn:name="MultiMPITest.unroutes" xil_pn:subbranch="Par"/>
    121     <file xil_pn:fileType="FILE_XPI" xil_pn:name="MultiMPITest.xpi"/>
    122     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="MultiMPITest.xst"/>
    123     <file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="MultiMPITest_beh.prj"/>
    124     <file xil_pn:fileType="FILE_HTML" xil_pn:name="MultiMPITest_envsettings.html"/>
    12531    <file xil_pn:fileType="FILE_NCD" xil_pn:name="MultiMPITest_guide.ncd" xil_pn:origination="imported"/>
    126     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="MultiMPITest_isim_beh.exe"/>
    127     <file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="MultiMPITest_isim_beh.wdb"/>
    128     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="MultiMPITest_map.map" xil_pn:subbranch="Map"/>
    129     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="MultiMPITest_map.mrp" xil_pn:subbranch="Map"/>
    130     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="MultiMPITest_map.ncd" xil_pn:subbranch="Map"/>
    131     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="MultiMPITest_map.ngm" xil_pn:subbranch="Map"/>
    132     <file xil_pn:fileType="FILE_XRPT" xil_pn:name="MultiMPITest_map.xrpt"/>
    133     <file xil_pn:fileType="FILE_XRPT" xil_pn:name="MultiMPITest_ngdbuild.xrpt"/>
    134     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="MultiMPITest_pad.csv" xil_pn:subbranch="Par"/>
    135     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="MultiMPITest_pad.txt" xil_pn:subbranch="Par"/>
    136     <file xil_pn:fileType="FILE_XRPT" xil_pn:name="MultiMPITest_par.xrpt"/>
    137     <file xil_pn:fileType="FILE_HTML" xil_pn:name="MultiMPITest_summary.html"/>
    138     <file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="MultiMPITest_summary.xml"/>
    139     <file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="MultiMPITest_usage.xml"/>
    140     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="MultiMPITest_vhdl.prj"/>
    141     <file xil_pn:fileType="FILE_XRPT" xil_pn:name="MultiMPITest_xst.xrpt"/>
    142     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Proto_receiv_isim_beh.exe"/>
    143     <file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="RAM_v.cmd_log"/>
    144     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="RAM_v.lso"/>
    145     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="RAM_v.ngc"/>
    146     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="RAM_v.ngr"/>
    147     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="RAM_v.prj"/>
    148     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="RAM_v.stx"/>
    149     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="RAM_v.syr"/>
    150     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="RAM_v.xst"/>
    151     <file xil_pn:fileType="FILE_HTML" xil_pn:name="RAM_v_envsettings.html"/>
    152     <file xil_pn:fileType="FILE_HTML" xil_pn:name="RAM_v_summary.html"/>
    153     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="RAM_v_vhdl.prj"/>
    154     <file xil_pn:fileType="FILE_XRPT" xil_pn:name="RAM_v_xst.xrpt"/>
    15532    <file xil_pn:fileType="FILE_NCD" xil_pn:name="SWITCH_GEN_guide.ncd" xil_pn:origination="imported"/>
    156     <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="_ngo"/>
    157     <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/map.xmsgs"/>
    158     <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
    159     <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/par.xmsgs"/>
    160     <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/trce.xmsgs"/>
    161     <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
    162     <file xil_pn:fileType="FILE_LOG" xil_pn:name="compxlib.log"/>
    163     <file xil_pn:fileType="FILE_LOG" xil_pn:name="fuse.log"/>
    164     <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="isim"/>
    165     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_CMD" xil_pn:name="isim.cmd"/>
    166     <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="planAhead_run_1"/>
    167     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="test_xbar_8x8_isim_beh.exe"/>
    168     <file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="test_xbar_8x8_stx_beh.prj"/>
    169     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testbench_isim_beh.exe"/>
    170     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_MODELSIM_LOG" xil_pn:name="vsim.wlf"/>
    171     <file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
    172     <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="work"/>
    173     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_INI" xil_pn:name="xilinxsim.ini"/>
    174     <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xlnx_auto_0_xdb"/>
    175     <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/>
    17633  </files>
    17734
    178   <transforms xmlns="http://www.xilinx.com/XMLSchema">
    179     <transform xil_pn:end_ts="1349108698" xil_pn:name="TRANEXT_compLibraries_FPGA" xil_pn:prop_ck="7616047539597174666" xil_pn:start_ts="1349108696">
    180       <status xil_pn:value="FailedRun"/>
    181       <status xil_pn:value="WarningsGenerated"/>
    182       <status xil_pn:value="ReadyToRun"/>
    183       <status xil_pn:value="OutOfDateForProperties"/>
    184       <status xil_pn:value="OutOfDateForOutputs"/>
    185       <status xil_pn:value="OutputChanged"/>
    186       <outfile xil_pn:name="compxlib.log"/>
    187     </transform>
    188     <transform xil_pn:end_ts="1352891540" xil_pn:name="TRAN_copyInitialToAbstractSimulation" xil_pn:start_ts="1352891540">
    189       <status xil_pn:value="SuccessfullyRun"/>
    190       <status xil_pn:value="ReadyToRun"/>
    191     </transform>
    192     <transform xil_pn:end_ts="1353950850" xil_pn:in_ck="6795544366157925958" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1353950850">
    193       <status xil_pn:value="SuccessfullyRun"/>
    194       <status xil_pn:value="ReadyToRun"/>
    195       <outfile xil_pn:name="../SWITCH_GENERIC_16_16/Arbiter.vhd"/>
    196       <outfile xil_pn:name="../SWITCH_GENERIC_16_16/CoreTypes.vhd"/>
    197       <outfile xil_pn:name="../SWITCH_GENERIC_16_16/Crossbar.vhd"/>
    198       <outfile xil_pn:name="../SWITCH_GENERIC_16_16/Crossbit.vhd"/>
    199       <outfile xil_pn:name="../SWITCH_GENERIC_16_16/FIFO_256_FWFT.vhd"/>
    200       <outfile xil_pn:name="../SWITCH_GENERIC_16_16/INPUT_PORT_MODULE.vhd"/>
    201       <outfile xil_pn:name="../SWITCH_GENERIC_16_16/OUTPUT_PORT_MODULE.vhd"/>
    202       <outfile xil_pn:name="../SWITCH_GENERIC_16_16/Proto_receiv.vhd"/>
    203       <outfile xil_pn:name="../SWITCH_GENERIC_16_16/RAM_256.vhd"/>
    204       <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER12_12.VHD"/>
    205       <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER13_13.VHD"/>
    206       <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER14_14.VHD"/>
    207       <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER15_15.VHD"/>
    208       <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER16_16.VHD"/>
    209       <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER2_2.VHD"/>
    210       <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER3_3.VHD"/>
    211       <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER4_4.VHD"/>
    212       <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER5_5.VHD"/>
    213       <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER6_6.VHD"/>
    214       <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER7_7.VHD"/>
    215       <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER8_8.VHD"/>
    216       <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SWITCH_GEN.vhd"/>
    217       <outfile xil_pn:name="../SWITCH_GENERIC_16_16/Scheduler.vhd"/>
    218       <outfile xil_pn:name="../SWITCH_GENERIC_16_16/proto_send.vhd"/>
    219       <outfile xil_pn:name="../SWITCH_GENERIC_16_16/stimuli1.vhd"/>
    220       <outfile xil_pn:name="../SWITCH_GENERIC_16_16/test_xbar_8x8.vhd"/>
    221       <outfile xil_pn:name="CORE_MPI.vhd"/>
    222       <outfile xil_pn:name="DEMUX1.vhd"/>
    223       <outfile xil_pn:name="DMA_ARBITER.vhd"/>
    224       <outfile xil_pn:name="EX1_FSM.vhd"/>
    225       <outfile xil_pn:name="EX2_FSM.vhd"/>
    226       <outfile xil_pn:name="EX3_FSM.vhd"/>
    227       <outfile xil_pn:name="EX4_FSM.vhd"/>
    228       <outfile xil_pn:name="Ex0_Fsm.vhd"/>
    229       <outfile xil_pn:name="FIFO_64_FWFT.vhd"/>
    230       <outfile xil_pn:name="FIfo_mem.vhd"/>
    231       <outfile xil_pn:name="FIfo_proc.vhd"/>
    232       <outfile xil_pn:name="MPICORETEST.vhd"/>
    233       <outfile xil_pn:name="MPI_CORE_SCHEDULER.vhd"/>
    234       <outfile xil_pn:name="MPI_NOC.vhd"/>
    235       <outfile xil_pn:name="MPI_PKG.vhd"/>
    236       <outfile xil_pn:name="MPI_RMA.vhd"/>
    237       <outfile xil_pn:name="MUX1.vhd"/>
    238       <outfile xil_pn:name="MUX8.vhd"/>
    239       <outfile xil_pn:name="MultiMPITest.vhd"/>
    240       <outfile xil_pn:name="PE.vhd"/>
    241       <outfile xil_pn:name="Packet_type.vhd"/>
    242       <outfile xil_pn:name="RAM_32_32.vhd"/>
    243       <outfile xil_pn:name="RAM_64.vhd"/>
    244       <outfile xil_pn:name="load_instr.vhd"/>
    245       <outfile xil_pn:name="round_robbin_machine.vhd"/>
    246       <outfile xil_pn:name="sim_fifo.vhd"/>
    247     </transform>
    248     <transform xil_pn:end_ts="1353951434" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-8804766714685316537" xil_pn:start_ts="1353951434">
    249       <status xil_pn:value="SuccessfullyRun"/>
    250       <status xil_pn:value="ReadyToRun"/>
    251     </transform>
    252     <transform xil_pn:end_ts="1353951434" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="225563001328936133" xil_pn:start_ts="1353951434">
    253       <status xil_pn:value="SuccessfullyRun"/>
    254       <status xil_pn:value="ReadyToRun"/>
    255     </transform>
    256     <transform xil_pn:end_ts="1352891540" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="8414388184515446556" xil_pn:start_ts="1352891540">
    257       <status xil_pn:value="SuccessfullyRun"/>
    258       <status xil_pn:value="ReadyToRun"/>
    259     </transform>
    260     <transform xil_pn:end_ts="1353950850" xil_pn:in_ck="6795544366157925958" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1353950850">
    261       <status xil_pn:value="SuccessfullyRun"/>
    262       <status xil_pn:value="ReadyToRun"/>
    263       <outfile xil_pn:name="../SWITCH_GENERIC_16_16/Arbiter.vhd"/>
    264       <outfile xil_pn:name="../SWITCH_GENERIC_16_16/CoreTypes.vhd"/>
    265       <outfile xil_pn:name="../SWITCH_GENERIC_16_16/Crossbar.vhd"/>
    266       <outfile xil_pn:name="../SWITCH_GENERIC_16_16/Crossbit.vhd"/>
    267       <outfile xil_pn:name="../SWITCH_GENERIC_16_16/FIFO_256_FWFT.vhd"/>
    268       <outfile xil_pn:name="../SWITCH_GENERIC_16_16/INPUT_PORT_MODULE.vhd"/>
    269       <outfile xil_pn:name="../SWITCH_GENERIC_16_16/OUTPUT_PORT_MODULE.vhd"/>
    270       <outfile xil_pn:name="../SWITCH_GENERIC_16_16/Proto_receiv.vhd"/>
    271       <outfile xil_pn:name="../SWITCH_GENERIC_16_16/RAM_256.vhd"/>
    272       <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER12_12.VHD"/>
    273       <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER13_13.VHD"/>
    274       <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER14_14.VHD"/>
    275       <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER15_15.VHD"/>
    276       <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER16_16.VHD"/>
    277       <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER2_2.VHD"/>
    278       <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER3_3.VHD"/>
    279       <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER4_4.VHD"/>
    280       <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER5_5.VHD"/>
    281       <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER6_6.VHD"/>
    282       <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER7_7.VHD"/>
    283       <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER8_8.VHD"/>
    284       <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SWITCH_GEN.vhd"/>
    285       <outfile xil_pn:name="../SWITCH_GENERIC_16_16/Scheduler.vhd"/>
    286       <outfile xil_pn:name="../SWITCH_GENERIC_16_16/proto_send.vhd"/>
    287       <outfile xil_pn:name="../SWITCH_GENERIC_16_16/stimuli1.vhd"/>
    288       <outfile xil_pn:name="../SWITCH_GENERIC_16_16/test_xbar_8x8.vhd"/>
    289       <outfile xil_pn:name="CORE_MPI.vhd"/>
    290       <outfile xil_pn:name="DEMUX1.vhd"/>
    291       <outfile xil_pn:name="DMA_ARBITER.vhd"/>
    292       <outfile xil_pn:name="EX1_FSM.vhd"/>
    293       <outfile xil_pn:name="EX2_FSM.vhd"/>
    294       <outfile xil_pn:name="EX3_FSM.vhd"/>
    295       <outfile xil_pn:name="EX4_FSM.vhd"/>
    296       <outfile xil_pn:name="Ex0_Fsm.vhd"/>
    297       <outfile xil_pn:name="FIFO_64_FWFT.vhd"/>
    298       <outfile xil_pn:name="FIfo_mem.vhd"/>
    299       <outfile xil_pn:name="FIfo_proc.vhd"/>
    300       <outfile xil_pn:name="MPICORETEST.vhd"/>
    301       <outfile xil_pn:name="MPI_CORE_SCHEDULER.vhd"/>
    302       <outfile xil_pn:name="MPI_NOC.vhd"/>
    303       <outfile xil_pn:name="MPI_PKG.vhd"/>
    304       <outfile xil_pn:name="MPI_RMA.vhd"/>
    305       <outfile xil_pn:name="MUX1.vhd"/>
    306       <outfile xil_pn:name="MUX8.vhd"/>
    307       <outfile xil_pn:name="MultiMPITest.vhd"/>
    308       <outfile xil_pn:name="PE.vhd"/>
    309       <outfile xil_pn:name="Packet_type.vhd"/>
    310       <outfile xil_pn:name="RAM_32_32.vhd"/>
    311       <outfile xil_pn:name="RAM_64.vhd"/>
    312       <outfile xil_pn:name="load_instr.vhd"/>
    313       <outfile xil_pn:name="round_robbin_machine.vhd"/>
    314       <outfile xil_pn:name="sim_fifo.vhd"/>
    315     </transform>
    316     <transform xil_pn:end_ts="1353951464" xil_pn:in_ck="6795544366157925958" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-69836859381131890" xil_pn:start_ts="1353951434">
    317       <status xil_pn:value="SuccessfullyRun"/>
    318       <status xil_pn:value="ReadyToRun"/>
    319       <outfile xil_pn:name="MultiMPITest_beh.prj"/>
    320       <outfile xil_pn:name="MultiMPITest_isim_beh.exe"/>
    321       <outfile xil_pn:name="fuse.log"/>
    322       <outfile xil_pn:name="isim"/>
    323       <outfile xil_pn:name="xilinxsim.ini"/>
    324     </transform>
    325     <transform xil_pn:end_ts="1353951464" xil_pn:in_ck="5972306979604129699" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="4736240422826914561" xil_pn:start_ts="1353951464">
    326       <status xil_pn:value="SuccessfullyRun"/>
    327       <status xil_pn:value="ReadyToRun"/>
    328       <outfile xil_pn:name="MultiMPITest_isim_beh.wdb"/>
    329       <outfile xil_pn:name="isim.cmd"/>
    330     </transform>
    331     <transform xil_pn:end_ts="1344237304" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1344237304">
    332       <status xil_pn:value="SuccessfullyRun"/>
    333       <status xil_pn:value="ReadyToRun"/>
    334     </transform>
    335     <transform xil_pn:end_ts="1345373166" xil_pn:in_ck="5944890944412384878" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-4542759591300251492" xil_pn:start_ts="1345373166">
    336       <status xil_pn:value="SuccessfullyRun"/>
    337       <status xil_pn:value="ReadyToRun"/>
    338       <status xil_pn:value="OutOfDateForInputs"/>
    339       <status xil_pn:value="OutOfDateForProperties"/>
    340       <status xil_pn:value="InputChanged"/>
    341     </transform>
    342   </transforms>
     35  <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
    34336
    34437</generated_project>

  • PROJECT_CORE_MPI/CORE_MPI/TRUNK/MultiMPITest_summary.html

    r15 r18  
    33<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
    44<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
    5 <TD ALIGN=CENTER COLSPAN='4'><B>MultiMPITest Project Status (11/05/2012 - 16:48:15)</B></TD></TR>
     5<TD ALIGN=CENTER COLSPAN='4'><B>MultiMPITest Project Status</B></TD></TR>
    66<TR ALIGN=LEFT>
    77<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
    88<TD>MPI_CORE_COMPONENTS.xise</TD>
    99<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
    10 <TD> No Errors </TD>
    1110</TR>
    1211<TR ALIGN=LEFT>
    … …  
    1413<TD>MultiMPITest</TD>
    1514<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
    16 <TD>Placed and Routed</TD>
     15<TD>New</TD>
    1716</TR>
    1817<TR ALIGN=LEFT>
    … …  
    2019<TD>xc6slx100-3fgg484</TD>
    2120<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
    22 <TD>
    23 No Errors</TD>
     21<TD>&nbsp;</TD>
    2422</TR>
    2523<TR ALIGN=LEFT>
    2624<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 12.3</TD>
    2725<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
    28 <TD ALIGN=LEFT><A HREF_DISABLED='C:/Core MPI/CORE_MPI\_xmsgs/*.xmsgs?&DataKey=Warning'>109 Warnings (71 new)</A></TD>
     26<TD>&nbsp;</TD>
    2927</TR>
    3028<TR ALIGN=LEFT>
    … …  
    3331<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
    3432<TD>
    35 <A HREF_DISABLED='C:/Core MPI/CORE_MPI\MultiMPITest.unroutes'>All Signals Completely Routed</A></TD>
     33&nbsp;</TD>
    3634</TR>
    3735<TR ALIGN=LEFT>
    … …  
    3937<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD>
    4038<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
    41 <TD>
    42 <font color="red"; face="Arial"><b>X </b></font>
    43 <A HREF_DISABLED='C:/Core MPI/CORE_MPI\MultiMPITest.ptwx?&DataKey=ConstraintsData'>4 Failing Constraints</A></TD>
     39<TD>&nbsp;</TD>
    4440</TR>
    4541<TR ALIGN=LEFT>
    4642<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
    47 <TD>
    48 <A HREF_DISABLED='C:/Core MPI/CORE_MPI\MultiMPITest_envsettings.html'>
    49 System Settings</A>
    50 </TD>
     43<TD>&nbsp;</TD>
    5144<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
    52 <TD>293 &nbsp;<A HREF_DISABLED='C:/Core MPI/CORE_MPI\MultiMPITest.twx?&DataKey=XmlTimingReport'>(Timing Report)</A></TD>
     45<TD>&nbsp;&nbsp;</TD>
    5346</TR>
    5447</TABLE>
    … …  
    5851&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
    5952<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='2'><B>Current Warnings</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=CurrentWarnings"><B>[-]</B></a></TD></TR>
    60 <TR ALIGN=LEFT BGCOLOR='#FFFF99'><TD><B>Translation Warnings</B></TD><TD COLSPAN='2'><B>New</B></TD></TR>
    61 <TR ALIGN=LEFT><TD>WARNING:NgdBuild:452: - logical net 'MPI_Node_Out[2]_PushOut&lt;7&gt;' has no driver</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
    62 <TR ALIGN=LEFT><TD>WARNING:NgdBuild:452: - logical net 'MPI_Node_Out[2]_PushOut&lt;6&gt;' has no driver</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
    63 <TR ALIGN=LEFT><TD>WARNING:NgdBuild:452: - logical net 'MPI_Node_Out[2]_PushOut&lt;5&gt;' has no driver</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
    64 <TR ALIGN=LEFT><TD>WARNING:NgdBuild:452: - logical net 'MPI_Node_Out[2]_PushOut&lt;3&gt;' has no driver</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
    65 <TR ALIGN=LEFT><TD>WARNING:NgdBuild:452: - logical net 'MPI_Node_Out[2]_PushOut&lt;2&gt;' has no driver</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
    66 <TR ALIGN=LEFT><TD>WARNING:NgdBuild:452: - logical net 'MPI_Node_Out[2]_PushOut&lt;1&gt;' has no driver</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
    67 <TR ALIGN=LEFT><TD>WARNING:NgdBuild:452: - logical net 'uut/connect_core[2].hardmpi/packet_ack' has no driver</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
    68 <TR ALIGN=LEFT><TD>WARNING:NgdBuild:452: - logical net 'uut/connect_core[2].hardmpi/MyRank&lt;3&gt;' has no driver</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
    69 <TR ALIGN=LEFT><TD>WARNING:NgdBuild:452: - logical net 'uut/connect_core[2].hardmpi/MyRank&lt;2&gt;' has no driver</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
    70 <TR ALIGN=LEFT><TD>WARNING:NgdBuild:452: - logical net 'uut/connect_core[2].hardmpi/MyRank&lt;1&gt;' has no driver</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
    71 <TR ALIGN=LEFT><TD>WARNING:NgdBuild:452: - logical net 'uut/connect_core[2].hardmpi/MyRank&lt;0&gt;' has no driver</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
    72 <TR ALIGN=LEFT><TD>WARNING:NgdBuild:452: - logical net 'uut/connect_core[1].hardmpi/packet_ack' has no driver</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
    73 <TR ALIGN=LEFT><TD>WARNING:NgdBuild:452: - logical net 'uut/connect_core[1].hardmpi/MyRank&lt;3&gt;' has no driver</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
    74 <TR ALIGN=LEFT><TD>WARNING:NgdBuild:452: - logical net 'uut/connect_core[1].hardmpi/MyRank&lt;2&gt;' has no driver</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
    75 <TR ALIGN=LEFT><TD>WARNING:NgdBuild:452: - logical net 'uut/connect_core[1].hardmpi/MyRank&lt;1&gt;' has no driver</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
    76 <TR ALIGN=LEFT><TD>WARNING:NgdBuild:452: - logical net 'uut/connect_core[1].hardmpi/MyRank&lt;0&gt;' has no driver</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
    77 <TR ALIGN=LEFT BGCOLOR='#FFFF99'><TD><B>Map Warnings (Only the first 50 listed)</B></TD><TD COLSPAN='2'><B>New</B></TD></TR>
    78 <TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net PE2/N315 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
    79 <TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net PE1/etPutGet_FSM_FFd7 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
    80 <TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/ex4_ram_wr is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
    81 <TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/ex4_ram_wr is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
    82 <TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/etcmd[3]_PWR_534_o_Mux_739_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
    83 <TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/MPI_CORE_EX4_FSM/etcmd[3]_PWR_534_o_Mux_739_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
    84 <TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/Mram_dma_wr_grant[4]_GND_656_o_Mux_42_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
    85 <TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/Mram_dma_wr_grant[4]_GND_656_o_Mux_42_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
    86 <TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_99_o_Mux_295_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
    87 <TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_99_o_Mux_295_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
    88 <TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/stInit2_FSM_FFd7 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
    89 <TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_290_o_Mux_59_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
    90 <TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_290_o_Mux_59_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
    91 <TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_148_o_Mux_387_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
    92 <TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_148_o_Mux_387_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
    93 <TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_72_o_Mux_259_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
    94 <TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_72_o_Mux_259_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
    95 <TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net PE1/etPutGet[3]_PWR_594_o_Mux_268_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
    96 <TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_44_o_Mux_211_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
    97 <TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_93_o_Mux_287_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
    98 <TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_93_o_Mux_287_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
    99 <TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_105_o_Mux_303_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
    100 <TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_105_o_Mux_303_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
    101 <TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_44_o_Mux_211_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
    102 <TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_66_o_Mux_251_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
    103 <TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_66_o_Mux_251_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
    104 <TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_90_o_Mux_283_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
    105 <TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_90_o_Mux_283_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
    106 <TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_108_o_Mux_307_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
    107 <TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_102_o_Mux_299_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
    108 <TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_102_o_Mux_299_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
    109 <TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_291_o_Mux_61_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
    110 <TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_291_o_Mux_61_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
    111 <TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_299_o_Mux_77_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
    112 <TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_299_o_Mux_77_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
    113 <TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_69_o_Mux_255_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
    114 <TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_69_o_Mux_255_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
    115 <TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_84_o_Mux_275_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
    116 <TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_84_o_Mux_275_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
    117 <TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_39_o_Mux_201_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
    118 <TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_81_o_Mux_271_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
    119 <TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_81_o_Mux_271_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
    120 <TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_124_o_Mux_339_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
    121 <TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_124_o_Mux_339_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
    122 <TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_432_o_Mux_383_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
    123 <TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_432_o_Mux_383_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
    124 <TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_164_o_Mux_419_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
    125 <TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_164_o_Mux_419_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
    126 <TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_60_o_Mux_243_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
    127 <TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_60_o_Mux_243_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
    128 <TR ALIGN=LEFT BGCOLOR='#FFFF99'><TD><B>Place and Route Warnings</B></TD><TD COLSPAN='2'><B>New</B></TD></TR>
    129 <TR ALIGN=LEFT><TD>WARNING:Par:288: - The signal uut/connect_core[2].hardmpi/Instruction_Fifo2/fifo_RAM_64/Mram_RAM1_RAMD_O has no load. PAR will not attempt to route this signal.</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
    130 <TR ALIGN=LEFT><TD>WARNING:Par:288: - The signal uut/connect_core[2].hardmpi/Instruction_Fifo2/fifo_RAM_64/Mram_RAM2_RAMD_O has no load. PAR will not attempt to route this signal.</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
    131 <TR ALIGN=LEFT><TD>WARNING:Par:288: - The signal uut/connect_core[2].hardmpi/Instruction_Fifo1/fifo_RAM_64/Mram_RAM2_RAMD_O has no load. PAR will not attempt to route this signal.</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
    132 <TR ALIGN=LEFT><TD>WARNING:Par:288: - The signal uut/connect_core[2].hardmpi/Instruction_Fifo1/fifo_RAM_64/Mram_RAM1_RAMD_O has no load. PAR will not attempt to route this signal.</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
    133 <TR ALIGN=LEFT><TD>WARNING:Par:288: - The signal uut/connect_core[1].hardmpi/Instruction_Fifo2/fifo_RAM_64/Mram_RAM2_RAMD_O has no load. PAR will not attempt to route this signal.</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
    134 <TR ALIGN=LEFT><TD>WARNING:Par:288: - The signal uut/connect_core[1].hardmpi/Instruction_Fifo1/fifo_RAM_64/Mram_RAM1_RAMD_O has no load. PAR will not attempt to route this signal.</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
    135 <TR ALIGN=LEFT><TD>WARNING:Par:288: - The signal uut/connect_core[1].hardmpi/Instruction_Fifo2/fifo_RAM_64/Mram_RAM1_RAMD_O has no load. PAR will not attempt to route this signal.</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
    136 <TR ALIGN=LEFT><TD>WARNING:Par:288: - The signal uut/connect_core[1].hardmpi/Instruction_Fifo1/fifo_RAM_64/Mram_RAM2_RAMD_O has no load. PAR will not attempt to route this signal.</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
    137 <TR ALIGN=LEFT><TD>WARNING:ParHelpers:361: - There are 8 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
    138 <TR ALIGN=LEFT><TD>WARNING:Par:283: - There are 8 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
     53<TR ALIGN=LEFT BGCOLOR='#FFFF99'><TD COLSPAN='3'><B>No Warnings Found</B></TD></TR>
    13954</TABLE>
    14055
    14156
    14257
    143 &nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
    144 <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='5'><B>Device Utilization Summary</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DeviceUtilizationSummary"><B>[-]</B></a></TD></TR>
    145 <TR ALIGN=CENTER BGCOLOR='#FFFF99'>
    146 <TD ALIGN=LEFT><B>Slice Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD><B>Utilization</B></TD><TD COLSPAN='2'><B>Note(s)</B></TD>
    147 </TR>
    148 <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice Registers</TD>
    149 <TD ALIGN=RIGHT>1,515</TD>
    150 <TD ALIGN=RIGHT>126,576</TD>
    151 <TD ALIGN=RIGHT>1%</TD>
    152 <TD COLSPAN='2'>&nbsp;</TD>
    153 </TR>
    154 <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as Flip Flops</TD>
    155 <TD ALIGN=RIGHT>1,137</TD>
    156 <TD>&nbsp;</TD>
    157 <TD>&nbsp;</TD>
    158 <TD COLSPAN='2'>&nbsp;</TD>
    159 </TR>
    160 <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as Latches</TD>
    161 <TD ALIGN=RIGHT>378</TD>
    162 <TD>&nbsp;</TD>
    163 <TD>&nbsp;</TD>
    164 <TD COLSPAN='2'>&nbsp;</TD>
    165 </TR>
    166 <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as Latch-thrus</TD>
    167 <TD ALIGN=RIGHT>0</TD>
    168 <TD>&nbsp;</TD>
    169 <TD>&nbsp;</TD>
    170 <TD COLSPAN='2'>&nbsp;</TD>
    171 </TR>
    172 <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as AND/OR logics</TD>
    173 <TD ALIGN=RIGHT>0</TD>
    174 <TD>&nbsp;</TD>
    175 <TD>&nbsp;</TD>
    176 <TD COLSPAN='2'>&nbsp;</TD>
    177 </TR>
    178 <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice LUTs</TD>
    179 <TD ALIGN=RIGHT>3,025</TD>
    180 <TD ALIGN=RIGHT>63,288</TD>
    181 <TD ALIGN=RIGHT>4%</TD>
    182 <TD COLSPAN='2'>&nbsp;</TD>
    183 </TR>
    184 <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as logic</TD>
    185 <TD ALIGN=RIGHT>2,942</TD>
    186 <TD ALIGN=RIGHT>63,288</TD>
    187 <TD ALIGN=RIGHT>4%</TD>
    188 <TD COLSPAN='2'>&nbsp;</TD>
    189 </TR>
    190 <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O6 output only</TD>
    191 <TD ALIGN=RIGHT>2,058</TD>
    192 <TD>&nbsp;</TD>
    193 <TD>&nbsp;</TD>
    194 <TD COLSPAN='2'>&nbsp;</TD>
    195 </TR>
    196 <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O5 output only</TD>
    197 <TD ALIGN=RIGHT>294</TD>
    198 <TD>&nbsp;</TD>
    199 <TD>&nbsp;</TD>
    200 <TD COLSPAN='2'>&nbsp;</TD>
    201 </TR>
    202 <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O5 and O6</TD>
    203 <TD ALIGN=RIGHT>590</TD>
    204 <TD>&nbsp;</TD>
    205 <TD>&nbsp;</TD>
    206 <TD COLSPAN='2'>&nbsp;</TD>
    207 </TR>
    208 <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number used as ROM</TD>
    209 <TD ALIGN=RIGHT>0</TD>
    210 <TD>&nbsp;</TD>
    211 <TD>&nbsp;</TD>
    212 <TD COLSPAN='2'>&nbsp;</TD>
    213 </TR>
    214 <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as Memory</TD>
    215 <TD ALIGN=RIGHT>48</TD>
    216 <TD ALIGN=RIGHT>15,616</TD>
    217 <TD ALIGN=RIGHT>1%</TD>
    218 <TD COLSPAN='2'>&nbsp;</TD>
    219 </TR>
    220 <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number used as Dual Port RAM</TD>
    221 <TD ALIGN=RIGHT>48</TD>
    222 <TD>&nbsp;</TD>
    223 <TD>&nbsp;</TD>
    224 <TD COLSPAN='2'>&nbsp;</TD>
    225 </TR>
    226 <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O6 output only</TD>
    227 <TD ALIGN=RIGHT>48</TD>
    228 <TD>&nbsp;</TD>
    229 <TD>&nbsp;</TD>
    230 <TD COLSPAN='2'>&nbsp;</TD>
    231 </TR>
    232 <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O5 output only</TD>
    233 <TD ALIGN=RIGHT>0</TD>
    234 <TD>&nbsp;</TD>
    235 <TD>&nbsp;</TD>
    236 <TD COLSPAN='2'>&nbsp;</TD>
    237 </TR>
    238 <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O5 and O6</TD>
    239 <TD ALIGN=RIGHT>0</TD>
    240 <TD>&nbsp;</TD>
    241 <TD>&nbsp;</TD>
    242 <TD COLSPAN='2'>&nbsp;</TD>
    243 </TR>
    244 <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number used as Single Port RAM</TD>
    245 <TD ALIGN=RIGHT>0</TD>
    246 <TD>&nbsp;</TD>
    247 <TD>&nbsp;</TD>
    248 <TD COLSPAN='2'>&nbsp;</TD>
    249 </TR>
    250 <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number used as Shift Register</TD>
    251 <TD ALIGN=RIGHT>0</TD>
    252 <TD>&nbsp;</TD>
    253 <TD>&nbsp;</TD>
    254 <TD COLSPAN='2'>&nbsp;</TD>
    255 </TR>
    256 <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used exclusively as route-thrus</TD>
    257 <TD ALIGN=RIGHT>35</TD>
    258 <TD>&nbsp;</TD>
    259 <TD>&nbsp;</TD>
    260 <TD COLSPAN='2'>&nbsp;</TD>
    261 </TR>
    262 <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number with same-slice register load</TD>
    263 <TD ALIGN=RIGHT>7</TD>
    264 <TD>&nbsp;</TD>
    265 <TD>&nbsp;</TD>
    266 <TD COLSPAN='2'>&nbsp;</TD>
    267 </TR>
    268 <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number with same-slice carry load</TD>
    269 <TD ALIGN=RIGHT>28</TD>
    270 <TD>&nbsp;</TD>
    271 <TD>&nbsp;</TD>
    272 <TD COLSPAN='2'>&nbsp;</TD>
    273 </TR>
    274 <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number with other load</TD>
    275 <TD ALIGN=RIGHT>0</TD>
    276 <TD>&nbsp;</TD>
    277 <TD>&nbsp;</TD>
    278 <TD COLSPAN='2'>&nbsp;</TD>
    279 </TR>
    280 <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of occupied Slices</TD>
    281 <TD ALIGN=RIGHT>1,099</TD>
    282 <TD ALIGN=RIGHT>15,822</TD>
    283 <TD ALIGN=RIGHT>6%</TD>
    284 <TD COLSPAN='2'>&nbsp;</TD>
    285 </TR>
    286 <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of LUT Flip Flop pairs used</TD>
    287 <TD ALIGN=RIGHT>3,230</TD>
    288 <TD>&nbsp;</TD>
    289 <TD>&nbsp;</TD>
    290 <TD COLSPAN='2'>&nbsp;</TD>
    291 </TR>
    292 <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number with an unused Flip Flop</TD>
    293 <TD ALIGN=RIGHT>1,806</TD>
    294 <TD ALIGN=RIGHT>3,230</TD>
    295 <TD ALIGN=RIGHT>55%</TD>
    296 <TD COLSPAN='2'>&nbsp;</TD>
    297 </TR>
    298 <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number with an unused LUT</TD>
    299 <TD ALIGN=RIGHT>205</TD>
    300 <TD ALIGN=RIGHT>3,230</TD>
    301 <TD ALIGN=RIGHT>6%</TD>
    302 <TD COLSPAN='2'>&nbsp;</TD>
    303 </TR>
    304 <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of fully used LUT-FF pairs</TD>
    305 <TD ALIGN=RIGHT>1,219</TD>
    306 <TD ALIGN=RIGHT>3,230</TD>
    307 <TD ALIGN=RIGHT>37%</TD>
    308 <TD COLSPAN='2'>&nbsp;</TD>
    309 </TR>
    310 <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of unique control sets</TD>
    311 <TD ALIGN=RIGHT>226</TD>
    312 <TD>&nbsp;</TD>
    313 <TD>&nbsp;</TD>
    314 <TD COLSPAN='2'>&nbsp;</TD>
    315 </TR>
    316 <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of slice register sites lost<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;to control set restrictions</TD>
    317 <TD ALIGN=RIGHT>749</TD>
    318 <TD ALIGN=RIGHT>126,576</TD>
    319 <TD ALIGN=RIGHT>1%</TD>
    320 <TD COLSPAN='2'>&nbsp;</TD>
    321 </TR>
    322 <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded <A HREF_DISABLED='C:/Core MPI/CORE_MPI\MultiMPITest_map.xrpt?&DataKey=IOBProperties'>IOBs</A></TD>
    323 <TD ALIGN=RIGHT>10</TD>
    324 <TD ALIGN=RIGHT>326</TD>
    325 <TD ALIGN=RIGHT>3%</TD>
    326 <TD COLSPAN='2'>&nbsp;</TD>
    327 </TR>
    328 <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of RAMB16BWERs</TD>
    329 <TD ALIGN=RIGHT>64</TD>
    330 <TD ALIGN=RIGHT>268</TD>
    331 <TD ALIGN=RIGHT>23%</TD>
    332 <TD COLSPAN='2'>&nbsp;</TD>
    333 </TR>
    334 <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of RAMB8BWERs</TD>
    335 <TD ALIGN=RIGHT>4</TD>
    336 <TD ALIGN=RIGHT>536</TD>
    337 <TD ALIGN=RIGHT>1%</TD>
    338 <TD COLSPAN='2'>&nbsp;</TD>
    339 </TR>
    340 <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFIO2/BUFIO2_2CLKs</TD>
    341 <TD ALIGN=RIGHT>0</TD>
    342 <TD ALIGN=RIGHT>32</TD>
    343 <TD ALIGN=RIGHT>0%</TD>
    344 <TD COLSPAN='2'>&nbsp;</TD>
    345 </TR>
    346 <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFIO2FB/BUFIO2FB_2CLKs</TD>
    347 <TD ALIGN=RIGHT>0</TD>
    348 <TD ALIGN=RIGHT>32</TD>
    349 <TD ALIGN=RIGHT>0%</TD>
    350 <TD COLSPAN='2'>&nbsp;</TD>
    351 </TR>
    352 <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFG/BUFGMUXs</TD>
    353 <TD ALIGN=RIGHT>3</TD>
    354 <TD ALIGN=RIGHT>16</TD>
    355 <TD ALIGN=RIGHT>18%</TD>
    356 <TD COLSPAN='2'>&nbsp;</TD>
    357 </TR>
    358 <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as BUFGs</TD>
    359 <TD ALIGN=RIGHT>3</TD>
    360 <TD>&nbsp;</TD>
    361 <TD>&nbsp;</TD>
    362 <TD COLSPAN='2'>&nbsp;</TD>
    363 </TR>
    364 <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as BUFGMUX</TD>
    365 <TD ALIGN=RIGHT>0</TD>
    366 <TD>&nbsp;</TD>
    367 <TD>&nbsp;</TD>
    368 <TD COLSPAN='2'>&nbsp;</TD>
    369 </TR>
    370 <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of DCM/DCM_CLKGENs</TD>
    371 <TD ALIGN=RIGHT>0</TD>
    372 <TD ALIGN=RIGHT>12</TD>
    373 <TD ALIGN=RIGHT>0%</TD>
    374 <TD COLSPAN='2'>&nbsp;</TD>
    375 </TR>
    376 <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of ILOGIC2/ISERDES2s</TD>
    377 <TD ALIGN=RIGHT>0</TD>
    378 <TD ALIGN=RIGHT>506</TD>
    379 <TD ALIGN=RIGHT>0%</TD>
    380 <TD COLSPAN='2'>&nbsp;</TD>
    381 </TR>
    382 <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of IODELAY2/IODRP2/IODRP2_MCBs</TD>
    383 <TD ALIGN=RIGHT>0</TD>
    384 <TD ALIGN=RIGHT>506</TD>
    385 <TD ALIGN=RIGHT>0%</TD>
    386 <TD COLSPAN='2'>&nbsp;</TD>
    387 </TR>
    388 <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of OLOGIC2/OSERDES2s</TD>
    389 <TD ALIGN=RIGHT>0</TD>
    390 <TD ALIGN=RIGHT>506</TD>
    391 <TD ALIGN=RIGHT>0%</TD>
    392 <TD COLSPAN='2'>&nbsp;</TD>
    393 </TR>
    394 <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BSCANs</TD>
    395 <TD ALIGN=RIGHT>0</TD>
    396 <TD ALIGN=RIGHT>4</TD>
    397 <TD ALIGN=RIGHT>0%</TD>
    398 <TD COLSPAN='2'>&nbsp;</TD>
    399 </TR>
    400 <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFHs</TD>
    401 <TD ALIGN=RIGHT>0</TD>
    402 <TD ALIGN=RIGHT>384</TD>
    403 <TD ALIGN=RIGHT>0%</TD>
    404 <TD COLSPAN='2'>&nbsp;</TD>
    405 </TR>
    406 <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFPLLs</TD>
    407 <TD ALIGN=RIGHT>0</TD>
    408 <TD ALIGN=RIGHT>8</TD>
    409 <TD ALIGN=RIGHT>0%</TD>
    410 <TD COLSPAN='2'>&nbsp;</TD>
    411 </TR>
    412 <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFPLL_MCBs</TD>
    413 <TD ALIGN=RIGHT>0</TD>
    414 <TD ALIGN=RIGHT>4</TD>
    415 <TD ALIGN=RIGHT>0%</TD>
    416 <TD COLSPAN='2'>&nbsp;</TD>
    417 </TR>
    418 <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of DSP48A1s</TD>
    419 <TD ALIGN=RIGHT>0</TD>
    420 <TD ALIGN=RIGHT>180</TD>
    421 <TD ALIGN=RIGHT>0%</TD>
    422 <TD COLSPAN='2'>&nbsp;</TD>
    423 </TR>
    424 <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of ICAPs</TD>
    425 <TD ALIGN=RIGHT>0</TD>
    426 <TD ALIGN=RIGHT>1</TD>
    427 <TD ALIGN=RIGHT>0%</TD>
    428 <TD COLSPAN='2'>&nbsp;</TD>
    429 </TR>
    430 <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of MCBs</TD>
    431 <TD ALIGN=RIGHT>0</TD>
    432 <TD ALIGN=RIGHT>4</TD>
    433 <TD ALIGN=RIGHT>0%</TD>
    434 <TD COLSPAN='2'>&nbsp;</TD>
    435 </TR>
    436 <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PCILOGICSEs</TD>
    437 <TD ALIGN=RIGHT>0</TD>
    438 <TD ALIGN=RIGHT>2</TD>
    439 <TD ALIGN=RIGHT>0%</TD>
    440 <TD COLSPAN='2'>&nbsp;</TD>
    441 </TR>
    442 <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PLL_ADVs</TD>
    443 <TD ALIGN=RIGHT>0</TD>
    444 <TD ALIGN=RIGHT>6</TD>
    445 <TD ALIGN=RIGHT>0%</TD>
    446 <TD COLSPAN='2'>&nbsp;</TD>
    447 </TR>
    448 <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PMVs</TD>
    449 <TD ALIGN=RIGHT>0</TD>
    450 <TD ALIGN=RIGHT>1</TD>
    451 <TD ALIGN=RIGHT>0%</TD>
    452 <TD COLSPAN='2'>&nbsp;</TD>
    453 </TR>
    454 <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of STARTUPs</TD>
    455 <TD ALIGN=RIGHT>0</TD>
    456 <TD ALIGN=RIGHT>1</TD>
    457 <TD ALIGN=RIGHT>0%</TD>
    458 <TD COLSPAN='2'>&nbsp;</TD>
    459 </TR>
    460 <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of SUSPEND_SYNCs</TD>
    461 <TD ALIGN=RIGHT>0</TD>
    462 <TD ALIGN=RIGHT>1</TD>
    463 <TD ALIGN=RIGHT>0%</TD>
    464 <TD COLSPAN='2'>&nbsp;</TD>
    465 </TR>
    466 <TR ALIGN=RIGHT><TD ALIGN=LEFT>Average Fanout of Non-Clock Nets</TD>
    467 <TD ALIGN=RIGHT>4.55</TD>
    468 <TD>&nbsp;</TD>
    469 <TD>&nbsp;</TD>
    470 <TD COLSPAN='2'>&nbsp;</TD>
    471 </TR>
    472 </TABLE>
    47358
    47459
    47560
    476 &nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
    477 <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='4'><B>Performance Summary</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=PerformanceSummary"><B>[-]</B></a></TD></TR>
    478 <TR ALIGN=LEFT>
    479 <TD BGCOLOR='#FFFF99'><B>Final Timing Score:</B></TD>
    480 <TD>293 (Setup: 293, Hold: 0)</TD>
    481 <TD BGCOLOR='#FFFF99'><B>Pinout Data:</B></TD>
    482 <TD COLSPAN='2'><A HREF_DISABLED='C:/Core MPI/CORE_MPI\MultiMPITest_par.xrpt?&DataKey=PinoutData'>Pinout Report</A></TD>
    483 </TR>
    484 <TR ALIGN=LEFT>
    485 <TD BGCOLOR='#FFFF99'><B>Routing Results:</B></TD><TD>
    486 <A HREF_DISABLED='C:/Core MPI/CORE_MPI\MultiMPITest.unroutes'>All Signals Completely Routed</A></TD>
    487 <TD BGCOLOR='#FFFF99'><B>Clock Data:</B></TD>
    488 <TD COLSPAN='2'><A HREF_DISABLED='C:/Core MPI/CORE_MPI\MultiMPITest_par.xrpt?&DataKey=ClocksData'>Clock Report</A></TD>
    489 </TR>
    490 <TR ALIGN=LEFT>
    491 <TD BGCOLOR='#FFFF99'><B>Timing Constraints:</B></TD>
    492 <TD>
    493 <font color="red"; face="Arial"><b>X </b></font>
    494 <A HREF_DISABLED='C:/Core MPI/CORE_MPI\MultiMPITest.ptwx?&DataKey=ConstraintsData'>4 Failing Constraints</A></TD>
    495 <TD BGCOLOR='#FFFF99'><B>&nbsp;</B></TD>
    496 <TD COLSPAN='2'>&nbsp;</TD>
    497 </TABLE>
    49861
    49962
    50063
    501 &nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
    502 <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='1'><B>Failing Constraints</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=FailingConstraints"><B>[-]</B></a></TD></TR>
    503 <TR ALIGN=LEFT BGCOLOR='#FFFF99'><TD COLSPAN='2'><B>All Constraints Were Met</B></TD></TR>
    504 </TABLE>
    505 &nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
    506 <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='1'><B>Clock Report</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=ClockReport"><B>[-]</B></a></TD></TR>
    507 <TR ALIGN=LEFT BGCOLOR='#FFFF99'><TD COLSPAN='2'><B>Data Not Yet Available</B></TD></TR>
    508 </TABLE>
     64
     65
     66
     67
    50968&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
    51069<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
    … …  
    51271<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
    51372<TR ALIGN=LEFT><TD>Synthesis Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
    514 <TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\MultiMPITest.bld'>Translation Report</A></TD><TD>Current</TD><TD>Tue 14. Aug 17:08:57 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Core MPI/CORE_MPI\_xmsgs/ngdbuild.xmsgs?&DataKey=Warning'>16 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
    515 <TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\MultiMPITest_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Tue 14. Aug 17:11:06 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Core MPI/CORE_MPI\_xmsgs/map.xmsgs?&DataKey=Warning'>83 Warnings (71 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Core MPI/CORE_MPI\_xmsgs/map.xmsgs?&DataKey=Info'>8 Infos (0 new)</A></TD></TR>
    516 <TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\MultiMPITest.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Tue 14. Aug 17:11:54 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Core MPI/CORE_MPI\_xmsgs/par.xmsgs?&DataKey=Warning'>10 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Core MPI/CORE_MPI\_xmsgs/par.xmsgs?&DataKey=Info'>4 Infos (0 new)</A></TD></TR>
     73<TR ALIGN=LEFT><TD>Translation Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
     74<TR ALIGN=LEFT><TD>Map Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
     75<TR ALIGN=LEFT><TD>Place and Route Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
    51776<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
    518 <TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\MultiMPITest.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Tue 14. Aug 17:12:09 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Core MPI/CORE_MPI\_xmsgs/trce.xmsgs?&DataKey=Info'>3 Infos (0 new)</A></TD></TR>
     77<TR ALIGN=LEFT><TD>Post-PAR Static Timing Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
    51978<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
    52079</TABLE>
    … …  
    52281<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
    52382<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
    524 <TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\isim.log'>ISIM Simulator Log</A></TD><TD>Current</TD><TD COLSPAN='2'>Fri 16. Nov 14:35:18 2012</TD></TR>
    525 <TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\usage_statistics_webtalk.html'>WebTalk Report</A></TD><TD>Current</TD><TD COLSPAN='2'>Fri 17. Aug 16:33:25 2012</TD></TR>
    526 <TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\webtalk.log'>WebTalk Log File</A></TD><TD>Current</TD><TD COLSPAN='2'>Fri 17. Aug 16:33:28 2012</TD></TR>
     83<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\isim.log'>ISIM Simulator Log</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Tue 27. Nov 11:49:23 2012</TD></TR>
     84<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\usage_statistics_webtalk.html'>WebTalk Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Fri 17. Aug 16:33:25 2012</TD></TR>
     85<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\webtalk.log'>WebTalk Log File</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Fri 17. Aug 16:33:28 2012</TD></TR>
    52786</TABLE>
    52887
    52988
    530 <br><center><b>Date Generated:</b> 11/19/2012 - 14:25:38</center>
     89<br><center><b>Date Generated:</b> 11/29/2012 - 18:13:05</center>
    53190</BODY></HTML>

  • PROJECT_CORE_MPI/CORE_MPI/TRUNK/iseconfig/MPI_CORE_COMPONENTS.projectmgr

    r15 r18  
    164164      </ClosedNodes>
    165165      <SelectedItems>
    166          <SelectedItem>C:\Core MPI\CORE_MPI\DMA_ARBITER.vhd</SelectedItem>
    167       </SelectedItems>
    168       <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
     166         <SelectedItem>C:\Core MPI\SWITCH_GENERIC_16_16\CoreTypes.vhd</SelectedItem>
     167      </SelectedItems>
     168      <ScrollbarPosition orientation="vertical" >17</ScrollbarPosition>
    169169      <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
    170170      <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000000000000010000000000000000000000000000000000000307000000040101000100000000000000000000000064ffffffff000000810000000000000004000001f90000000100000000000000440000000100000000000000660000000100000000000000640000000100000000</ViewHeaderState>
    171171      <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
    172       <CurrentItem>C:\Core MPI\CORE_MPI\DMA_ARBITER.vhd</CurrentItem>
     172      <CurrentItem>C:\Core MPI\SWITCH_GENERIC_16_16\CoreTypes.vhd</CurrentItem>
    173173   </ItemView>
    174174   <ItemView guiview="Library" >
    … …  
    243243      </ClosedNodes>
    244244      <SelectedItems>
    245          <SelectedItem>MultiMPITest - behavior (C:/Core MPI/CORE_MPI/MultiMPITest.vhd)</SelectedItem>
     245         <SelectedItem>xc6slx100-3fgg484</SelectedItem>
    246246      </SelectedItems>
    247247      <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
    … …  
    249249      <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000002c1000000020000000000000000000000000000000064ffffffff000000810000000000000002000002c10000000100000000000000000000000100000000</ViewHeaderState>
    250250      <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
    251       <CurrentItem>MultiMPITest - behavior (C:/Core MPI/CORE_MPI/MultiMPITest.vhd)</CurrentItem>
     251      <CurrentItem>xc6slx100-3fgg484</CurrentItem>
    252252   </ItemView>
    253253   <ItemView engineview="BehavioralSim" sourcetype="" guiview="Process" >
    … …  
    257257      </ClosedNodes>
    258258      <SelectedItems>
    259          <SelectedItem>Compile HDL Simulation Libraries</SelectedItem>
     259         <SelectedItem></SelectedItem>
    260260      </SelectedItems>
    261261      <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
    … …  
    263263      <ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000010000000000000000000000000000000000000000000000010d000000010000000100000000000000000000000064ffffffff0000008100000000000000010000010d0000000100000000</ViewHeaderState>
    264264      <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
    265       <CurrentItem>Compile HDL Simulation Libraries</CurrentItem>
     265      <CurrentItem></CurrentItem>
    266266   </ItemView>
    267267   <ItemView engineview="BehavioralSim" sourcetype="DESUT_VHDL_ARCHITECTURE" guiview="Process" >

  • PROJECT_CORE_MPI/CORE_MPI/TRUNK/iseconfig/MultiMPITest.xreport

    r15 r18  
    22<report-views version="2.0" >
    33 <header>
    4   <DateModified>2012-11-19T10:27:50</DateModified>
     4  <DateModified>2012-11-29T18:13:05</DateModified>
    55  <ModuleName>MultiMPITest</ModuleName>
    66  <SummaryTimeStamp>2012-11-05T16:48:15</SummaryTimeStamp>
Note: See TracChangeset for help on using the changeset viewer.