- Timestamp:
- Feb 12, 2009, 12:55:06 PM (15 years ago)
- Location:
- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end
- Files:
-
- 1 added
- 43 edited
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Context_State/include/Types.h (modified) (2 diffs)
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Context_State/src/Context_State_genMoore.cpp (modified) (2 diffs)
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Context_State/src/Context_State_transition.cpp (modified) (8 diffs)
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Decod_unit/Decod/SelfTest/src/test.cpp (modified) (3 diffs)
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Decod_unit/Decod/include/Decod.h (modified) (1 diff)
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Decod_unit/Decod/src/Decod_allocation.cpp (modified) (1 diff)
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Decod_unit/Decod/src/Decod_deallocation.cpp (modified) (1 diff)
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Decod_unit/Decod/src/Decod_genMealy.cpp (modified) (5 diffs)
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Decod_unit/Decod_queue/SelfTest/src/test.cpp (modified) (6 diffs)
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Decod_unit/Decod_queue/include/Decod_queue.h (modified) (3 diffs)
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Decod_unit/Decod_queue/include/Types.h (modified) (3 diffs)
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Decod_unit/Decod_queue/src/Decod_queue_allocation.cpp (modified) (2 diffs)
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Decod_unit/Decod_queue/src/Decod_queue_deallocation.cpp (modified) (2 diffs)
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Decod_unit/Decod_queue/src/Decod_queue_genMealy_decod_out.cpp (modified) (1 diff)
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Decod_unit/Decod_queue/src/Decod_queue_genMoore.cpp (modified) (1 diff)
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Decod_unit/Decod_queue/src/Decod_queue_transition.cpp (modified) (7 diffs)
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Decod_unit/SelfTest/src/test.cpp (modified) (3 diffs)
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Decod_unit/include/Decod_unit.h (modified) (1 diff)
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Decod_unit/src/Decod_unit_allocation.cpp (modified) (4 diffs)
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Decod_unit/src/Decod_unit_deallocation.cpp (modified) (1 diff)
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Front_end_Glue/SelfTest/config-context_1-decod_unit_1.cfg (modified) (1 diff)
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Front_end_Glue/SelfTest/config-context_4-decod_unit_1.cfg (modified) (1 diff)
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Front_end_Glue/SelfTest/config-context_4-decod_unit_2-a.cfg (modified) (1 diff)
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Front_end_Glue/SelfTest/config-context_4-decod_unit_2-b.cfg (modified) (1 diff)
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Front_end_Glue/SelfTest/config-context_4-decod_unit_4.cfg (modified) (1 diff)
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Front_end_Glue/SelfTest/config-min.cfg (modified) (1 diff)
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Front_end_Glue/SelfTest/src/main.cpp (modified) (4 diffs)
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Front_end_Glue/SelfTest/src/test.cpp (modified) (3 diffs)
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Front_end_Glue/include/Front_end_Glue.h (modified) (2 diffs)
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Front_end_Glue/include/Parameters.h (modified) (1 diff)
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Front_end_Glue/src/Front_end_Glue.cpp (modified) (1 diff)
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Front_end_Glue/src/Front_end_Glue_allocation.cpp (modified) (1 diff)
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Front_end_Glue/src/Front_end_Glue_deallocation.cpp (modified) (1 diff)
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Front_end_Glue/src/Front_end_Glue_genMealy_nb_inst.cpp (added)
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Front_end_Glue/src/Parameters.cpp (modified) (2 diffs)
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Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/src/Branch_Target_Buffer_Glue_genMealy_predict.cpp (modified) (4 diffs)
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Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_genMealy_predict.cpp (modified) (1 diff)
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Prediction_unit/Branch_Target_Buffer/src/Branch_Target_Buffer_allocation.cpp (modified) (1 diff)
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Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_transition.cpp (modified) (12 diffs)
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SelfTest/src/test.cpp (modified) (6 diffs)
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include/Front_end.h (modified) (2 diffs)
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src/Front_end_allocation.cpp (modified) (8 diffs)
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src/Front_end_deallocation.cpp (modified) (2 diffs)
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src/Parameters.cpp (modified) (3 diffs)
Legend:
- Unmodified
- Added
- Removed
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trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Types.h
r105 r108 33 33 CONTEXT_STATE_KO_MISS_LOAD_ADDR , // update address manager 34 34 CONTEXT_STATE_KO_MISS_LOAD_WAITEND , // wait end of event (miss load)) 35 CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_ADDR , // update address manager 36 CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_WAITEND, // wait end of event (miss branch) 35 37 // CONTEXT_STATE_KO_MSYNC , // wait completion of all memory operation 36 38 // CONTEXT_STATE_KO_MSYNC_ISSUE , // issue msync operation … … 64 66 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MISS_BRANCH_ADDR : return "context_state_ko_miss_branch_addr" ; break; 65 67 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MISS_BRANCH_WAITEND : return "context_state_ko_miss_branch_waitend"; break; 68 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_ADDR : return "context_state_ko_miss_branch_and_load_addr" ; break; 69 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_WAITEND : return "context_state_ko_miss_branch_and_load_waitend"; break; 66 70 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MISS_LOAD_ADDR : return "context_state_ko_miss_load_addr" ; break; 67 71 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MISS_LOAD_WAITEND : return "context_state_ko_miss_load_waitend" ; break; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_genMoore.cpp
r105 r108 33 33 Tcontrol_t val = ((state == CONTEXT_STATE_KO_EXCEP_ADDR ) or 34 34 (state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR) or 35 (state == CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_ADDR) or 35 36 (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR ) or 36 37 (state == CONTEXT_STATE_KO_PSYNC_ADDR ) or … … 53 54 { 54 55 case CONTEXT_STATE_KO_EXCEP_ADDR : (type = EVENT_TYPE_EXCEPTION ); break; 56 case CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_ADDR: 55 57 case CONTEXT_STATE_KO_MISS_BRANCH_ADDR: (type = EVENT_TYPE_BRANCH_MISS_SPECULATION); break; 56 58 case CONTEXT_STATE_KO_MISS_LOAD_ADDR : (type = EVENT_TYPE_LOAD_MISS_SPECULATION ); break; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_transition.cpp
r106 r108 82 82 break; 83 83 } 84 case CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_WAITEND : 85 { 86 // Wait end of all instruction 87 if (inst_all == 0) 88 89 // state = CONTEXT_STATE_OK; // @@@ TODO : make MISS fast (miss decod) 90 state = CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_ADDR; 91 break; 92 } 84 93 case CONTEXT_STATE_KO_EXCEP_SPR : 85 94 { … … 93 102 } 94 103 case CONTEXT_STATE_KO_MISS_LOAD_ADDR : 104 { 105 // nothing, wait the update of internal register (pc) 106 break; 107 } 108 case CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_ADDR : 95 109 { 96 110 // nothing, wait the update of internal register (pc) … … 209 223 210 224 // priority : miss > excep > spr/sync 211 uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR ) or 212 (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR ) or 213 (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND) or 214 (state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND ))?2:((state == EVENT_TYPE_EXCEPTION)?1:0); 225 uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR ) or 226 (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR ) or 227 (state == CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_ADDR ) or 228 (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND ) or 229 (state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND ) or 230 (state == CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_WAITEND))?2:((state == EVENT_TYPE_EXCEPTION)?1:0); 215 231 uint8_t priority1 = 2; // miss 216 232 … … 272 288 273 289 // miss > excep > spr/sync 274 uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR ) or 275 (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR ) or 276 (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND) or 277 (state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND ))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0); 290 uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR ) or 291 (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR ) or 292 (state == CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_ADDR ) or 293 (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND ) or 294 (state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND ) or 295 (state == CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_WAITEND))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0); 278 296 uint8_t priority1 = (state == EVENT_TYPE_EXCEPTION)?1:0; 279 297 … … 405 423 406 424 // miss > excep > spr/sync 407 uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR ) or 408 (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR ) or 409 (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND) or 410 (state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND ))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0); 425 uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR ) or 426 (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR ) or 427 (state == CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_ADDR ) or 428 (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND ) or 429 (state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND ) or 430 (state == CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_WAITEND))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0); 411 431 uint8_t priority1 = (state == EVENT_TYPE_EXCEPTION)?1:2; // else load_miss_speculation (EVENT_TYPE_MISS_SPECULATION) 412 432 … … 437 457 { 438 458 case EVENT_TYPE_EXCEPTION : {state_next = CONTEXT_STATE_KO_EXCEP; break;} 439 case EVENT_TYPE_LOAD_MISS_SPECULATION : {state_next = CONTEXT_STATE_KO_MISS_LOAD_WAITEND; break;} 459 case EVENT_TYPE_LOAD_MISS_SPECULATION : 460 { 461 // Test if previous branch occure 462 if ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR ) or 463 (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND ) or 464 (state == CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_ADDR ) or 465 (state == CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_WAITEND)) 466 state_next = CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_WAITEND; 467 else 468 state_next = CONTEXT_STATE_KO_MISS_LOAD_WAITEND; 469 break; 470 } 440 471 case EVENT_TYPE_BRANCH_MISS_SPECULATION : 441 472 case EVENT_TYPE_SPR_ACCESS : … … 480 511 } 481 512 case CONTEXT_STATE_KO_MISS_BRANCH_ADDR: 513 482 514 // { 483 515 // reg_STATE [i] = CONTEXT_STATE_KO_MISS_WAITEND; //@@@ TODO : make MISS fast (miss decod) … … 489 521 { 490 522 reg_STATE [i] = CONTEXT_STATE_OK; 523 break; 524 } 525 case CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_ADDR: 526 { 527 reg_STATE [i] = CONTEXT_STATE_KO_MISS_LOAD_ADDR; 491 528 break; 492 529 } -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/src/test.cpp
r105 r108 71 71 ALLOC1_SC_SIGNAL(out_DECOD_NO_EXECUTE ,"out_DECOD_NO_EXECUTE ",Tcontrol_t ,_param->_nb_inst_decod); 72 72 ALLOC1_SC_SIGNAL(out_DECOD_IS_DELAY_SLOT ,"out_DECOD_IS_DELAY_SLOT ",Tcontrol_t ,_param->_nb_inst_decod); 73 #ifdef DEBUG 74 ALLOC1_SC_SIGNAL(out_DECOD_ADDRESS ,"out_DECOD_ADDRESS ",Tgeneral_data_t ,_param->_nb_inst_decod); 75 #endif 73 76 ALLOC1_SC_SIGNAL(out_DECOD_ADDRESS_NEXT ,"out_DECOD_ADDRESS_NEXT ",Tgeneral_data_t ,_param->_nb_inst_decod); 74 77 ALLOC1_SC_SIGNAL(out_DECOD_HAS_IMMEDIAT ,"out_DECOD_HAS_IMMEDIAT ",Tcontrol_t ,_param->_nb_inst_decod); … … 148 151 INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_NO_EXECUTE ,_param->_nb_inst_decod); 149 152 INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_IS_DELAY_SLOT ,_param->_nb_inst_decod); 153 #ifdef DEBUG 154 INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_ADDRESS ,_param->_nb_inst_decod); 155 #endif 150 156 INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_ADDRESS_NEXT ,_param->_nb_inst_decod); 151 157 INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_HAS_IMMEDIAT ,_param->_nb_inst_decod); … … 450 456 delete [] out_DECOD_NO_EXECUTE ; 451 457 delete [] out_DECOD_IS_DELAY_SLOT ; 458 #ifdef DEBUG 459 delete [] out_DECOD_ADDRESS ; 460 #endif 452 461 delete [] out_DECOD_ADDRESS_NEXT ; 453 462 delete [] out_DECOD_HAS_IMMEDIAT ; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/include/Decod.h
r105 r108 88 88 public : SC_OUT(Tcontrol_t ) ** out_DECOD_NO_EXECUTE ;//[nb_inst_decod] 89 89 public : SC_OUT(Tcontrol_t ) ** out_DECOD_IS_DELAY_SLOT ;//[nb_inst_decod] 90 #ifdef DEBUG 91 public : SC_OUT(Tgeneral_data_t ) ** out_DECOD_ADDRESS ;//[nb_inst_decod] 92 #endif 90 93 public : SC_OUT(Tgeneral_data_t ) ** out_DECOD_ADDRESS_NEXT ;//[nb_inst_decod] 91 94 public : SC_OUT(Tcontrol_t ) ** out_DECOD_HAS_IMMEDIAT ;//[nb_inst_decod] -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_allocation.cpp
r105 r108 89 89 ALLOC1_SIGNAL_OUT(out_DECOD_NO_EXECUTE ,"no_execute" ,Tcontrol_t ,1 ); 90 90 ALLOC1_SIGNAL_OUT(out_DECOD_IS_DELAY_SLOT,"is_delay_slot",Tcontrol_t ,1 ); 91 #ifdef DEBUG 92 ALLOC1_SIGNAL_OUT(out_DECOD_ADDRESS ,"address" ,Tgeneral_data_t ,_param->_size_instruction_address ); 93 #endif 91 94 ALLOC1_SIGNAL_OUT(out_DECOD_ADDRESS_NEXT ,"address_next" ,Tgeneral_data_t ,_param->_size_instruction_address ); 92 95 ALLOC1_SIGNAL_OUT(out_DECOD_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t ,1 ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_deallocation.cpp
r105 r108 49 49 DELETE1_SIGNAL(out_DECOD_NO_EXECUTE ,_param->_nb_inst_decod,1 ); 50 50 DELETE1_SIGNAL(out_DECOD_IS_DELAY_SLOT,_param->_nb_inst_decod,1 ); 51 #ifdef DEBUG 52 DELETE1_SIGNAL(out_DECOD_ADDRESS ,_param->_nb_inst_decod,_param->_size_instruction_address ); 53 #endif 51 54 DELETE1_SIGNAL(out_DECOD_ADDRESS_NEXT ,_param->_nb_inst_decod,_param->_size_instruction_address ); 52 55 DELETE1_SIGNAL(out_DECOD_HAS_IMMEDIAT ,_param->_nb_inst_decod,1 ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_genMealy.cpp
r107 r108 43 43 44 44 Tcontrol_t can_continue [_param->_nb_context]; 45 Tcontrol_t can_continue_next [_param->_nb_context]; 45 // Tcontrol_t can_continue_next [_param->_nb_context]; 46 // Tcontrol_t have_decod_branch [_param->_nb_context]; 46 47 47 48 for (uint32_t i=0; i<_param->_nb_context; i++) … … 52 53 53 54 can_continue [i] = PORT_READ(in_CONTEXT_DECOD_ENABLE [i]); 54 can_continue_next [i] = PORT_READ(in_CONTEXT_DECOD_ENABLE [i]); 55 // can_continue_next [i] = PORT_READ(in_CONTEXT_DECOD_ENABLE [i]); 56 // have_decod_branch [i] = false; 55 57 } 56 58 … … 79 81 log_printf(TRACE,Decod,FUNCTION," * decod_ack [%d] : %d",i,PORT_READ(in_DECOD_ACK [i])); 80 82 81 can_continue [x] = can_continue_next [x];83 // can_continue [x] = can_continue_next [x]; 82 84 83 85 decod_val [i] = true; // fetch_val and decod_enable … … 139 141 PORT_WRITE(out_DECOD_NO_EXECUTE [i], _decod_instruction->_no_execute ); 140 142 PORT_WRITE(out_DECOD_IS_DELAY_SLOT [i], _decod_instruction->_is_delay_slot ); 141 // PORT_WRITE(out_DECOD_ADDRESS [i], addr); 143 #ifdef DEBUG 144 PORT_WRITE(out_DECOD_ADDRESS [i], addr); 145 #endif 142 146 // if ((type == TYPE_BRANCH) and 143 147 // ((_decod_instruction->_branch_condition = BRANCH_CONDITION_FLAG_SET) or … … 193 197 194 198 //can_continue_next [x] = PORT_READ(in_PREDICT_CAN_CONTINUE [i]); // can continue is set if direction is "not take" (also, continue is sequential order) 195 can_continue_next [x] = false; // one branch per context, the DS don't execute 199 can_continue [x] = false; // one branch per context, the DS don't execute 200 // can_continue_next [x] = false; // one branch per context, the DS don't execute 201 // have_decod_branch [x] = true; 196 202 } 197 203 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/SelfTest/src/test.cpp
r105 r108 60 60 ALLOC1_SC_SIGNAL( in_DECOD_IN_NO_EXECUTE ," in_DECOD_IN_NO_EXECUTE ",Tcontrol_t ,_param->_nb_inst_decod); 61 61 ALLOC1_SC_SIGNAL( in_DECOD_IN_IS_DELAY_SLOT ," in_DECOD_IN_IS_DELAY_SLOT ",Tcontrol_t ,_param->_nb_inst_decod); 62 #ifdef DEBUG 63 ALLOC1_SC_SIGNAL( in_DECOD_IN_ADDRESS ," in_DECOD_IN_ADDRESS ",Tgeneral_data_t ,_param->_nb_inst_decod); 64 #endif 62 65 ALLOC1_SC_SIGNAL( in_DECOD_IN_ADDRESS_NEXT ," in_DECOD_IN_ADDRESS_NEXT ",Tgeneral_data_t ,_param->_nb_inst_decod); 63 66 ALLOC1_SC_SIGNAL( in_DECOD_IN_HAS_IMMEDIAT ," in_DECOD_IN_HAS_IMMEDIAT ",Tcontrol_t ,_param->_nb_inst_decod); … … 84 87 ALLOC1_SC_SIGNAL(out_DECOD_OUT_NO_EXECUTE ,"out_DECOD_OUT_NO_EXECUTE ",Tcontrol_t ,_param->_nb_inst_decod); 85 88 ALLOC1_SC_SIGNAL(out_DECOD_OUT_IS_DELAY_SLOT ,"out_DECOD_OUT_IS_DELAY_SLOT",Tcontrol_t ,_param->_nb_inst_decod); 89 #ifdef DEBUG 90 ALLOC1_SC_SIGNAL(out_DECOD_OUT_ADDRESS ,"out_DECOD_OUT_ADDRESS ",Tgeneral_data_t ,_param->_nb_inst_decod); 91 #endif 86 92 ALLOC1_SC_SIGNAL(out_DECOD_OUT_ADDRESS_NEXT ,"out_DECOD_OUT_ADDRESS_NEXT ",Tgeneral_data_t ,_param->_nb_inst_decod); 87 93 ALLOC1_SC_SIGNAL(out_DECOD_OUT_HAS_IMMEDIAT ,"out_DECOD_OUT_HAS_IMMEDIAT ",Tcontrol_t ,_param->_nb_inst_decod); … … 125 131 INSTANCE1_SC_SIGNAL(_Decod_queue, in_DECOD_IN_NO_EXECUTE ,_param->_nb_inst_decod); 126 132 INSTANCE1_SC_SIGNAL(_Decod_queue, in_DECOD_IN_IS_DELAY_SLOT ,_param->_nb_inst_decod); 133 #ifdef DEBUG 134 INSTANCE1_SC_SIGNAL(_Decod_queue, in_DECOD_IN_ADDRESS ,_param->_nb_inst_decod); 135 #endif 127 136 INSTANCE1_SC_SIGNAL(_Decod_queue, in_DECOD_IN_ADDRESS_NEXT ,_param->_nb_inst_decod); 128 137 INSTANCE1_SC_SIGNAL(_Decod_queue, in_DECOD_IN_HAS_IMMEDIAT ,_param->_nb_inst_decod); … … 151 160 INSTANCE1_SC_SIGNAL(_Decod_queue,out_DECOD_OUT_NO_EXECUTE ,_param->_nb_inst_decod); 152 161 INSTANCE1_SC_SIGNAL(_Decod_queue,out_DECOD_OUT_IS_DELAY_SLOT ,_param->_nb_inst_decod); 162 #ifdef DEBUG 163 INSTANCE1_SC_SIGNAL(_Decod_queue,out_DECOD_OUT_ADDRESS ,_param->_nb_inst_decod); 164 #endif 153 165 INSTANCE1_SC_SIGNAL(_Decod_queue,out_DECOD_OUT_ADDRESS_NEXT ,_param->_nb_inst_decod); 154 166 INSTANCE1_SC_SIGNAL(_Decod_queue,out_DECOD_OUT_HAS_IMMEDIAT ,_param->_nb_inst_decod); … … 304 316 DELETE1_SC_SIGNAL( in_DECOD_IN_NO_EXECUTE ,_param->_nb_inst_decod); 305 317 DELETE1_SC_SIGNAL( in_DECOD_IN_IS_DELAY_SLOT ,_param->_nb_inst_decod); 318 #ifdef DEBUG 319 DELETE1_SC_SIGNAL( in_DECOD_IN_ADDRESS ,_param->_nb_inst_decod); 320 #endif 306 321 DELETE1_SC_SIGNAL( in_DECOD_IN_ADDRESS_NEXT ,_param->_nb_inst_decod); 307 322 DELETE1_SC_SIGNAL( in_DECOD_IN_HAS_IMMEDIAT ,_param->_nb_inst_decod); … … 328 343 DELETE1_SC_SIGNAL(out_DECOD_OUT_NO_EXECUTE ,_param->_nb_inst_decod); 329 344 DELETE1_SC_SIGNAL(out_DECOD_OUT_IS_DELAY_SLOT ,_param->_nb_inst_decod); 345 #ifdef DEBUG 346 DELETE1_SC_SIGNAL(out_DECOD_OUT_ADDRESS ,_param->_nb_inst_decod); 347 #endif 330 348 DELETE1_SC_SIGNAL(out_DECOD_OUT_ADDRESS_NEXT ,_param->_nb_inst_decod); 331 349 DELETE1_SC_SIGNAL(out_DECOD_OUT_HAS_IMMEDIAT ,_param->_nb_inst_decod); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/include/Decod_queue.h
r105 r108 75 75 public : SC_IN (Tcontrol_t ) ** in_DECOD_IN_NO_EXECUTE ;//[nb_inst_decod] 76 76 public : SC_IN (Tcontrol_t ) ** in_DECOD_IN_IS_DELAY_SLOT ;//[nb_inst_decod] 77 #ifdef DEBUG 78 public : SC_IN (Tgeneral_data_t ) ** in_DECOD_IN_ADDRESS ;//[nb_inst_decod] 79 #endif 77 80 public : SC_IN (Tgeneral_data_t ) ** in_DECOD_IN_ADDRESS_NEXT ;//[nb_inst_decod] 78 81 public : SC_IN (Tcontrol_t ) ** in_DECOD_IN_HAS_IMMEDIAT ;//[nb_inst_decod] … … 100 103 public : SC_OUT(Tcontrol_t ) ** out_DECOD_OUT_NO_EXECUTE ;//[nb_inst_decod] 101 104 public : SC_OUT(Tcontrol_t ) ** out_DECOD_OUT_IS_DELAY_SLOT ;//[nb_inst_decod] 105 #ifdef DEBUG 106 public : SC_OUT(Tgeneral_data_t ) ** out_DECOD_OUT_ADDRESS ;//[nb_inst_decod] 107 #endif 102 108 public : SC_OUT(Tgeneral_data_t ) ** out_DECOD_OUT_ADDRESS_NEXT ;//[nb_inst_decod] 103 109 public : SC_OUT(Tcontrol_t ) ** out_DECOD_OUT_HAS_IMMEDIAT ;//[nb_inst_decod] … … 129 135 private : std::list<decod_queue_entry_t*>* reg_QUEUE ; 130 136 private : uint32_t * reg_NB_INST ;//[nb_context] 131 137 private : uint32_t reg_LAST_SLOT ; 138 132 139 // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 133 140 private : Tcontrol_t * internal_DECOD_IN_ACK ;//[nb_inst_decod] -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/include/Types.h
r105 r108 30 30 public : Tcontrol_t * _no_execute ; 31 31 public : Tcontrol_t * _is_delay_slot ; 32 #ifdef DEBUG 33 public : Tgeneral_data_t * _address ; 34 #endif 32 35 public : Tgeneral_data_t * _address_next ; 33 36 public : Tcontrol_t * _has_immediat ; … … 56 59 _no_execute = new Tcontrol_t [_nb_inst]; 57 60 _is_delay_slot = new Tcontrol_t [_nb_inst]; 61 #ifdef DEBUG 62 _address = new Tgeneral_data_t [_nb_inst]; 63 #endif 58 64 _address_next = new Tgeneral_data_t [_nb_inst]; 59 65 _has_immediat = new Tcontrol_t [_nb_inst]; … … 85 91 delete [] _no_execute ; 86 92 delete [] _is_delay_slot ; 93 #ifdef DEBUG 94 delete [] _address ; 95 #endif 87 96 delete [] _address_next ; 88 97 delete [] _has_immediat ; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_allocation.cpp
r105 r108 67 67 ALLOC1_SIGNAL_IN ( in_DECOD_IN_NO_EXECUTE ,"no_execute" ,Tcontrol_t ,1 ); 68 68 ALLOC1_SIGNAL_IN ( in_DECOD_IN_IS_DELAY_SLOT ,"is_delay_slot",Tcontrol_t ,1 ); 69 #ifdef DEBUG 70 ALLOC1_SIGNAL_IN ( in_DECOD_IN_ADDRESS ,"address" ,Tgeneral_data_t ,_param->_size_instruction_address ); 71 #endif 69 72 ALLOC1_SIGNAL_IN ( in_DECOD_IN_ADDRESS_NEXT ,"address_next" ,Tgeneral_data_t ,_param->_size_instruction_address ); 70 73 ALLOC1_SIGNAL_IN ( in_DECOD_IN_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t ,1 ); … … 96 99 ALLOC1_SIGNAL_OUT(out_DECOD_OUT_NO_EXECUTE ,"no_execute" ,Tcontrol_t ,1 ); 97 100 ALLOC1_SIGNAL_OUT(out_DECOD_OUT_IS_DELAY_SLOT ,"is_delay_slot",Tcontrol_t ,1 ); 101 #ifdef DEBUG 102 ALLOC1_SIGNAL_OUT(out_DECOD_OUT_ADDRESS ,"address" ,Tgeneral_data_t ,_param->_size_instruction_address ); 103 #endif 98 104 ALLOC1_SIGNAL_OUT(out_DECOD_OUT_ADDRESS_NEXT ,"address_next" ,Tgeneral_data_t ,_param->_size_instruction_address ); 99 105 ALLOC1_SIGNAL_OUT(out_DECOD_OUT_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t ,1 ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_deallocation.cpp
r105 r108 37 37 DELETE1_SIGNAL( in_DECOD_IN_NO_EXECUTE ,_param->_nb_inst_decod,1 ); 38 38 DELETE1_SIGNAL( in_DECOD_IN_IS_DELAY_SLOT ,_param->_nb_inst_decod,1 ); 39 #ifdef DEBUG 40 DELETE1_SIGNAL( in_DECOD_IN_ADDRESS ,_param->_nb_inst_decod,_param->_size_instruction_address ); 41 #endif 39 42 DELETE1_SIGNAL( in_DECOD_IN_ADDRESS_NEXT ,_param->_nb_inst_decod,_param->_size_instruction_address ); 40 43 DELETE1_SIGNAL( in_DECOD_IN_HAS_IMMEDIAT ,_param->_nb_inst_decod,1 ); … … 61 64 DELETE1_SIGNAL(out_DECOD_OUT_NO_EXECUTE ,_param->_nb_inst_decod,1 ); 62 65 DELETE1_SIGNAL(out_DECOD_OUT_IS_DELAY_SLOT ,_param->_nb_inst_decod,1 ); 66 #ifdef DEBUG 67 DELETE1_SIGNAL(out_DECOD_OUT_ADDRESS ,_param->_nb_inst_decod,_param->_size_instruction_address ); 68 #endif 63 69 DELETE1_SIGNAL(out_DECOD_OUT_ADDRESS_NEXT ,_param->_nb_inst_decod,_param->_size_instruction_address ); 64 70 DELETE1_SIGNAL(out_DECOD_OUT_HAS_IMMEDIAT ,_param->_nb_inst_decod,1 ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_genMealy_decod_out.cpp
r106 r108 35 35 if (not reg_QUEUE->empty()) 36 36 for (uint32_t i=0; i<_param->_nb_inst_decod; i++) 37 if (reg_QUEUE->front()->_val [i]) 38 { 39 log_printf(TRACE,Decod_queue,FUNCTION,_(" * Queue is not empty, slot [%d] is valid."),i); 37 { 38 uint32_t index = reg_LAST_SLOT + i; 40 39 41 Tcontext_t context = reg_QUEUE->front()->_context_id [i]; 42 Tdepth_t depth = reg_QUEUE->front()->_depth [i]; 43 Tdepth_t depth_min = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN [context]):0; 44 Tdepth_t depth_max = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MAX [context]):0; 45 Tcontrol_t depth_full = PORT_READ(in_DEPTH_FULL[context]); 40 // Stop 41 if (index >= _param->_nb_inst_decod) 42 break; 46 43 47 // is a valid instruction ? 48 // If DEPTH_CURRENT : 49 // equal at DEPTH_MIN -> not speculative 50 // not include ]DEPTH_MIN:DEPTH_MAX] -> previous branch miss 51 // include ]DEPTH_MIN:DEPTH_MAX] -> speculative 44 if (reg_QUEUE->front()->_val [index]) 45 { 46 log_printf(TRACE,Decod_queue,FUNCTION,_(" * Queue is not empty, slot [%d] is valid."),i); 47 48 Tcontext_t context = reg_QUEUE->front()->_context_id [index]; 49 Tdepth_t depth = reg_QUEUE->front()->_depth [index]; 50 Tdepth_t depth_min = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN [context]):0; 51 Tdepth_t depth_max = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MAX [context]):0; 52 Tcontrol_t depth_full = PORT_READ(in_DEPTH_FULL[context]); 52 53 53 // All case 54 // ....... min ...X... max ....... OK 55 // ....... min ....... max ...X... KO 56 // ...X... min ....... max ....... KO 57 // ....... max ....... min ...X... OK 58 // ...X... max ....... min ....... OK 59 // ....... max ...X... min ....... KO 54 // is a valid instruction ? 55 // If DEPTH_CURRENT : 56 // equal at DEPTH_MIN -> not speculative 57 // not include ]DEPTH_MIN:DEPTH_MAX] -> previous branch miss 58 // include ]DEPTH_MIN:DEPTH_MAX] -> speculative 59 60 // All case 61 // ....... min ...X... max ....... OK 62 // ....... min ....... max ...X... KO 63 // ...X... min ....... max ....... KO 64 // ....... max ....... min ...X... OK 65 // ...X... max ....... min ....... OK 66 // ....... max ...X... min ....... KO 67 68 Tcontrol_t is_valid = ((depth == depth_min) or 69 depth_full or 70 ((depth_min <= depth_max)? 71 ((depth >= depth_min) and (depth <=depth_max)): 72 ((depth >= depth_min) or (depth <=depth_max)))); 73 //Tcontrol_t is_valid = ((depth == depth_min) or 74 // ((depth_min < depth_max)? 75 // (depth<=depth_max): 76 // ((depth > depth_min) or (depth <= depth_max)))); 77 //Tcontrol_t is_valid = depth <= depth_max; 60 78 61 Tcontrol_t is_valid = ((depth == depth_min) or 62 depth_full or 63 ((depth_min <= depth_max)? 64 ((depth >= depth_min) and (depth <=depth_max)): 65 ((depth >= depth_min) or (depth <=depth_max)))); 66 // Tcontrol_t is_valid = ((depth == depth_min) or 67 // ((depth_min < depth_max)? 68 // (depth<=depth_max): 69 // ((depth > depth_min) or (depth <= depth_max)))); 70 // Tcontrol_t is_valid = depth <= depth_max; 71 72 log_printf(TRACE,Decod_queue,FUNCTION," * is_valid : %d",is_valid); 73 log_printf(TRACE,Decod_queue,FUNCTION," * context : %d",context); 74 log_printf(TRACE,Decod_queue,FUNCTION," * depth : %d",depth); 75 log_printf(TRACE,Decod_queue,FUNCTION," * depth_min : %d",depth_min); 76 log_printf(TRACE,Decod_queue,FUNCTION," * depth_max : %d",depth_max); 77 log_printf(TRACE,Decod_queue,FUNCTION," * depth_full : %d",depth_full); 78 log_printf(TRACE,Decod_queue,FUNCTION," * address_next : 0x%x (0x%x)",reg_QUEUE->front()->_address_next[i],reg_QUEUE->front()->_address_next[i]<<2); 79 internal_DECOD_OUT_VAL [i] = 1; // in all case, val is set (entry is not empty, and instruction is valid) 80 if (is_valid) 81 { 82 val [i] = 1; 83 internal_DECOD_OUT_ACK [i] = PORT_READ(in_DECOD_OUT_ACK [i]); 84 } 85 else 86 { 87 // Consume the instruction (to erase) 88 internal_DECOD_OUT_ACK [i] = 1; 89 } 90 } 79 log_printf(TRACE,Decod_queue,FUNCTION," * is_valid : %d",is_valid); 80 log_printf(TRACE,Decod_queue,FUNCTION," * context : %d",context); 81 log_printf(TRACE,Decod_queue,FUNCTION," * depth : %d",depth); 82 log_printf(TRACE,Decod_queue,FUNCTION," * depth_min : %d",depth_min); 83 log_printf(TRACE,Decod_queue,FUNCTION," * depth_max : %d",depth_max); 84 log_printf(TRACE,Decod_queue,FUNCTION," * depth_full : %d",depth_full); 85 #ifdef DEBUG 86 log_printf(TRACE,Decod_queue,FUNCTION," * address : 0x%x (0x%x)",reg_QUEUE->front()->_address [index],reg_QUEUE->front()->_address [index]<<2); 87 #endif 88 log_printf(TRACE,Decod_queue,FUNCTION," * address_next : 0x%x (0x%x)",reg_QUEUE->front()->_address_next[index],reg_QUEUE->front()->_address_next[index]<<2); 89 internal_DECOD_OUT_VAL [index] = 1; // in all case, val is set (entry is not empty, and instruction is valid) 90 if (is_valid) 91 { 92 val [i] = 1; 93 internal_DECOD_OUT_ACK [index] = PORT_READ(in_DECOD_OUT_ACK [i]); 94 } 95 else 96 { 97 // Consume the instruction (to erase) 98 internal_DECOD_OUT_ACK [index] = 1; 99 } 100 } 101 } 91 102 92 103 for (uint32_t i=0; i<_param->_nb_inst_decod; i++) 93 104 { 94 105 log_printf(TRACE,Decod_queue,FUNCTION," * DECOD_OUT_VAL : %d",val [i]); 95 96 106 107 PORT_WRITE(out_DECOD_OUT_VAL [i],val [i]); 97 108 } 98 109 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_genMoore.cpp
r105 r108 44 44 for (uint32_t i=0; i<_param->_nb_inst_decod; i++) 45 45 { 46 uint32_t index = reg_LAST_SLOT + i; 47 48 // Stop 49 if (index >= _param->_nb_inst_decod) 50 break; 51 46 52 if (_param->_have_port_context_id) 47 PORT_WRITE(out_DECOD_OUT_CONTEXT_ID [i],reg_QUEUE->front()->_context_id [i ]);53 PORT_WRITE(out_DECOD_OUT_CONTEXT_ID [i],reg_QUEUE->front()->_context_id [index]); 48 54 if (_param->_have_port_depth) 49 PORT_WRITE(out_DECOD_OUT_DEPTH [i],reg_QUEUE->front()->_depth [i]); 50 PORT_WRITE(out_DECOD_OUT_TYPE [i],reg_QUEUE->front()->_type [i]); 51 PORT_WRITE(out_DECOD_OUT_OPERATION [i],reg_QUEUE->front()->_operation [i]); 52 PORT_WRITE(out_DECOD_OUT_NO_EXECUTE [i],reg_QUEUE->front()->_no_execute [i]); 53 PORT_WRITE(out_DECOD_OUT_IS_DELAY_SLOT [i],reg_QUEUE->front()->_is_delay_slot [i]); 54 PORT_WRITE(out_DECOD_OUT_ADDRESS_NEXT [i],reg_QUEUE->front()->_address_next [i]); 55 PORT_WRITE(out_DECOD_OUT_HAS_IMMEDIAT [i],reg_QUEUE->front()->_has_immediat [i]); 56 PORT_WRITE(out_DECOD_OUT_IMMEDIAT [i],reg_QUEUE->front()->_immediat [i]); 57 PORT_WRITE(out_DECOD_OUT_READ_RA [i],reg_QUEUE->front()->_read_ra [i]); 58 PORT_WRITE(out_DECOD_OUT_NUM_REG_RA [i],reg_QUEUE->front()->_num_reg_ra [i]); 59 PORT_WRITE(out_DECOD_OUT_READ_RB [i],reg_QUEUE->front()->_read_rb [i]); 60 PORT_WRITE(out_DECOD_OUT_NUM_REG_RB [i],reg_QUEUE->front()->_num_reg_rb [i]); 61 PORT_WRITE(out_DECOD_OUT_READ_RC [i],reg_QUEUE->front()->_read_rc [i]); 62 PORT_WRITE(out_DECOD_OUT_NUM_REG_RC [i],reg_QUEUE->front()->_num_reg_rc [i]); 63 PORT_WRITE(out_DECOD_OUT_WRITE_RD [i],reg_QUEUE->front()->_write_rd [i]); 64 PORT_WRITE(out_DECOD_OUT_NUM_REG_RD [i],reg_QUEUE->front()->_num_reg_rd [i]); 65 PORT_WRITE(out_DECOD_OUT_WRITE_RE [i],reg_QUEUE->front()->_write_re [i]); 66 PORT_WRITE(out_DECOD_OUT_NUM_REG_RE [i],reg_QUEUE->front()->_num_reg_re [i]); 67 PORT_WRITE(out_DECOD_OUT_EXCEPTION_USE [i],reg_QUEUE->front()->_exception_use [i]); 68 PORT_WRITE(out_DECOD_OUT_EXCEPTION [i],reg_QUEUE->front()->_exception [i]); 55 PORT_WRITE(out_DECOD_OUT_DEPTH [i],reg_QUEUE->front()->_depth [index]); 56 PORT_WRITE(out_DECOD_OUT_TYPE [i],reg_QUEUE->front()->_type [index]); 57 PORT_WRITE(out_DECOD_OUT_OPERATION [i],reg_QUEUE->front()->_operation [index]); 58 PORT_WRITE(out_DECOD_OUT_NO_EXECUTE [i],reg_QUEUE->front()->_no_execute [index]); 59 PORT_WRITE(out_DECOD_OUT_IS_DELAY_SLOT [i],reg_QUEUE->front()->_is_delay_slot [index]); 60 #ifdef DEBUG 61 PORT_WRITE(out_DECOD_OUT_ADDRESS [i],reg_QUEUE->front()->_address [index]); 62 #endif 63 PORT_WRITE(out_DECOD_OUT_ADDRESS_NEXT [i],reg_QUEUE->front()->_address_next [index]); 64 PORT_WRITE(out_DECOD_OUT_HAS_IMMEDIAT [i],reg_QUEUE->front()->_has_immediat [index]); 65 PORT_WRITE(out_DECOD_OUT_IMMEDIAT [i],reg_QUEUE->front()->_immediat [index]); 66 PORT_WRITE(out_DECOD_OUT_READ_RA [i],reg_QUEUE->front()->_read_ra [index]); 67 PORT_WRITE(out_DECOD_OUT_NUM_REG_RA [i],reg_QUEUE->front()->_num_reg_ra [index]); 68 PORT_WRITE(out_DECOD_OUT_READ_RB [i],reg_QUEUE->front()->_read_rb [index]); 69 PORT_WRITE(out_DECOD_OUT_NUM_REG_RB [i],reg_QUEUE->front()->_num_reg_rb [index]); 70 PORT_WRITE(out_DECOD_OUT_READ_RC [i],reg_QUEUE->front()->_read_rc [index]); 71 PORT_WRITE(out_DECOD_OUT_NUM_REG_RC [i],reg_QUEUE->front()->_num_reg_rc [index]); 72 PORT_WRITE(out_DECOD_OUT_WRITE_RD [i],reg_QUEUE->front()->_write_rd [index]); 73 PORT_WRITE(out_DECOD_OUT_NUM_REG_RD [i],reg_QUEUE->front()->_num_reg_rd [index]); 74 PORT_WRITE(out_DECOD_OUT_WRITE_RE [i],reg_QUEUE->front()->_write_re [index]); 75 PORT_WRITE(out_DECOD_OUT_NUM_REG_RE [i],reg_QUEUE->front()->_num_reg_re [index]); 76 PORT_WRITE(out_DECOD_OUT_EXCEPTION_USE [i],reg_QUEUE->front()->_exception_use [index]); 77 PORT_WRITE(out_DECOD_OUT_EXCEPTION [i],reg_QUEUE->front()->_exception [index]); 69 78 } 70 79 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_transition.cpp
r105 r108 31 31 for (uint32_t i=0; i<_param->_nb_context; i++) 32 32 reg_NB_INST [i]=0; 33 34 reg_LAST_SLOT = 0; 33 35 } 34 36 else … … 62 64 entry->_no_execute [i] = PORT_READ(in_DECOD_IN_NO_EXECUTE [i]); 63 65 entry->_is_delay_slot [i] = PORT_READ(in_DECOD_IN_IS_DELAY_SLOT [i]); 66 #ifdef DEBUG 67 entry->_address [i] = PORT_READ(in_DECOD_IN_ADDRESS [i]); 68 #endif 64 69 entry->_address_next [i] = PORT_READ(in_DECOD_IN_ADDRESS_NEXT [i]); 65 70 entry->_has_immediat [i] = PORT_READ(in_DECOD_IN_HAS_IMMEDIAT [i]); … … 90 95 if (not reg_QUEUE->empty()) 91 96 { 92 bool find = false;97 bool find = false; 93 98 94 99 for (uint32_t i=0; i<_param->_nb_inst_decod; i++) 95 100 { 96 101 // Test transaction : if ok then invalid slot 102 // In order by rename logic 97 103 if (internal_DECOD_OUT_VAL [i] and internal_DECOD_OUT_ACK[i]) 98 104 { 99 105 log_printf(TRACE,Decod_queue,FUNCTION,_(" * DECOD_OUT [%d]"),i); 100 106 107 #ifdef DEBUG_TEST 108 if (reg_LAST_SLOT != i) 109 throw ERRORMORPHEO(FUNCTION,toString(_("reg_LAST_SLOT (%d) is different at decod_out port (%d)."),reg_LAST_SLOT,i)); 110 #endif 111 reg_LAST_SLOT ++; 112 101 113 reg_QUEUE->front()->_val [i] = 0; 102 114 … … 108 120 } 109 121 // Test if slot is (again) valid, if yes, then have less one instruction in the entry 110 find |= reg_QUEUE->front()->_val [i];122 find |= reg_QUEUE->front()->_val [i]; 111 123 } 112 124 113 // test if can free the entry 114 125 // test if can free the entry : test if have consume all entry 126 if (not find) // no valid instruction in current slot 115 127 { 116 128 log_printf(TRACE,Decod_queue,FUNCTION,_(" * POP queue")); … … 119 131 delete reg_QUEUE->front(); 120 132 reg_QUEUE->pop_front(); 133 134 reg_LAST_SLOT = 0; 121 135 } 122 136 } … … 125 139 #if defined(DEBUG) and defined(DEBUG_Decod_queue) and (DEBUG >= DEBUG_TRACE) 126 140 log_printf(TRACE,Decod_queue,FUNCTION," * Dump decod_queue"); 141 log_printf(TRACE,Decod_queue,FUNCTION," * reg_LAST_SLOT : %d",reg_LAST_SLOT); 127 142 uint32_t x=0; 128 143 for (std::list<decod_queue_entry_t*>::iterator it=reg_QUEUE->begin(); … … 144 159 ,(*it)->_no_execute [i] 145 160 ,(*it)->_is_delay_slot [i] 146 ,(*it)->_address _next[i]147 ,(*it)->_address _next[i]<<2161 ,(*it)->_address [i] 162 ,(*it)->_address [i]<<2 148 163 ,(*it)->_has_immediat [i] 149 164 ,(*it)->_immediat [i] -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/SelfTest/src/test.cpp
r105 r108 73 73 ALLOC1_SC_SIGNAL(out_DECOD_NO_EXECUTE ,"out_DECOD_NO_EXECUTE ",Tcontrol_t ,_param->_nb_inst_decod); 74 74 ALLOC1_SC_SIGNAL(out_DECOD_IS_DELAY_SLOT ,"out_DECOD_IS_DELAY_SLOT ",Tcontrol_t ,_param->_nb_inst_decod); 75 #ifdef DEBUG 76 ALLOC1_SC_SIGNAL(out_DECOD_ADDRESS ,"out_DECOD_ADDRESS ",Tgeneral_data_t ,_param->_nb_inst_decod); 77 #endif 75 78 ALLOC1_SC_SIGNAL(out_DECOD_ADDRESS_NEXT ,"out_DECOD_ADDRESS_NEXT ",Tgeneral_data_t ,_param->_nb_inst_decod); 76 79 ALLOC1_SC_SIGNAL(out_DECOD_HAS_IMMEDIAT ,"out_DECOD_HAS_IMMEDIAT ",Tcontrol_t ,_param->_nb_inst_decod); … … 159 162 INSTANCE1_SC_SIGNAL(_Decod_unit,out_DECOD_NO_EXECUTE ,_param->_nb_inst_decod); 160 163 INSTANCE1_SC_SIGNAL(_Decod_unit,out_DECOD_IS_DELAY_SLOT ,_param->_nb_inst_decod); 164 #ifdef DEBUG 165 INSTANCE1_SC_SIGNAL(_Decod_unit,out_DECOD_ADDRESS ,_param->_nb_inst_decod); 166 #endif 161 167 INSTANCE1_SC_SIGNAL(_Decod_unit,out_DECOD_ADDRESS_NEXT ,_param->_nb_inst_decod); 162 168 INSTANCE1_SC_SIGNAL(_Decod_unit,out_DECOD_HAS_IMMEDIAT ,_param->_nb_inst_decod); … … 490 496 DELETE1_SC_SIGNAL(out_DECOD_NO_EXECUTE ,_param->_nb_inst_decod); 491 497 DELETE1_SC_SIGNAL(out_DECOD_IS_DELAY_SLOT ,_param->_nb_inst_decod); 498 #ifdef DEBUG 499 DELETE1_SC_SIGNAL(out_DECOD_ADDRESS ,_param->_nb_inst_decod); 500 #endif 492 501 DELETE1_SC_SIGNAL(out_DECOD_ADDRESS_NEXT ,_param->_nb_inst_decod); 493 502 DELETE1_SC_SIGNAL(out_DECOD_HAS_IMMEDIAT ,_param->_nb_inst_decod); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/include/Decod_unit.h
r105 r108 87 87 public : SC_OUT(Tcontrol_t ) ** out_DECOD_NO_EXECUTE ;//[nb_inst_decod] 88 88 public : SC_OUT(Tcontrol_t ) ** out_DECOD_IS_DELAY_SLOT ;//[nb_inst_decod] 89 #ifdef DEBUG 90 public : SC_OUT(Tgeneral_data_t ) ** out_DECOD_ADDRESS ;//[nb_inst_decod] 91 #endif 89 92 public : SC_OUT(Tgeneral_data_t ) ** out_DECOD_ADDRESS_NEXT ;//[nb_inst_decod] 90 93 public : SC_OUT(Tcontrol_t ) ** out_DECOD_HAS_IMMEDIAT ;//[nb_inst_decod] -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/src/Decod_unit_allocation.cpp
r105 r108 89 89 ALLOC1_SIGNAL_OUT(out_DECOD_NO_EXECUTE ,"no_execute" ,Tcontrol_t ,1 ); 90 90 ALLOC1_SIGNAL_OUT(out_DECOD_IS_DELAY_SLOT,"is_delay_slot",Tcontrol_t ,1 ); 91 #ifdef DEBUG 92 ALLOC1_SIGNAL_OUT(out_DECOD_ADDRESS ,"address" ,Tgeneral_data_t ,_param->_size_instruction_address ); 93 #endif 91 94 ALLOC1_SIGNAL_OUT(out_DECOD_ADDRESS_NEXT ,"address_next" ,Tgeneral_data_t ,_param->_size_instruction_address ); 92 95 ALLOC1_SIGNAL_OUT(out_DECOD_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t ,1 ); … … 293 296 COMPONENT_MAP(_component,src ,"out_DECOD_" +toString(i)+"_IS_DELAY_SLOT", 294 297 dest, "in_DECOD_IN_"+toString(i)+"_IS_DELAY_SLOT"); 298 #ifdef DEBUG 299 COMPONENT_MAP(_component,src ,"out_DECOD_" +toString(i)+"_ADDRESS" , 300 dest, "in_DECOD_IN_"+toString(i)+"_ADDRESS" ); 301 #endif 295 302 COMPONENT_MAP(_component,src ,"out_DECOD_" +toString(i)+"_ADDRESS_NEXT" , 296 303 dest, "in_DECOD_IN_"+toString(i)+"_ADDRESS_NEXT" ); … … 435 442 // in_DECOD_IN_NO_EXECUTE - component decod 436 443 // in_DECOD_IN_IS_DELAY_SLOT - component decod 444 // in_DECOD_IN_ADDRESS - component decod 437 445 // in_DECOD_IN_ADDRESS_NEXT - component decod 438 446 // in_DECOD_IN_HAS_IMMEDIAT - component decod … … 478 486 PORT_MAP(_component,src ,"out_DECOD_OUT_"+toString(i)+"_IS_DELAY_SLOT", 479 487 dest,"out_DECOD_" +toString(i)+"_IS_DELAY_SLOT"); 488 #ifdef DEBUG 489 PORT_MAP(_component,src ,"out_DECOD_OUT_"+toString(i)+"_ADDRESS" , 490 dest,"out_DECOD_" +toString(i)+"_ADDRESS" ); 491 #endif 480 492 PORT_MAP(_component,src ,"out_DECOD_OUT_"+toString(i)+"_ADDRESS_NEXT" , 481 493 dest,"out_DECOD_" +toString(i)+"_ADDRESS_NEXT" ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/src/Decod_unit_deallocation.cpp
r105 r108 48 48 DELETE1_SIGNAL(out_DECOD_NO_EXECUTE ,_param->_nb_inst_decod,1 ); 49 49 DELETE1_SIGNAL(out_DECOD_IS_DELAY_SLOT ,_param->_nb_inst_decod,1 ); 50 #ifdef DEBUG 51 DELETE1_SIGNAL(out_DECOD_ADDRESS ,_param->_nb_inst_decod,_param->_size_instruction_address ); 52 #endif 50 53 DELETE1_SIGNAL(out_DECOD_ADDRESS_NEXT ,_param->_nb_inst_decod,_param->_size_instruction_address ); 51 54 DELETE1_SIGNAL(out_DECOD_HAS_IMMEDIAT ,_param->_nb_inst_decod,1 ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/config-context_1-decod_unit_1.cfg
r88 r108 8 8 2 2 +1 # size_depth [0] [nb_context] 9 9 4 4 +1 # nb_branch_speculated [0] [nb_context] 10 4 4 +1 # size_nb_inst_decod -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/config-context_4-decod_unit_1.cfg
r88 r108 17 17 2 2 +1 # nb_branch_speculated [2] [nb_context] 18 18 8 8 +1 # nb_branch_speculated [3] [nb_context] 19 4 4 +1 # size_nb_inst_decod -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/config-context_4-decod_unit_2-a.cfg
r88 r108 18 18 2 2 +1 # nb_branch_speculated [2] [nb_context] 19 19 8 8 +1 # nb_branch_speculated [3] [nb_context] 20 4 4 +1 # size_nb_inst_decod -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/config-context_4-decod_unit_2-b.cfg
r88 r108 18 18 2 2 +1 # nb_branch_speculated [2] [nb_context] 19 19 8 8 +1 # nb_branch_speculated [3] [nb_context] 20 4 4 +1 # size_nb_inst_decod -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/config-context_4-decod_unit_4.cfg
r88 r108 20 20 2 2 +1 # nb_branch_speculated [2] [nb_context] 21 21 8 8 +1 # nb_branch_speculated [3] [nb_context] 22 4 4 +1 # size_nb_inst_decod -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/config-min.cfg
r88 r108 8 8 0 0 +1 # size_depth [0] [nb_context] 9 9 1 1 +1 # nb_branch_speculated [0] [nb_context] 10 1 1 +1 # size_nb_inst_decod -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/src/main.cpp
r88 r108 8 8 #include "Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/include/test.h" 9 9 10 #define NB_PARAMS 410 #define NB_PARAMS 5 11 11 12 12 void usage (int argc, char * argv[]) … … 22 22 err (_(" * size_depth [nb_context] (uint32_t)\n")); 23 23 err (_(" * nb_branch_speculated [nb_context] (uint32_t)\n")); 24 err (_(" * size_nb_inst_decod (uint32_t)\n")); 24 25 25 26 exit (1); … … 69 70 _nb_branch_speculated [i] = fromString<uint32_t>(argv[x++]); 70 71 72 uint32_t _size_nb_inst_decod = fromString<uint32_t>(argv[x++]); 73 71 74 std::vector<uint32_t> * _translate_context_id_from_decod_unit = new std::vector<uint32_t> [_nb_decod_unit]; 72 75 … … 87 90 _size_depth , 88 91 _nb_branch_speculated , 92 _size_nb_inst_decod , 89 93 true // is_toplevel 90 94 ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/src/test.cpp
r101 r108 104 104 ALLOC2_SC_SIGNAL(out_CONTEXT_DECOD_UNIT_DEPTH_VAL ,"out_CONTEXT_DECOD_UNIT_DEPTH_VAL ",Tcontrol_t,_param->_nb_decod_unit,_param->_decod_unit_nb_context [it1]); 105 105 ALLOC2_SC_SIGNAL(out_CONTEXT_DECOD_UNIT_DEPTH ,"out_CONTEXT_DECOD_UNIT_DEPTH ",Tdepth_t ,_param->_nb_decod_unit,_param->_decod_unit_nb_context [it1]); 106 107 ALLOC1_SC_SIGNAL(out_NB_INST_DECOD_ALL ,"out_NB_INST_DECOD_ALL ",Tcounter_t,_param->_nb_context); 108 ALLOC1_SC_SIGNAL( in_NB_INST_DECOD_UNIT_DECOD_ALL ," in_NB_INST_DECOD_UNIT_DECOD_ALL ",Tcounter_t,_param->_nb_context); 109 ALLOC1_SC_SIGNAL(out_NB_INST_CONTEXT_STATE_DECOD_ALL ,"out_NB_INST_CONTEXT_STATE_DECOD_ALL ",Tcounter_t,_param->_nb_context); 106 110 107 111 /******************************************************** … … 182 186 } 183 187 188 INSTANCE1_SC_SIGNAL(_Front_end_Glue,out_NB_INST_DECOD_ALL ,_param->_nb_context); 189 INSTANCE1_SC_SIGNAL(_Front_end_Glue, in_NB_INST_DECOD_UNIT_DECOD_ALL ,_param->_nb_context); 190 INSTANCE1_SC_SIGNAL(_Front_end_Glue,out_NB_INST_CONTEXT_STATE_DECOD_ALL ,_param->_nb_context); 191 184 192 msg(_("<%s> : Start Simulation ............\n"),name.c_str()); 185 193 … … 282 290 DELETE2_SC_SIGNAL(out_CONTEXT_DECOD_UNIT_DEPTH_VAL ,_param->_nb_decod_unit,_param->_decod_unit_nb_context [it1]); 283 291 DELETE2_SC_SIGNAL(out_CONTEXT_DECOD_UNIT_DEPTH ,_param->_nb_decod_unit,_param->_decod_unit_nb_context [it1]); 292 293 DELETE1_SC_SIGNAL(out_NB_INST_DECOD_ALL ,_param->_nb_context); 294 DELETE1_SC_SIGNAL( in_NB_INST_DECOD_UNIT_DECOD_ALL ,_param->_nb_context); 295 DELETE1_SC_SIGNAL(out_NB_INST_CONTEXT_STATE_DECOD_ALL ,_param->_nb_context); 284 296 } 285 297 #endif -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/include/Front_end_Glue.h
r101 r108 133 133 public : SC_OUT(Tcontrol_t ) *** out_CONTEXT_DECOD_UNIT_DEPTH_VAL ;//[nb_decod_unit][nb_decod_unit_context] 134 134 public : SC_OUT(Tdepth_t ) *** out_CONTEXT_DECOD_UNIT_DEPTH ;//[nb_decod_unit][nb_decod_unit_context] 135 136 // ~~~~~[ Interface : "nb_inst" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 137 public : SC_OUT(Tcounter_t ) ** out_NB_INST_DECOD_ALL ;//[nb_context] 138 139 public : SC_IN (Tcounter_t ) ** in_NB_INST_DECOD_UNIT_DECOD_ALL ;//[nb_context] 140 141 public : SC_OUT(Tcounter_t ) ** out_NB_INST_CONTEXT_STATE_DECOD_ALL ;//[nb_context] 142 135 143 136 144 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ … … 177 185 public : void genMealy_event (void); 178 186 public : void genMealy_depth (void); 187 public : void genMealy_nb_inst (void); 179 188 #endif 180 189 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/include/Parameters.h
r88 r108 54 54 uint32_t * size_depth , 55 55 uint32_t * nb_branch_speculated , 56 uint32_t size_nb_inst_decod , 56 57 uint32_t is_toplevel=false); 57 58 // public : Parameters (Parameters & param) ; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue.cpp
r101 r108 176 176 # endif 177 177 178 log_printf(INFO,Front_end_Glue,FUNCTION,_("<%s> : Method - genMealy_nb_inst"),_name.c_str()); 179 180 SC_METHOD (genMealy_nb_inst); 181 dont_initialize (); 182 // sensitive << (*(in_CLOCK)).neg(); // don't need internal register 183 for (uint32_t i=0; i<_param->_nb_context; ++i) 184 sensitive << (*( in_NB_INST_DECOD_UNIT_DECOD_ALL [i])); 185 186 # ifdef SYSTEMCASS_SPECIFIC 187 // List dependency information 188 # endif 178 189 179 190 #endif -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_allocation.cpp
r101 r108 155 155 _ALLOC2_SIGNAL_OUT(out_CONTEXT_DECOD_UNIT_DEPTH ,"DECOD_UNIT_DEPTH" ,Tdepth_t ,_param->_size_depth ,_param->_nb_decod_unit,_param->_decod_unit_nb_context [it1]); 156 156 } 157 157 158 // ~~~~~[ Interface : "nb_inst" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 159 { 160 ALLOC1_INTERFACE("nb_inst",OUT,EAST,_("nb inst"),_param->_nb_context); 161 162 ALLOC1_SIGNAL_OUT(out_NB_INST_DECOD_ALL ,"DECOD_ALL" ,Tcounter_t ,_param->_size_nb_inst_decod); 163 ALLOC1_SIGNAL_IN ( in_NB_INST_DECOD_UNIT_DECOD_ALL ,"DECOD_UNIT_DECOD_ALL" ,Tcounter_t ,_param->_size_nb_inst_decod); 164 ALLOC1_SIGNAL_OUT(out_NB_INST_CONTEXT_STATE_DECOD_ALL ,"CONTEXT_STATE_DECOD_ALL" ,Tcounter_t ,_param->_size_nb_inst_decod); 165 } 166 158 167 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 159 168 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_deallocation.cpp
r101 r108 87 87 DELETE2_SIGNAL(out_CONTEXT_DECOD_UNIT_DEPTH_VAL ,_param->_nb_decod_unit,_param->_decod_unit_nb_context [it1],1); 88 88 DELETE2_SIGNAL(out_CONTEXT_DECOD_UNIT_DEPTH ,_param->_nb_decod_unit,_param->_decod_unit_nb_context [it1],_param->_size_depth); 89 90 DELETE1_SIGNAL(out_NB_INST_DECOD_ALL ,_param->_nb_context,_param->_size_nb_inst_decod); 91 DELETE1_SIGNAL( in_NB_INST_DECOD_UNIT_DECOD_ALL ,_param->_nb_context,_param->_size_nb_inst_decod); 92 DELETE1_SIGNAL(out_NB_INST_CONTEXT_STATE_DECOD_ALL ,_param->_nb_context,_param->_size_nb_inst_decod); 89 93 } 90 94 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Parameters.cpp
r88 r108 28 28 uint32_t * size_depth , 29 29 uint32_t * nb_branch_speculated , 30 uint32_t size_nb_inst_decod , 30 31 uint32_t is_toplevel): 31 32 morpheo::behavioural::Parameters() … … 55 56 _size_instruction_address = size_address; 56 57 _size_depth = max<uint32_t>(size_depth,_nb_context); 57 58 _size_nb_inst_decod = size_nb_inst_decod; 59 58 60 _have_port_context_id = _size_context_id > 0; 59 61 _have_port_depth = _size_depth > 0; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/src/Branch_Target_Buffer_Glue_genMealy_predict.cpp
r98 r108 28 28 { 29 29 log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION," * PREDICT [%d]",i); 30 31 Tcontrol_t val = PORT_READ(in_PREDICT_VAL [i]); 32 Tcontrol_t register_ack = PORT_READ(in_PREDICT_REGISTER_ACK [i]); 33 Tcontrol_t sort_val = (_param->_have_port_victim)?PORT_READ(in_PREDICT_SORT_VAL [i]):true; 34 Tcontrol_t victim_ack = (_param->_have_port_victim)?PORT_READ(in_PREDICT_VICTIM_ACK [i]):true; 35 36 log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION," * val : %d",val ); 37 log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION," * register_ack : %d",register_ack); 38 log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION," * sort_val : %d",sort_val ); 39 log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION," * victim_ack : %d",victim_ack ); 40 30 41 Tptr_t index = (_param->_have_port_victim)?PORT_READ(in_PREDICT_SORT_INDEX [i]):0; 31 Tcontrol_t hit = PORT_READ(in_PREDICT_REGISTER_HIT [i][index]); 42 Tcontrol_t hit = // (_param->_have_port_victim)?sort_val: 43 PORT_READ(in_PREDICT_REGISTER_HIT [i][index]); 32 44 Tgeneral_data_t address_src = PORT_READ(in_PREDICT_REGISTER_ADDRESS_SRC [i][index]); 33 45 … … 44 56 PORT_WRITE(out_PREDICT_IS_ACCURATE [i],PORT_READ(in_PREDICT_REGISTER_IS_ACCURATE [i][index])); 45 57 46 Tcontrol_t val = PORT_READ(in_PREDICT_VAL [i]);47 Tcontrol_t register_ack = PORT_READ(in_PREDICT_REGISTER_ACK [i]);48 Tcontrol_t sort_val = (_param->_have_port_victim)?PORT_READ(in_PREDICT_SORT_VAL [i]):true;49 Tcontrol_t victim_ack = (_param->_have_port_victim)?PORT_READ(in_PREDICT_VICTIM_ACK [i]):true;50 51 log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION," * val : %d",val );52 log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION," * register_ack : %d",register_ack);53 log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION," * sort_val : %d",sort_val );54 log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION," * victim_ack : %d",victim_ack );55 56 58 PORT_WRITE(out_PREDICT_ACK [i], ( 57 59 // val and 58 60 register_ack and 59 61 // sort_val and 60 62 victim_ack 61 63 )); … … 63 65 val and 64 66 // register_ack and 65 67 // sort_val and 66 68 victim_ack 67 69 )); … … 71 73 PORT_WRITE(out_PREDICT_VICTIM_VAL [i], ( 72 74 val and 73 register_ack and74 sort_val //and75 register_ack // and 76 // sort_val and 75 77 // victim_ack 76 78 )); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_genMealy_predict.cpp
r88 r108 54 54 // * context is the same 55 55 // * address_src must be higher that the address, because the address lower is previous the current pc. 56 // * prediction is no accurate is address_dest is not valid. 56 57 PORT_WRITE(out_PREDICT_HIT [i][j],hit); 57 58 PORT_WRITE(out_PREDICT_ADDRESS_SRC [i][j],reg_BTB[num_bank][j]._address_src ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/src/Branch_Target_Buffer_allocation.cpp
r88 r108 224 224 dest,"out_PREDICT_"+toString(i)+"_"+toString(j)+"_ADDRESS_SRC"); 225 225 226 // out_OUTPUT_VAL -> glue227 // out_OUTPUT_INDEX -> glue228 // out_OUTPUT_ADDRESS -> no exist229 226 } 230 } 227 228 // 1 output 229 // out_OUTPUT_VAL -> glue 230 // out_OUTPUT_INDEX -> glue 231 // out_OUTPUT_ADDRESS -> no exist 232 } 231 233 232 234 //================================================================ -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_transition.cpp
r107 r108 126 126 if (reg_UPT_BOTTOM [i] != reg_UPT_TOP [i]) 127 127 reg_UPT_EMPTY [i] = false; 128 129 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_TOP : %d",reg_UPT_TOP [i]); 130 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_TOP_EVENT : %d",reg_UPT_TOP_EVENT [i]); 131 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_UPDATE : %d",reg_UPT_UPDATE [i]); 132 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_EMPTY : %d",reg_UPT_EMPTY [i]); 128 133 } 129 134 … … 210 215 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss_decod : %d",miss_decod); 211 216 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * upt_ptr_write : %d",upt_ptr_write); 212 217 213 218 if (miss_ifetch or miss_decod) 214 219 { … … 218 223 throw ERRORMORPHEO(FUNCTION,_("Decod : invalid event state.")); 219 224 #endif 220 221 225 if (reg_UFPT_NB_NEED_UPDATE [context] == 0) 222 226 { … … 312 316 reg_UPT_EMPTY [context] = false; 313 317 // reg_UPT_UPDATE [context] = reg_UPT_TOP [context]; 318 319 // if (miss_ifetch or miss_decod) 320 // reg_UPT_TOP_EVENT [context] = reg_UPT_TOP [context]; 314 321 } 315 316 // ===================================================================317 // =====[ BRANCH_COMPLETE ]===========================================318 // ===================================================================319 320 // The branch is complete321 // * Hit prediction :322 // * update status323 // * Miss prediction :324 for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++)325 if (PORT_READ(in_BRANCH_COMPLETE_VAL[i]) and internal_BRANCH_COMPLETE_ACK [i])326 {327 Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_BRANCH_COMPLETE_CONTEXT_ID [i]):0;328 Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_BRANCH_COMPLETE_DEPTH [i]):0;329 Tcontrol_t miss = internal_BRANCH_COMPLETE_MISS_PREDICTION [i];330 Tcontrol_t good_take = internal_BRANCH_COMPLETE_TAKE [i];331 Taddress_t good_addr = internal_BRANCH_COMPLETE_ADDRESS_DEST [i];332 333 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * BRANCH_COMPLETE[%d] - Accepted",i);334 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context);335 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth : %d",depth);336 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss : %d",miss);337 338 if (miss)339 {340 // Have a miss !!!341 // Flush UPFT342 flush_UFPT [context] = true;343 344 // Flush UPT345 uint32_t top = reg_UPT_TOP [context];346 uint32_t new_update = ((top==0)?_param->_size_upt_queue[context]:top)-1;347 348 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * top : %d",top);349 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * new_update : %d",new_update);350 351 for (uint32_t j=(depth+1)%_param->_size_upt_queue[context];352 j!=top;353 j=(j+1)%_param->_size_upt_queue[context])354 reg_UPDATE_PREDICTION_TABLE [context][j]._state = UPDATE_PREDICTION_STATE_EVENT;355 356 357 // reg_UPT_BOTTOM [context];358 reg_UPT_TOP [context] = depth;359 reg_UPT_TOP_EVENT [context] = top;360 361 if (reg_UPT_BOTTOM [context] == reg_UPT_TOP [context])362 reg_UPT_EMPTY [context] = true;363 364 #ifdef DEBUG_TEST365 if (reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_WAIT_END)366 throw ERRORMORPHEO(FUNCTION,_("Branch complete : invalid upt state."));367 #endif368 369 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_KO (branch_complete, ifetch hit)",context,depth);370 reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_KO;371 372 Taddress_t address_src = reg_UPDATE_PREDICTION_TABLE [context][depth]._address_src;373 event_state_t event_state = reg_EVENT_STATE [context];374 bool previous_update_ras = ((event_state == EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT ) or375 (event_state == EVENT_STATE_MISS_FLUSH_UPT ) or376 (event_state == EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT) or377 (event_state == EVENT_STATE_EVENT_FLUSH_UPT));378 // bool update_ras = (new_update != depth);379 380 // log_printf(TRACE,Update_Prediction_Table,FUNCTION," * update_ras : %d",update_ras);381 382 if (reg_UFPT_NB_NEED_UPDATE [context] > 0)383 {384 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT (branch_complete - miss)",context);385 reg_EVENT_STATE [context] = EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT;386 }387 else388 {389 // if (not previous_update_ras)390 {391 // have ras prediction ?392 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_MISS_FLUSH_UPT (branch_complete - miss)",context);393 394 reg_EVENT_STATE [context] = EVENT_STATE_MISS_FLUSH_UPT;395 396 }397 }398 399 if (not previous_update_ras)400 {401 reg_UPT_UPDATE [context] = new_update;402 }403 // else no update404 405 reg_EVENT_DEPTH [context] = depth;406 reg_EVENT_ADDRESS_SRC [context] = address_src; // delay_slot is compute in Context_State407 reg_EVENT_ADDRESS_DEST_VAL[context] = good_take;408 reg_EVENT_ADDRESS_DEST [context] = good_addr;409 }410 else411 {412 // Hit case413 414 #ifdef DEBUG_TEST415 if (reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_WAIT_END)416 throw ERRORMORPHEO(FUNCTION,_("Branch complete : invalid upt state."));417 #endif418 419 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_OK (branch_complete, ifetch hit)",context,depth);420 reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_OK;421 }422 423 // In all case : update good_take424 reg_UPDATE_PREDICTION_TABLE [context][depth]._good_take = good_take;425 426 // Write address_dest if need read register427 Tbranch_condition_t condition = reg_UPDATE_PREDICTION_TABLE [context][depth]._condition;428 429 if ((condition == BRANCH_CONDITION_READ_REGISTER_WITHOUT_WRITE_STACK) or430 (condition == BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK ) or431 (condition == BRANCH_CONDITION_READ_STACK ) )432 reg_UPDATE_PREDICTION_TABLE [context][depth]._address_dest = good_addr;433 }434 322 435 323 // =================================================================== … … 599 487 } 600 488 489 490 // =================================================================== 491 // =====[ BRANCH_COMPLETE ]=========================================== 492 // =================================================================== 493 494 // The branch is complete 495 // * Hit prediction : 496 // * update status 497 // * Miss prediction : 498 for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++) 499 if (PORT_READ(in_BRANCH_COMPLETE_VAL[i]) and internal_BRANCH_COMPLETE_ACK [i]) 500 { 501 Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_BRANCH_COMPLETE_CONTEXT_ID [i]):0; 502 Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_BRANCH_COMPLETE_DEPTH [i]):0; 503 Tcontrol_t miss = internal_BRANCH_COMPLETE_MISS_PREDICTION [i]; 504 Tcontrol_t good_take = internal_BRANCH_COMPLETE_TAKE [i]; 505 Taddress_t good_addr = internal_BRANCH_COMPLETE_ADDRESS_DEST [i]; 506 507 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * BRANCH_COMPLETE[%d] - Accepted",i); 508 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context); 509 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth : %d",depth); 510 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss : %d",miss); 511 512 if (miss) 513 { 514 // Have a miss !!! 515 // Flush UPFT 516 flush_UFPT [context] = true; 517 518 // Flush UPT 519 uint32_t top = reg_UPT_TOP [context]; 520 uint32_t new_update = ((top==0)?_param->_size_upt_queue[context]:top)-1; 521 522 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * top : %d",top); 523 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * new_update : %d",new_update); 524 525 for (uint32_t j=(depth+1)%_param->_size_upt_queue[context]; 526 j!=top; 527 j=(j+1)%_param->_size_upt_queue[context]) 528 reg_UPDATE_PREDICTION_TABLE [context][j]._state = UPDATE_PREDICTION_STATE_EVENT; 529 530 531 // reg_UPT_BOTTOM [context]; 532 reg_UPT_TOP [context] = depth; 533 reg_UPT_TOP_EVENT [context] = top; 534 535 if (reg_UPT_BOTTOM [context] == reg_UPT_TOP [context]) 536 reg_UPT_EMPTY [context] = true; 537 538 #ifdef DEBUG_TEST 539 if (reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_WAIT_END) 540 throw ERRORMORPHEO(FUNCTION,_("Branch complete : invalid upt state.")); 541 #endif 542 543 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_KO (branch_complete, ifetch hit)",context,depth); 544 reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_KO; 545 546 Taddress_t address_src = reg_UPDATE_PREDICTION_TABLE [context][depth]._address_src; 547 event_state_t event_state = reg_EVENT_STATE [context]; 548 bool previous_update_ras = ((event_state == EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT ) or 549 (event_state == EVENT_STATE_MISS_FLUSH_UPT ) or 550 (event_state == EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT) or 551 (event_state == EVENT_STATE_EVENT_FLUSH_UPT)); 552 // bool update_ras = (new_update != depth); 553 554 // log_printf(TRACE,Update_Prediction_Table,FUNCTION," * update_ras : %d",update_ras); 555 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * previous_update_ras : %d",previous_update_ras); 556 557 if (reg_UFPT_NB_NEED_UPDATE [context] > 0) 558 { 559 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT (branch_complete - miss)",context); 560 reg_EVENT_STATE [context] = EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT; 561 } 562 else 563 { 564 // if (not previous_update_ras) 565 { 566 // have ras prediction ? 567 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_MISS_FLUSH_UPT (branch_complete - miss)",context); 568 569 reg_EVENT_STATE [context] = EVENT_STATE_MISS_FLUSH_UPT; 570 571 } 572 } 573 574 if (not previous_update_ras) 575 { 576 reg_UPT_UPDATE [context] = new_update; 577 } 578 // else no update 579 580 reg_EVENT_DEPTH [context] = depth; 581 reg_EVENT_ADDRESS_SRC [context] = address_src; // delay_slot is compute in Context_State 582 reg_EVENT_ADDRESS_DEST_VAL[context] = good_take; 583 reg_EVENT_ADDRESS_DEST [context] = good_addr; 584 } 585 else 586 { 587 // Hit case 588 589 // #ifdef DEBUG_TEST 590 // if (reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_WAIT_END) 591 // throw ERRORMORPHEO(FUNCTION,_("Branch complete : invalid upt state.")); 592 // #endif 593 594 if (reg_UPDATE_PREDICTION_TABLE [context][depth]._state == UPDATE_PREDICTION_STATE_WAIT_END) 595 { 596 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_OK (branch_complete, ifetch hit)",context,depth); 597 reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_OK; 598 } 599 } 600 601 // In all case : update good_take 602 reg_UPDATE_PREDICTION_TABLE [context][depth]._good_take = good_take; 603 604 // Write address_dest if need read register 605 Tbranch_condition_t condition = reg_UPDATE_PREDICTION_TABLE [context][depth]._condition; 606 607 if ((condition == BRANCH_CONDITION_READ_REGISTER_WITHOUT_WRITE_STACK) or 608 (condition == BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK ) or 609 (condition == BRANCH_CONDITION_READ_STACK ) ) 610 reg_UPDATE_PREDICTION_TABLE [context][depth]._address_dest = good_addr; 611 } 612 601 613 // =================================================================== 602 614 // =====[ BRANCH_EVENT ]============================================== … … 695 707 uint32_t bottom = reg_UPT_BOTTOM [i]; 696 708 uint32_t new_update = ((top==0)?_param->_size_upt_queue[i]:top)-1; 697 uint32_t full = ((depth == top) and (top == bottom) and not reg_UPT_EMPTY [i]); 709 bool full = ((depth == top) and (top == bottom) and not reg_UPT_EMPTY [i]); 710 // bool empty = reg_UPT_EMPTY [i]; 711 698 712 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * top : %d",top); 699 713 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth : %d",depth); 700 714 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * new_update : %d",new_update); 701 715 702 // Test empty 703 if (not reg_UPT_EMPTY [i]) 716 event_state_t event_state = reg_EVENT_STATE [i]; 717 bool previous_update_ras = ((event_state == EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT ) or 718 (event_state == EVENT_STATE_MISS_FLUSH_UPT ) or 719 (event_state == EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT) or 720 (event_state == EVENT_STATE_EVENT_FLUSH_UPT)); 721 722 bool find = false; // have slot to update ??? 723 724 // flush all slot after the event 725 for (uint32_t j=(depth+1)%_param->_size_upt_queue[i]; 726 j!=top; 727 j=(j+1)%_param->_size_upt_queue[i]) 728 if ((reg_UPDATE_PREDICTION_TABLE [i][j]._state != UPDATE_PREDICTION_STATE_END) and 729 (reg_UPDATE_PREDICTION_TABLE [i][j]._state != UPDATE_PREDICTION_STATE_EMPTY)) 730 { 731 find = true; 732 reg_UPDATE_PREDICTION_TABLE [i][j]._state = UPDATE_PREDICTION_STATE_EVENT; 733 } 734 735 if ((reg_UPDATE_PREDICTION_TABLE [i][depth]._state != UPDATE_PREDICTION_STATE_END) and 736 (reg_UPDATE_PREDICTION_TABLE [i][depth]._state != UPDATE_PREDICTION_STATE_EMPTY)) 704 737 { 705 #ifdef DEBUG_TEST 706 if (reg_UPDATE_PREDICTION_TABLE [i][depth]._state != UPDATE_PREDICTION_STATE_WAIT_END) 707 throw ERRORMORPHEO(FUNCTION,_("Branch complete : invalid upt state.")); 708 #endif 738 find = true; 709 739 reg_UPDATE_PREDICTION_TABLE [i][depth]._state = UPDATE_PREDICTION_STATE_EVENT; 710 740 } 741 742 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * find : %d",find); 743 744 // Test if have update slot 745 if (find) 746 { 711 747 // flush all slot after the event 712 748 for (uint32_t j=(depth+1)%_param->_size_upt_queue[i]; … … 714 750 j=(j+1)%_param->_size_upt_queue[i]) 715 751 reg_UPDATE_PREDICTION_TABLE [i][j]._state = UPDATE_PREDICTION_STATE_EVENT; 752 753 reg_UPDATE_PREDICTION_TABLE [i][depth]._state = UPDATE_PREDICTION_STATE_EVENT; 754 755 // reg_UPT_BOTTOM [i]; 756 // TODO : special case : event is an exception on branch, also depth is not valid 757 reg_UPT_TOP [i] = depth; // depth is again valid 758 reg_UPT_TOP_EVENT [i] = top; 759 760 if (bottom == reg_UPT_TOP [i]) 761 reg_UPT_EMPTY [i] = true; 716 762 } 763 764 bool update_ras = find and ((top != depth) or full); 765 766 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * update_ras : %d",update_ras); 767 768 if (not previous_update_ras and update_ras) 769 reg_UPT_UPDATE [i] = new_update; 717 770 718 // reg_UPT_BOTTOM [i];719 // TODO : special case : event is an exception on branch, also depth is not valid720 reg_UPT_TOP [i] = depth; // depth is again valid721 reg_UPT_TOP_EVENT [i] = top;722 723 if (bottom == reg_UPT_TOP [i])724 reg_UPT_EMPTY [i] = true;725 726 reg_EVENT_VAL [i] = true;727 reg_EVENT_UPT_PTR [i] = depth;728 event_state_t event_state = reg_EVENT_STATE [i];729 bool previous_update_ras = ((event_state == EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT ) or730 (event_state == EVENT_STATE_MISS_FLUSH_UPT ) or731 (event_state == EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT) or732 (event_state == EVENT_STATE_EVENT_FLUSH_UPT));733 bool update_ras = (top != depth) or full;734 735 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * update_ras : %d",update_ras);736 737 771 // new state : 738 772 // * test if ufpt is empty … … 741 775 // * ok : nothing 742 776 // * ko : flush upt 777 reg_EVENT_VAL [i] = true; 778 reg_EVENT_UPT_PTR [i] = depth; 779 743 780 if (reg_UFPT_NB_NEED_UPDATE [i] > 0) 744 781 { … … 766 803 else 767 804 { 805 // special case : nothing 806 reg_EVENT_VAL [i] = false; 807 768 808 reg_EVENT_STATE [i] = EVENT_STATE_OK; 769 809 } 770 810 } 771 772 if (not previous_update_ras and update_ras) 773 { 774 reg_UPT_UPDATE [i] = new_update; 775 } 811 776 812 // else no update 777 813 … … 817 853 { 818 854 for (uint32_t j=0; j<_param->_size_ufpt_queue[i]; ++j) 819 { 820 reg_UFPT_NB_UPDATE [i] ++; 821 reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._state = UPDATE_FETCH_PREDICTION_STATE_EVENT; 822 } 855 // EMPTY : no event 856 // END : already update 857 // EVENT : previous event 858 if (reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._state == UPDATE_FETCH_PREDICTION_STATE_WAIT_DECOD) 859 { 860 reg_UFPT_NB_UPDATE [i] ++; 861 reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._state = UPDATE_FETCH_PREDICTION_STATE_EVENT; 862 } 823 863 824 864 // TOP is next write slot : last slot is TOP-1 … … 862 902 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_STATE : %s" ,toString(reg_EVENT_STATE [i]).c_str()); 863 903 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_DEPTH : %d" ,reg_EVENT_DEPTH [i]); 864 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_ADDRESS_SRC : %.8x ",reg_EVENT_ADDRESS_SRC [i]);904 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_ADDRESS_SRC : %.8x (%.8x)",reg_EVENT_ADDRESS_SRC [i],reg_EVENT_ADDRESS_SRC [i]<<2); 865 905 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_ADDRESS_DEST_VAL: %d" ,reg_EVENT_ADDRESS_DEST_VAL[i]); 866 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_ADDRESS_DEST : %.8x ",reg_EVENT_ADDRESS_DEST [i]);906 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_ADDRESS_DEST : %.8x (%.8x)",reg_EVENT_ADDRESS_DEST [i],reg_EVENT_ADDRESS_DEST [i]<<2); 867 907 868 908 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Update_Fetch_Prediction_Table [%d]",i); … … 914 954 } 915 955 #endif 956 957 #ifdef DEBUG_TEST 958 for (uint32_t i=0; i<_param->_nb_context; i++) 959 { 960 if (reg_UFPT_NB_NEED_UPDATE [i] > _param->_size_ufpt_queue[i]) 961 throw ERRORMORPHEO(FUNCTION,toString(_("reg_UFPT_NB_NEED_UPDATE [%d] (%d) is > at size_ufpt_queue (%d).\n"),i,reg_UFPT_NB_NEED_UPDATE [i],_param->_size_ufpt_queue[i])); 962 if (reg_UFPT_NB_UPDATE [i] > _param->_size_ufpt_queue[i]) 963 throw ERRORMORPHEO(FUNCTION,toString(_("reg_UFPT_NB_UPDATE [%d] (%d) is > at size_ufpt_queue (%d).\n"),i,reg_UFPT_NB_UPDATE [i],_param->_size_ufpt_queue[i])); 964 } 965 #endif 966 916 967 } 917 968 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/src/test.cpp
r105 r108 68 68 ALLOC1_SC_SIGNAL(out_DECOD_NO_EXECUTE ,"out_DECOD_NO_EXECUTE ",Tcontrol_t ,_param->_sum_inst_decod); 69 69 ALLOC1_SC_SIGNAL(out_DECOD_IS_DELAY_SLOT ,"out_DECOD_IS_DELAY_SLOT ",Tcontrol_t ,_param->_sum_inst_decod); 70 #ifdef DEBUG 71 ALLOC1_SC_SIGNAL(out_DECOD_ADDRESS ,"out_DECOD_ADDRESS ",Tgeneral_data_t ,_param->_sum_inst_decod); 72 #endif 70 73 ALLOC1_SC_SIGNAL(out_DECOD_ADDRESS_NEXT ,"out_DECOD_ADDRESS_NEXT ",Tgeneral_data_t ,_param->_sum_inst_decod); 71 74 ALLOC1_SC_SIGNAL(out_DECOD_HAS_IMMEDIAT ,"out_DECOD_HAS_IMMEDIAT ",Tcontrol_t ,_param->_sum_inst_decod); … … 116 119 ALLOC1_SC_SIGNAL( in_NB_INST_COMMIT_ALL ," in_NB_INST_COMMIT_ALL ",Tcounter_t ,_param->_nb_context); 117 120 ALLOC1_SC_SIGNAL( in_NB_INST_COMMIT_MEM ," in_NB_INST_COMMIT_MEM ",Tcounter_t ,_param->_nb_context); 121 ALLOC1_SC_SIGNAL(out_NB_INST_DECOD_ALL ,"out_NB_INST_DECOD_ALL ",Tcounter_t ,_param->_nb_context); 118 122 ALLOC1_SC_SIGNAL(out_DEPTH_MIN ,"out_DEPTH_MIN ",Tdepth_t ,_param->_nb_context); 119 123 ALLOC1_SC_SIGNAL(out_DEPTH_MAX ,"out_DEPTH_MAX ",Tdepth_t ,_param->_nb_context); … … 156 160 INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_NO_EXECUTE ,_param->_sum_inst_decod); 157 161 INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_IS_DELAY_SLOT ,_param->_sum_inst_decod); 162 #ifdef DEBUG 163 INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_ADDRESS ,_param->_sum_inst_decod); 164 #endif 158 165 INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_ADDRESS_NEXT ,_param->_sum_inst_decod); 159 166 INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_HAS_IMMEDIAT ,_param->_sum_inst_decod); … … 208 215 INSTANCE1_SC_SIGNAL(_Front_end, in_NB_INST_COMMIT_ALL ,_param->_nb_context); 209 216 INSTANCE1_SC_SIGNAL(_Front_end, in_NB_INST_COMMIT_MEM ,_param->_nb_context); 217 INSTANCE1_SC_SIGNAL(_Front_end,out_NB_INST_DECOD_ALL ,_param->_nb_context); 210 218 if (_param->_have_port_depth) 211 219 { … … 317 325 DELETE1_SC_SIGNAL(out_DECOD_NO_EXECUTE ,_param->_sum_inst_decod); 318 326 DELETE1_SC_SIGNAL(out_DECOD_IS_DELAY_SLOT ,_param->_sum_inst_decod); 327 #ifdef DEBUG 328 DELETE1_SC_SIGNAL(out_DECOD_ADDRESS ,_param->_sum_inst_decod); 329 #endif 319 330 DELETE1_SC_SIGNAL(out_DECOD_ADDRESS_NEXT ,_param->_sum_inst_decod); 320 331 DELETE1_SC_SIGNAL(out_DECOD_HAS_IMMEDIAT ,_param->_sum_inst_decod); … … 365 376 DELETE1_SC_SIGNAL( in_NB_INST_COMMIT_ALL ,_param->_nb_context); 366 377 DELETE1_SC_SIGNAL( in_NB_INST_COMMIT_MEM ,_param->_nb_context); 378 DELETE1_SC_SIGNAL(out_NB_INST_DECOD_ALL ,_param->_nb_context); 367 379 DELETE1_SC_SIGNAL(out_DEPTH_MIN ,_param->_nb_context); 368 380 DELETE1_SC_SIGNAL(out_DEPTH_MAX ,_param->_nb_context); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/include/Front_end.h
r105 r108 94 94 public : SC_OUT(Tcontrol_t ) ** out_DECOD_NO_EXECUTE ;//[sum_inst_decod] 95 95 public : SC_OUT(Tcontrol_t ) ** out_DECOD_IS_DELAY_SLOT ;//[sum_inst_decod] 96 #ifdef DEBUG 97 public : SC_OUT(Tgeneral_data_t ) ** out_DECOD_ADDRESS ;//[sum_inst_decod] 98 #endif 96 99 public : SC_OUT(Tgeneral_data_t ) ** out_DECOD_ADDRESS_NEXT ;//[sum_inst_decod] 97 100 public : SC_OUT(Tcontrol_t ) ** out_DECOD_HAS_IMMEDIAT ;//[sum_inst_decod] … … 152 155 public : SC_IN (Tcounter_t ) ** in_NB_INST_COMMIT_ALL ;//[nb_context] 153 156 public : SC_IN (Tcounter_t ) ** in_NB_INST_COMMIT_MEM ;//[nb_context] 157 public : SC_OUT(Tcounter_t ) ** out_NB_INST_DECOD_ALL ;//[nb_context] 154 158 155 159 // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Front_end_allocation.cpp
r105 r108 97 97 ALLOC1_SIGNAL_OUT (out_DECOD_NO_EXECUTE ,"NO_EXECUTE" ,Tcontrol_t ,1 ); 98 98 ALLOC1_SIGNAL_OUT (out_DECOD_IS_DELAY_SLOT ,"IS_DELAY_SLOT" ,Tcontrol_t ,1 ); 99 #ifdef DEBUG 100 ALLOC1_SIGNAL_OUT (out_DECOD_ADDRESS ,"ADDRESS" ,Tgeneral_data_t ,_param->_size_instruction_address ); 101 #endif 99 102 ALLOC1_SIGNAL_OUT (out_DECOD_ADDRESS_NEXT ,"ADDRESS_NEXT" ,Tgeneral_data_t ,_param->_size_instruction_address ); 100 103 ALLOC1_SIGNAL_OUT (out_DECOD_HAS_IMMEDIAT ,"HAS_IMMEDIAT" ,Tcontrol_t ,1 ); … … 175 178 ALLOC1_SIGNAL_IN ( in_NB_INST_COMMIT_ALL ,"COMMIT_ALL" ,Tcounter_t ,_param->_size_nb_inst_commit); 176 179 ALLOC1_SIGNAL_IN ( in_NB_INST_COMMIT_MEM ,"COMMIT_MEM" ,Tcounter_t ,_param->_size_nb_inst_commit); 180 ALLOC1_SIGNAL_OUT (out_NB_INST_DECOD_ALL ,"DECOD_ALL" ,Tcounter_t ,_param->_size_nb_inst_decod ); 177 181 } 178 182 … … 699 703 PORT_MAP(_component,src ,"out_DECOD_"+toString(j)+"_IS_DELAY_SLOT", 700 704 dest,"out_DECOD_"+toString(x)+"_IS_DELAY_SLOT"); 705 #ifdef DEBUG 706 PORT_MAP(_component,src ,"out_DECOD_"+toString(j)+"_ADDRESS" , 707 dest,"out_DECOD_"+toString(x)+"_ADDRESS" ); 708 #endif 701 709 PORT_MAP(_component,src ,"out_DECOD_"+toString(j)+"_ADDRESS_NEXT" , 702 710 dest,"out_DECOD_"+toString(x)+"_ADDRESS_NEXT" ); … … 809 817 uint32_t y=(_param->_translate_context_id_from_decod_unit[i])[j]; 810 818 811 dest = _name+"_ context_state";819 dest = _name+"_glue"; 812 820 #ifdef POSITION 813 821 _component->interface_map (src ,"nb_inst_"+toString(j), … … 815 823 #endif 816 824 817 COMPONENT_MAP(_component,src ,"out_NB_INST_"+toString(j)+ "_DECOD_ALL",818 dest, "in_NB_INST_"+toString(y)+"_DECOD_ ALL");825 COMPONENT_MAP(_component,src ,"out_NB_INST_"+toString(j)+ "_DECOD_ALL", 826 dest, "in_NB_INST_"+toString(y)+"_DECOD_UNIT_DECOD_ALL"); 819 827 } 820 828 … … 965 973 966 974 // ~~~~~[ Interface : "nb_inst" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 967 // in_NB_INST_DECOD_ALL - component_decod_unit968 969 975 for (uint32_t i=0; i<_param->_nb_context; ++i) 970 976 { 971 977 dest = _name; 972 978 #ifdef POSITION 973 _component->interface_map (src ,"nb_inst ",974 dest,"nb_inst ");979 _component->interface_map (src ,"nb_inst_"+toString(i), 980 dest,"nb_inst_"+toString(i)); 975 981 #endif 976 982 … … 979 985 PORT_MAP(_component,src , "in_NB_INST_"+toString(i)+"_COMMIT_MEM", 980 986 dest, "in_NB_INST_"+toString(i)+"_COMMIT_MEM"); 987 988 dest = _name+"_glue"; 989 #ifdef POSITION 990 _component->interface_map (src ,"nb_inst_"+toString(i), 991 dest,"nb_inst_"+toString(i)); 992 #endif 993 994 COMPONENT_MAP(_component,src , "in_NB_INST_"+toString(i)+ "_DECOD_ALL", 995 dest,"out_NB_INST_"+toString(i)+"_CONTEXT_STATE_DECOD_ALL"); 981 996 } 982 997 … … 1218 1233 // out_CONTEXT_DECOD_UNIT_DEPTH_VAL - component_decod_unit 1219 1234 // out_CONTEXT_DECOD_UNIT_DEPTH - component_decod_unit 1235 1236 // ~~~~~[ Interface : "nb_inst" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1237 for (uint32_t i=0; i<_param->_nb_context; ++i) 1238 { 1239 dest = _name; 1240 #ifdef POSITION 1241 _component->interface_map (src ,"nb_inst_"+toString(i), 1242 dest,"nb_inst_"+toString(i)); 1243 #endif 1244 1245 PORT_MAP(_component,src ,"out_NB_INST_"+toString(i)+"_DECOD_ALL", 1246 dest,"out_NB_INST_"+toString(i)+"_DECOD_ALL"); 1247 1248 // in_NB_INST_DECOD_UNIT_DECOD_ALL - component_decod_unit 1249 // out_NB_INST_CONTEXT_STATE_DECOD_ALL - component_context_state 1250 } 1220 1251 } 1221 1252 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Front_end_deallocation.cpp
r105 r108 49 49 DELETE1_SIGNAL(out_DECOD_NO_EXECUTE ,_param->_sum_inst_decod,1 ); 50 50 DELETE1_SIGNAL(out_DECOD_IS_DELAY_SLOT ,_param->_sum_inst_decod,1 ); 51 #ifdef DEBUG 52 DELETE1_SIGNAL(out_DECOD_ADDRESS ,_param->_sum_inst_decod,_param->_size_instruction_address ); 53 #endif 51 54 DELETE1_SIGNAL(out_DECOD_ADDRESS_NEXT ,_param->_sum_inst_decod,_param->_size_instruction_address ); 52 55 DELETE1_SIGNAL(out_DECOD_HAS_IMMEDIAT ,_param->_sum_inst_decod,1 ); … … 102 105 DELETE1_SIGNAL( in_NB_INST_COMMIT_ALL ,_param->_nb_context,_param->_size_nb_inst_commit); 103 106 DELETE1_SIGNAL( in_NB_INST_COMMIT_MEM ,_param->_nb_context,_param->_size_nb_inst_commit); 107 DELETE1_SIGNAL(out_NB_INST_DECOD_ALL ,_param->_nb_context,_param->_size_nb_inst_decod); 104 108 105 109 DELETE1_SIGNAL(out_DEPTH_MIN ,_param->_nb_context,_param->_size_depth ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Parameters.cpp
r106 r108 109 109 _array_size_nb_inst_decod [i] = log2(_size_decod_queue[i]+1); 110 110 111 uint32_t size_nb_inst_decod = max<uint32_t>(_array_size_nb_inst_decod,_nb_decod_unit); 112 111 113 _param_ifetch_unit = new behavioural::core::multi_front_end::front_end::ifetch_unit::Parameters * [_nb_context]; 112 114 for (uint32_t i=0; i<_nb_context; ++i) … … 236 238 size_instruction_address , 237 239 _array_size_depth , 238 _upt_size_queue //_nb_branch_speculated 240 _upt_size_queue ,//_nb_branch_speculated 241 size_nb_inst_decod 239 242 ); 240 243 … … 244 247 _size_instruction_address = size_instruction_address; 245 248 _size_general_data = size_general_data; 246 _size_nb_inst_decod = max<uint32_t>(_array_size_nb_inst_decod,_nb_decod_unit);249 _size_nb_inst_decod = size_nb_inst_decod; 247 250 _size_nb_inst_commit = size_nb_inst_commit; 248 251 _size_depth = max<uint32_t>(_array_size_depth,_nb_context);
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