Changeset 117 for trunk/IPs/systemC/processor
- Timestamp:
- May 16, 2009, 4:42:39 PM (16 years ago)
- Location:
- trunk/IPs/systemC/processor/Morpheo
- Files:
-
- 11 added
- 1 deleted
- 102 edited
- 8 moved
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Behavioural/Core/Core_Glue/SelfTest/config-min.cfg (modified) (2 diffs)
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Behavioural/Core/Core_Glue/SelfTest/src/main.cpp (modified) (10 diffs)
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Behavioural/Core/Core_Glue/SelfTest/src/test.cpp (modified) (6 diffs)
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Behavioural/Core/Core_Glue/include/Core_Glue.h (modified) (1 diff)
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Behavioural/Core/Core_Glue/include/Parameters.h (modified) (7 diffs)
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Behavioural/Core/Core_Glue/src/Core_Glue.cpp (modified) (1 diff)
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Behavioural/Core/Core_Glue/src/Core_Glue_allocation.cpp (modified) (2 diffs)
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Behavioural/Core/Core_Glue/src/Core_Glue_deallocation.cpp (modified) (2 diffs)
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Behavioural/Core/Core_Glue/src/Core_Glue_genMealy_issue.cpp (modified) (2 diffs)
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Behavioural/Core/Core_Glue/src/Core_Glue_transition.cpp (modified) (2 diffs)
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Behavioural/Core/Core_Glue/src/Parameters.cpp (modified) (9 diffs)
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Behavioural/Core/Dcache_Access/src/Dcache_Access_genMealy_req.cpp (modified) (2 diffs)
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Behavioural/Core/Icache_Access/src/Icache_Access_genMealy_req.cpp (modified) (2 diffs)
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Behavioural/Core/Icache_Access/src/Parameters_msg_error.cpp (modified) (1 diff)
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Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_genMealy.cpp (modified) (1 diff)
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Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_transition.cpp (modified) (1 diff)
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Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/src/test2.cpp (modified) (2 diffs)
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Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h (modified) (2 diffs)
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Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_allocation.cpp (modified) (2 diffs)
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Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_deallocation.cpp (modified) (2 diffs)
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Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMoore.cpp (modified) (1 diff)
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Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_transition.cpp (modified) (13 diffs)
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Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Parameters.cpp (modified) (1 diff)
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Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/include/Types.h (modified) (1 diff)
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Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_transition.cpp (modified) (1 diff)
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Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue_genMoore.cpp (modified) (1 diff)
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Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/src/Read_unit_to_Execution_unit_genMealy.cpp (modified) (5 diffs)
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Behavioural/Core/Multi_Execute_loop/Execute_loop/src/Parameters.cpp (modified) (1 diff)
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Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Types.h (modified) (1 diff)
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Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_transition.cpp (modified) (3 diffs)
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Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/Instruction/src/Instruction.cpp (modified) (1 diff)
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Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/SelfTest/src/test.cpp (modified) (1 diff)
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Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_allocation.cpp (modified) (1 diff)
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Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Parameters.h (modified) (1 diff)
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Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_allocation.cpp (modified) (1 diff)
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Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_commit.cpp (modified) (2 diffs)
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Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_insert.cpp (modified) (1 diff)
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Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp (modified) (2 diffs)
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Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Parameters.cpp (modified) (1 diff)
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Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/SelfTest/config_min.cfg (modified) (2 diffs)
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Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/SelfTest/config_mono_rename_unit.cfg (modified) (2 diffs)
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Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/SelfTest/config_multi_rename_unit.cfg (modified) (2 diffs)
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Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/SelfTest/src/main.cpp (modified) (9 diffs)
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Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/SelfTest/src/test.cpp (modified) (2 diffs)
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Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/include/Parameters.h (modified) (4 diffs)
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Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_function_in_order_genMealy_issue_out.cpp (modified) (3 diffs)
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Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_function_out_of_order_genMoore.cpp (modified) (2 diffs)
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Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_transition.cpp (modified) (1 diff)
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Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Parameters.cpp (modified) (4 diffs)
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Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Parameters_msg_error.cpp (modified) (2 diffs)
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Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/SelfTest/src/test.cpp (modified) (4 diffs)
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Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/include/Reexecute_unit.h (modified) (1 diff)
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Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_allocation.cpp (modified) (1 diff)
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Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_deallocation.cpp (modified) (1 diff)
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Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_genMealy_commit.cpp (modified) (1 diff)
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Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/SelfTest/src/test.cpp (modified) (2 diffs)
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Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/SelfTest/src/test.cpp (modified) (3 diffs)
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Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/include/Register_translation_unit_Glue.h (modified) (1 diff)
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Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/src/Register_translation_unit_Glue_allocation.cpp (modified) (1 diff)
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Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/src/Register_translation_unit_Glue_deallocation.cpp (modified) (1 diff)
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Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/src/Register_translation_unit_Glue_genMealy_insert.cpp (modified) (1 diff)
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Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/SelfTest/src/test.cpp (modified) (12 diffs)
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Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/include/Stat_List_unit.h (modified) (1 diff)
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Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/include/Types.h (modified) (6 diffs)
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Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/src/Stat_List_unit_allocation.cpp (modified) (1 diff)
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Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/src/Stat_List_unit_deallocation.cpp (modified) (1 diff)
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Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/src/Stat_List_unit_transition.cpp (modified) (1 diff)
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Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/src/Register_translation_unit_allocation.cpp (modified) (1 diff)
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Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/configuration.cfg (modified) (2 diffs)
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Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/src/main.cpp (modified) (9 diffs)
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Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/src/test.cpp (modified) (1 diff)
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Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/SelfTest/src/main.cpp (modified) (3 diffs)
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Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/include/Parameters.h (modified) (2 diffs)
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Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/include/SPR.h (modified) (1 diff)
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Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Parameters.cpp (modified) (2 diffs)
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Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_allocation.cpp (modified) (1 diff)
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Behavioural/Core/Multi_OOO_Engine/OOO_Engine/include/Parameters.h (modified) (4 diffs)
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Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_allocation.cpp (modified) (2 diffs)
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Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/Parameters.cpp (modified) (8 diffs)
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Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/Parameters_print.cpp (modified) (1 diff)
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Behavioural/Core/SelfTest/src/test.cpp (modified) (1 diff)
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Behavioural/Core/include/Parameters.h (modified) (7 diffs)
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Behavioural/Core/src/Core_allocation.cpp (modified) (3 diffs)
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Behavioural/Core/src/Parameters.cpp (modified) (20 diffs)
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Behavioural/Core/src/Parameters_msg_error.cpp (modified) (3 diffs)
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Behavioural/Core/src/Parameters_print.cpp (modified) (2 diffs)
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Behavioural/Generic/Queue/SelfTest/src/main.cpp (modified) (1 diff)
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Behavioural/Makefile.Common (modified) (3 diffs)
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Behavioural/Makefile.Component (modified) (2 diffs)
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Behavioural/Makefile.Selftest (modified) (6 diffs)
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Behavioural/Makefile.Synthesis (modified) (3 diffs)
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Behavioural/include/Constants.h (modified) (1 diff)
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Behavioural/include/Parameters.h (modified) (1 diff)
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Behavioural/include/Version.h (modified) (1 diff)
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Behavioural/src/Parameters.cpp (modified) (1 diff)
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Behavioural/src/Parameters_copy.cpp (modified) (1 diff)
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Behavioural/src/SPR_access_mode_implement_group.cpp (modified) (1 diff)
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Behavioural/src/Simulation_test_end.cpp (modified) (1 diff)
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Common/include/ErrorMorpheo.h (modified) (3 diffs)
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Common/src/MemCheck.cpp (modified) (2 diffs)
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Files/Instance_debug.cfg (deleted)
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Files/Instance_x1_w1_0.cfg (moved) (moved from trunk/IPs/systemC/processor/Morpheo/Files/Instance_min.cfg) (2 diffs)
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Files/Instance_x1_w1_1.cfg (moved) (moved from trunk/IPs/systemC/processor/Morpheo/Files/Instance_w1_1.cfg) (8 diffs)
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Files/Instance_x1_w1_2.cfg (moved) (moved from trunk/IPs/systemC/processor/Morpheo/Files/Instance_w1_2.cfg) (8 diffs)
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Files/Instance_x1_w1_3.cfg (moved) (moved from trunk/IPs/systemC/processor/Morpheo/Files/Instance_w1_3.cfg) (10 diffs)
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Files/Instance_x1_w1_4.cfg (moved) (moved from trunk/IPs/systemC/processor/Morpheo/Files/Instance_w1_4.cfg) (8 diffs)
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Files/Instance_x1_w2_1.cfg (moved) (moved from trunk/IPs/systemC/processor/Morpheo/Files/Instance_w2_1.cfg) (9 diffs)
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Files/Instance_x1_w2_2.cfg (added)
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Files/Instance_x1_w2_3.cfg (added)
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Files/Instance_x1_w2_4.cfg (added)
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Files/Instance_x1_w4_1.cfg (moved) (moved from trunk/IPs/systemC/processor/Morpheo/Files/Instance_w4_1.cfg) (6 diffs)
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Files/Instance_x1_w4_2.cfg (added)
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Files/Instance_x2_w1_0.cfg (added)
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Files/Instance_x2_w1_1.cfg (added)
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Files/Instance_x2_w1_2.cfg (added)
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Files/Instance_x2_w1_3.cfg (added)
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Files/Instance_x2_w1_4.cfg (added)
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Files/Morpheo.gen (modified) (1 diff)
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Files/Morpheo.sim (modified) (2 diffs)
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Files/debug.sim (added)
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Script/instruction_flow_diff.sh (added)
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Script/instruction_flow_dump.sh (moved) (moved from trunk/IPs/systemC/processor/Morpheo/Script/instruction_flow.sh) (1 diff)
Legend:
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trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/SelfTest/config-min.cfg
r88 r117 1 1 Core_Glue 2 2 1 1 +1 # nb_front_end 3 1 1 +1 # nb_context [0] [nb_front_end]4 1 1 +1 # nb_ooo_engine 5 1 1 +1 # nb_execute_loop 6 1 1 +1 # ooo_engine_nb_front_end [0] [nb_ooo_engine]7 1 1 +1 # ooo_engine_nb_execute_loop [0] [nb_ooo_engine]8 1 1 +1 # execute_loop_nb_ooo_engine [0] [nb_execute_loop]9 1 1 +1 # nb_inst_decod [0] [nb_front_end]10 1 1 +1 # front_end_nb_inst_branch_complete [0] [nb_front_end]11 1 1 +1 # ooo_engine_nb_inst_branch_complete [0] [nb_ooo_engine]12 1 1 +1 # nb_inst_insert [0] [nb_ooo_engine]13 1 1 +1 # nb_inst_issue [0] [nb_ooo_engine]14 1 1 +1 # nb_inst_execute [0][0] [nb_ooo_engine][ooo_engine_nb_execute_loop]15 1 1 +1 # nb_read_unit [0] [nb_execute_loop]16 1 1 +1 # nb_write_unit [0] [nb_execute_loop]3 1 1 +1 # nb_context [0] [nb_front_end] 4 1 1 +1 # nb_ooo_engine 5 1 1 +1 # nb_execute_loop 6 1 1 +1 # ooo_engine_nb_front_end [0] [nb_ooo_engine] 7 1 1 +1 # ooo_engine_nb_execute_loop [0] [nb_ooo_engine] 8 1 1 +1 # execute_loop_nb_ooo_engine [0] [nb_execute_loop] 9 1 1 +1 # nb_inst_decod [0] [nb_front_end] 10 1 1 +1 # front_end_nb_inst_branch_complete [0] [nb_front_end] 11 1 1 +1 # ooo_engine_nb_inst_branch_complete [0] [nb_ooo_engine] 12 1 1 +1 # nb_inst_insert [0] [nb_ooo_engine] 13 1 1 +1 # nb_inst_issue [0] [nb_ooo_engine] 14 1 1 +1 # nb_inst_execute [0][0] [nb_ooo_engine][ooo_engine_nb_execute_loop] 15 1 1 +1 # nb_read_unit [0] [nb_execute_loop] 16 1 1 +1 # nb_write_unit [0] [nb_execute_loop] 17 17 1 1 +1 # size_depth 18 18 1 1 +1 # size_rob_ptr … … 25 25 1 1 +1 # dispatch_priority 26 26 1 1 +1 # dispatch_load_balancing 27 1 1 +1 # table_dispatch [0][0][0][0] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit]28 0 0 +1 # translate_ooo_engine_num_front_end [0][0] [nb_ooo_engine][ooo_engine_nb_front_end]29 0 0 +1 # translate_ooo_engine_num_execute_loop [0][0] [nb_ooo_engine][ooo_engine_nb_execute_loop]30 0 0 +1 # translate_execute_loop_num_ooo_engine [0][0] [nb_execute_loop][execute_loop_nb_ooo_engine]27 1 1 +1 # table_dispatch [0][0][0][0] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 28 0 0 +1 # translate_ooo_engine_num_front_end [0][0] [nb_ooo_engine][ooo_engine_nb_front_end] 29 0 0 +1 # translate_ooo_engine_num_execute_loop [0][0] [nb_ooo_engine][ooo_engine_nb_execute_loop] 30 0 0 +1 # translate_execute_loop_num_ooo_engine [0][0] [nb_execute_loop][execute_loop_nb_ooo_engine] -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/SelfTest/src/main.cpp
r88 r117 25 25 err (_(" * ooo_engine_nb_inst_branch_complete [nb_ooo_engine] (uint32_t )\n")); 26 26 err (_(" * nb_inst_insert [nb_ooo_engine] (uint32_t )\n")); 27 err (_(" * nb_inst_issue [nb_ooo_engine] (uint32_t )\n")); 27 //err (_(" * nb_inst_issue_queue [nb_ooo_engine] (uint32_t )\n")); 28 err (_(" * nb_inst_issue_slot [nb_ooo_engine] (uint32_t )\n")); 28 29 err (_(" * nb_inst_execute [nb_ooo_engine][ooo_engine_nb_execute_loop] (uint32_t )\n")); 29 30 err (_(" * nb_read_unit [nb_execute_loop] (uint32_t )\n")); … … 40 41 err (_(" * dispatch_load_balancing (Tload_balancing_t)\n")); 41 42 err (_(" * table_dispatch [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] (bool )\n")); 43 // err (_(" * table_issue_type [execute_loop][nb_read_unit][MAX_TYPE] (bool )\n")); 44 // err (_(" * TYPE_ALU \n")); 45 // err (_(" * TYPE_SHIFT \n")); 46 // err (_(" * TYPE_MOVE \n")); 47 // err (_(" * TYPE_TEST \n")); 48 // err (_(" * TYPE_MUL \n")); 49 // err (_(" * TYPE_DIV \n")); 50 // err (_(" * TYPE_EXTEND \n")); 51 // err (_(" * TYPE_FIND \n")); 52 // err (_(" * TYPE_SPECIAL\n")); 53 // err (_(" * TYPE_CUSTOM \n")); 54 // err (_(" * TYPE_BRANCH \n")); 55 // err (_(" * TYPE_MEMORY \n")); 42 56 err (_(" * translate_ooo_engine_num_front_end [nb_ooo_engine][ooo_engine_nb_front_end] (uint32_t )\n")); 43 57 err (_(" * translate_ooo_engine_num_execute_loop [nb_ooo_engine][ooo_engine_nb_execute_loop] (uint32_t )\n")); … … 72 86 uint32_t * ooo_engine_nb_inst_branch_complete ;//[nb_ooo_engine] 73 87 uint32_t * nb_inst_insert ;//[nb_ooo_engine] 74 uint32_t * nb_inst_issue 88 uint32_t * nb_inst_issue_slot ;//[nb_ooo_engine] 75 89 uint32_t ** nb_inst_execute ;//[nb_ooo_engine][ooo_engine_nb_execute_loop] 76 90 uint32_t * nb_read_unit ;//[nb_execute_loop] … … 86 100 Tpriority_t dispatch_priority ; 87 101 Tload_balancing_t dispatch_load_balancing ; 88 bool **** table_dispatch ;//[nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 102 bool **** table_dispatch ;//[nb_ooo_engine][nb_inst_issue_slot][execute_loop][nb_read_unit] 103 bool *** table_issue_type ;// [execute_loop][nb_read_unit][MAX_TYPE] 89 104 uint32_t ** translate_ooo_engine_num_front_end ;//[nb_ooo_engine][ooo_engine_nb_front_end] 90 105 uint32_t ** translate_ooo_engine_num_execute_loop;//[nb_ooo_engine][ooo_engine_nb_execute_loop] … … 119 134 SELFTEST1(ooo_engine_nb_inst_branch_complete ,uint32_t ,argv,x,nb_ooo_engine); 120 135 SELFTEST1(nb_inst_insert ,uint32_t ,argv,x,nb_ooo_engine); 121 SELFTEST1(nb_inst_issue 136 SELFTEST1(nb_inst_issue_slot ,uint32_t ,argv,x,nb_ooo_engine); 122 137 123 138 uint32_t sum_ooo_engine_nb_front_end = 0; … … 129 144 sum_ooo_engine_nb_front_end += ooo_engine_nb_front_end [i]; 130 145 sum_ooo_engine_nb_execute_loop += ooo_engine_nb_execute_loop [i]; 131 sum_nb_inst_issue += nb_inst_issue 146 sum_nb_inst_issue += nb_inst_issue_slot [i]; 132 147 } 133 148 … … 177 192 SELFTEST0(dispatch_load_balancing ,Tload_balancing_t,argv,x); 178 193 179 SELFTEST4(table_dispatch ,bool ,argv,x,nb_ooo_engine,nb_inst_issue[it1],nb_execute_loop,nb_read_unit[it3]); 194 SELFTEST4(table_dispatch ,bool ,argv,x,nb_ooo_engine,nb_inst_issue_slot[it1],nb_execute_loop,nb_read_unit[it3]); 195 196 ALLOC3 (table_issue_type ,bool ,nb_execute_loop,nb_read_unit[it1],MAX_TYPE); 197 198 for (uint32_t i=0; i<nb_execute_loop; ++i) 199 for (uint32_t j=0; j<nb_read_unit[i]; ++j) 200 for (uint32_t k=0; k<MAX_TYPE; ++k) 201 // table_issue_type [i][j][k] = false; 202 table_issue_type [i][j][k] = true; 203 204 // for (uint32_t i=0; i<nb_execute_loop; ++i) 205 // for (uint32_t j=0; j<nb_read_unit[i]; ++j) 206 // { 207 // table_issue_type [i][j][TYPE_ALU ] = fromString<bool>(argv[x++]); 208 // table_issue_type [i][j][TYPE_SHIFT ] = fromString<bool>(argv[x++]); 209 // table_issue_type [i][j][TYPE_MOVE ] = fromString<bool>(argv[x++]); 210 // table_issue_type [i][j][TYPE_TEST ] = fromString<bool>(argv[x++]); 211 // table_issue_type [i][j][TYPE_MUL ] = fromString<bool>(argv[x++]); 212 // table_issue_type [i][j][TYPE_DIV ] = fromString<bool>(argv[x++]); 213 // table_issue_type [i][j][TYPE_EXTEND ] = fromString<bool>(argv[x++]); 214 // table_issue_type [i][j][TYPE_FIND ] = fromString<bool>(argv[x++]); 215 // table_issue_type [i][j][TYPE_SPECIAL] = fromString<bool>(argv[x++]); 216 // table_issue_type [i][j][TYPE_CUSTOM ] = fromString<bool>(argv[x++]); 217 // table_issue_type [i][j][TYPE_BRANCH ] = fromString<bool>(argv[x++]); 218 // table_issue_type [i][j][TYPE_MEMORY ] = fromString<bool>(argv[x++]); 219 // } 220 180 221 SELFTEST2(translate_ooo_engine_num_front_end ,uint32_t ,argv,x,nb_ooo_engine,ooo_engine_nb_front_end[it1]); 181 222 SELFTEST2(translate_ooo_engine_num_execute_loop,uint32_t ,argv,x,nb_ooo_engine,ooo_engine_nb_execute_loop[it1]); … … 198 239 ooo_engine_nb_inst_branch_complete ,//[nb_ooo_engine] 199 240 nb_inst_insert ,//[nb_ooo_engine] 200 nb_inst_issue ,//[nb_ooo_engine] 241 nb_inst_issue_slot ,//[nb_ooo_engine] 242 nb_inst_issue_slot ,//[nb_ooo_engine] 201 243 nb_inst_execute ,//[nb_ooo_engine][ooo_engine_nb_execute_loop] 202 244 nb_read_unit ,//[nb_execute_loop] … … 212 254 dispatch_priority , 213 255 dispatch_load_balancing , 214 table_dispatch ,//[nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 256 table_dispatch ,//[nb_ooo_engine][nb_inst_issue_slot][execute_loop][nb_read_unit] 257 table_issue_type ,// [execute_loop][nb_read_unit][MAX_TYPE] 215 258 translate_ooo_engine_num_front_end ,//[nb_ooo_engine][ooo_engine_nb_front_end] 216 259 translate_ooo_engine_num_execute_loop,//[nb_ooo_engine][ooo_engine_nb_execute_loop] … … 245 288 DELETE2(translate_ooo_engine_num_execute_loop,nb_ooo_engine,ooo_engine_nb_execute_loop[it1]); 246 289 DELETE2(translate_ooo_engine_num_front_end ,nb_ooo_engine,ooo_engine_nb_front_end[it1]); 247 DELETE4(table_dispatch ,nb_ooo_engine,nb_inst_issue[it1],nb_execute_loop,nb_read_unit[it2]); 290 DELETE3(table_issue_type ,nb_execute_loop,nb_read_unit[it1],MAX_TYPE); 291 DELETE4(table_dispatch ,nb_ooo_engine,nb_inst_issue_slot[it1],nb_execute_loop,nb_read_unit[it2]); 248 292 DELETE1(nb_write_unit ,nb_execute_loop); 249 293 DELETE1(nb_read_unit ,nb_execute_loop); 250 294 DELETE2(nb_inst_execute ,nb_ooo_engine,ooo_engine_nb_execute_loop[it1]); 251 DELETE1(nb_inst_issue 295 DELETE1(nb_inst_issue_slot ,nb_ooo_engine); 252 296 DELETE1(ooo_engine_nb_inst_branch_complete ,nb_ooo_engine); 253 297 DELETE1(front_end_nb_inst_branch_complete ,nb_front_end); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/SelfTest/src/test.cpp
r105 r117 48 48 sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5); 49 49 sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET"); 50 51 sc_signal<Tcontext_t > *** out_RENAME_FRONT_END_ID ; 52 sc_signal<Tcontrol_t > *** out_BRANCH_COMPLETE_FRONT_END_VAL ; 53 sc_signal<Tcontrol_t > *** in_BRANCH_COMPLETE_FRONT_END_ACK ; 54 sc_signal<Tcontext_t > *** out_BRANCH_COMPLETE_FRONT_END_CONTEXT_ID ; 55 sc_signal<Tdepth_t > *** out_BRANCH_COMPLETE_FRONT_END_DEPTH ; 56 sc_signal<Taddress_t > *** out_BRANCH_COMPLETE_FRONT_END_ADDRESS ; 57 sc_signal<Tcontrol_t > *** out_BRANCH_COMPLETE_FRONT_END_NO_SEQUENCE ; 58 sc_signal<Tcontrol_t > *** in_BRANCH_COMPLETE_FRONT_END_MISS_PREDICTION ; 59 sc_signal<Tcontrol_t > *** in_BRANCH_COMPLETE_OOO_ENGINE_VAL ; 60 sc_signal<Tcontrol_t > *** out_BRANCH_COMPLETE_OOO_ENGINE_ACK ; 61 sc_signal<Tcontext_t > *** in_BRANCH_COMPLETE_OOO_ENGINE_FRONT_END_ID ; 62 sc_signal<Tcontext_t > *** in_BRANCH_COMPLETE_OOO_ENGINE_CONTEXT_ID ; 63 sc_signal<Tdepth_t > *** in_BRANCH_COMPLETE_OOO_ENGINE_DEPTH ; 64 sc_signal<Taddress_t > *** in_BRANCH_COMPLETE_OOO_ENGINE_ADDRESS ; 65 sc_signal<Tcontrol_t > *** in_BRANCH_COMPLETE_OOO_ENGINE_NO_SEQUENCE ; 66 sc_signal<Tcontrol_t > *** out_BRANCH_COMPLETE_OOO_ENGINE_MISS_PREDICTION; 67 sc_signal<Tcontrol_t > ** out_COMMIT_EVENT_FRONT_END_VAL ; 68 sc_signal<Tcontrol_t > ** in_COMMIT_EVENT_FRONT_END_ACK ; 69 sc_signal<Tcontext_t > ** out_COMMIT_EVENT_FRONT_END_CONTEXT_ID ; 70 sc_signal<Tdepth_t > ** out_COMMIT_EVENT_FRONT_END_DEPTH ; 71 sc_signal<Tevent_type_t > ** out_COMMIT_EVENT_FRONT_END_TYPE ; 72 sc_signal<Tcontrol_t > ** out_COMMIT_EVENT_FRONT_END_IS_DELAY_SLOT ; 73 sc_signal<Taddress_t > ** out_COMMIT_EVENT_FRONT_END_ADDRESS ; 74 sc_signal<Tcontrol_t > ** out_COMMIT_EVENT_FRONT_END_ADDRESS_EPCR_VAL ; 75 sc_signal<Taddress_t > ** out_COMMIT_EVENT_FRONT_END_ADDRESS_EPCR ; 76 sc_signal<Tcontrol_t > ** out_COMMIT_EVENT_FRONT_END_ADDRESS_EEAR_VAL ; 77 sc_signal<Tgeneral_data_t > ** out_COMMIT_EVENT_FRONT_END_ADDRESS_EEAR ; 78 sc_signal<Tcontrol_t > ** in_COMMIT_EVENT_OOO_ENGINE_VAL ; 79 sc_signal<Tcontrol_t > ** out_COMMIT_EVENT_OOO_ENGINE_ACK ; 80 sc_signal<Tcontext_t > ** in_COMMIT_EVENT_OOO_ENGINE_FRONT_END_ID ; 81 sc_signal<Tcontext_t > ** in_COMMIT_EVENT_OOO_ENGINE_CONTEXT_ID ; 82 sc_signal<Tdepth_t > ** in_COMMIT_EVENT_OOO_ENGINE_DEPTH ; 83 sc_signal<Tevent_type_t > ** in_COMMIT_EVENT_OOO_ENGINE_TYPE ; 84 sc_signal<Tcontrol_t > ** in_COMMIT_EVENT_OOO_ENGINE_IS_DELAY_SLOT ; 85 sc_signal<Taddress_t > ** in_COMMIT_EVENT_OOO_ENGINE_ADDRESS ; 86 sc_signal<Tcontrol_t > ** in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EPCR_VAL ; 87 sc_signal<Taddress_t > ** in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EPCR ; 88 sc_signal<Tcontrol_t > ** in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EEAR_VAL ; 89 sc_signal<Tgeneral_data_t > ** in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EEAR ; 90 sc_signal<Tcontrol_t > *** in_ISSUE_OOO_ENGINE_VAL ; 91 sc_signal<Tcontrol_t > *** out_ISSUE_OOO_ENGINE_ACK ; 92 sc_signal<Tcontext_t > *** in_ISSUE_OOO_ENGINE_FRONT_END_ID ; 93 sc_signal<Tcontext_t > *** in_ISSUE_OOO_ENGINE_CONTEXT_ID ; 94 sc_signal<Tpacket_t > *** in_ISSUE_OOO_ENGINE_PACKET_ID ; 95 sc_signal<Ttype_t > *** in_ISSUE_OOO_ENGINE_TYPE ; 96 sc_signal<Toperation_t > *** in_ISSUE_OOO_ENGINE_OPERATION ; 97 sc_signal<Tlsq_ptr_t > *** in_ISSUE_OOO_ENGINE_STORE_QUEUE_PTR_WRITE ; 98 sc_signal<Tlsq_ptr_t > *** in_ISSUE_OOO_ENGINE_LOAD_QUEUE_PTR_WRITE ; 99 sc_signal<Tcontrol_t > *** in_ISSUE_OOO_ENGINE_HAS_IMMEDIAT ; 100 sc_signal<Tgeneral_data_t > *** in_ISSUE_OOO_ENGINE_IMMEDIAT ; 101 sc_signal<Tcontrol_t > *** in_ISSUE_OOO_ENGINE_READ_RA ; 102 sc_signal<Tgeneral_address_t> *** in_ISSUE_OOO_ENGINE_NUM_REG_RA ; 103 sc_signal<Tcontrol_t > *** in_ISSUE_OOO_ENGINE_READ_RB ; 104 sc_signal<Tgeneral_address_t> *** in_ISSUE_OOO_ENGINE_NUM_REG_RB ; 105 sc_signal<Tcontrol_t > *** in_ISSUE_OOO_ENGINE_READ_RC ; 106 sc_signal<Tspecial_address_t> *** in_ISSUE_OOO_ENGINE_NUM_REG_RC ; 107 sc_signal<Tcontrol_t > *** in_ISSUE_OOO_ENGINE_WRITE_RD ; 108 sc_signal<Tgeneral_address_t> *** in_ISSUE_OOO_ENGINE_NUM_REG_RD ; 109 sc_signal<Tcontrol_t > *** in_ISSUE_OOO_ENGINE_WRITE_RE ; 110 sc_signal<Tspecial_address_t> *** in_ISSUE_OOO_ENGINE_NUM_REG_RE ; 111 sc_signal<Tcontrol_t > *** out_ISSUE_EXECUTE_LOOP_VAL ; 112 sc_signal<Tcontrol_t > *** in_ISSUE_EXECUTE_LOOP_ACK ; 113 sc_signal<Tcontext_t > *** out_ISSUE_EXECUTE_LOOP_CONTEXT_ID ; 114 sc_signal<Tcontext_t > *** out_ISSUE_EXECUTE_LOOP_FRONT_END_ID ; 115 sc_signal<Tcontext_t > *** out_ISSUE_EXECUTE_LOOP_OOO_ENGINE_ID ; 116 sc_signal<Tpacket_t > *** out_ISSUE_EXECUTE_LOOP_PACKET_ID ; 117 sc_signal<Toperation_t > *** out_ISSUE_EXECUTE_LOOP_OPERATION ; 118 sc_signal<Ttype_t > *** out_ISSUE_EXECUTE_LOOP_TYPE ; 119 sc_signal<Tlsq_ptr_t > *** out_ISSUE_EXECUTE_LOOP_STORE_QUEUE_PTR_WRITE ; 120 sc_signal<Tlsq_ptr_t > *** out_ISSUE_EXECUTE_LOOP_LOAD_QUEUE_PTR_WRITE ; 121 sc_signal<Tcontrol_t > *** out_ISSUE_EXECUTE_LOOP_HAS_IMMEDIAT ; 122 sc_signal<Tgeneral_data_t > *** out_ISSUE_EXECUTE_LOOP_IMMEDIAT ; 123 sc_signal<Tcontrol_t > *** out_ISSUE_EXECUTE_LOOP_READ_RA ; 124 sc_signal<Tgeneral_address_t> *** out_ISSUE_EXECUTE_LOOP_NUM_REG_RA ; 125 sc_signal<Tcontrol_t > *** out_ISSUE_EXECUTE_LOOP_READ_RB ; 126 sc_signal<Tgeneral_address_t> *** out_ISSUE_EXECUTE_LOOP_NUM_REG_RB ; 127 sc_signal<Tcontrol_t > *** out_ISSUE_EXECUTE_LOOP_READ_RC ; 128 sc_signal<Tspecial_address_t> *** out_ISSUE_EXECUTE_LOOP_NUM_REG_RC ; 129 sc_signal<Tcontrol_t > *** out_ISSUE_EXECUTE_LOOP_WRITE_RD ; 130 sc_signal<Tgeneral_address_t> *** out_ISSUE_EXECUTE_LOOP_NUM_REG_RD ; 131 sc_signal<Tcontrol_t > *** out_ISSUE_EXECUTE_LOOP_WRITE_RE ; 132 sc_signal<Tspecial_address_t> *** out_ISSUE_EXECUTE_LOOP_NUM_REG_RE ; 133 sc_signal<Tcontrol_t > **** out_EXECUTE_OOO_ENGINE_VAL ; 134 sc_signal<Tcontrol_t > **** in_EXECUTE_OOO_ENGINE_ACK ; 135 sc_signal<Tcontext_t > **** out_EXECUTE_OOO_ENGINE_FRONT_END_ID ; 136 sc_signal<Tcontext_t > **** out_EXECUTE_OOO_ENGINE_CONTEXT_ID ; 137 sc_signal<Tpacket_t > **** out_EXECUTE_OOO_ENGINE_PACKET_ID ; 138 //sc_signal<Ttype_t > **** out_EXECUTE_OOO_ENGINE_TYPE ; 139 //sc_signal<Toperation_t > **** out_EXECUTE_OOO_ENGINE_OPERATION ; 140 sc_signal<Tspecial_data_t > **** out_EXECUTE_OOO_ENGINE_FLAGS ; 141 sc_signal<Texception_t > **** out_EXECUTE_OOO_ENGINE_EXCEPTION ; 142 sc_signal<Tcontrol_t > **** out_EXECUTE_OOO_ENGINE_NO_SEQUENCE ; 143 sc_signal<Taddress_t > **** out_EXECUTE_OOO_ENGINE_ADDRESS ; 144 sc_signal<Tgeneral_data_t > **** out_EXECUTE_OOO_ENGINE_DATA ; 145 sc_signal<Tcontrol_t > *** in_EXECUTE_EXECUTE_LOOP_VAL ; 146 sc_signal<Tcontrol_t > *** out_EXECUTE_EXECUTE_LOOP_ACK ; 147 sc_signal<Tcontext_t > *** in_EXECUTE_EXECUTE_LOOP_CONTEXT_ID ; 148 sc_signal<Tcontext_t > *** in_EXECUTE_EXECUTE_LOOP_FRONT_END_ID ; 149 sc_signal<Tcontext_t > *** in_EXECUTE_EXECUTE_LOOP_OOO_ENGINE_ID ; 150 sc_signal<Tpacket_t > *** in_EXECUTE_EXECUTE_LOOP_PACKET_ID ; 151 //sc_signal<Toperation_t > *** in_EXECUTE_EXECUTE_LOOP_OPERATION ; 152 //sc_signal<Ttype_t > *** in_EXECUTE_EXECUTE_LOOP_TYPE ; 153 sc_signal<Tspecial_data_t > *** in_EXECUTE_EXECUTE_LOOP_FLAGS ; 154 sc_signal<Texception_t > *** in_EXECUTE_EXECUTE_LOOP_EXCEPTION ; 155 sc_signal<Tcontrol_t > *** in_EXECUTE_EXECUTE_LOOP_NO_SEQUENCE ; 156 sc_signal<Taddress_t > *** in_EXECUTE_EXECUTE_LOOP_ADDRESS ; 157 sc_signal<Tgeneral_data_t > *** in_EXECUTE_EXECUTE_LOOP_DATA ; 158 sc_signal<Tcontrol_t > *** in_INSERT_OOO_ENGINE_VAL ; 159 sc_signal<Tcontrol_t > *** out_INSERT_OOO_ENGINE_ACK ; 160 sc_signal<Tcontrol_t > *** in_INSERT_OOO_ENGINE_RD_USE ; 161 sc_signal<Tgeneral_address_t> *** in_INSERT_OOO_ENGINE_RD_NUM_REG ; 162 sc_signal<Tcontrol_t > *** in_INSERT_OOO_ENGINE_RE_USE ; 163 sc_signal<Tspecial_address_t> *** in_INSERT_OOO_ENGINE_RE_NUM_REG ; 164 sc_signal<Tcontrol_t > **** out_INSERT_EXECUTE_LOOP_VAL ; 165 sc_signal<Tcontrol_t > **** in_INSERT_EXECUTE_LOOP_ACK ; 166 sc_signal<Tcontrol_t > **** out_INSERT_EXECUTE_LOOP_RD_USE ; 167 sc_signal<Tgeneral_address_t> **** out_INSERT_EXECUTE_LOOP_RD_NUM_REG ; 168 sc_signal<Tcontrol_t > **** out_INSERT_EXECUTE_LOOP_RE_USE ; 169 sc_signal<Tspecial_address_t> **** out_INSERT_EXECUTE_LOOP_RE_NUM_REG ; 50 170 51 171 ALLOC2_SC_SIGNAL(out_RENAME_FRONT_END_ID ,"out_RENAME_FRONT_END_ID ",Tcontext_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); … … 88 208 ALLOC1_SC_SIGNAL( in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EEAR_VAL ," in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EEAR_VAL ",Tcontrol_t ,_param->_nb_ooo_engine); 89 209 ALLOC1_SC_SIGNAL( in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EEAR ," in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EEAR ",Tgeneral_data_t ,_param->_nb_ooo_engine); 90 ALLOC2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_VAL ," in_ISSUE_OOO_ENGINE_VAL ",Tcontrol_t ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1]);91 ALLOC2_SC_SIGNAL(out_ISSUE_OOO_ENGINE_ACK ,"out_ISSUE_OOO_ENGINE_ACK ",Tcontrol_t ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1]);92 ALLOC2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_FRONT_END_ID ," in_ISSUE_OOO_ENGINE_FRONT_END_ID ",Tcontext_t ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1]);93 ALLOC2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_CONTEXT_ID ," in_ISSUE_OOO_ENGINE_CONTEXT_ID ",Tcontext_t ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1]);94 ALLOC2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_PACKET_ID ," in_ISSUE_OOO_ENGINE_PACKET_ID ",Tpacket_t ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1]);95 ALLOC2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_TYPE ," in_ISSUE_OOO_ENGINE_TYPE ",Ttype_t ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1]);96 ALLOC2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_OPERATION ," in_ISSUE_OOO_ENGINE_OPERATION ",Toperation_t ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1]);97 ALLOC2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_STORE_QUEUE_PTR_WRITE ," in_ISSUE_OOO_ENGINE_STORE_QUEUE_PTR_WRITE ",Tlsq_ptr_t ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1]);98 ALLOC2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_LOAD_QUEUE_PTR_WRITE ," in_ISSUE_OOO_ENGINE_LOAD_QUEUE_PTR_WRITE ",Tlsq_ptr_t ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1]);99 ALLOC2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_HAS_IMMEDIAT ," in_ISSUE_OOO_ENGINE_HAS_IMMEDIAT ",Tcontrol_t ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1]);100 ALLOC2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_IMMEDIAT ," in_ISSUE_OOO_ENGINE_IMMEDIAT ",Tgeneral_data_t ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1]);101 ALLOC2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_READ_RA ," in_ISSUE_OOO_ENGINE_READ_RA ",Tcontrol_t ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1]);102 ALLOC2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_NUM_REG_RA ," in_ISSUE_OOO_ENGINE_NUM_REG_RA ",Tgeneral_address_t,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1]);103 ALLOC2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_READ_RB ," in_ISSUE_OOO_ENGINE_READ_RB ",Tcontrol_t ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1]);104 ALLOC2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_NUM_REG_RB ," in_ISSUE_OOO_ENGINE_NUM_REG_RB ",Tgeneral_address_t,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1]);105 ALLOC2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_READ_RC ," in_ISSUE_OOO_ENGINE_READ_RC ",Tcontrol_t ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1]);106 ALLOC2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_NUM_REG_RC ," in_ISSUE_OOO_ENGINE_NUM_REG_RC ",Tspecial_address_t,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1]);107 ALLOC2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_WRITE_RD ," in_ISSUE_OOO_ENGINE_WRITE_RD ",Tcontrol_t ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1]);108 ALLOC2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_NUM_REG_RD ," in_ISSUE_OOO_ENGINE_NUM_REG_RD ",Tgeneral_address_t,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1]);109 ALLOC2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_WRITE_RE ," in_ISSUE_OOO_ENGINE_WRITE_RE ",Tcontrol_t ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1]);110 ALLOC2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_NUM_REG_RE ," in_ISSUE_OOO_ENGINE_NUM_REG_RE ",Tspecial_address_t,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1]);210 ALLOC2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_VAL ," in_ISSUE_OOO_ENGINE_VAL ",Tcontrol_t ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]); 211 ALLOC2_SC_SIGNAL(out_ISSUE_OOO_ENGINE_ACK ,"out_ISSUE_OOO_ENGINE_ACK ",Tcontrol_t ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]); 212 ALLOC2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_FRONT_END_ID ," in_ISSUE_OOO_ENGINE_FRONT_END_ID ",Tcontext_t ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]); 213 ALLOC2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_CONTEXT_ID ," in_ISSUE_OOO_ENGINE_CONTEXT_ID ",Tcontext_t ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]); 214 ALLOC2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_PACKET_ID ," in_ISSUE_OOO_ENGINE_PACKET_ID ",Tpacket_t ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]); 215 ALLOC2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_TYPE ," in_ISSUE_OOO_ENGINE_TYPE ",Ttype_t ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]); 216 ALLOC2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_OPERATION ," in_ISSUE_OOO_ENGINE_OPERATION ",Toperation_t ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]); 217 ALLOC2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_STORE_QUEUE_PTR_WRITE ," in_ISSUE_OOO_ENGINE_STORE_QUEUE_PTR_WRITE ",Tlsq_ptr_t ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]); 218 ALLOC2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_LOAD_QUEUE_PTR_WRITE ," in_ISSUE_OOO_ENGINE_LOAD_QUEUE_PTR_WRITE ",Tlsq_ptr_t ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]); 219 ALLOC2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_HAS_IMMEDIAT ," in_ISSUE_OOO_ENGINE_HAS_IMMEDIAT ",Tcontrol_t ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]); 220 ALLOC2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_IMMEDIAT ," in_ISSUE_OOO_ENGINE_IMMEDIAT ",Tgeneral_data_t ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]); 221 ALLOC2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_READ_RA ," in_ISSUE_OOO_ENGINE_READ_RA ",Tcontrol_t ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]); 222 ALLOC2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_NUM_REG_RA ," in_ISSUE_OOO_ENGINE_NUM_REG_RA ",Tgeneral_address_t,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]); 223 ALLOC2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_READ_RB ," in_ISSUE_OOO_ENGINE_READ_RB ",Tcontrol_t ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]); 224 ALLOC2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_NUM_REG_RB ," in_ISSUE_OOO_ENGINE_NUM_REG_RB ",Tgeneral_address_t,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]); 225 ALLOC2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_READ_RC ," in_ISSUE_OOO_ENGINE_READ_RC ",Tcontrol_t ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]); 226 ALLOC2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_NUM_REG_RC ," in_ISSUE_OOO_ENGINE_NUM_REG_RC ",Tspecial_address_t,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]); 227 ALLOC2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_WRITE_RD ," in_ISSUE_OOO_ENGINE_WRITE_RD ",Tcontrol_t ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]); 228 ALLOC2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_NUM_REG_RD ," in_ISSUE_OOO_ENGINE_NUM_REG_RD ",Tgeneral_address_t,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]); 229 ALLOC2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_WRITE_RE ," in_ISSUE_OOO_ENGINE_WRITE_RE ",Tcontrol_t ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]); 230 ALLOC2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_NUM_REG_RE ," in_ISSUE_OOO_ENGINE_NUM_REG_RE ",Tspecial_address_t,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]); 111 231 ALLOC2_SC_SIGNAL(out_ISSUE_EXECUTE_LOOP_VAL ,"out_ISSUE_EXECUTE_LOOP_VAL ",Tcontrol_t ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); 112 232 ALLOC2_SC_SIGNAL( in_ISSUE_EXECUTE_LOOP_ACK ," in_ISSUE_EXECUTE_LOOP_ACK ",Tcontrol_t ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); … … 168 288 ALLOC3_SC_SIGNAL(out_INSERT_EXECUTE_LOOP_RE_USE ,"out_INSERT_EXECUTE_LOOP_RE_USE ",Tcontrol_t ,_param->_nb_execute_loop,_param->_execute_loop_nb_ooo_engine[it1],_param->_execute_loop_nb_inst_insert[it1][it2]); 169 289 ALLOC3_SC_SIGNAL(out_INSERT_EXECUTE_LOOP_RE_NUM_REG ,"out_INSERT_EXECUTE_LOOP_RE_NUM_REG ",Tspecial_address_t ,_param->_nb_execute_loop,_param->_execute_loop_nb_ooo_engine[it1],_param->_execute_loop_nb_inst_insert[it1][it2]); 170 171 290 172 291 /******************************************************** … … 229 348 INSTANCE1_SC_SIGNAL(_Core_Glue, in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EEAR_VAL ,_param->_nb_ooo_engine); 230 349 INSTANCE1_SC_SIGNAL(_Core_Glue, in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EEAR ,_param->_nb_ooo_engine); 231 INSTANCE2_SC_SIGNAL(_Core_Glue, in_ISSUE_OOO_ENGINE_VAL ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1]);232 INSTANCE2_SC_SIGNAL(_Core_Glue,out_ISSUE_OOO_ENGINE_ACK ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1]);350 INSTANCE2_SC_SIGNAL(_Core_Glue, in_ISSUE_OOO_ENGINE_VAL ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]); 351 INSTANCE2_SC_SIGNAL(_Core_Glue,out_ISSUE_OOO_ENGINE_ACK ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]); 233 352 if (_param->_have_port_front_end_id) 234 INSTANCE2_SC_SIGNAL(_Core_Glue, in_ISSUE_OOO_ENGINE_FRONT_END_ID ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1]);353 INSTANCE2_SC_SIGNAL(_Core_Glue, in_ISSUE_OOO_ENGINE_FRONT_END_ID ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]); 235 354 if (_param->_have_port_context_id) 236 INSTANCE2_SC_SIGNAL(_Core_Glue, in_ISSUE_OOO_ENGINE_CONTEXT_ID ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1]);355 INSTANCE2_SC_SIGNAL(_Core_Glue, in_ISSUE_OOO_ENGINE_CONTEXT_ID ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]); 237 356 if (_param->_have_port_rob_ptr) 238 INSTANCE2_SC_SIGNAL(_Core_Glue, in_ISSUE_OOO_ENGINE_PACKET_ID ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1]);239 INSTANCE2_SC_SIGNAL(_Core_Glue, in_ISSUE_OOO_ENGINE_TYPE ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1]);240 INSTANCE2_SC_SIGNAL(_Core_Glue, in_ISSUE_OOO_ENGINE_OPERATION ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1]);241 INSTANCE2_SC_SIGNAL(_Core_Glue, in_ISSUE_OOO_ENGINE_STORE_QUEUE_PTR_WRITE ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1]);357 INSTANCE2_SC_SIGNAL(_Core_Glue, in_ISSUE_OOO_ENGINE_PACKET_ID ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]); 358 INSTANCE2_SC_SIGNAL(_Core_Glue, in_ISSUE_OOO_ENGINE_TYPE ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]); 359 INSTANCE2_SC_SIGNAL(_Core_Glue, in_ISSUE_OOO_ENGINE_OPERATION ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]); 360 INSTANCE2_SC_SIGNAL(_Core_Glue, in_ISSUE_OOO_ENGINE_STORE_QUEUE_PTR_WRITE ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]); 242 361 if (_param->_have_port_load_queue_ptr) 243 INSTANCE2_SC_SIGNAL(_Core_Glue, in_ISSUE_OOO_ENGINE_LOAD_QUEUE_PTR_WRITE ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1]);244 INSTANCE2_SC_SIGNAL(_Core_Glue, in_ISSUE_OOO_ENGINE_HAS_IMMEDIAT ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1]);245 INSTANCE2_SC_SIGNAL(_Core_Glue, in_ISSUE_OOO_ENGINE_IMMEDIAT ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1]);246 INSTANCE2_SC_SIGNAL(_Core_Glue, in_ISSUE_OOO_ENGINE_READ_RA ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1]);247 INSTANCE2_SC_SIGNAL(_Core_Glue, in_ISSUE_OOO_ENGINE_NUM_REG_RA ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1]);248 INSTANCE2_SC_SIGNAL(_Core_Glue, in_ISSUE_OOO_ENGINE_READ_RB ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1]);249 INSTANCE2_SC_SIGNAL(_Core_Glue, in_ISSUE_OOO_ENGINE_NUM_REG_RB ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1]);250 INSTANCE2_SC_SIGNAL(_Core_Glue, in_ISSUE_OOO_ENGINE_READ_RC ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1]);251 INSTANCE2_SC_SIGNAL(_Core_Glue, in_ISSUE_OOO_ENGINE_NUM_REG_RC ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1]);252 INSTANCE2_SC_SIGNAL(_Core_Glue, in_ISSUE_OOO_ENGINE_WRITE_RD ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1]);253 INSTANCE2_SC_SIGNAL(_Core_Glue, in_ISSUE_OOO_ENGINE_NUM_REG_RD ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1]);254 INSTANCE2_SC_SIGNAL(_Core_Glue, in_ISSUE_OOO_ENGINE_WRITE_RE ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1]);255 INSTANCE2_SC_SIGNAL(_Core_Glue, in_ISSUE_OOO_ENGINE_NUM_REG_RE ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1]);362 INSTANCE2_SC_SIGNAL(_Core_Glue, in_ISSUE_OOO_ENGINE_LOAD_QUEUE_PTR_WRITE ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]); 363 INSTANCE2_SC_SIGNAL(_Core_Glue, in_ISSUE_OOO_ENGINE_HAS_IMMEDIAT ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]); 364 INSTANCE2_SC_SIGNAL(_Core_Glue, in_ISSUE_OOO_ENGINE_IMMEDIAT ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]); 365 INSTANCE2_SC_SIGNAL(_Core_Glue, in_ISSUE_OOO_ENGINE_READ_RA ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]); 366 INSTANCE2_SC_SIGNAL(_Core_Glue, in_ISSUE_OOO_ENGINE_NUM_REG_RA ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]); 367 INSTANCE2_SC_SIGNAL(_Core_Glue, in_ISSUE_OOO_ENGINE_READ_RB ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]); 368 INSTANCE2_SC_SIGNAL(_Core_Glue, in_ISSUE_OOO_ENGINE_NUM_REG_RB ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]); 369 INSTANCE2_SC_SIGNAL(_Core_Glue, in_ISSUE_OOO_ENGINE_READ_RC ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]); 370 INSTANCE2_SC_SIGNAL(_Core_Glue, in_ISSUE_OOO_ENGINE_NUM_REG_RC ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]); 371 INSTANCE2_SC_SIGNAL(_Core_Glue, in_ISSUE_OOO_ENGINE_WRITE_RD ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]); 372 INSTANCE2_SC_SIGNAL(_Core_Glue, in_ISSUE_OOO_ENGINE_NUM_REG_RD ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]); 373 INSTANCE2_SC_SIGNAL(_Core_Glue, in_ISSUE_OOO_ENGINE_WRITE_RE ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]); 374 INSTANCE2_SC_SIGNAL(_Core_Glue, in_ISSUE_OOO_ENGINE_NUM_REG_RE ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]); 256 375 INSTANCE2_SC_SIGNAL(_Core_Glue,out_ISSUE_EXECUTE_LOOP_VAL ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); 257 376 INSTANCE2_SC_SIGNAL(_Core_Glue, in_ISSUE_EXECUTE_LOOP_ACK ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); … … 476 595 477 596 for (uint32_t i=0; i<_param->_nb_ooo_engine; ++i) 478 for (uint32_t j=0; j<_param->_nb_inst_issue [i]; ++j)597 for (uint32_t j=0; j<_param->_nb_inst_issue_queue[i]; ++j) 479 598 { 480 599 Tcontext_t front_end_id = rand() % _param->_ooo_engine_nb_front_end [i]; … … 714 833 DELETE1_SC_SIGNAL( in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EEAR_VAL ,_param->_nb_ooo_engine); 715 834 DELETE1_SC_SIGNAL( in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EEAR ,_param->_nb_ooo_engine); 716 DELETE2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_VAL ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1]);717 DELETE2_SC_SIGNAL(out_ISSUE_OOO_ENGINE_ACK ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1]);718 DELETE2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_FRONT_END_ID ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1]);719 DELETE2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_CONTEXT_ID ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1]);720 DELETE2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_PACKET_ID ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1]);721 DELETE2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_TYPE ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1]);722 DELETE2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_OPERATION ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1]);723 DELETE2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_STORE_QUEUE_PTR_WRITE ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1]);724 DELETE2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_LOAD_QUEUE_PTR_WRITE ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1]);725 DELETE2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_HAS_IMMEDIAT ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1]);726 DELETE2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_IMMEDIAT ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1]);727 DELETE2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_READ_RA ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1]);728 DELETE2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_NUM_REG_RA ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1]);729 DELETE2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_READ_RB ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1]);730 DELETE2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_NUM_REG_RB ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1]);731 DELETE2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_READ_RC ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1]);732 DELETE2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_NUM_REG_RC ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1]);733 DELETE2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_WRITE_RD ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1]);734 DELETE2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_NUM_REG_RD ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1]);735 DELETE2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_WRITE_RE ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1]);736 DELETE2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_NUM_REG_RE ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1]);835 DELETE2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_VAL ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]); 836 DELETE2_SC_SIGNAL(out_ISSUE_OOO_ENGINE_ACK ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]); 837 DELETE2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_FRONT_END_ID ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]); 838 DELETE2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_CONTEXT_ID ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]); 839 DELETE2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_PACKET_ID ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]); 840 DELETE2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_TYPE ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]); 841 DELETE2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_OPERATION ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]); 842 DELETE2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_STORE_QUEUE_PTR_WRITE ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]); 843 DELETE2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_LOAD_QUEUE_PTR_WRITE ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]); 844 DELETE2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_HAS_IMMEDIAT ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]); 845 DELETE2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_IMMEDIAT ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]); 846 DELETE2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_READ_RA ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]); 847 DELETE2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_NUM_REG_RA ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]); 848 DELETE2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_READ_RB ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]); 849 DELETE2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_NUM_REG_RB ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]); 850 DELETE2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_READ_RC ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]); 851 DELETE2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_NUM_REG_RC ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]); 852 DELETE2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_WRITE_RD ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]); 853 DELETE2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_NUM_REG_RD ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]); 854 DELETE2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_WRITE_RE ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]); 855 DELETE2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_NUM_REG_RE ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]); 737 856 DELETE2_SC_SIGNAL(out_ISSUE_EXECUTE_LOOP_VAL ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); 738 857 DELETE2_SC_SIGNAL( in_ISSUE_EXECUTE_LOOP_ACK ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/include/Core_Glue.h
r111 r117 204 204 205 205 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 206 private : generic::priority::Priority ** _priority_ooo_engine; //[nb_execute_loop] 206 //private : generic::priority::Priority ** _priority_ooo_engine; //[nb_execute_loop] 207 private : generic::priority::Priority * _priority_ooo_engine; 207 208 private : generic::priority::Priority ** _priority_read_unit ; //[nb_execute_loop] 208 209 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/include/Parameters.h
r88 r117 18 18 namespace core_glue { 19 19 20 21 20 class Parameters : public morpheo::behavioural::Parameters 22 21 { … … 33 32 public : uint32_t * _ooo_engine_nb_inst_branch_complete ;//[nb_ooo_engine] 34 33 public : uint32_t * _nb_inst_insert ;//[nb_ooo_engine] 35 public : uint32_t * _nb_inst_issue ;//[nb_ooo_engine] 34 public : uint32_t * _nb_inst_reexecute ;//[nb_ooo_engine] 35 public : uint32_t * _nb_inst_issue_queue ;//[nb_ooo_engine] 36 public : uint32_t * _nb_inst_issue_slot ;//[nb_ooo_engine] 36 37 public : uint32_t ** _nb_inst_execute ;//[nb_ooo_engine][ooo_engine_nb_execute_loop] 38 public : bool * _issue_queue_in_order ;//[nb_ooo_engine] 37 39 public : uint32_t * _nb_read_unit ;//[nb_execute_loop] 38 40 public : uint32_t * _nb_write_unit ;//[nb_execute_loop] … … 50 52 public : Tpriority_t _dispatch_priority ; 51 53 public : Tload_balancing_t _dispatch_load_balancing ; 52 public : bool **** _table_dispatch ;//[nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 54 public : bool **** _table_dispatch ;//[nb_ooo_engine][nb_inst_issue_slot][execute_loop][nb_read_unit] 55 public : bool *** _table_issue_type ;// [execute_loop][nb_read_unit][nb_type] 53 56 public : uint32_t ** _translate_ooo_engine_num_front_end ;//[nb_ooo_engine][ooo_engine_nb_front_end] 54 57 public : uint32_t ** _translate_ooo_engine_num_execute_loop;//[nb_ooo_engine][ooo_engine_nb_execute_loop] … … 61 64 62 65 public : uint32_t ** _execute_loop_nb_inst_insert ;//[nb_execute_loop][execute_loop_nb_ooo_engine] 63 public : uint32_t ** _execute_loop_nb_inst_issue 66 public : uint32_t ** _execute_loop_nb_inst_issue_slot ;//[nb_execute_loop][execute_loop_nb_ooo_engine] 64 67 //public : uint32_t * _link_execute_loop_with_ooo_engine ;//[nb_ooo_engine] 65 68 … … 70 73 public : uint32_t _max_nb_write_unit ; 71 74 public : uint32_t _max_nb_inst_insert ; 72 public : uint32_t _max_nb_inst_issue ; 75 public : uint32_t _max_nb_inst_issue_queue ; 76 public : uint32_t _max_nb_inst_issue_slot ; 73 77 public : uint32_t _max_nb_read_unit ; 74 78 … … 86 90 uint32_t * ooo_engine_nb_inst_branch_complete ,//[nb_ooo_engine] 87 91 uint32_t * nb_inst_insert ,//[nb_ooo_engine] 88 uint32_t * nb_inst_issue ,//[nb_ooo_engine] 92 uint32_t * nb_inst_reexecute ,//[nb_ooo_engine] 93 uint32_t * nb_inst_issue_queue ,//[nb_ooo_engine] 94 uint32_t * nb_inst_issue_slot ,//[nb_ooo_engine] 89 95 uint32_t ** nb_inst_execute ,//[nb_ooo_engine][ooo_engine_nb_execute_loop] 96 bool * issue_queue_in_order ,//[nb_ooo_engine] 90 97 uint32_t * nb_read_unit ,//[nb_execute_loop] 91 98 uint32_t * nb_write_unit ,//[nb_execute_loop] … … 100 107 Tpriority_t dispatch_priority , 101 108 Tload_balancing_t dispatch_load_balancing , 102 bool **** table_dispatch ,//[nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 109 bool **** table_dispatch ,//[nb_ooo_engine][nb_inst_issue_slot][execute_loop][nb_read_unit] 110 bool *** table_issue_type ,// [execute_loop][nb_read_unit][nb_type] 111 // bool *** table_issue_thread ,// [execute_loop][nb_read_unit][nb_thread] 103 112 uint32_t ** translate_ooo_engine_num_front_end ,//[nb_ooo_engine][ooo_engine_nb_front_end] 104 113 uint32_t ** translate_ooo_engine_num_execute_loop,//[nb_ooo_engine][ooo_engine_nb_execute_loop] -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue.cpp
r105 r117 160 160 161 161 for (uint32_t i=0; i<_param->_nb_ooo_engine; ++i) 162 for (uint32_t j=0; j<_param->_nb_inst_issue [i]; ++j)162 for (uint32_t j=0; j<_param->_nb_inst_issue_queue [i]; ++j) 163 163 { 164 164 sensitive << (*(in_ISSUE_OOO_ENGINE_VAL [i][j])) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_allocation.cpp
r112 r117 133 133 // ~~~~~[ Interface : "issue" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 134 134 { 135 ALLOC2_INTERFACE_BEGIN("issue_ooo_engine",SOUTH,IN ,_("Issue : request between rename unit and execute loop"),_param->_nb_ooo_engine,_param->_nb_inst_issue [it1]);136 137 _ALLOC2_SIGNAL_IN ( in_ISSUE_OOO_ENGINE_VAL ,"VAL" ,Tcontrol_t ,1 ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1]);138 _ALLOC2_SIGNAL_OUT(out_ISSUE_OOO_ENGINE_ACK ,"ACK" ,Tcontrol_t ,1 ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1]);139 _ALLOC2_SIGNAL_IN ( in_ISSUE_OOO_ENGINE_FRONT_END_ID ,"FRONT_END_ID" ,Tcontext_t ,_param->_size_front_end_id ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1]);140 _ALLOC2_SIGNAL_IN ( in_ISSUE_OOO_ENGINE_CONTEXT_ID ,"CONTEXT_ID" ,Tcontext_t ,_param->_size_context_id ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1]);141 _ALLOC2_SIGNAL_IN ( in_ISSUE_OOO_ENGINE_PACKET_ID ,"PACKET_ID" ,Tpacket_t ,_param->_size_rob_ptr ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1]);142 _ALLOC2_SIGNAL_IN ( in_ISSUE_OOO_ENGINE_TYPE ,"TYPE" ,Ttype_t ,_param->_size_type ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1]);143 _ALLOC2_SIGNAL_IN ( in_ISSUE_OOO_ENGINE_OPERATION ,"OPERATION" ,Toperation_t ,_param->_size_operation ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1]);144 _ALLOC2_SIGNAL_IN ( in_ISSUE_OOO_ENGINE_STORE_QUEUE_PTR_WRITE ,"STORE_QUEUE_PTR_WRITE",Tlsq_ptr_t ,_param->_size_store_queue_ptr ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1]);145 _ALLOC2_SIGNAL_IN ( in_ISSUE_OOO_ENGINE_LOAD_QUEUE_PTR_WRITE ,"LOAD_QUEUE_PTR_WRITE" ,Tlsq_ptr_t ,_param->_size_load_queue_ptr ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1]);146 _ALLOC2_SIGNAL_IN ( in_ISSUE_OOO_ENGINE_HAS_IMMEDIAT ,"HAS_IMMEDIAT" ,Tcontrol_t ,1 ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1]);147 _ALLOC2_SIGNAL_IN ( in_ISSUE_OOO_ENGINE_IMMEDIAT ,"IMMEDIAT" ,Tgeneral_data_t ,_param->_size_general_data ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1]);148 _ALLOC2_SIGNAL_IN ( in_ISSUE_OOO_ENGINE_READ_RA ,"READ_RA" ,Tcontrol_t ,1 ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1]);149 _ALLOC2_SIGNAL_IN ( in_ISSUE_OOO_ENGINE_NUM_REG_RA ,"NUM_REG_RA" ,Tgeneral_address_t,_param->_size_general_register,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1]);150 _ALLOC2_SIGNAL_IN ( in_ISSUE_OOO_ENGINE_READ_RB ,"READ_RB" ,Tcontrol_t ,1 ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1]);151 _ALLOC2_SIGNAL_IN ( in_ISSUE_OOO_ENGINE_NUM_REG_RB ,"NUM_REG_RB" ,Tgeneral_address_t,_param->_size_general_register,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1]);152 _ALLOC2_SIGNAL_IN ( in_ISSUE_OOO_ENGINE_READ_RC ,"READ_RC" ,Tcontrol_t ,1 ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1]);153 _ALLOC2_SIGNAL_IN ( in_ISSUE_OOO_ENGINE_NUM_REG_RC ,"NUM_REG_RC" ,Tspecial_address_t,_param->_size_special_register,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1]);154 _ALLOC2_SIGNAL_IN ( in_ISSUE_OOO_ENGINE_WRITE_RD ,"WRITE_RD" ,Tcontrol_t ,1 ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1]);155 _ALLOC2_SIGNAL_IN ( in_ISSUE_OOO_ENGINE_NUM_REG_RD ,"NUM_REG_RD" ,Tgeneral_address_t,_param->_size_general_register,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1]);156 _ALLOC2_SIGNAL_IN ( in_ISSUE_OOO_ENGINE_WRITE_RE ,"WRITE_RE" ,Tcontrol_t ,1 ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1]);157 _ALLOC2_SIGNAL_IN ( in_ISSUE_OOO_ENGINE_NUM_REG_RE ,"NUM_REG_RE" ,Tspecial_address_t,_param->_size_special_register,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1]);158 159 ALLOC2_INTERFACE_END(_param->_nb_ooo_engine,_param->_nb_inst_issue [it1]);135 ALLOC2_INTERFACE_BEGIN("issue_ooo_engine",SOUTH,IN ,_("Issue : request between rename unit and execute loop"),_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]); 136 137 _ALLOC2_SIGNAL_IN ( in_ISSUE_OOO_ENGINE_VAL ,"VAL" ,Tcontrol_t ,1 ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]); 138 _ALLOC2_SIGNAL_OUT(out_ISSUE_OOO_ENGINE_ACK ,"ACK" ,Tcontrol_t ,1 ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]); 139 _ALLOC2_SIGNAL_IN ( in_ISSUE_OOO_ENGINE_FRONT_END_ID ,"FRONT_END_ID" ,Tcontext_t ,_param->_size_front_end_id ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]); 140 _ALLOC2_SIGNAL_IN ( in_ISSUE_OOO_ENGINE_CONTEXT_ID ,"CONTEXT_ID" ,Tcontext_t ,_param->_size_context_id ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]); 141 _ALLOC2_SIGNAL_IN ( in_ISSUE_OOO_ENGINE_PACKET_ID ,"PACKET_ID" ,Tpacket_t ,_param->_size_rob_ptr ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]); 142 _ALLOC2_SIGNAL_IN ( in_ISSUE_OOO_ENGINE_TYPE ,"TYPE" ,Ttype_t ,_param->_size_type ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]); 143 _ALLOC2_SIGNAL_IN ( in_ISSUE_OOO_ENGINE_OPERATION ,"OPERATION" ,Toperation_t ,_param->_size_operation ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]); 144 _ALLOC2_SIGNAL_IN ( in_ISSUE_OOO_ENGINE_STORE_QUEUE_PTR_WRITE ,"STORE_QUEUE_PTR_WRITE",Tlsq_ptr_t ,_param->_size_store_queue_ptr ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]); 145 _ALLOC2_SIGNAL_IN ( in_ISSUE_OOO_ENGINE_LOAD_QUEUE_PTR_WRITE ,"LOAD_QUEUE_PTR_WRITE" ,Tlsq_ptr_t ,_param->_size_load_queue_ptr ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]); 146 _ALLOC2_SIGNAL_IN ( in_ISSUE_OOO_ENGINE_HAS_IMMEDIAT ,"HAS_IMMEDIAT" ,Tcontrol_t ,1 ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]); 147 _ALLOC2_SIGNAL_IN ( in_ISSUE_OOO_ENGINE_IMMEDIAT ,"IMMEDIAT" ,Tgeneral_data_t ,_param->_size_general_data ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]); 148 _ALLOC2_SIGNAL_IN ( in_ISSUE_OOO_ENGINE_READ_RA ,"READ_RA" ,Tcontrol_t ,1 ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]); 149 _ALLOC2_SIGNAL_IN ( in_ISSUE_OOO_ENGINE_NUM_REG_RA ,"NUM_REG_RA" ,Tgeneral_address_t,_param->_size_general_register,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]); 150 _ALLOC2_SIGNAL_IN ( in_ISSUE_OOO_ENGINE_READ_RB ,"READ_RB" ,Tcontrol_t ,1 ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]); 151 _ALLOC2_SIGNAL_IN ( in_ISSUE_OOO_ENGINE_NUM_REG_RB ,"NUM_REG_RB" ,Tgeneral_address_t,_param->_size_general_register,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]); 152 _ALLOC2_SIGNAL_IN ( in_ISSUE_OOO_ENGINE_READ_RC ,"READ_RC" ,Tcontrol_t ,1 ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]); 153 _ALLOC2_SIGNAL_IN ( in_ISSUE_OOO_ENGINE_NUM_REG_RC ,"NUM_REG_RC" ,Tspecial_address_t,_param->_size_special_register,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]); 154 _ALLOC2_SIGNAL_IN ( in_ISSUE_OOO_ENGINE_WRITE_RD ,"WRITE_RD" ,Tcontrol_t ,1 ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]); 155 _ALLOC2_SIGNAL_IN ( in_ISSUE_OOO_ENGINE_NUM_REG_RD ,"NUM_REG_RD" ,Tgeneral_address_t,_param->_size_general_register,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]); 156 _ALLOC2_SIGNAL_IN ( in_ISSUE_OOO_ENGINE_WRITE_RE ,"WRITE_RE" ,Tcontrol_t ,1 ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]); 157 _ALLOC2_SIGNAL_IN ( in_ISSUE_OOO_ENGINE_NUM_REG_RE ,"NUM_REG_RE" ,Tspecial_address_t,_param->_size_special_register,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]); 158 159 ALLOC2_INTERFACE_END(_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1]); 160 160 } 161 161 … … 257 257 258 258 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 259 _priority_ooo_engine = new generic::priority::Priority * [_param->_nb_execute_loop]; 259 _priority_ooo_engine = new generic::priority::Priority (_name+"_priority_ooo_engine", 260 _param->_dispatch_priority , 261 _param->_dispatch_load_balancing, 262 _param->_nb_ooo_engine , 263 _param->_nb_inst_issue_slot , 264 _param->_nb_ooo_engine 265 ); 266 267 // _priority_ooo_engine = new generic::priority::Priority * [_param->_nb_execute_loop]; 260 268 _priority_read_unit = new generic::priority::Priority * [_param->_nb_execute_loop]; 261 269 262 270 for (uint32_t i=0; i<_param->_nb_execute_loop; ++i) 263 271 { 264 _priority_ooo_engine [i] = new generic::priority::Priority (_name+"_priority_ooo_engine_"+toString(i),265 _param->_dispatch_priority ,266 _param->_dispatch_load_balancing,267 _param->_execute_loop_nb_ooo_engine[i],268 _param->_execute_loop_nb_inst_issue[i],269 _param->_execute_loop_nb_ooo_engine[i]270 );272 // _priority_ooo_engine [i] = new generic::priority::Priority (_name+"_priority_ooo_engine_"+toString(i), 273 // _param->_dispatch_priority , 274 // _param->_dispatch_load_balancing, 275 // _param->_execute_loop_nb_ooo_engine [i], 276 // _param->_execute_loop_nb_inst_issue_slot [i], 277 // _param->_execute_loop_nb_ooo_engine [i] 278 // ); 271 279 272 280 _priority_read_unit [i] = new generic::priority::Priority (_name+"_priority_read_unit_"+toString(i), -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_deallocation.cpp
r111 r117 70 70 DELETE1_SIGNAL( in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EEAR ,_param->_nb_ooo_engine,_param->_size_spr); 71 71 72 DELETE2_SIGNAL( in_ISSUE_OOO_ENGINE_VAL ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1],1);73 DELETE2_SIGNAL(out_ISSUE_OOO_ENGINE_ACK ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1],1);74 DELETE2_SIGNAL( in_ISSUE_OOO_ENGINE_FRONT_END_ID ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1],_param->_size_front_end_id);75 DELETE2_SIGNAL( in_ISSUE_OOO_ENGINE_CONTEXT_ID ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1],_param->_size_context_id);76 DELETE2_SIGNAL( in_ISSUE_OOO_ENGINE_PACKET_ID ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1],_param->_size_rob_ptr);77 DELETE2_SIGNAL( in_ISSUE_OOO_ENGINE_TYPE ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1],_param->_size_type);78 DELETE2_SIGNAL( in_ISSUE_OOO_ENGINE_OPERATION ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1],_param->_size_operation);79 DELETE2_SIGNAL( in_ISSUE_OOO_ENGINE_STORE_QUEUE_PTR_WRITE ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1],_param->_size_store_queue_ptr);80 DELETE2_SIGNAL( in_ISSUE_OOO_ENGINE_LOAD_QUEUE_PTR_WRITE ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1],_param->_size_load_queue_ptr);81 DELETE2_SIGNAL( in_ISSUE_OOO_ENGINE_HAS_IMMEDIAT ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1],1);82 DELETE2_SIGNAL( in_ISSUE_OOO_ENGINE_IMMEDIAT ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1],_param->_size_general_data);83 DELETE2_SIGNAL( in_ISSUE_OOO_ENGINE_READ_RA ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1],1);84 DELETE2_SIGNAL( in_ISSUE_OOO_ENGINE_NUM_REG_RA ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1],_param->_size_general_register);85 DELETE2_SIGNAL( in_ISSUE_OOO_ENGINE_READ_RB ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1],1);86 DELETE2_SIGNAL( in_ISSUE_OOO_ENGINE_NUM_REG_RB ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1],_param->_size_general_register);87 DELETE2_SIGNAL( in_ISSUE_OOO_ENGINE_READ_RC ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1],1);88 DELETE2_SIGNAL( in_ISSUE_OOO_ENGINE_NUM_REG_RC ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1],_param->_size_special_register);89 DELETE2_SIGNAL( in_ISSUE_OOO_ENGINE_WRITE_RD ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1],1);90 DELETE2_SIGNAL( in_ISSUE_OOO_ENGINE_NUM_REG_RD ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1],_param->_size_general_register);91 DELETE2_SIGNAL( in_ISSUE_OOO_ENGINE_WRITE_RE ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1],1);92 DELETE2_SIGNAL( in_ISSUE_OOO_ENGINE_NUM_REG_RE ,_param->_nb_ooo_engine,_param->_nb_inst_issue [it1],_param->_size_special_register);72 DELETE2_SIGNAL( in_ISSUE_OOO_ENGINE_VAL ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1],1); 73 DELETE2_SIGNAL(out_ISSUE_OOO_ENGINE_ACK ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1],1); 74 DELETE2_SIGNAL( in_ISSUE_OOO_ENGINE_FRONT_END_ID ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1],_param->_size_front_end_id); 75 DELETE2_SIGNAL( in_ISSUE_OOO_ENGINE_CONTEXT_ID ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1],_param->_size_context_id); 76 DELETE2_SIGNAL( in_ISSUE_OOO_ENGINE_PACKET_ID ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1],_param->_size_rob_ptr); 77 DELETE2_SIGNAL( in_ISSUE_OOO_ENGINE_TYPE ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1],_param->_size_type); 78 DELETE2_SIGNAL( in_ISSUE_OOO_ENGINE_OPERATION ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1],_param->_size_operation); 79 DELETE2_SIGNAL( in_ISSUE_OOO_ENGINE_STORE_QUEUE_PTR_WRITE ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1],_param->_size_store_queue_ptr); 80 DELETE2_SIGNAL( in_ISSUE_OOO_ENGINE_LOAD_QUEUE_PTR_WRITE ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1],_param->_size_load_queue_ptr); 81 DELETE2_SIGNAL( in_ISSUE_OOO_ENGINE_HAS_IMMEDIAT ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1],1); 82 DELETE2_SIGNAL( in_ISSUE_OOO_ENGINE_IMMEDIAT ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1],_param->_size_general_data); 83 DELETE2_SIGNAL( in_ISSUE_OOO_ENGINE_READ_RA ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1],1); 84 DELETE2_SIGNAL( in_ISSUE_OOO_ENGINE_NUM_REG_RA ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1],_param->_size_general_register); 85 DELETE2_SIGNAL( in_ISSUE_OOO_ENGINE_READ_RB ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1],1); 86 DELETE2_SIGNAL( in_ISSUE_OOO_ENGINE_NUM_REG_RB ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1],_param->_size_general_register); 87 DELETE2_SIGNAL( in_ISSUE_OOO_ENGINE_READ_RC ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1],1); 88 DELETE2_SIGNAL( in_ISSUE_OOO_ENGINE_NUM_REG_RC ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1],_param->_size_special_register); 89 DELETE2_SIGNAL( in_ISSUE_OOO_ENGINE_WRITE_RD ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1],1); 90 DELETE2_SIGNAL( in_ISSUE_OOO_ENGINE_NUM_REG_RD ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1],_param->_size_general_register); 91 DELETE2_SIGNAL( in_ISSUE_OOO_ENGINE_WRITE_RE ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1],1); 92 DELETE2_SIGNAL( in_ISSUE_OOO_ENGINE_NUM_REG_RE ,_param->_nb_ooo_engine,_param->_nb_inst_issue_queue[it1],_param->_size_special_register); 93 93 94 94 DELETE2_SIGNAL(out_ISSUE_EXECUTE_LOOP_VAL ,_param->_nb_execute_loop,_param->_nb_read_unit[it1],1); … … 160 160 for (uint32_t i=0; i<_param->_nb_execute_loop; ++i) 161 161 { 162 162 // delete _priority_ooo_engine [i]; 163 163 delete _priority_read_unit [i]; 164 164 } 165 165 // delete [] _priority_ooo_engine; 166 166 delete [] _priority_read_unit ; 167 delete _priority_ooo_engine; 167 168 168 169 delete _component; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_genMealy_issue.cpp
r115 r117 15 15 namespace core_glue { 16 16 17 /* 18 OOO SLOT Execute Loop 19 ---+ +----- 20 | +-----+ +-----+ | 21 -+->| | | |-+-> 22 | | |-()->| | | 23 -+->| _ _ | | |-+-> 24 | | _X_ |-()->| | | 25 -+->| | | | +----- 26 | | |-()->| | 27 -+->| | | | +----- 28 | +-----+ | | | 29 ---+ crossbar | _ _ |-+-> 30 | _X_ | | 31 ---+ | |-+-> 32 | +-----+ | | | 33 -+->| | | | +----- 34 | | |-()->| | 35 -+->| _ _ | | | +----- 36 | | _X_ |-()->| | | 37 -+->| | | |-+-> 38 | | |-()->| | | 39 -+->| | | |-+-> 40 | +-----+ +-----+ | 41 ---+ crossbar dispatch +----- 42 */ 43 44 45 // class num_read_unit_t 46 // { 47 // public : const uint32_t num_execute_loop; 48 // public : const uint32_t num_read_unit; 49 50 // public : num_read_unit_t (uint32_t num_execute_loop, 51 // uint32_t num_read_unit) : 52 // this->num_execute_loop (num_execute_loop), 53 // this->num_read_unit (num_read_unit ) 54 // {}; 55 // } 17 56 18 57 #undef FUNCTION … … 23 62 log_function(Core_Glue,FUNCTION,_name.c_str()); 24 63 25 Tcontrol_t ISSUE_OOO_ENGINE_ACK [_param->_nb_ooo_engine ][_param->_max_nb_inst_issue]; 26 Tcontrol_t ISSUE_EXECUTE_LOOP_VAL [_param->_nb_execute_loop][_param->_max_nb_read_unit ]; 27 bool READ_UNIT_ENABLE [_param->_nb_execute_loop][_param->_max_nb_read_unit ]; 28 64 Tcontrol_t ISSUE_OOO_ENGINE_ACK [_param->_nb_ooo_engine ][_param->_max_nb_inst_issue_queue]; 65 Tcontrol_t ISSUE_EXECUTE_LOOP_VAL [_param->_nb_execute_loop][_param->_max_nb_read_unit]; 66 Tcontrol_t READ_UNIT_ENABLE [_param->_nb_execute_loop][_param->_max_nb_read_unit]; 67 Tcontrol_t SLOT_ENABLE [_param->_nb_ooo_engine ][_param->_max_nb_inst_issue_slot]; 68 29 69 // Init -> all at 0 30 70 for (uint32_t i=0; i<_param->_nb_ooo_engine; ++i) 31 for (uint32_t j=0; j<_param->_nb_inst_issue[i]; ++j) 32 ISSUE_OOO_ENGINE_ACK [i][j] = 0; 71 { 72 for (uint32_t j=0; j<_param->_nb_inst_issue_queue[i]; ++j) 73 ISSUE_OOO_ENGINE_ACK [i][j] = 0; 74 for (uint32_t j=0; j<_param->_nb_inst_issue_slot[i]; ++j) 75 SLOT_ENABLE [i][j] = 1; 76 } 77 33 78 for (uint32_t i=0; i<_param->_nb_execute_loop; ++i) 34 79 for (uint32_t j=0; j<_param->_nb_read_unit[i]; ++j) 35 80 { 36 81 ISSUE_EXECUTE_LOOP_VAL [i][j] = 0; 82 37 83 // Read unit is enable is signal ack is set 38 84 READ_UNIT_ENABLE [i][j] = (PORT_READ(in_ISSUE_EXECUTE_LOOP_ACK [i][j]) == 1); 39 log_printf(TRACE,Core_Glue,FUNCTION," * Read_unit [%d][%d] : %d",i,j,READ_UNIT_ENABLE[i][j]);85 log_printf(TRACE,Core_Glue,FUNCTION," * Read_unit [%d][%d].enable : %d",i,j,READ_UNIT_ENABLE[i][j]); 40 86 } 41 87 88 // std::list<num_read_unit_t> SLOT_TYPE [_param->_nb_ooo_engine][_param->_max_nb_inst_issue_slot][_param->_nb_type]; 89 90 // // for each read_unit 91 // for (uint32_t i=0; i<_param->_nb_execute_loop; ++i) 92 // for (uint32_t j=0; j<_param->_nb_read_unit[i]; ++j) 93 // // test if this read_unit can receive an instruction 94 // if (PORT_READ(in_ISSUE_EXECUTE_LOOP_ACK [i][j]) == 1) 95 // for (uint32_t x=0; x<_nb_ooo_engine; ++x) 96 // for (uint32_t y=0; y<_nb_inst_issue_slot[y]; ++y) 97 // // test if can dispatch 98 // if (_param->_table_dispatch [x][y][i][j]) 99 // for (uint32_t k=0;k<_param->_nb_type; ++k) 100 // // Can receive this type 101 // if (_param->_table_dispatch [i][j][k]) 102 // SLOT_TYPE[x][y][k].push_back(num_read_unit_t(i,j)); 103 104 // // Select an issue_slot of an ooo_engine 105 // std::list<generic::priority::select_t> * select_ooo_engine = _priority_ooo_engine->select(); 106 // for (std::list<generic::priority::select_t>::iterator it_ooo_engine=select_ooo_engine->begin(); 107 // it_ooo_engine!=select_ooo_engine->end(); 108 // ++it_ooo_engine) 109 // { 110 // // ... get id of the most priotary 111 // const uint32_t num_ooo_engine = it_ooo_engine->grp; 112 // const uint32_t num_inst_issue_slot = it_ooo_engine->elt; 113 114 // // Test if this ooo_engine is enable (can be desable if issue in_order) 115 // if (OOO_ENGINE_ENABLE[num_ooo_engine]) 116 // { 117 118 // } 119 // } 120 121 for (uint32_t num_ooo_engine=0; num_ooo_engine<_param->_nb_ooo_engine; ++num_ooo_engine) 122 for (uint32_t num_inst_issue_queue=0; num_inst_issue_queue<_param->_nb_inst_issue_queue[num_ooo_engine]; ++num_inst_issue_queue) 123 { 124 bool find = false; 125 126 Tcontrol_t val = PORT_READ(in_ISSUE_OOO_ENGINE_VAL [num_ooo_engine][num_inst_issue_queue]); 127 Ttype_t type = PORT_READ(in_ISSUE_OOO_ENGINE_TYPE [num_ooo_engine][num_inst_issue_queue]); 128 129 log_printf(TRACE,Core_Glue,FUNCTION," * num_ooo_engine : %d",num_ooo_engine ); 130 log_printf(TRACE,Core_Glue,FUNCTION," * num_inst_issue_queue : %d",num_inst_issue_queue); 131 log_printf(TRACE,Core_Glue,FUNCTION," * val : %d",val); 132 log_printf(TRACE,Core_Glue,FUNCTION," * type : %d",type); 133 134 if (val) 135 for (uint32_t num_inst_issue_slot=0; num_inst_issue_slot<_param->_nb_inst_issue_slot[num_ooo_engine]; ++num_inst_issue_slot) 136 { 137 log_printf(TRACE,Core_Glue,FUNCTION," * num_inst_issue_slot : %d",num_inst_issue_slot); 138 139 // scan all read_unit 140 141 if (SLOT_ENABLE [num_ooo_engine][num_inst_issue_slot]) 142 for (uint32_t num_execute_loop=0; num_execute_loop<_param->_nb_execute_loop; ++num_execute_loop) 143 { 144 for (uint32_t num_read_unit=0; num_read_unit<_param->_nb_read_unit[num_execute_loop]; ++num_read_unit) 145 { 146 Tcontrol_t ack = READ_UNIT_ENABLE [num_execute_loop][num_read_unit]; 147 148 log_printf(TRACE,Core_Glue,FUNCTION," * num_execute_loop : %d",num_execute_loop); 149 log_printf(TRACE,Core_Glue,FUNCTION," * num_read_unit : %d",num_read_unit ); 150 log_printf(TRACE,Core_Glue,FUNCTION," * read_unit_enable : %d",ack ); 151 152 // test if : 153 // * read_unit can accept an instruction (valid and no previous instruction) 154 // * slot can issue an instruction at this read_unit 155 // * read_unit can accept this type 156 if (ack and 157 _param->_table_dispatch [num_ooo_engine][num_inst_issue_slot][num_execute_loop][num_read_unit] and 158 _param->_table_issue_type [num_execute_loop][num_read_unit][type]) 159 { 160 log_printf(TRACE,Core_Glue,FUNCTION," * find !!!"); 161 162 // find ! 163 // Transaction 164 READ_UNIT_ENABLE [num_execute_loop][num_read_unit] = false; // now, this read_unit is busy 165 ISSUE_EXECUTE_LOOP_VAL [num_execute_loop][num_read_unit] = 1; // = val 166 ISSUE_OOO_ENGINE_ACK [num_ooo_engine][num_inst_issue_queue] = 1; // = ack 167 SLOT_ENABLE [num_ooo_engine][num_inst_issue_slot] = false; // now this slot is used 168 169 if (_param->_have_port_context_id) 170 PORT_WRITE(out_ISSUE_EXECUTE_LOOP_CONTEXT_ID [num_execute_loop][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_CONTEXT_ID [num_ooo_engine][num_inst_issue_queue])); 171 if (_param->_have_port_front_end_id) 172 PORT_WRITE(out_ISSUE_EXECUTE_LOOP_FRONT_END_ID [num_execute_loop][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_FRONT_END_ID [num_ooo_engine][num_inst_issue_queue])); 173 if (_param->_have_port_ooo_engine_id) 174 { 175 Tcontext_t ooo_engine_id = 0; 176 PORT_WRITE(out_ISSUE_EXECUTE_LOOP_OOO_ENGINE_ID [num_execute_loop][num_read_unit],ooo_engine_id); 177 } 178 if (_param->_have_port_rob_ptr) 179 PORT_WRITE(out_ISSUE_EXECUTE_LOOP_PACKET_ID [num_execute_loop][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_PACKET_ID [num_ooo_engine][num_inst_issue_queue])); 180 PORT_WRITE(out_ISSUE_EXECUTE_LOOP_OPERATION [num_execute_loop][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_OPERATION [num_ooo_engine][num_inst_issue_queue])); 181 PORT_WRITE(out_ISSUE_EXECUTE_LOOP_TYPE [num_execute_loop][num_read_unit],type); 182 PORT_WRITE(out_ISSUE_EXECUTE_LOOP_STORE_QUEUE_PTR_WRITE [num_execute_loop][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_STORE_QUEUE_PTR_WRITE [num_ooo_engine][num_inst_issue_queue])); 183 if (_param->_have_port_load_queue_ptr) 184 PORT_WRITE(out_ISSUE_EXECUTE_LOOP_LOAD_QUEUE_PTR_WRITE [num_execute_loop][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_LOAD_QUEUE_PTR_WRITE [num_ooo_engine][num_inst_issue_queue])); 185 PORT_WRITE(out_ISSUE_EXECUTE_LOOP_HAS_IMMEDIAT [num_execute_loop][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_HAS_IMMEDIAT [num_ooo_engine][num_inst_issue_queue])); 186 PORT_WRITE(out_ISSUE_EXECUTE_LOOP_IMMEDIAT [num_execute_loop][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_IMMEDIAT [num_ooo_engine][num_inst_issue_queue])); 187 PORT_WRITE(out_ISSUE_EXECUTE_LOOP_READ_RA [num_execute_loop][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_READ_RA [num_ooo_engine][num_inst_issue_queue])); 188 PORT_WRITE(out_ISSUE_EXECUTE_LOOP_NUM_REG_RA [num_execute_loop][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_NUM_REG_RA [num_ooo_engine][num_inst_issue_queue])); 189 PORT_WRITE(out_ISSUE_EXECUTE_LOOP_READ_RB [num_execute_loop][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_READ_RB [num_ooo_engine][num_inst_issue_queue])); 190 PORT_WRITE(out_ISSUE_EXECUTE_LOOP_NUM_REG_RB [num_execute_loop][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_NUM_REG_RB [num_ooo_engine][num_inst_issue_queue])); 191 PORT_WRITE(out_ISSUE_EXECUTE_LOOP_READ_RC [num_execute_loop][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_READ_RC [num_ooo_engine][num_inst_issue_queue])); 192 PORT_WRITE(out_ISSUE_EXECUTE_LOOP_NUM_REG_RC [num_execute_loop][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_NUM_REG_RC [num_ooo_engine][num_inst_issue_queue])); 193 PORT_WRITE(out_ISSUE_EXECUTE_LOOP_WRITE_RD [num_execute_loop][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_WRITE_RD [num_ooo_engine][num_inst_issue_queue])); 194 PORT_WRITE(out_ISSUE_EXECUTE_LOOP_NUM_REG_RD [num_execute_loop][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_NUM_REG_RD [num_ooo_engine][num_inst_issue_queue])); 195 PORT_WRITE(out_ISSUE_EXECUTE_LOOP_WRITE_RE [num_execute_loop][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_WRITE_RE [num_ooo_engine][num_inst_issue_queue])); 196 PORT_WRITE(out_ISSUE_EXECUTE_LOOP_NUM_REG_RE [num_execute_loop][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_NUM_REG_RE [num_ooo_engine][num_inst_issue_queue])); 197 198 199 find = true; 200 break; 201 } 202 //if (find) 203 // break; 204 } 205 if (find) 206 break; 207 } 208 if (find) 209 break; 210 } 211 212 if (_param->_issue_queue_in_order [num_ooo_engine] and 213 not find and 214 (num_inst_issue_queue >= _param->_nb_inst_reexecute [num_ooo_engine])) 215 { 216 log_printf(TRACE,Core_Glue,FUNCTION," * stop scan !!!"); 217 218 break; // stop scan 219 } 220 } 221 222 // Write output 223 for (uint32_t i=0; i<_param->_nb_ooo_engine; ++i) 224 for (uint32_t j=0; j<_param->_nb_inst_issue_queue[i]; ++j) 225 PORT_WRITE(out_ISSUE_OOO_ENGINE_ACK [i][j], ISSUE_OOO_ENGINE_ACK [i][j]); 226 for (uint32_t i=0; i<_param->_nb_execute_loop; ++i) 227 for (uint32_t j=0; j<_param->_nb_read_unit[i]; ++j) 228 PORT_WRITE(out_ISSUE_EXECUTE_LOOP_VAL [i][j], ISSUE_EXECUTE_LOOP_VAL [i][j]); 229 230 log_end(Core_Glue,FUNCTION); 231 }; 232 233 }; // end namespace core_glue 234 }; // end namespace core 235 236 }; // end namespace behavioural 237 }; // end namespace morpheo 238 #endif 239 240 /* 241 bool OOO_ENGINE_ENABLE [_param->_nb_ooo_engine ]; 242 Tcontrol_t SLOT_ENABLE [_param->_nb_ooo_engine ][_param->_max_nb_inst_issue_slot]; 243 bool READ_UNIT_ENABLE [_param->_nb_execute_loop][_param->_max_nb_read_unit]; 244 245 // Init -> all at 0 246 for (uint32_t i=0; i<_param->_nb_ooo_engine; ++i) 247 { 248 OOO_ENGINE_ENABLE [i] = true; 249 250 for (uint32_t j=0; j<_param->_nb_inst_issue_slot[i]; ++j) 251 SLOT_ENABLE [i][j] = 1; 252 } 253 254 for (uint32_t i=0; i<_param->_nb_execute_loop; ++i) 255 for (uint32_t j=0; j<_param->_nb_read_unit[i]; ++j) 256 { 257 // Read unit is enable is signal ack is set 258 READ_UNIT_ENABLE [i][j] = (PORT_READ(in_ISSUE_EXECUTE_LOOP_ACK [i][j]) == 1); 259 log_printf(TRACE,Core_Glue,FUNCTION," * Read_unit [%d][%d].enable : %d",i,j,READ_UNIT_ENABLE[i][j]); 260 } 261 262 263 // for each execute_loop 42 264 for (uint32_t i=0; i<_param->_nb_execute_loop; ++i) 43 265 { 44 log_printf(TRACE,Core_Glue,FUNCTION," * execute_loop [%d]",i); 45 46 // for each issue of each ooo_engine ... 47 std::list<generic::priority::select_t> * select_ooo_engine = _priority_ooo_engine[i]->select(); 48 for (std::list<generic::priority::select_t>::iterator it_ooo_engine=select_ooo_engine->begin(); 49 it_ooo_engine!=select_ooo_engine->end(); 50 ++it_ooo_engine) 266 // Scan all read_unit 267 std::list<generic::priority::select_t> * select_read_unit = _priority_read_unit[i]->select(); 268 for (std::list<generic::priority::select_t>::iterator it_read_unit=select_read_unit->begin(); 269 it_read_unit!=select_read_unit->end(); 270 ++it_read_unit) 51 271 { 52 // get id 53 const uint32_t ooo_engine_id = it_ooo_engine->grp; 54 const uint32_t num_ooo_engine = _param->_translate_execute_loop_num_ooo_engine [i][ooo_engine_id]; 55 const uint32_t num_inst_issue = it_ooo_engine->elt; 56 57 log_printf(TRACE,Core_Glue,FUNCTION," * num_ooo_engine [%d] (id -> %d)",num_ooo_engine, ooo_engine_id); 58 log_printf(TRACE,Core_Glue,FUNCTION," * num_inst_issue : %d",num_inst_issue); 59 60 Tcontrol_t ooo_engine_val = PORT_READ(in_ISSUE_OOO_ENGINE_VAL [num_ooo_engine][num_inst_issue]); 61 62 log_printf(TRACE,Core_Glue,FUNCTION," * ISSUE_OOO_ENGINE_VAL : %d",ooo_engine_val); 63 64 // test if have a request ? 65 // if (ooo_engine_val) 272 // get the most priotary ... 273 uint32_t num_read_unit = it_read_unit->grp; 274 275 log_printf(TRACE,Core_Glue,FUNCTION," * read_unit [%d][%d]",i,num_read_unit); 276 277 // ... and test if this read_unit is valid 278 if (READ_UNIT_ENABLE [i][num_read_unit]) 66 279 { 67 // // If ooo_engine can issue instruction on multiple execute_loop 68 // if (not ISSUE_OOO_ENGINE_ACK [num_ooo_engine][num_inst_issue]) 69 70 // Scan all read_unit 71 std::list<generic::priority::select_t> * select_read_unit = _priority_read_unit[i]->select(); 72 for (std::list<generic::priority::select_t>::iterator it_read_unit=select_read_unit->begin(); 73 it_read_unit!=select_read_unit->end(); 74 ++it_read_unit) 75 { 76 uint32_t num_read_unit = it_read_unit->grp; 77 78 // Test if have an link and read unit is enable 79 log_printf(TRACE,Core_Glue,FUNCTION," * read_unit : %d",num_read_unit); 80 log_printf(TRACE,Core_Glue,FUNCTION," * READ_UNIT_ENABLE : %d",READ_UNIT_ENABLE [i][num_read_unit]); 81 log_printf(TRACE,Core_Glue,FUNCTION," * table_dispatch : %d",_param->_table_dispatch [num_ooo_engine][num_inst_issue][i][num_read_unit]); 82 83 Tcontrol_t read_unit_enable = READ_UNIT_ENABLE [i][num_read_unit]; 84 85 // Test if the read_unit is not busy and if an link is between the issue slot and read_unit 86 if (read_unit_enable and 87 _param->_table_dispatch [num_ooo_engine][num_inst_issue][i][num_read_unit]) 88 { 89 log_printf(TRACE,Core_Glue,FUNCTION," * find !!!"); 90 91 // Transaction 92 READ_UNIT_ENABLE [i][num_read_unit] = false; // now, this read_unit is busy 93 ISSUE_EXECUTE_LOOP_VAL [i][num_read_unit] = ooo_engine_val; // = 1 94 ISSUE_OOO_ENGINE_ACK [num_ooo_engine][num_inst_issue] = read_unit_enable; // = 1 95 96 if (_param->_have_port_context_id) 97 PORT_WRITE(out_ISSUE_EXECUTE_LOOP_CONTEXT_ID [i][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_CONTEXT_ID [num_ooo_engine][num_inst_issue])); 98 if (_param->_have_port_front_end_id) 99 PORT_WRITE(out_ISSUE_EXECUTE_LOOP_FRONT_END_ID [i][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_FRONT_END_ID [num_ooo_engine][num_inst_issue])); 100 if (_param->_have_port_ooo_engine_id) 101 PORT_WRITE(out_ISSUE_EXECUTE_LOOP_OOO_ENGINE_ID [i][num_read_unit],ooo_engine_id); 102 if (_param->_have_port_rob_ptr) 103 PORT_WRITE(out_ISSUE_EXECUTE_LOOP_PACKET_ID [i][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_PACKET_ID [num_ooo_engine][num_inst_issue])); 104 PORT_WRITE(out_ISSUE_EXECUTE_LOOP_OPERATION [i][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_OPERATION [num_ooo_engine][num_inst_issue])); 105 PORT_WRITE(out_ISSUE_EXECUTE_LOOP_TYPE [i][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_TYPE [num_ooo_engine][num_inst_issue])); 106 PORT_WRITE(out_ISSUE_EXECUTE_LOOP_STORE_QUEUE_PTR_WRITE [i][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_STORE_QUEUE_PTR_WRITE [num_ooo_engine][num_inst_issue])); 107 if (_param->_have_port_load_queue_ptr) 108 PORT_WRITE(out_ISSUE_EXECUTE_LOOP_LOAD_QUEUE_PTR_WRITE [i][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_LOAD_QUEUE_PTR_WRITE [num_ooo_engine][num_inst_issue])); 109 PORT_WRITE(out_ISSUE_EXECUTE_LOOP_HAS_IMMEDIAT [i][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_HAS_IMMEDIAT [num_ooo_engine][num_inst_issue])); 110 PORT_WRITE(out_ISSUE_EXECUTE_LOOP_IMMEDIAT [i][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_IMMEDIAT [num_ooo_engine][num_inst_issue])); 111 PORT_WRITE(out_ISSUE_EXECUTE_LOOP_READ_RA [i][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_READ_RA [num_ooo_engine][num_inst_issue])); 112 PORT_WRITE(out_ISSUE_EXECUTE_LOOP_NUM_REG_RA [i][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_NUM_REG_RA [num_ooo_engine][num_inst_issue])); 113 PORT_WRITE(out_ISSUE_EXECUTE_LOOP_READ_RB [i][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_READ_RB [num_ooo_engine][num_inst_issue])); 114 PORT_WRITE(out_ISSUE_EXECUTE_LOOP_NUM_REG_RB [i][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_NUM_REG_RB [num_ooo_engine][num_inst_issue])); 115 PORT_WRITE(out_ISSUE_EXECUTE_LOOP_READ_RC [i][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_READ_RC [num_ooo_engine][num_inst_issue])); 116 PORT_WRITE(out_ISSUE_EXECUTE_LOOP_NUM_REG_RC [i][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_NUM_REG_RC [num_ooo_engine][num_inst_issue])); 117 PORT_WRITE(out_ISSUE_EXECUTE_LOOP_WRITE_RD [i][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_WRITE_RD [num_ooo_engine][num_inst_issue])); 118 PORT_WRITE(out_ISSUE_EXECUTE_LOOP_NUM_REG_RD [i][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_NUM_REG_RD [num_ooo_engine][num_inst_issue])); 119 PORT_WRITE(out_ISSUE_EXECUTE_LOOP_WRITE_RE [i][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_WRITE_RE [num_ooo_engine][num_inst_issue])); 120 PORT_WRITE(out_ISSUE_EXECUTE_LOOP_NUM_REG_RE [i][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_NUM_REG_RE [num_ooo_engine][num_inst_issue])); 121 122 break; // find : stop scan read_unit 123 } 280 bool find = false; 281 282 // This read_unit is valid, now find an valid instruction 283 // for each issue of each ooo_engine ... 284 std::list<generic::priority::select_t> * select_ooo_engine = _priority_ooo_engine[i]->select(); 285 for (std::list<generic::priority::select_t>::iterator it_ooo_engine=select_ooo_engine->begin(); 286 it_ooo_engine!=select_ooo_engine->end(); 287 ++it_ooo_engine) 288 { 289 // ... get id of the most priotary 290 const uint32_t ooo_engine_id = it_ooo_engine->grp; 291 const uint32_t num_ooo_engine = _param->_translate_execute_loop_num_ooo_engine [i][ooo_engine_id]; 292 const uint32_t num_inst_issue_slot = it_ooo_engine->elt; 293 294 log_printf(TRACE,Core_Glue,FUNCTION," * num_ooo_engine [%d (%d)][%d]",num_ooo_engine, ooo_engine_id,num_inst_issue_slot); 295 296 if (OOO_ENGINE_ENABLE [num_ooo_engine] and SLOT_ENABLE [num_ooo_engine][num_inst_issue_slot]) 297 { 298 uint32_t num_inst_issue_queue = 0; 299 for (; num_inst_issue_queue < _param->_nb_inst_issue_queue [num_ooo_engine]; num_inst_issue_queue ++) 300 { 301 // Test if this instruction is not previously send at a read_unit 302 if (not ISSUE_OOO_ENGINE_ACK [num_ooo_engine][num_inst_issue_queue]) 303 { 304 Tcontrol_t ooo_engine_val = PORT_READ(in_ISSUE_OOO_ENGINE_VAL [num_ooo_engine][num_inst_issue_queue]); 305 Ttype_t type = PORT_READ(in_ISSUE_OOO_ENGINE_TYPE [num_ooo_engine][num_inst_issue_queue]); 306 // Test if have an link and read unit is enable 307 bool can_dispatch = _param->_table_dispatch [num_ooo_engine][num_inst_issue_slot][i][num_read_unit]; 308 bool can_issue_type = _param->_table_issue_type [i][num_read_unit][type]; 309 310 log_printf(TRACE,Core_Glue,FUNCTION," * num_ooo_engine_queue : %d",num_inst_issue_queue); 311 log_printf(TRACE,Core_Glue,FUNCTION," * type : %s",toString(type).c_str()); 312 log_printf(TRACE,Core_Glue,FUNCTION," * ISSUE_OOO_ENGINE_VAL : %d",ooo_engine_val); 313 log_printf(TRACE,Core_Glue,FUNCTION," * table_dispatch : %d",can_dispatch); 314 log_printf(TRACE,Core_Glue,FUNCTION," * table_issue_type : %d",can_issue_type); 315 316 317 // test if have a request ? 318 // and test if have a link between the issue slot and read_unit 319 // and if the read_unit accept this instruction's type 320 if (ooo_engine_val and 321 can_dispatch and 322 can_issue_type) 323 { 324 // log_printf(TRACE,Core_Glue,FUNCTION," * find !!!"); 325 326 // Transaction 327 READ_UNIT_ENABLE [i][num_read_unit] = false; // now, this read_unit is busy 328 ISSUE_EXECUTE_LOOP_VAL [i][num_read_unit] = ooo_engine_val; 329 ISSUE_OOO_ENGINE_ACK [num_ooo_engine][num_inst_issue_queue] = 1; 330 SLOT_ENABLE [num_ooo_engine][num_inst_issue_slot] = 0; // now this slot is used 331 332 if (_param->_have_port_context_id) 333 PORT_WRITE(out_ISSUE_EXECUTE_LOOP_CONTEXT_ID [i][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_CONTEXT_ID [num_ooo_engine][num_inst_issue_queue])); 334 if (_param->_have_port_front_end_id) 335 PORT_WRITE(out_ISSUE_EXECUTE_LOOP_FRONT_END_ID [i][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_FRONT_END_ID [num_ooo_engine][num_inst_issue_queue])); 336 if (_param->_have_port_ooo_engine_id) 337 PORT_WRITE(out_ISSUE_EXECUTE_LOOP_OOO_ENGINE_ID [i][num_read_unit],ooo_engine_id); 338 if (_param->_have_port_rob_ptr) 339 PORT_WRITE(out_ISSUE_EXECUTE_LOOP_PACKET_ID [i][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_PACKET_ID [num_ooo_engine][num_inst_issue_queue])); 340 PORT_WRITE(out_ISSUE_EXECUTE_LOOP_OPERATION [i][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_OPERATION [num_ooo_engine][num_inst_issue_queue])); 341 PORT_WRITE(out_ISSUE_EXECUTE_LOOP_TYPE [i][num_read_unit],type); 342 PORT_WRITE(out_ISSUE_EXECUTE_LOOP_STORE_QUEUE_PTR_WRITE [i][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_STORE_QUEUE_PTR_WRITE [num_ooo_engine][num_inst_issue_queue])); 343 if (_param->_have_port_load_queue_ptr) 344 PORT_WRITE(out_ISSUE_EXECUTE_LOOP_LOAD_QUEUE_PTR_WRITE [i][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_LOAD_QUEUE_PTR_WRITE [num_ooo_engine][num_inst_issue_queue])); 345 PORT_WRITE(out_ISSUE_EXECUTE_LOOP_HAS_IMMEDIAT [i][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_HAS_IMMEDIAT [num_ooo_engine][num_inst_issue_queue])); 346 PORT_WRITE(out_ISSUE_EXECUTE_LOOP_IMMEDIAT [i][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_IMMEDIAT [num_ooo_engine][num_inst_issue_queue])); 347 PORT_WRITE(out_ISSUE_EXECUTE_LOOP_READ_RA [i][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_READ_RA [num_ooo_engine][num_inst_issue_queue])); 348 PORT_WRITE(out_ISSUE_EXECUTE_LOOP_NUM_REG_RA [i][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_NUM_REG_RA [num_ooo_engine][num_inst_issue_queue])); 349 PORT_WRITE(out_ISSUE_EXECUTE_LOOP_READ_RB [i][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_READ_RB [num_ooo_engine][num_inst_issue_queue])); 350 PORT_WRITE(out_ISSUE_EXECUTE_LOOP_NUM_REG_RB [i][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_NUM_REG_RB [num_ooo_engine][num_inst_issue_queue])); 351 PORT_WRITE(out_ISSUE_EXECUTE_LOOP_READ_RC [i][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_READ_RC [num_ooo_engine][num_inst_issue_queue])); 352 PORT_WRITE(out_ISSUE_EXECUTE_LOOP_NUM_REG_RC [i][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_NUM_REG_RC [num_ooo_engine][num_inst_issue_queue])); 353 PORT_WRITE(out_ISSUE_EXECUTE_LOOP_WRITE_RD [i][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_WRITE_RD [num_ooo_engine][num_inst_issue_queue])); 354 PORT_WRITE(out_ISSUE_EXECUTE_LOOP_NUM_REG_RD [i][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_NUM_REG_RD [num_ooo_engine][num_inst_issue_queue])); 355 PORT_WRITE(out_ISSUE_EXECUTE_LOOP_WRITE_RE [i][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_WRITE_RE [num_ooo_engine][num_inst_issue_queue])); 356 PORT_WRITE(out_ISSUE_EXECUTE_LOOP_NUM_REG_RE [i][num_read_unit],PORT_READ(in_ISSUE_OOO_ENGINE_NUM_REG_RE [num_ooo_engine][num_inst_issue_queue])); 357 358 find = true;// find : stop scan read_unit 359 } 360 } 361 if (find) 362 break; 363 } 364 365 if (find) 366 { 367 log_printf(TRACE,Core_Glue,FUNCTION," * find !!!"); 368 break; 369 } 370 else 371 { 372 log_printf(TRACE,Core_Glue,FUNCTION," * not find !!!"); 373 log_printf(TRACE,Core_Glue,FUNCTION," * issue_queue_in_order: %d",_param->_issue_queue_in_order [num_ooo_engine]); 374 log_printf(TRACE,Core_Glue,FUNCTION," * num_inst_issue_queue: %d",num_inst_issue_queue); 375 log_printf(TRACE,Core_Glue,FUNCTION," * nb_inst_reexecute : %d",_param->_nb_inst_reexecute [num_ooo_engine]); 376 377 if (_param->_issue_queue_in_order [num_ooo_engine] and 378 (num_inst_issue_queue >= _param->_nb_inst_reexecute [num_ooo_engine])) 379 OOO_ENGINE_ENABLE [num_ooo_engine] = false; 380 } 381 } 124 382 } 125 383 } 126 384 } 127 385 } 128 129 // Write output 130 for (uint32_t i=0; i<_param->_nb_ooo_engine; ++i) 131 for (uint32_t j=0; j<_param->_nb_inst_issue[i]; ++j) 132 PORT_WRITE(out_ISSUE_OOO_ENGINE_ACK [i][j], ISSUE_OOO_ENGINE_ACK [i][j]); 133 for (uint32_t i=0; i<_param->_nb_execute_loop; ++i) 134 for (uint32_t j=0; j<_param->_nb_read_unit[i]; ++j) 135 PORT_WRITE(out_ISSUE_EXECUTE_LOOP_VAL [i][j], ISSUE_EXECUTE_LOOP_VAL [i][j]); 136 137 log_end(Core_Glue,FUNCTION); 138 }; 139 140 }; // end namespace core_glue 141 }; // end namespace core 142 143 }; // end namespace behavioural 144 }; // end namespace morpheo 145 #endif 386 */ 387 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_transition.cpp
r111 r117 25 25 for (uint32_t i=0; i<_param->_nb_execute_loop; ++i) 26 26 { 27 27 // _priority_ooo_engine [i]->reset(); 28 28 _priority_read_unit [i]->reset(); 29 29 } 30 _priority_ooo_engine->reset(); 31 30 32 } 31 33 else … … 34 36 for (uint32_t i=0; i<_param->_nb_execute_loop; ++i) 35 37 { 36 38 // _priority_ooo_engine [i]->transition(); 37 39 _priority_read_unit [i]->transition(); 38 40 } 41 _priority_ooo_engine->transition(); 39 42 } 40 43 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Parameters.cpp
r88 r117 30 30 uint32_t * ooo_engine_nb_inst_branch_complete ,//[nb_ooo_engine] 31 31 uint32_t * nb_inst_insert ,//[nb_ooo_engine] 32 uint32_t * nb_inst_issue ,//[nb_ooo_engine] 32 uint32_t * nb_inst_reexecute ,//[nb_ooo_engine] 33 uint32_t * nb_inst_issue_queue ,//[nb_ooo_engine] 34 uint32_t * nb_inst_issue_slot ,//[nb_ooo_engine] 33 35 uint32_t ** nb_inst_execute ,//[nb_ooo_engine][ooo_engine_nb_execute_loop] 36 bool * issue_queue_in_order ,//[nb_ooo_engine] 34 37 uint32_t * nb_read_unit ,//[nb_execute_loop] 35 38 uint32_t * nb_write_unit ,//[nb_execute_loop] … … 44 47 Tpriority_t dispatch_priority , 45 48 Tload_balancing_t dispatch_load_balancing , 46 bool **** table_dispatch ,//[nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] 49 bool **** table_dispatch ,//[nb_ooo_engine][nb_inst_issue_slot][execute_loop][nb_read_unit] 50 bool *** table_issue_type ,// [execute_loop][nb_read_unit][nb_type] 47 51 uint32_t ** translate_ooo_engine_num_front_end ,//[nb_ooo_engine][ooo_engine_nb_front_end] 48 52 uint32_t ** translate_ooo_engine_num_execute_loop,//[nb_ooo_engine][ooo_engine_nb_execute_loop] … … 63 67 _ooo_engine_nb_inst_branch_complete = ooo_engine_nb_inst_branch_complete ; 64 68 _nb_inst_insert = nb_inst_insert ; 65 _nb_inst_issue = nb_inst_issue ; 69 _nb_inst_reexecute = nb_inst_reexecute ; 70 _nb_inst_issue_queue = nb_inst_issue_queue ; 71 _nb_inst_issue_slot = nb_inst_issue_slot ; 66 72 _nb_inst_execute = nb_inst_execute ; 73 _issue_queue_in_order = issue_queue_in_order ; 67 74 _nb_read_unit = nb_read_unit ; 68 75 _nb_write_unit = nb_write_unit ; … … 70 77 _dispatch_load_balancing = dispatch_load_balancing ; 71 78 _table_dispatch = table_dispatch ; 79 _table_issue_type = table_issue_type ; 72 80 _translate_ooo_engine_num_front_end = translate_ooo_engine_num_front_end ; 73 81 _translate_ooo_engine_num_execute_loop = translate_ooo_engine_num_execute_loop; … … 78 86 ALLOC1(_link_ooo_engine_with_front_end,uint32_t,_nb_front_end); 79 87 ALLOC1(_translate_num_front_end_to_ooo_engine_front_end_id,uint32_t,_nb_front_end); 80 81 88 for (uint32_t i=0; i<_nb_ooo_engine; ++i) 82 89 for (uint32_t j=0; j<_ooo_engine_nb_front_end[i]; ++j) … … 102 109 103 110 ALLOC2(_execute_loop_nb_inst_insert,uint32_t,_nb_execute_loop,_execute_loop_nb_ooo_engine[it1]); 104 ALLOC2(_execute_loop_nb_inst_issue ,uint32_t,_nb_execute_loop,_execute_loop_nb_ooo_engine[it1]);111 ALLOC2(_execute_loop_nb_inst_issue_slot ,uint32_t,_nb_execute_loop,_execute_loop_nb_ooo_engine[it1]); 105 112 106 113 for (uint32_t i=0; i<_nb_execute_loop; ++i) … … 108 115 { 109 116 uint32_t num_ooo_engine = _translate_execute_loop_num_ooo_engine [i][j]; 110 _execute_loop_nb_inst_issue [i][j] = _nb_inst_issue[num_ooo_engine];111 _execute_loop_nb_inst_insert [i][j] = _nb_inst_insert[num_ooo_engine];117 _execute_loop_nb_inst_issue_slot [i][j] = _nb_inst_issue_slot [num_ooo_engine]; 118 _execute_loop_nb_inst_insert [i][j] = _nb_inst_insert [num_ooo_engine]; 112 119 } 113 120 … … 118 125 _max_nb_write_unit = max<uint32_t>(_nb_write_unit ,_nb_execute_loop); 119 126 _max_nb_inst_insert = max<uint32_t>(_nb_inst_insert ,_nb_ooo_engine); 120 _max_nb_inst_issue = max<uint32_t>(_nb_inst_issue ,_nb_ooo_engine); 127 _max_nb_inst_issue_queue = max<uint32_t>(_nb_inst_issue_queue ,_nb_ooo_engine); 128 _max_nb_inst_issue_slot = max<uint32_t>(_nb_inst_issue_slot ,_nb_ooo_engine); 121 129 _max_nb_read_unit = max<uint32_t>(_nb_read_unit ,_nb_execute_loop); 122 130 … … 171 179 log_begin(Core_Glue,FUNCTION); 172 180 173 DELETE2(_execute_loop_nb_inst_issue ,_nb_execute_loop,_execute_loop_nb_ooo_engine[it1]);181 DELETE2(_execute_loop_nb_inst_issue_slot,_nb_execute_loop,_execute_loop_nb_ooo_engine[it1]); 174 182 DELETE2(_execute_loop_nb_inst_insert,_nb_execute_loop,_execute_loop_nb_ooo_engine[it1]); 175 183 DELETE2(_translate_num_execute_loop_to_ooo_engine_execute_loop_id, _nb_execute_loop,_execute_loop_nb_ooo_engine[it1]); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/src/Dcache_Access_genMealy_req.cpp
r88 r117 52 52 uint32_t num_port = _param->_table_routing[num_execute_loop][num_load_store_unit][num_cache_access]; 53 53 Tcontrol_t dcache_req_ack = PORT_READ(in_DCACHE_REQ_ACK [num_port]); 54 55 log_printf(TRACE,Dcache_Access,FUNCTION," * num_port : %d",num_port); 54 56 55 57 #ifdef STATISTICS … … 66 68 lsq_req_ack [num_execute_loop][num_load_store_unit][num_cache_access] = dcache_req_ack; 67 69 70 log_printf(TRACE,Dcache_Access,FUNCTION," * kane - dcache"); 71 68 72 if (_param->_have_port_dcache_thread_id) 69 73 { 70 74 Tcontext_t num_context = (_param->_have_port_lsq_thread_id [num_execute_loop][num_load_store_unit])?PORT_READ(in_LSQ_REQ_THREAD_ID [num_execute_loop][num_load_store_unit][num_cache_access]):0; 71 PORT_WRITE(out_DCACHE_REQ_THREAD_ID [num_port], _param->_translate_load_store_unit_to_thread[num_execute_loop][num_load_store_unit][num_context]); 75 Tcontext_t num_thread = _param->_translate_load_store_unit_to_thread[num_execute_loop][num_load_store_unit][num_context]; 76 log_printf(TRACE,Dcache_Access,FUNCTION," * num_context : %d",num_context); 77 log_printf(TRACE,Dcache_Access,FUNCTION," * num_thread : %d",num_thread ); 78 79 80 PORT_WRITE(out_DCACHE_REQ_THREAD_ID [num_port], num_thread); 72 81 } 73 82 // PORT_WRITE(out_DCACHE_REQ_THREAD_ID [num_port], ((num_execute_loop << _param->_shift_num_execute_loop )+ -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/src/Icache_Access_genMealy_req.cpp
r88 r117 50 50 Tcontrol_t icache_req_ack = PORT_READ(in_ICACHE_REQ_ACK [num_port]); 51 51 52 log_printf(TRACE,Dcache_Access,FUNCTION," * num_port : %d",num_port); 53 52 54 #ifdef STATISTICS 53 55 if (icache_req_ack) … … 63 65 context_req_ack [num_front_end][num_context] = icache_req_ack; 64 66 67 log_printf(TRACE,Dcache_Access,FUNCTION," * kane - icache"); 68 65 69 if (_param->_have_port_icache_thread_id) 66 PORT_WRITE(out_ICACHE_REQ_THREAD_ID [num_port], _param->_translate_context_to_thread[num_front_end][num_context]); 70 { 71 Tcontext_t num_thread = _param->_translate_context_to_thread[num_front_end][num_context]; 72 log_printf(TRACE,Dcache_Access,FUNCTION," * num_context : %d",num_context); 73 log_printf(TRACE,Dcache_Access,FUNCTION," * num_thread : %d",num_thread ); 74 75 PORT_WRITE(out_ICACHE_REQ_THREAD_ID [num_port], num_thread); 76 } 67 77 // if (_param->_have_port_icache_packet_id) 68 78 if (_param->_have_port_packet_id [num_front_end][num_context]) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/src/Parameters_msg_error.cpp
r88 r117 44 44 45 45 for (uint32_t i=0; i<_nb_front_end; i++) 46 for (uint32_t j=0; j<_nb_context [i]; j++) 47 { 48 uint32_t num_thread = _translate_context_to_thread [i][j]; 49 if (num_thread >= _nb_thread) 50 test.error(toString(_("Context [%d][%d] is linked with an invalid thread id.\n"),i,j)); 51 else 52 if (thread_link [num_thread] == true) 53 test.error(toString(_("Context [%d][%d] is linked with an already used thread id.\n"),i,j)); 46 { 47 for (uint32_t j=0; j<_nb_context [i]; j++) 48 { 49 uint32_t num_thread = _translate_context_to_thread [i][j]; 50 51 if (num_thread >= _nb_thread) 52 test.error(toString(_("Context [%d][%d] is linked with an invalid thread id.\n"),i,j)); 54 53 else 55 thread_link [num_thread] = true; 56 } 54 if (thread_link [num_thread] == true) 55 test.error(toString(_("Context [%d][%d] is linked with an already used thread id.\n"),i,j)); 56 else 57 thread_link [num_thread] = true; 58 } 59 } 57 60 58 61 for (uint32_t i=0; i<_nb_thread; ++i) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_genMealy.cpp
r116 r117 26 26 log_function(Functionnal_unit,FUNCTION,_name.c_str()); 27 27 28 { 29 internal_EXECUTE_OUT_VAL = (reg_BUSY_OUT and (_execute_operation_out->_timing._latence == 0)); 30 31 PORT_WRITE(out_EXECUTE_OUT_VAL , internal_EXECUTE_OUT_VAL); 32 } 33 34 { 35 internal_EXECUTE_IN_ACK = (not reg_BUSY_IN or 36 (reg_BUSY_IN and (not reg_BUSY_OUT or 37 (internal_EXECUTE_OUT_VAL and PORT_READ(in_EXECUTE_OUT_ACK))))); 38 39 PORT_WRITE(out_EXECUTE_IN_ACK , internal_EXECUTE_IN_ACK); 40 } 28 if (PORT_READ(in_NRESET) != 0) 29 { 30 { 31 internal_EXECUTE_OUT_VAL = (reg_BUSY_OUT and (_execute_operation_out->_timing._latence == 0)); 32 33 PORT_WRITE(out_EXECUTE_OUT_VAL , internal_EXECUTE_OUT_VAL); 34 } 35 36 { 37 internal_EXECUTE_IN_ACK = (not reg_BUSY_IN or 38 (reg_BUSY_IN and (not reg_BUSY_OUT or 39 (internal_EXECUTE_OUT_VAL and PORT_READ(in_EXECUTE_OUT_ACK))))); 40 41 PORT_WRITE(out_EXECUTE_IN_ACK , internal_EXECUTE_IN_ACK); 42 } 43 } 41 44 42 45 log_end(Functionnal_unit,FUNCTION); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_transition.cpp
r116 r117 60 60 61 61 if (reg_BUSY_IN and not reg_BUSY_OUT) 62 // if (not reg_BUSY_OUT_old or)63 62 { 64 63 reg_BUSY_OUT = reg_BUSY_IN; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/src/test2.cpp
r113 r117 70 70 sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET"); 71 71 72 // ~~~~~[ Interface "memory_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 72 sc_signal<Tcontrol_t > ** in_MEMORY_IN_VAL ; 73 sc_signal<Tcontrol_t > ** out_MEMORY_IN_ACK ; 74 sc_signal<Tcontext_t > ** in_MEMORY_IN_CONTEXT_ID ; 75 sc_signal<Tcontext_t > ** in_MEMORY_IN_FRONT_END_ID ; 76 sc_signal<Tcontext_t > ** in_MEMORY_IN_OOO_ENGINE_ID ; 77 sc_signal<Tpacket_t > ** in_MEMORY_IN_PACKET_ID ; 78 sc_signal<Toperation_t > ** in_MEMORY_IN_OPERATION ; 79 sc_signal<Ttype_t > ** in_MEMORY_IN_TYPE ; 80 sc_signal<Tlsq_ptr_t > ** in_MEMORY_IN_STORE_QUEUE_PTR_WRITE; 81 sc_signal<Tlsq_ptr_t > ** in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ; 82 sc_signal<Tcontrol_t > ** in_MEMORY_IN_HAS_IMMEDIAT ; 83 sc_signal<Tgeneral_data_t > ** in_MEMORY_IN_IMMEDIAT ; 84 sc_signal<Tgeneral_data_t > ** in_MEMORY_IN_DATA_RA ; 85 sc_signal<Tgeneral_data_t > ** in_MEMORY_IN_DATA_RB ; 86 sc_signal<Tspecial_data_t > ** in_MEMORY_IN_DATA_RC ; 87 sc_signal<Tcontrol_t > ** in_MEMORY_IN_WRITE_RD ; 88 sc_signal<Tgeneral_address_t> ** in_MEMORY_IN_NUM_REG_RD ; 89 sc_signal<Tcontrol_t > ** in_MEMORY_IN_WRITE_RE ; 90 sc_signal<Tspecial_address_t> ** in_MEMORY_IN_NUM_REG_RE ; 91 sc_signal<Tcontrol_t > ** out_MEMORY_OUT_VAL ; 92 sc_signal<Tcontrol_t > ** in_MEMORY_OUT_ACK ; 93 sc_signal<Tcontext_t > ** out_MEMORY_OUT_CONTEXT_ID ; 94 sc_signal<Tcontext_t > ** out_MEMORY_OUT_FRONT_END_ID ; 95 sc_signal<Tcontext_t > ** out_MEMORY_OUT_OOO_ENGINE_ID ; 96 sc_signal<Tpacket_t > ** out_MEMORY_OUT_PACKET_ID ; 97 //sc_signal<Toperation_t > ** out_MEMORY_OUT_OPERATION ; 98 //sc_signal<Ttype_t > ** out_MEMORY_OUT_TYPE ; 99 sc_signal<Tcontrol_t > ** out_MEMORY_OUT_WRITE_RD ; 100 sc_signal<Tgeneral_address_t> ** out_MEMORY_OUT_NUM_REG_RD ; 101 sc_signal<Tgeneral_data_t > ** out_MEMORY_OUT_DATA_RD ; 102 sc_signal<Tcontrol_t > ** out_MEMORY_OUT_WRITE_RE ; 103 sc_signal<Tspecial_address_t> ** out_MEMORY_OUT_NUM_REG_RE ; 104 sc_signal<Tspecial_data_t > ** out_MEMORY_OUT_DATA_RE ; 105 sc_signal<Texception_t > ** out_MEMORY_OUT_EXCEPTION ; 106 sc_signal<Tcontrol_t > ** out_MEMORY_OUT_NO_SEQUENCE ; 107 sc_signal<Taddress_t > ** out_MEMORY_OUT_ADDRESS ; 108 sc_signal<Tcontrol_t > ** out_DCACHE_REQ_VAL ; 109 sc_signal<Tcontrol_t > ** in_DCACHE_REQ_ACK ; 110 sc_signal<Tcontext_t > ** out_DCACHE_REQ_CONTEXT_ID ; 111 sc_signal<Tpacket_t > ** out_DCACHE_REQ_PACKET_ID ; 112 sc_signal<Tdcache_address_t > ** out_DCACHE_REQ_ADDRESS ; 113 sc_signal<Tdcache_type_t > ** out_DCACHE_REQ_TYPE ; 114 sc_signal<Tdcache_data_t > ** out_DCACHE_REQ_WDATA ; 115 sc_signal<Tcontrol_t > ** in_DCACHE_RSP_VAL ; 116 sc_signal<Tcontrol_t > ** out_DCACHE_RSP_ACK ; 117 sc_signal<Tcontext_t > ** in_DCACHE_RSP_CONTEXT_ID ; 118 sc_signal<Tpacket_t > ** in_DCACHE_RSP_PACKET_ID ; 119 sc_signal<Tdcache_data_t > ** in_DCACHE_RSP_RDATA ; 120 sc_signal<Tdcache_error_t > ** in_DCACHE_RSP_ERROR ; 121 sc_signal<Tcontrol_t > ** out_BYPASS_MEMORY_VAL ; 122 sc_signal<Tcontext_t > ** out_BYPASS_MEMORY_OOO_ENGINE_ID ; 123 sc_signal<Tgeneral_address_t> ** out_BYPASS_MEMORY_NUM_REG ; 124 sc_signal<Tgeneral_data_t > ** out_BYPASS_MEMORY_DATA ; 125 73 126 ALLOC1_SC_SIGNAL( in_MEMORY_IN_VAL ," in_MEMORY_IN_VAL ",Tcontrol_t ,_param->_nb_inst_memory); 74 127 ALLOC1_SC_SIGNAL(out_MEMORY_IN_ACK ,"out_MEMORY_IN_ACK ",Tcontrol_t ,_param->_nb_inst_memory); … … 379 432 tab_request[66].modif(550,0,0,0,65,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,1,0,0x0 ,0x0 ,0x0 ,1,0,0,0x55508570); // just to wait the dcache_rsp 380 433 381 const uint32_t nb_request = 64;//_param->_nb_packet; 434 const uint32_t nb_request = 66;//_param->_nb_packet; 435 // const uint32_t nb_request = 64;//_param->_nb_packet; 382 436 383 437 for (uint32_t i=0; i<nb_request; i++) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h
r110 r117 157 157 158 158 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 159 protected : Tstore_queue_entry_t * _store_queue ;160 protected : Tload_queue_entry_t * _load_queue ;161 protected : Tspeculative_access_queue_entry_t * _speculative_access_queue ;159 protected : Tstore_queue_entry_t * _store_queue ;//[size_store_queue] 160 protected : Tload_queue_entry_t * _load_queue ;//[size_load_queue] 161 protected : Tspeculative_access_queue_entry_t * _speculative_access_queue ;//[size_speculative_access_queue] 162 162 protected : morpheo::behavioural::generic::queue_control::Queue_Control * _speculative_access_queue_control; 163 163 … … 174 174 175 175 // Registers 176 public : Tlsq_ptr_t reg_STORE_QUEUE_PTR_READ; 177 //public : Tlsq_ptr_t reg_LOAD_QUEUE_PTR_READ ; 178 public : Tlsq_ptr_t reg_LOAD_QUEUE_CHECK_PRIORITY ; 176 public : Tlsq_ptr_t * reg_STORE_QUEUE_NB_CHECK ;//[size_store_queue] 177 public : Tlsq_ptr_t reg_STORE_QUEUE_PTR_READ ; 178 //public : Tlsq_ptr_t reg_LOAD_QUEUE_PTR_READ ; 179 public : Tlsq_ptr_t reg_LOAD_QUEUE_CHECK_PRIORITY; 179 180 180 181 // signal -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_allocation.cpp
r112 r117 146 146 147 147 // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 148 if (usage_is_set(_usage,USE_SYSTEMC)) 149 { 150 _speculative_access_queue_control = new morpheo::behavioural::generic::queue_control::Queue_Control (_param->_size_speculative_access_queue); 148 151 149 // internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ = new Tlsq_ptr_t [_param->_nb_cache_port]; 152 ALLOC1(_store_queue ,Tstore_queue_entry_t ,_param->_size_store_queue); 153 ALLOC1(_load_queue ,Tload_queue_entry_t ,_param->_size_load_queue); 154 ALLOC1(_speculative_access_queue,Tspeculative_access_queue_entry_t,_param->_size_speculative_access_queue); 150 155 151 // internal_MEMORY_IN_ACK = new Tcontrol_t [_param->_nb_inst_memory]; 152 // internal_MEMORY_OUT_VAL = new Tcontrol_t [_param->_nb_inst_memory]; 153 // internal_MEMORY_OUT_SELECT_QUEUE = new Tselect_queue_t [_param->_nb_inst_memory]; 154 // internal_MEMORY_OUT_PTR = new Tlsq_ptr_t [_param->_nb_inst_memory]; 155 156 // internal_DCACHE_RSP_ACK = new Tcontrol_t [_param->_nb_cache_port]; 157 // internal_DCACHE_REQ_VAL = new Tcontrol_t [_param->_nb_cache_port]; 158 // internal_DCACHE_REQ_SELECT_QUEUE = new Tselect_queue_t [_param->_nb_cache_port]; 156 ALLOC1(reg_STORE_QUEUE_NB_CHECK ,Tlsq_ptr_t ,_param->_size_store_queue); 157 158 // ALLOC1(internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ,Tlsq_ptr_t ,_param->_nb_cache_port); 159 160 // ALLOC1(internal_MEMORY_IN_ACK ,Tcontrol_t ,_param->_nb_inst_memory); 161 // ALLOC1(internal_MEMORY_OUT_VAL ,Tcontrol_t ,_param->_nb_inst_memory); 162 // ALLOC1(internal_MEMORY_OUT_SELECT_QUEUE ,Tselect_queue_t,_param->_nb_inst_memory); 163 // ALLOC1(internal_MEMORY_OUT_PTR ,Tlsq_ptr_t ,_param->_nb_inst_memory); 164 165 // ALLOC1(internal_DCACHE_RSP_ACK ,Tcontrol_t ,_param->_nb_cache_port ); 166 // ALLOC1(internal_DCACHE_REQ_VAL ,Tcontrol_t ,_param->_nb_cache_port ); 167 // ALLOC1(internal_DCACHE_REQ_SELECT_QUEUE ,Tselect_queue_t,_param->_nb_cache_port ); 168 } 159 169 160 170 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ … … 164 174 _component->generate_file(); 165 175 #endif 166 167 _store_queue = new Tstore_queue_entry_t [_param->_size_store_queue];168 _load_queue = new Tload_queue_entry_t [_param->_size_load_queue];169 _speculative_access_queue = new Tspeculative_access_queue_entry_t [_param->_size_speculative_access_queue];170 _speculative_access_queue_control = new morpheo::behavioural::generic::queue_control::Queue_Control (_param->_size_speculative_access_queue);171 176 172 177 log_printf(FUNC,Load_store_unit,FUNCTION,"End"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_deallocation.cpp
r97 r117 95 95 96 96 // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 97 delete _speculative_access_queue_control ; 97 98 98 // delete [] internal_MEMORY_IN_ACK ; 99 // delete [] internal_MEMORY_OUT_VAL ; 100 // delete [] internal_MEMORY_OUT_SELECT_QUEUE; 101 // delete [] internal_MEMORY_OUT_PTR ; 102 103 // delete [] internal_DCACHE_RSP_ACK ; 104 // delete [] internal_DCACHE_REQ_VAL ; 105 // delete [] internal_DCACHE_REQ_SELECT_QUEUE; 99 DELETE1(_store_queue ,_param->_size_store_queue); 100 DELETE1(_load_queue ,_param->_size_load_queue); 101 DELETE1(_speculative_access_queue,_param->_size_speculative_access_queue); 106 102 107 // delete [] internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ; 103 DELETE1(reg_STORE_QUEUE_NB_CHECK ,_param->_size_store_queue); 104 105 // DELETE1(internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ,_param->_nb_cache_port); 106 107 // DELETE1(internal_MEMORY_IN_ACK ,_param->_nb_inst_memory); 108 // DELETE1(internal_MEMORY_OUT_VAL ,_param->_nb_inst_memory); 109 // DELETE1(internal_MEMORY_OUT_SELECT_QUEUE ,_param->_nb_inst_memory); 110 // DELETE1(internal_MEMORY_OUT_PTR ,_param->_nb_inst_memory); 111 112 // DELETE1(internal_DCACHE_RSP_ACK ,_param->_nb_cache_port ); 113 // DELETE1(internal_DCACHE_REQ_VAL ,_param->_nb_cache_port ); 114 // DELETE1(internal_DCACHE_REQ_SELECT_QUEUE ,_param->_nb_cache_port ); 108 115 } 109 116 … … 112 119 delete _component; 113 120 114 delete [] _store_queue ;115 delete [] _load_queue ;116 delete _speculative_access_queue_control ;117 delete [] _speculative_access_queue ;118 121 119 122 log_printf(FUNC,Load_store_unit,FUNCTION,"End"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMoore.cpp
r104 r117 98 98 { 99 99 log_printf(TRACE,Load_store_unit,FUNCTION," * Store queue"); 100 if (_store_queue [reg_STORE_QUEUE_PTR_READ]._state == STORE_QUEUE_COMMIT) 100 // Can retire an store instruction if : 101 // * state is commit 102 // * none load must check this store 103 if ((_store_queue [reg_STORE_QUEUE_PTR_READ]._state == STORE_QUEUE_COMMIT) and 104 (reg_STORE_QUEUE_NB_CHECK [reg_STORE_QUEUE_PTR_READ] == 0)) 101 105 { 102 106 log_printf(TRACE,Load_store_unit,FUNCTION," * find : %d",reg_STORE_QUEUE_PTR_READ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_transition.cpp
r112 r117 242 242 243 243 for (uint32_t i=0; i< _param->_size_store_queue ; i++) 244 { 245 reg_STORE_QUEUE_NB_CHECK [i] = 0; 244 246 _store_queue [i]._state = STORE_QUEUE_EMPTY; 247 } 245 248 246 249 for (uint32_t i=0; i< _param->_size_load_queue ; i++) … … 252 255 else 253 256 { 257 //================================================================ 258 // Interface "MEMORY_OUT" 259 //================================================================ 260 261 if (( internal_MEMORY_OUT_VAL == 1) and 262 (PORT_READ(in_MEMORY_OUT_ACK[0]) == 1)) 263 { 264 log_printf(TRACE,Load_store_unit,FUNCTION," * MEMORY_OUT[0] transaction"); 265 266 switch (internal_MEMORY_OUT_SELECT_QUEUE) 267 { 268 case SELECT_STORE_QUEUE : 269 { 270 // ======================= 271 // ===== STORE_QUEUE ===== 272 // ======================= 273 274 log_printf(TRACE,Load_store_unit,FUNCTION," * store_queue [%d]",reg_STORE_QUEUE_PTR_READ); 275 276 // Entry flush and increase the read pointer 277 _store_queue [reg_STORE_QUEUE_PTR_READ]._state = STORE_QUEUE_EMPTY; 278 279 reg_STORE_QUEUE_PTR_READ = (reg_STORE_QUEUE_PTR_READ+1)%_param->_size_store_queue; 280 281 break; 282 } 283 case SELECT_LOAD_QUEUE : 284 { 285 // ====================== 286 // ===== LOAD_QUEUE ===== 287 // ====================== 288 289 log_printf(TRACE,Load_store_unit,FUNCTION," * load_queue [%d]",internal_MEMORY_OUT_PTR); 290 291 // Entry flush and increase the read pointer 292 293 _load_queue [internal_MEMORY_OUT_PTR]._state = LOAD_QUEUE_EMPTY; 294 295 // reg_LOAD_QUEUE_PTR_READ = (reg_LOAD_QUEUE_PTR_READ+1)%_param->_size_load_queue; 296 297 break; 298 } 299 case SELECT_LOAD_QUEUE_SPECULATIVE : 300 { 301 log_printf(TRACE,Load_store_unit,FUNCTION," * load_queue [%d] (speculative)",internal_MEMORY_OUT_PTR); 302 303 // !!! WARNING !!! 304 // !!! Test special case : 305 // !!! in a cycle an instruction can check the last store AND commit instruction 306 // !!! also the memory_out is before the port_check 307 308 _load_queue [internal_MEMORY_OUT_PTR]._state = LOAD_QUEUE_CHECK; 309 // NOTE : a speculative load write in the register file. 310 // if the speculation is a miss, write_rd is re set at 1. 311 _load_queue [internal_MEMORY_OUT_PTR]._write_rd = 0; 312 313 #ifdef STATISTICS 314 if (usage_is_set(_usage,USE_STATISTICS)) 315 (*_stat_nb_inst_load_commit_speculative) ++; 316 #endif 317 318 break; 319 } 320 321 break; 322 } 323 } 324 254 325 //================================================================ 255 326 // Interface "PORT_CHECK" … … 278 349 279 350 // find a entry that it need a check 280 Tlsq_ptr_t index_store = _load_queue[index_load]._store_queue_ptr_write; 351 Tlsq_ptr_t index_store = _load_queue[index_load]._store_queue_ptr_write; 352 Tlsq_ptr_t index_store_old = index_store; 353 281 354 // Init variable 282 355 bool end_check = false; … … 534 607 // The check is finish if all bit is set 535 608 end_check = (_load_queue[index_load]._check_hit_byte == _param->_mask_check_hit_byte); 609 536 610 } 537 611 } … … 553 627 log_printf(TRACE,Load_store_unit,FUNCTION," * next"); 554 628 log_printf(TRACE,Load_store_unit,FUNCTION," * new store_queue_ptr_write : %d",index_store); 629 630 log_printf(TRACE,Load_store_unit,FUNCTION," * update reg_STORE_QUEUE_NB_CHECK"); 631 #ifdef DEBUG 632 if (reg_STORE_QUEUE_NB_CHECK [index_store] == 0) 633 throw ERRORMORPHEO(FUNCTION,_("reg_STORE_QUEUE_NB_CHECK must be > 0\n")); 634 #endif 635 reg_STORE_QUEUE_NB_CHECK [index_store] --; 636 555 637 // if (_load_queue[index_load]._store_queue_ptr_write == 0) 556 638 // _load_queue[index_load]._store_queue_ptr_write = _param->_size_store_queue-1; … … 615 697 log_printf(TRACE,Load_store_unit,FUNCTION," * state new : %s",toString(_load_queue[index_load]._state).c_str()); 616 698 log_printf(TRACE,Load_store_unit,FUNCTION," * exception : %d",_load_queue[index_load]._exception); 699 700 if (end_check) 701 { 702 log_printf(TRACE,Load_store_unit,FUNCTION," * end check, decrease all nb_check"); 703 704 uint32_t i=index_store; 705 while (i!=reg_STORE_QUEUE_PTR_READ) 706 { 707 i=((i==0)?_param->_size_store_queue:i)-1; 708 709 #ifdef DEBUG 710 if (reg_STORE_QUEUE_NB_CHECK [i] == 0) 711 throw ERRORMORPHEO(FUNCTION,_("reg_STORE_QUEUE_NB_CHECK must be > 0\n")); 712 #endif 713 714 reg_STORE_QUEUE_NB_CHECK [i] --; 715 //i=(i+1)%_param->_size_store_queue; 716 } 717 } 617 718 } 618 719 } … … 803 904 804 905 //================================================================ 805 // Interface "MEMORY_OUT"806 //================================================================807 808 if (( internal_MEMORY_OUT_VAL == 1) and809 (PORT_READ(in_MEMORY_OUT_ACK[0]) == 1))810 {811 log_printf(TRACE,Load_store_unit,FUNCTION," * MEMORY_OUT[0] transaction");812 813 switch (internal_MEMORY_OUT_SELECT_QUEUE)814 {815 case SELECT_STORE_QUEUE :816 {817 // =======================818 // ===== STORE_QUEUE =====819 // =======================820 821 log_printf(TRACE,Load_store_unit,FUNCTION," * store_queue [%d]",reg_STORE_QUEUE_PTR_READ);822 823 // Entry flush and increase the read pointer824 _store_queue [reg_STORE_QUEUE_PTR_READ]._state = STORE_QUEUE_EMPTY;825 826 reg_STORE_QUEUE_PTR_READ = (reg_STORE_QUEUE_PTR_READ+1)%_param->_size_store_queue;827 828 break;829 }830 case SELECT_LOAD_QUEUE :831 {832 // ======================833 // ===== LOAD_QUEUE =====834 // ======================835 836 log_printf(TRACE,Load_store_unit,FUNCTION," * load_queue [%d]",internal_MEMORY_OUT_PTR);837 838 // Entry flush and increase the read pointer839 840 _load_queue [internal_MEMORY_OUT_PTR]._state = LOAD_QUEUE_EMPTY;841 842 // reg_LOAD_QUEUE_PTR_READ = (reg_LOAD_QUEUE_PTR_READ+1)%_param->_size_load_queue;843 844 break;845 }846 case SELECT_LOAD_QUEUE_SPECULATIVE :847 {848 log_printf(TRACE,Load_store_unit,FUNCTION," * load_queue [%d] (speculative)",internal_MEMORY_OUT_PTR);849 850 _load_queue [internal_MEMORY_OUT_PTR]._state = LOAD_QUEUE_CHECK;851 // NOTE : a speculative load write in the register file.852 // if the speculation is a miss, write_rd is re set at 1.853 _load_queue [internal_MEMORY_OUT_PTR]._write_rd = 0;854 855 #ifdef STATISTICS856 if (usage_is_set(_usage,USE_STATISTICS))857 (*_stat_nb_inst_load_commit_speculative) ++;858 #endif859 860 break;861 }862 863 break;864 }865 }866 867 //================================================================868 906 // Interface "DCACHE_REQ" 869 907 //================================================================ … … 943 981 Tdcache_address_t address_lsb = (address & _param->_mask_address_lsb); 944 982 Tdcache_address_t check_hit_byte = gen_mask_not<Tdcache_address_t>(address_lsb+(memory_size(operation)>>3)-1,address_lsb) & _param->_mask_check_hit_byte; 983 Tlsq_ptr_t store_queue_ptr_write = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._store_queue_ptr_write; 945 984 946 985 log_printf(TRACE,Load_store_unit,FUNCTION," * address : 0x%.8x", address); … … 955 994 _load_queue [ptr_write]._packet_id = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._packet_id; 956 995 _load_queue [ptr_write]._operation = operation; 957 _load_queue [ptr_write]._store_queue_ptr_write = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._store_queue_ptr_write;996 _load_queue [ptr_write]._store_queue_ptr_write = store_queue_ptr_write; 958 997 _load_queue [ptr_write]._address = address; 959 998 _load_queue [ptr_write]._check_hit_byte = check_hit_byte; … … 964 1003 // NOTE : if have an exception, must write in register, because a depend instruction wait the load data. 965 1004 _load_queue [ptr_write]._write_rd = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._write_rd ; 966 967 1005 _load_queue [ptr_write]._num_reg_rd = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._num_reg_rd ; 968 1006 _load_queue [ptr_write]._exception = exception; … … 980 1018 (*_stat_nb_inst_load) ++; 981 1019 #endif 1020 1021 // Only load need check 1022 if (is_operation_memory_load(_load_queue [ptr_write]._operation)) 1023 { 1024 log_printf(TRACE,Load_store_unit,FUNCTION," * update nb_check"); 1025 log_printf(TRACE,Load_store_unit,FUNCTION," * store_queue_ptr_write : %d",store_queue_ptr_write); 1026 log_printf(TRACE,Load_store_unit,FUNCTION," * reg_STORE_QUEUE_PTR_READ : %d",reg_STORE_QUEUE_PTR_READ); 1027 1028 uint32_t i=store_queue_ptr_write; 1029 while (i!=reg_STORE_QUEUE_PTR_READ) 1030 { 1031 i=((i==0)?_param->_size_store_queue:i)-1; 1032 1033 log_printf(TRACE,Load_store_unit,FUNCTION," * i : %d",i); 1034 1035 reg_STORE_QUEUE_NB_CHECK [i] ++; 1036 } 1037 } 982 1038 } 983 1039 … … 1075 1131 uint32_t j = (reg_STORE_QUEUE_PTR_READ+i)%_param->_size_store_queue; 1076 1132 1077 log_printf(TRACE,Load_store_unit,FUNCTION," [%.4d] %.4d %.4d %.4d, %.4d, %.4d, %.4d, %.8x %.8x, %.2d, % s",1133 log_printf(TRACE,Load_store_unit,FUNCTION," [%.4d] %.4d %.4d %.4d, %.4d, %.4d, %.4d, %.8x %.8x, %.2d, %.2d %s", 1078 1134 j, 1079 1135 _store_queue[j]._context_id , … … 1088 1144 //_store_queue[j]._num_reg_rd , 1089 1145 _store_queue[j]._exception , 1146 reg_STORE_QUEUE_NB_CHECK [j] , 1090 1147 toString(_store_queue[j]._state).c_str()); 1091 1148 } -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Parameters.cpp
r104 r117 58 58 59 59 _size_dcache_context_id = log2(nb_context) + log2(nb_front_end) + log2(nb_ooo_engine); 60 _size_dcache_packet_id = (log2((size_store_queue>size_load_queue)?size_store_queue:size_load_queue))+1; 61 60 _size_dcache_packet_id = log2((size_store_queue>size_load_queue)?size_store_queue:size_load_queue)+1; 62 61 _have_port_dcache_context_id = _size_dcache_context_id>0; 63 62 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/include/Types.h
r98 r117 121 121 _immediat = x._immediat ; 122 122 _read_ra = x._read_ra ; 123 _read_ra_val = x._read_ra == 1; //if not must read, the registerFile is already access123 _read_ra_val = ((x._read_ra == 1) and (x._num_reg_ra != 0)); //if not must read, the registerFile is already access 124 124 _num_reg_ra = x._num_reg_ra ; 125 _data_ra_val = ((x._read_ra == 0) or (x._num_reg_ra == 0)); //if not must read, the data is already valid 125 // _data_ra_val = ((x._read_ra == 0) or (x._num_reg_ra == 0)); //if not must read, the data is already valid 126 _data_ra_val = not _read_ra_val; 126 127 _data_ra = 0 ; 127 128 _read_rb = x._read_rb ; 128 _read_rb_val = x._read_rb == 1;129 _read_rb_val = ((x._read_rb == 1) and (x._num_reg_rb != 0)); 129 130 _num_reg_rb = x._num_reg_rb ; 130 _data_rb_val = ((x._read_rb == 0) or (x._num_reg_rb == 0)); 131 // _data_rb_val = ((x._read_rb == 0) or (x._num_reg_rb == 0)); 132 _data_rb_val = not _read_rb_val; 131 133 _data_rb = 0 ; 132 134 _read_rc = x._read_rc ; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_transition.cpp
r112 r117 65 65 66 66 if(_param->_have_port_context_id ) 67 67 entry->_context_id = PORT_READ(in_READ_QUEUE_IN_CONTEXT_ID ); 68 68 if(_param->_have_port_front_end_id ) 69 69 entry->_front_end_id = PORT_READ(in_READ_QUEUE_IN_FRONT_END_ID); 70 70 if(_param->_have_port_ooo_engine_id) 71 71 entry->_ooo_engine_id= PORT_READ(in_READ_QUEUE_IN_OOO_ENGINE_ID); 72 72 if(_param->_have_port_rob_ptr ) 73 73 entry->_rob_id = PORT_READ(in_READ_QUEUE_IN_ROB_ID ); 74 74 entry->_operation = PORT_READ(in_READ_QUEUE_IN_OPERATION ); 75 75 entry->_type = PORT_READ(in_READ_QUEUE_IN_TYPE ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue_genMoore.cpp
r115 r117 100 100 internal_WRITE_QUEUE_OUT_VAL = ((not _queue->empty() ) and 101 101 (not _queue->front()->_write_rd) and 102 (not _queue->front()->_write_re)); 102 (not _queue->front()->_write_re) and 103 (_queue->front()->_exception != EXCEPTION_MEMORY_LOAD_SPECULATIVE) 104 ); 103 105 104 106 PORT_WRITE(out_WRITE_QUEUE_OUT_VAL, internal_WRITE_QUEUE_OUT_VAL); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/src/Read_unit_to_Execution_unit_genMealy.cpp
r97 r117 22 22 void Read_unit_to_Execution_unit::genMealy (void) 23 23 { 24 log_printf(FUNC,Read_unit_to_Execution_unit,FUNCTION,"Begin"); 24 log_begin(Read_unit_to_Execution_unit,FUNCTION); 25 log_function(Read_unit_to_Execution_unit,FUNCTION,_name.c_str()); 25 26 26 27 bool execute_unit_use [_param->_nb_execute_unit][_param->_max_nb_execute_unit_port]; … … 35 36 bool ack = false; 36 37 37 log_printf(TRACE,Read_unit_to_Execution_unit,FUNCTION," Test Read_unit[%d][%d]",i,j);38 log_printf(TRACE,Read_unit_to_Execution_unit,FUNCTION," * Test Read_unit[%d][%d]",i,j); 38 39 39 40 if (PORT_READ(in_READ_UNIT_OUT_VAL [i][j]) == true) 40 41 { 41 log_printf(TRACE,Read_unit_to_Execution_unit,FUNCTION,"* have a valid entry.");42 log_printf(TRACE,Read_unit_to_Execution_unit,FUNCTION," * have a valid entry."); 42 43 43 44 Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_READ_UNIT_OUT_CONTEXT_ID [i][j]):0; … … 51 52 #ifdef DEBUG_TEST 52 53 if (_destination[i][num_thread][type].empty()) 53 throw ERRORMORPHEO(FUNCTION,"Invalid Operation : They have no execute_unit to receive a operation from the read_unit ["+toString(i)+"], thread ["+toString(num_thread)+"] and a operation's type ["+toString(type)+"].");54 throw ERRORMORPHEO(FUNCTION,toString(_("Invalid Operation : They have no execute_unit to receive a operation from the read_unit [%d], thread [%d] and a operation's type [%s]."),i,num_thread,toString(type).c_str())); 54 55 #endif 55 56 … … 62 63 uint32_t port = (*it).elt; 63 64 64 log_printf(TRACE,Read_unit_to_Execution_unit,FUNCTION," * Test destination [%d][%d].",dest,port);65 log_printf(TRACE,Read_unit_to_Execution_unit,FUNCTION," * Test destination [%d][%d].",dest,port); 65 66 66 67 if (execute_unit_use [dest][port] == false) 67 68 { 68 log_printf(TRACE,Read_unit_to_Execution_unit,FUNCTION,"* Is ok! Link.");69 log_printf(TRACE,Read_unit_to_Execution_unit,FUNCTION," * Is ok! Link."); 69 70 70 71 // have find !!! … … 104 105 PORT_WRITE(out_EXECUTE_UNIT_IN_VAL[i][j], execute_unit_use[i][j]); 105 106 106 log_ printf(FUNC,Read_unit_to_Execution_unit,FUNCTION,"End");107 log_end(Read_unit_to_Execution_unit,FUNCTION); 107 108 }; 108 109 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/src/Parameters.cpp
r115 r117 531 531 } 532 532 533 _have_port_dcache_context_id = (_max_size_dcache_context_id>1); 534 533 // log_printf(TRACE,Load_store_unit,FUNCTION,"kane : size_dcache_context_id : %d",_max_size_dcache_context_id ); 534 // log_printf(TRACE,Load_store_unit,FUNCTION,"kane : size_dcache_packet_id : %d",_max_size_dcache_packet_id ); 535 536 _have_port_dcache_context_id = (_max_size_dcache_context_id>0); 537 538 // log_printf(TRACE,Load_store_unit,FUNCTION,"kane : have_port_dcache_context_id : %d",_have_port_dcache_context_id); 535 539 536 540 if (is_toplevel) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Types.h
r111 r117 41 41 CONTEXT_STATE_KO_MSYNC_EXEC , // wait completion of msync operation 42 42 // CONTEXT_STATE_KO_PSYNC , // wait completion of all operation and after flush pipeline 43 CONTEXT_STATE_KO_PSYNC_FLUSH , // wait completion of all 43 CONTEXT_STATE_KO_PSYNC_FLUSH , // wait completion of all 44 44 CONTEXT_STATE_KO_PSYNC_ADDR , // wait completion of all 45 45 // CONTEXT_STATE_KO_CSYNC , // wait completion of all operation and after flush pipeline and flush ALL units (MMU, cache ...) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_transition.cpp
r111 r117 352 352 log_printf(TRACE,Context_State,FUNCTION," * BRANCH_COMPLETE [%d]",i); 353 353 354 context_state_t state = reg_STATE [i]; 354 Tcontext_t context_id = (_param->_have_port_context_id)?PORT_READ(in_BRANCH_COMPLETE_CONTEXT_ID [i]):0; 355 356 context_state_t state = reg_STATE [context_id]; 355 357 356 358 Tdepth_t depth = (_param->_have_port_depth)?PORT_READ(in_BRANCH_COMPLETE_DEPTH [i]):0; 357 Tdepth_t depth_cur = reg_EVENT_DEPTH [ i];358 Tdepth_t depth_min = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN [ i]):0;359 Tdepth_t depth_max = _param->_nb_inst_branch_speculated [ i];359 Tdepth_t depth_cur = reg_EVENT_DEPTH [context_id]; 360 Tdepth_t depth_min = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN [context_id]):0; 361 Tdepth_t depth_max = _param->_nb_inst_branch_speculated [context_id]; 360 362 361 363 Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min)); … … 375 377 ((depth1==depth0) and (priority1>=priority0))); // >= because another branch can be a miss prediction with same depth 376 378 379 log_printf(TRACE,Context_State,FUNCTION," * context_id: %d",context_id); 377 380 log_printf(TRACE,Context_State,FUNCTION," * depth : %d",depth ); 378 381 log_printf(TRACE,Context_State,FUNCTION," * depth_cur : %d",depth_cur ); … … 387 390 if (is_valid) 388 391 { 389 // reg_STATE [ i] = CONTEXT_STATE_KO_MISS_BRANCH_ADDR;390 reg_STATE [ i] = CONTEXT_STATE_KO_MISS_BRANCH_WAIT_UPDATE;391 reg_EVENT_DEPTH [ i] = depth;392 // reg_STATE [context_id] = CONTEXT_STATE_KO_MISS_BRANCH_ADDR; 393 reg_STATE [context_id] = CONTEXT_STATE_KO_MISS_BRANCH_WAIT_UPDATE; 394 reg_EVENT_DEPTH [context_id] = depth; 392 395 } 393 396 } -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/Instruction/src/Instruction.cpp
r101 r117 24 24 namespace decod { 25 25 26 #define EXTENDS(x,nb_bits) extend<Tgeneral_data_t>( 32, x,true ,nb_bits)27 #define EXTENDZ(x,nb_bits) extend<Tgeneral_data_t>( 32, x,false,nb_bits)26 #define EXTENDS(x,nb_bits) extend<Tgeneral_data_t>(param->_size_data, x,true ,nb_bits) 27 #define EXTENDZ(x,nb_bits) extend<Tgeneral_data_t>(param->_size_data, x,false,nb_bits) 28 28 29 29 void instruction_decod (decod_instruction_t * inst, decod_param_t * param) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/SelfTest/src/test.cpp
r112 r117 52 52 sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5); 53 53 sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET"); 54 55 sc_signal<Tcontrol_t > *** in_IFETCH_VAL ; 56 sc_signal<Tcontrol_t > *** out_IFETCH_ACK ; 57 sc_signal<Tinstruction_t > *** in_IFETCH_INSTRUCTION ; 58 59 sc_signal<Tcontext_t > ** in_IFETCH_CONTEXT_ID ; 60 sc_signal<Tgeneral_address_t > ** in_IFETCH_ADDRESS ; 61 //sc_signal<Tgeneral_address_t > ** in_IFETCH_ADDRESS_NEXT ; 62 sc_signal<Tinst_ifetch_ptr_t > ** in_IFETCH_INST_IFETCH_PTR ; 63 sc_signal<Tbranch_state_t > ** in_IFETCH_BRANCH_STATE ; 64 sc_signal<Tprediction_ptr_t > ** in_IFETCH_BRANCH_UPDATE_PREDICTION_ID ; 65 sc_signal<Texception_t > ** in_IFETCH_EXCEPTION ; 66 67 sc_signal<Tcontrol_t > ** out_DECOD_VAL ; 68 sc_signal<Tcontrol_t > ** in_DECOD_ACK ; 69 sc_signal<Tcontext_t > ** out_DECOD_CONTEXT_ID ; 70 sc_signal<Tdepth_t > ** out_DECOD_DEPTH ; 71 sc_signal<Ttype_t > ** out_DECOD_TYPE ; 72 sc_signal<Toperation_t > ** out_DECOD_OPERATION ; 73 sc_signal<Tcontrol_t > ** out_DECOD_NO_EXECUTE ; 74 sc_signal<Tcontrol_t > ** out_DECOD_IS_DELAY_SLOT ; 75 sc_signal<Tgeneral_data_t > ** out_DECOD_ADDRESS ; 76 77 sc_signal<Tgeneral_data_t > ** out_DECOD_ADDRESS_NEXT ; 78 sc_signal<Tcontrol_t > ** out_DECOD_HAS_IMMEDIAT ; 79 sc_signal<Tgeneral_data_t > ** out_DECOD_IMMEDIAT ; 80 sc_signal<Tcontrol_t > ** out_DECOD_READ_RA ; 81 sc_signal<Tgeneral_address_t > ** out_DECOD_NUM_REG_RA ; 82 sc_signal<Tcontrol_t > ** out_DECOD_READ_RB ; 83 sc_signal<Tgeneral_address_t > ** out_DECOD_NUM_REG_RB ; 84 sc_signal<Tcontrol_t > ** out_DECOD_READ_RC ; 85 sc_signal<Tspecial_address_t > ** out_DECOD_NUM_REG_RC ; 86 sc_signal<Tcontrol_t > ** out_DECOD_WRITE_RD ; 87 sc_signal<Tgeneral_address_t > ** out_DECOD_NUM_REG_RD ; 88 sc_signal<Tcontrol_t > ** out_DECOD_WRITE_RE ; 89 sc_signal<Tspecial_address_t > ** out_DECOD_NUM_REG_RE ; 90 sc_signal<Texception_t > ** out_DECOD_EXCEPTION_USE ; 91 sc_signal<Texception_t > ** out_DECOD_EXCEPTION ; 92 93 sc_signal<Tcontrol_t > ** out_PREDICT_VAL ; 94 sc_signal<Tcontrol_t > ** in_PREDICT_ACK ; 95 sc_signal<Tcontext_t > ** out_PREDICT_CONTEXT_ID ; 96 sc_signal<Tcontrol_t > ** out_PREDICT_MATCH_INST_IFETCH_PTR ; 97 sc_signal<Tbranch_state_t > ** out_PREDICT_BRANCH_STATE ; 98 sc_signal<Tprediction_ptr_t > ** out_PREDICT_BRANCH_UPDATE_PREDICTION_ID; 99 sc_signal<Tbranch_condition_t> ** out_PREDICT_BRANCH_CONDITION ; 100 //sc_signal<Tcontrol_t > ** out_PREDICT_BRANCH_STACK_WRITE ; 101 sc_signal<Tcontrol_t > ** out_PREDICT_BRANCH_DIRECTION ; 102 sc_signal<Tgeneral_data_t > ** out_PREDICT_ADDRESS_SRC ; 103 sc_signal<Tgeneral_data_t > ** out_PREDICT_ADDRESS_DEST ; 104 sc_signal<Tcontrol_t > ** in_PREDICT_CAN_CONTINUE ; 105 106 sc_signal<Tdepth_t > ** in_DEPTH_MIN ; 107 sc_signal<Tdepth_t > ** in_DEPTH_MAX ; 108 sc_signal<Tcontrol_t > ** in_DEPTH_FULL ; 109 110 sc_signal<Tcounter_t > ** out_NB_INST_DECOD_ALL ; 111 112 sc_signal<Tcontrol_t > ** in_CONTEXT_DECOD_ENABLE ; 113 sc_signal<Tcontrol_t > ** in_CONTEXT_DEPTH_VAL ; 114 sc_signal<Tdepth_t > ** in_CONTEXT_DEPTH ; 115 116 sc_signal<Tcontrol_t > * out_CONTEXT_EVENT_VAL ; 117 sc_signal<Tcontrol_t > * in_CONTEXT_EVENT_ACK ; 118 sc_signal<Tcontext_t > * out_CONTEXT_EVENT_CONTEXT_ID ; 119 sc_signal<Tdepth_t > * out_CONTEXT_EVENT_DEPTH ; 120 sc_signal<Tevent_type_t > * out_CONTEXT_EVENT_TYPE ; 121 sc_signal<Tcontrol_t > * out_CONTEXT_EVENT_IS_DELAY_SLOT ; 122 sc_signal<Tgeneral_data_t > * out_CONTEXT_EVENT_ADDRESS ; 123 sc_signal<Tgeneral_data_t > * out_CONTEXT_EVENT_ADDRESS_EPCR ; 124 125 54 126 55 127 ALLOC2_SC_SIGNAL( in_IFETCH_VAL ," in_IFETCH_VAL ",Tcontrol_t ,_param->_nb_context, _param->_nb_inst_fetch[it1]); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_allocation.cpp
r112 r117 242 242 243 243 #if defined(DEBUG) and defined(DEBUG_Update_Prediction_Table) and (DEBUG_Update_Prediction_Table == true) 244 directory_init (); 245 244 246 branchement_log_file = new std::ofstream [_param->_nb_thread]; 245 247 for (uint32_t i=0; i<_param->_nb_thread; ++i) 246 248 if (_param->_have_thread [i]) 247 249 { 248 std::string filename = "Branchement_prediction-thread_" + toString(i) +".log";250 std::string filename = MORPHEO_LOG+"/"+toString(getpid())+"-Branchement_prediction-thread_"+toString(i)+".log"; 249 251 250 252 branchement_log_file [i] .open(filename.c_str() ,std::ios::out | std::ios::trunc); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Parameters.h
r110 r117 60 60 public : uint32_t ** _array_size_depth ;//[nb_front_end][nb_context] 61 61 //public : uint32_t _max_size_depth ; 62 public : Tpacket_t _shift_num_bank ; 63 public : Tpacket_t _mask_size_bank ; 62 63 //public : Tpacket_t _shift_num_bank ; 64 public : Tpacket_t _mask_num_bank ; 65 public : Tpacket_t _shift_num_slot ; 66 //public : Tpacket_t _mask_num_slot ; 67 64 68 65 69 //public : bool _have_port_front_end_id ; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_allocation.cpp
r112 r117 336 336 337 337 #if defined(DEBUG) and defined(DEBUG_Commit_unit) and (DEBUG_Commit_unit == true) 338 directory_init (); 339 338 340 instruction_log_file = new std::ofstream [_param->_nb_thread]; 339 341 for (uint32_t i=0; i<_param->_nb_thread; ++i) 340 342 if (_param->_have_thread [i]) 341 343 { 342 std::string filename = "Instruction_flow-thread_" + toString(i) +".log";344 std::string filename = MORPHEO_LOG+"/"+toString(getpid())+"-Instruction_flow-thread_"+toString(i)+"-"+toString(getpid())+".log"; 343 345 344 346 instruction_log_file [i] .open(filename.c_str() ,std::ios::out | std::ios::trunc); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_commit.cpp
r100 r117 49 49 // packet_id number can 50 50 Tpacket_t packet_id = (_param->_have_port_rob_ptr )?PORT_READ(in_COMMIT_PACKET_ID [i]):0; 51 uint32_t num_bank = packet_id >> _param->_shift_num_bank;51 uint32_t num_bank = packet_id & _param->_mask_num_bank; 52 52 uint32_t num_bank_access = bank_nb_access [num_bank]; 53 53 … … 62 62 internal_BANK_COMMIT_NUM_INST [num_bank][num_bank_access] = i; 63 63 64 Tpacket_t num_packet = packet_id & _param->_mask_size_bank;64 Tpacket_t num_packet = packet_id >> _param->_shift_num_slot; 65 65 66 66 // find the good entry !!! -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_insert.cpp
r112 r117 99 99 insert_ack [num_rename_unit][num_inst_insert] = true; 100 100 101 Tpacket_t packet_id = (( num_bank << _param->_shift_num_bank) | reg_BANK_PTR [num_bank]);101 Tpacket_t packet_id = ((reg_BANK_PTR [num_bank] << _param->_shift_num_slot) | num_bank); 102 102 103 103 #ifdef SYSTEMC_VHDL_COMPATIBILITY -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp
r115 r117 392 392 log_printf(TRACE,Commit_unit,FUNCTION," * front_end_id : %d",front_end_id ); 393 393 log_printf(TRACE,Commit_unit,FUNCTION," * context_id : %d",context_id ); 394 log_printf(TRACE,Commit_unit,FUNCTION," * rob_ptr : %d",(( num_bank << _param->_shift_num_bank) | entry->ptr));394 log_printf(TRACE,Commit_unit,FUNCTION," * rob_ptr : %d",((entry->ptr << _param->_shift_num_slot) | num_bank)); 395 395 log_printf(TRACE,Commit_unit,FUNCTION," * num_thread : %d",num_thread ); 396 396 log_printf(TRACE,Commit_unit,FUNCTION," * type : %s",toString(type).c_str()); … … 740 740 num_bank , 741 741 (*it)->ptr , 742 (( num_bank << _param->_shift_num_bank) | (*it)->ptr),742 (((*it)->ptr << _param->_shift_num_slot) | num_bank), 743 743 (*it)->front_end_id , 744 744 (*it)->context_id , -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Parameters.cpp
r110 r117 71 71 _max_nb_inst_retire = max<uint32_t>(_nb_inst_retire,_nb_rename_unit); 72 72 _size_bank = _size_queue/_nb_bank; 73 _shift_num_bank = log2(_size_bank); 74 _mask_size_bank = gen_mask<Tpacket_t>(log2(_size_bank)); 73 74 // _shift_num_bank = 0; 75 _mask_num_bank = gen_mask<Tpacket_t>(log2(_nb_bank)); 76 _shift_num_slot = log2(_nb_bank); 77 // _mask_num_slot = gen_mask<Tpacket_t>(log2(_size_bank)); 75 78 76 79 _have_port_rename_unit_id = _size_rename_unit_id > 0; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/SelfTest/config_min.cfg
r111 r117 13 13 1 1 *2 # size_store_queue_ptr 14 14 0 0 *2 # size_load_queue_ptr 15 1 1 *2 # nb_inst_issue16 15 1 1 *2 # nb_inst_rename [0] [nb_rename_unit] 17 16 1 1 *2 # nb_inst_reexecute … … 19 18 1 1 *2 # priority 20 19 1 1 *2 # load_balancing 21 1 1 +1 # table_routing [0][0] [nb_rename_unit][nb_inst_issue]22 1 1 +1 # table_issue_type [0][TYPE_ALU ] [nb_inst_issue][nb_type]23 1 1 +1 # table_issue_type [0][TYPE_SHIFT ] [nb_inst_issue][nb_type]24 1 1 +1 # table_issue_type [0][TYPE_MOVE ] [nb_inst_issue][nb_type]25 1 1 +1 # table_issue_type [0][TYPE_TEST ] [nb_inst_issue][nb_type]26 1 1 +1 # table_issue_type [0][TYPE_MUL ] [nb_inst_issue][nb_type]27 1 1 +1 # table_issue_type [0][TYPE_DIV ] [nb_inst_issue][nb_type]28 1 1 +1 # table_issue_type [0][TYPE_EXTEND ] [nb_inst_issue][nb_type]29 1 1 +1 # table_issue_type [0][TYPE_FIND ] [nb_inst_issue][nb_type]30 1 1 +1 # table_issue_type [0][TYPE_SPECIAL] [nb_inst_issue][nb_type]31 1 1 +1 # table_issue_type [0][TYPE_CUSTOM ] [nb_inst_issue][nb_type]32 1 1 +1 # table_issue_type [0][TYPE_BRANCH ] [nb_inst_issue][nb_type]33 1 1 +1 # table_issue_type [0][TYPE_MEMORY ] [nb_inst_issue][nb_type] -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/SelfTest/config_mono_rename_unit.cfg
r111 r117 13 13 1 1 *2 # size_store_queue_ptr 14 14 0 0 *2 # size_load_queue_ptr 15 2 2 *4 # nb_inst_issue16 15 1 4 *4 # nb_inst_rename [0] [nb_rename_unit] 17 16 1 4 *4 # nb_inst_reexecute … … 19 18 1 1 *2 # priority 20 19 1 1 *2 # load_balancing 21 1 1 +1 # table_routing [0][0] [nb_rename_unit][nb_inst_issue]22 1 1 +1 # table_routing [0][1] [nb_rename_unit][nb_inst_issue]23 1 1 +1 # table_issue_type [0][TYPE_ALU ] [nb_inst_issue][nb_type]24 1 1 +1 # table_issue_type [0][TYPE_SHIFT ] [nb_inst_issue][nb_type]25 1 1 +1 # table_issue_type [0][TYPE_MOVE ] [nb_inst_issue][nb_type]26 1 1 +1 # table_issue_type [0][TYPE_TEST ] [nb_inst_issue][nb_type]27 0 0 +1 # table_issue_type [0][TYPE_MUL ] [nb_inst_issue][nb_type]28 0 0 +1 # table_issue_type [0][TYPE_DIV ] [nb_inst_issue][nb_type]29 1 1 +1 # table_issue_type [0][TYPE_EXTEND ] [nb_inst_issue][nb_type]30 1 1 +1 # table_issue_type [0][TYPE_FIND ] [nb_inst_issue][nb_type]31 0 0 +1 # table_issue_type [0][TYPE_SPECIAL] [nb_inst_issue][nb_type]32 0 0 +1 # table_issue_type [0][TYPE_CUSTOM ] [nb_inst_issue][nb_type]33 0 0 +1 # table_issue_type [0][TYPE_BRANCH ] [nb_inst_issue][nb_type]34 1 1 +1 # table_issue_type [0][TYPE_MEMORY ] [nb_inst_issue][nb_type]35 1 1 +1 # table_issue_type [1][TYPE_ALU ] [nb_inst_issue][nb_type]36 1 1 +1 # table_issue_type [1][TYPE_SHIFT ] [nb_inst_issue][nb_type]37 1 1 +1 # table_issue_type [1][TYPE_MOVE ] [nb_inst_issue][nb_type]38 1 1 +1 # table_issue_type [1][TYPE_TEST ] [nb_inst_issue][nb_type]39 1 1 +1 # table_issue_type [1][TYPE_MUL ] [nb_inst_issue][nb_type]40 1 1 +1 # table_issue_type [1][TYPE_DIV ] [nb_inst_issue][nb_type]41 0 0 +1 # table_issue_type [1][TYPE_EXTEND ] [nb_inst_issue][nb_type]42 0 0 +1 # table_issue_type [1][TYPE_FIND ] [nb_inst_issue][nb_type]43 1 1 +1 # table_issue_type [1][TYPE_SPECIAL] [nb_inst_issue][nb_type]44 1 1 +1 # table_issue_type [1][TYPE_CUSTOM ] [nb_inst_issue][nb_type]45 1 1 +1 # table_issue_type [1][TYPE_BRANCH ] [nb_inst_issue][nb_type]46 0 0 +1 # table_issue_type [1][TYPE_MEMORY ] [nb_inst_issue][nb_type] -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/SelfTest/config_multi_rename_unit.cfg
r111 r117 13 13 1 1 *2 # size_store_queue_ptr 14 14 0 0 *2 # size_load_queue_ptr 15 4 4 *4 # nb_inst_issue16 15 4 4 *4 # nb_inst_rename [0] [nb_rename_unit] 17 16 1 1 *4 # nb_inst_rename [1] [nb_rename_unit] … … 22 21 1 1 *2 # priority 23 22 1 1 *2 # load_balancing 24 1 1 +1 # table_routing [0][0] [nb_rename_unit][nb_inst_issue]25 1 1 +1 # table_routing [0][1] [nb_rename_unit][nb_inst_issue]26 0 0 +1 # table_routing [0][2] [nb_rename_unit][nb_inst_issue]27 0 0 +1 # table_routing [0][3] [nb_rename_unit][nb_inst_issue]28 1 1 +1 # table_routing [1][0] [nb_rename_unit][nb_inst_issue]29 1 1 +1 # table_routing [1][1] [nb_rename_unit][nb_inst_issue]30 0 0 +1 # table_routing [1][2] [nb_rename_unit][nb_inst_issue]31 0 0 +1 # table_routing [1][3] [nb_rename_unit][nb_inst_issue]32 0 0 +1 # table_routing [2][0] [nb_rename_unit][nb_inst_issue]33 0 0 +1 # table_routing [2][1] [nb_rename_unit][nb_inst_issue]34 1 1 +1 # table_routing [2][2] [nb_rename_unit][nb_inst_issue]35 1 1 +1 # table_routing [2][3] [nb_rename_unit][nb_inst_issue]36 0 0 +1 # table_routing [3][0] [nb_rename_unit][nb_inst_issue]37 0 0 +1 # table_routing [3][1] [nb_rename_unit][nb_inst_issue]38 1 1 +1 # table_routing [3][2] [nb_rename_unit][nb_inst_issue]39 1 1 +1 # table_routing [3][3] [nb_rename_unit][nb_inst_issue]40 1 1 +1 # table_issue_type [0][TYPE_ALU ] [nb_inst_issue][nb_type]41 1 1 +1 # table_issue_type [0][TYPE_SHIFT ] [nb_inst_issue][nb_type]42 1 1 +1 # table_issue_type [0][TYPE_MOVE ] [nb_inst_issue][nb_type]43 1 1 +1 # table_issue_type [0][TYPE_TEST ] [nb_inst_issue][nb_type]44 1 1 +1 # table_issue_type [0][TYPE_MUL ] [nb_inst_issue][nb_type]45 1 1 +1 # table_issue_type [0][TYPE_DIV ] [nb_inst_issue][nb_type]46 1 1 +1 # table_issue_type [0][TYPE_EXTEND ] [nb_inst_issue][nb_type]47 1 1 +1 # table_issue_type [0][TYPE_FIND ] [nb_inst_issue][nb_type]48 1 1 +1 # table_issue_type [0][TYPE_SPECIAL] [nb_inst_issue][nb_type]49 1 1 +1 # table_issue_type [0][TYPE_CUSTOM ] [nb_inst_issue][nb_type]50 1 1 +1 # table_issue_type [0][TYPE_BRANCH ] [nb_inst_issue][nb_type]51 1 1 +1 # table_issue_type [0][TYPE_MEMORY ] [nb_inst_issue][nb_type]52 1 1 +1 # table_issue_type [1][TYPE_ALU ] [nb_inst_issue][nb_type]53 1 1 +1 # table_issue_type [1][TYPE_SHIFT ] [nb_inst_issue][nb_type]54 1 1 +1 # table_issue_type [1][TYPE_MOVE ] [nb_inst_issue][nb_type]55 1 1 +1 # table_issue_type [1][TYPE_TEST ] [nb_inst_issue][nb_type]56 1 1 +1 # table_issue_type [1][TYPE_MUL ] [nb_inst_issue][nb_type]57 1 1 +1 # table_issue_type [1][TYPE_DIV ] [nb_inst_issue][nb_type]58 1 1 +1 # table_issue_type [1][TYPE_EXTEND ] [nb_inst_issue][nb_type]59 1 1 +1 # table_issue_type [1][TYPE_FIND ] [nb_inst_issue][nb_type]60 1 1 +1 # table_issue_type [1][TYPE_SPECIAL] [nb_inst_issue][nb_type]61 1 1 +1 # table_issue_type [1][TYPE_CUSTOM ] [nb_inst_issue][nb_type]62 1 1 +1 # table_issue_type [1][TYPE_BRANCH ] [nb_inst_issue][nb_type]63 1 1 +1 # table_issue_type [1][TYPE_MEMORY ] [nb_inst_issue][nb_type]64 1 1 +1 # table_issue_type [2][TYPE_ALU ] [nb_inst_issue][nb_type]65 1 1 +1 # table_issue_type [2][TYPE_SHIFT ] [nb_inst_issue][nb_type]66 1 1 +1 # table_issue_type [2][TYPE_MOVE ] [nb_inst_issue][nb_type]67 1 1 +1 # table_issue_type [2][TYPE_TEST ] [nb_inst_issue][nb_type]68 1 1 +1 # table_issue_type [2][TYPE_MUL ] [nb_inst_issue][nb_type]69 1 1 +1 # table_issue_type [2][TYPE_DIV ] [nb_inst_issue][nb_type]70 1 1 +1 # table_issue_type [2][TYPE_EXTEND ] [nb_inst_issue][nb_type]71 1 1 +1 # table_issue_type [2][TYPE_FIND ] [nb_inst_issue][nb_type]72 1 1 +1 # table_issue_type [2][TYPE_SPECIAL] [nb_inst_issue][nb_type]73 1 1 +1 # table_issue_type [2][TYPE_CUSTOM ] [nb_inst_issue][nb_type]74 1 1 +1 # table_issue_type [2][TYPE_BRANCH ] [nb_inst_issue][nb_type]75 1 1 +1 # table_issue_type [2][TYPE_MEMORY ] [nb_inst_issue][nb_type]76 1 1 +1 # table_issue_type [3][TYPE_ALU ] [nb_inst_issue][nb_type]77 1 1 +1 # table_issue_type [3][TYPE_SHIFT ] [nb_inst_issue][nb_type]78 1 1 +1 # table_issue_type [3][TYPE_MOVE ] [nb_inst_issue][nb_type]79 1 1 +1 # table_issue_type [3][TYPE_TEST ] [nb_inst_issue][nb_type]80 1 1 +1 # table_issue_type [3][TYPE_MUL ] [nb_inst_issue][nb_type]81 1 1 +1 # table_issue_type [3][TYPE_DIV ] [nb_inst_issue][nb_type]82 1 1 +1 # table_issue_type [3][TYPE_EXTEND ] [nb_inst_issue][nb_type]83 1 1 +1 # table_issue_type [3][TYPE_FIND ] [nb_inst_issue][nb_type]84 1 1 +1 # table_issue_type [3][TYPE_SPECIAL] [nb_inst_issue][nb_type]85 1 1 +1 # table_issue_type [3][TYPE_CUSTOM ] [nb_inst_issue][nb_type]86 1 1 +1 # table_issue_type [3][TYPE_BRANCH ] [nb_inst_issue][nb_type]87 1 1 +1 # table_issue_type [3][TYPE_MEMORY ] [nb_inst_issue][nb_type] -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/SelfTest/src/main.cpp
r111 r117 8 8 #include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/SelfTest/include/test.h" 9 9 10 #define NB_PARAMS 1 810 #define NB_PARAMS 17 11 11 12 12 void usage (int argc, char * argv[]) … … 27 27 err (_(" * size_store_queue_ptr (uint32_t )\n")); 28 28 err (_(" * size_load_queue_ptr (uint32_t )\n")); 29 err (_(" * nb_inst_issue (uint32_t )\n"));30 29 err (_(" * nb_inst_rename [nb_rename_unit] (uint32_t )\n")); 31 30 err (_(" * nb_inst_reexecute (uint32_t )\n")); … … 33 32 err (_(" * priority (Tpriority_t )\n")); 34 33 err (_(" * load_balancing (Tload_balancing_t )\n")); 35 err (_(" * table_routing [nb_rename_unit][nb_inst_issue] (bool )\n"));36 err (_(" * table_routing[nb_inst_issue][nb_type] (bool )\n"));37 err (_(" * TYPE_ALU \n"));38 err (_(" * TYPE_SHIFT \n"));39 err (_(" * TYPE_MOVE \n"));40 err (_(" * TYPE_TEST \n"));41 err (_(" * TYPE_MUL \n"));42 err (_(" * TYPE_DIV \n"));43 err (_(" * TYPE_EXTEND \n"));44 err (_(" * TYPE_FIND \n"));45 err (_(" * TYPE_SPECIAL\n"));46 err (_(" * TYPE_CUSTOM \n"));47 err (_(" * TYPE_BRANCH \n"));48 err (_(" * TYPE_MEMORY \n"));34 // err (_(" * table_routing [nb_rename_unit][nb_inst_issue] (bool )\n")); 35 // err (_(" * table_issue_type [nb_inst_issue][nb_type] (bool )\n")); 36 // err (_(" * TYPE_ALU \n")); 37 // err (_(" * TYPE_SHIFT \n")); 38 // err (_(" * TYPE_MOVE \n")); 39 // err (_(" * TYPE_TEST \n")); 40 // err (_(" * TYPE_MUL \n")); 41 // err (_(" * TYPE_DIV \n")); 42 // err (_(" * TYPE_EXTEND \n")); 43 // err (_(" * TYPE_FIND \n")); 44 // err (_(" * TYPE_SPECIAL\n")); 45 // err (_(" * TYPE_CUSTOM \n")); 46 // err (_(" * TYPE_BRANCH \n")); 47 // err (_(" * TYPE_MEMORY \n")); 49 48 50 49 exit (1); … … 68 67 uint32_t _nb_rename_unit = fromString<uint32_t >(argv[x++]); 69 68 70 if (argc <= static_cast<int>(2+NB_PARAMS+_nb_rename_unit))69 if (argc != static_cast<int>(2+NB_PARAMS+_nb_rename_unit)) 71 70 usage (argc, argv); 72 71 … … 81 80 uint32_t _size_store_queue_ptr = fromString<uint32_t >(argv[x++]); 82 81 uint32_t _size_load_queue_ptr = fromString<uint32_t >(argv[x++]); 83 82 //uint32_t _nb_inst_issue = fromString<uint32_t >(argv[x++]); 84 83 uint32_t * _nb_inst_rename = new uint32_t [_nb_rename_unit]; 85 84 for (uint32_t i=0; i<_nb_rename_unit; i++) … … 90 89 Tload_balancing_t _load_balancing = fromString<Tload_balancing_t>(argv[x++]); 91 90 92 if (argc != static_cast<int>(2+NB_PARAMS+_nb_rename_unit+(_nb_rename_unit+12)*_nb_inst_issue))93 usage (argc, argv);91 // if (argc != static_cast<int>(2+NB_PARAMS+_nb_rename_unit+(_nb_rename_unit+12)*_nb_inst_issue)) 92 // usage (argc, argv); 94 93 95 bool ** _table_routing = new bool * [_nb_rename_unit];96 for (uint32_t i=0; i<_nb_rename_unit; i++)97 {98 _table_routing [i] = new bool [_nb_inst_issue];99 for (uint32_t j=0; j<_nb_inst_issue; j++)100 _table_routing [i][j] = fromString<bool>(argv[x++]);101 }94 // bool ** _table_routing = new bool * [_nb_rename_unit]; 95 // for (uint32_t i=0; i<_nb_rename_unit; i++) 96 // { 97 // _table_routing [i] = new bool [_nb_inst_issue]; 98 // for (uint32_t j=0; j<_nb_inst_issue; j++) 99 // _table_routing [i][j] = fromString<bool>(argv[x++]); 100 // } 102 101 103 bool ** _table_issue_type = new bool * [_nb_inst_issue];104 for (uint32_t i=0; i<_nb_inst_issue; i++)105 {106 _table_issue_type [i] = new bool [_nb_inst_issue];102 // bool ** _table_issue_type = new bool * [_nb_inst_issue]; 103 // for (uint32_t i=0; i<_nb_inst_issue; i++) 104 // { 105 // _table_issue_type [i] = new bool [_nb_inst_issue]; 107 106 108 _table_issue_type [i][TYPE_ALU ] = fromString<bool>(argv[x++]);109 _table_issue_type [i][TYPE_SHIFT ] = fromString<bool>(argv[x++]);110 _table_issue_type [i][TYPE_MOVE ] = fromString<bool>(argv[x++]);111 _table_issue_type [i][TYPE_TEST ] = fromString<bool>(argv[x++]);112 _table_issue_type [i][TYPE_MUL ] = fromString<bool>(argv[x++]);113 _table_issue_type [i][TYPE_DIV ] = fromString<bool>(argv[x++]);114 _table_issue_type [i][TYPE_EXTEND ] = fromString<bool>(argv[x++]);115 _table_issue_type [i][TYPE_FIND ] = fromString<bool>(argv[x++]);116 _table_issue_type [i][TYPE_SPECIAL] = fromString<bool>(argv[x++]);117 _table_issue_type [i][TYPE_CUSTOM ] = fromString<bool>(argv[x++]);118 _table_issue_type [i][TYPE_BRANCH ] = fromString<bool>(argv[x++]);119 _table_issue_type [i][TYPE_MEMORY ] = fromString<bool>(argv[x++]);120 }107 // _table_issue_type [i][TYPE_ALU ] = fromString<bool>(argv[x++]); 108 // _table_issue_type [i][TYPE_SHIFT ] = fromString<bool>(argv[x++]); 109 // _table_issue_type [i][TYPE_MOVE ] = fromString<bool>(argv[x++]); 110 // _table_issue_type [i][TYPE_TEST ] = fromString<bool>(argv[x++]); 111 // _table_issue_type [i][TYPE_MUL ] = fromString<bool>(argv[x++]); 112 // _table_issue_type [i][TYPE_DIV ] = fromString<bool>(argv[x++]); 113 // _table_issue_type [i][TYPE_EXTEND ] = fromString<bool>(argv[x++]); 114 // _table_issue_type [i][TYPE_FIND ] = fromString<bool>(argv[x++]); 115 // _table_issue_type [i][TYPE_SPECIAL] = fromString<bool>(argv[x++]); 116 // _table_issue_type [i][TYPE_CUSTOM ] = fromString<bool>(argv[x++]); 117 // _table_issue_type [i][TYPE_BRANCH ] = fromString<bool>(argv[x++]); 118 // _table_issue_type [i][TYPE_MEMORY ] = fromString<bool>(argv[x++]); 119 // } 121 120 122 121 int _return = EXIT_SUCCESS; … … 137 136 _size_store_queue_ptr , 138 137 _size_load_queue_ptr , 139 _nb_inst_issue ,138 // _nb_inst_issue , 140 139 _nb_inst_rename , 141 140 _nb_inst_reexecute , … … 143 142 _priority , 144 143 _load_balancing , 145 _table_routing ,146 _table_issue_type ,144 // _table_routing , 145 // _table_issue_type , 147 146 true // is_toplevel 148 147 ); … … 173 172 delete [] _nb_inst_rename; 174 173 175 for (uint32_t i=0; i<_nb_rename_unit; i++)176 delete [] _table_routing [i];177 delete [] _table_routing ;178 for (uint32_t i=0; i<_nb_inst_issue; i++)179 delete [] _table_issue_type [i];180 delete [] _table_issue_type;174 // for (uint32_t i=0; i<_nb_rename_unit; i++) 175 // delete [] _table_routing [i]; 176 // delete [] _table_routing ; 177 // for (uint32_t i=0; i<_nb_inst_issue; i++) 178 // delete [] _table_issue_type [i]; 179 // delete [] _table_issue_type; 181 180 182 181 return (_return); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/SelfTest/src/test.cpp
r110 r117 48 48 sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5); 49 49 sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET"); 50 51 sc_signal<Tcontrol_t > *** in_ISSUE_IN_VAL ; 52 sc_signal<Tcontrol_t > *** out_ISSUE_IN_ACK ; 53 sc_signal<Tcontext_t > *** in_ISSUE_IN_CONTEXT_ID ; 54 sc_signal<Tcontext_t > *** in_ISSUE_IN_FRONT_END_ID ; 55 sc_signal<Tpacket_t > *** in_ISSUE_IN_PACKET_ID ; 56 sc_signal<Toperation_t > *** in_ISSUE_IN_OPERATION ; 57 sc_signal<Ttype_t > *** in_ISSUE_IN_TYPE ; 58 sc_signal<Tlsq_ptr_t > *** in_ISSUE_IN_STORE_QUEUE_PTR_WRITE ; 59 sc_signal<Tlsq_ptr_t > *** in_ISSUE_IN_LOAD_QUEUE_PTR_WRITE ; 60 sc_signal<Tcontrol_t > *** in_ISSUE_IN_HAS_IMMEDIAT ; 61 sc_signal<Tgeneral_data_t > *** in_ISSUE_IN_IMMEDIAT ; 62 sc_signal<Tcontrol_t > *** in_ISSUE_IN_READ_RA ; 63 sc_signal<Tgeneral_address_t> *** in_ISSUE_IN_NUM_REG_RA ; 64 sc_signal<Tcontrol_t > *** in_ISSUE_IN_READ_RB ; 65 sc_signal<Tgeneral_address_t> *** in_ISSUE_IN_NUM_REG_RB ; 66 sc_signal<Tcontrol_t > *** in_ISSUE_IN_READ_RC ; 67 sc_signal<Tspecial_address_t> *** in_ISSUE_IN_NUM_REG_RC ; 68 sc_signal<Tcontrol_t > *** in_ISSUE_IN_WRITE_RD ; 69 sc_signal<Tgeneral_address_t> *** in_ISSUE_IN_NUM_REG_RD ; 70 sc_signal<Tcontrol_t > *** in_ISSUE_IN_WRITE_RE ; 71 sc_signal<Tspecial_address_t> *** in_ISSUE_IN_NUM_REG_RE ; 72 sc_signal<Tcontrol_t > ** in_REEXECUTE_VAL ; 73 sc_signal<Tcontrol_t > ** out_REEXECUTE_ACK ; 74 sc_signal<Tcontext_t > ** in_REEXECUTE_CONTEXT_ID ; 75 sc_signal<Tcontext_t > ** in_REEXECUTE_FRONT_END_ID ; 76 sc_signal<Tpacket_t > ** in_REEXECUTE_PACKET_ID ; 77 sc_signal<Toperation_t > ** in_REEXECUTE_OPERATION ; 78 sc_signal<Ttype_t > ** in_REEXECUTE_TYPE ; 79 sc_signal<Tlsq_ptr_t > ** in_REEXECUTE_STORE_QUEUE_PTR_WRITE; 80 sc_signal<Tlsq_ptr_t > ** in_REEXECUTE_LOAD_QUEUE_PTR_WRITE ; 81 sc_signal<Tcontrol_t > ** in_REEXECUTE_HAS_IMMEDIAT ; 82 sc_signal<Tgeneral_data_t > ** in_REEXECUTE_IMMEDIAT ; 83 sc_signal<Tcontrol_t > ** in_REEXECUTE_READ_RA ; 84 sc_signal<Tgeneral_address_t> ** in_REEXECUTE_NUM_REG_RA ; 85 sc_signal<Tcontrol_t > ** in_REEXECUTE_READ_RB ; 86 sc_signal<Tgeneral_address_t> ** in_REEXECUTE_NUM_REG_RB ; 87 sc_signal<Tcontrol_t > ** in_REEXECUTE_READ_RC ; 88 sc_signal<Tspecial_address_t> ** in_REEXECUTE_NUM_REG_RC ; 89 sc_signal<Tcontrol_t > ** in_REEXECUTE_WRITE_RD ; 90 sc_signal<Tgeneral_address_t> ** in_REEXECUTE_NUM_REG_RD ; 91 sc_signal<Tcontrol_t > ** in_REEXECUTE_WRITE_RE ; 92 sc_signal<Tspecial_address_t> ** in_REEXECUTE_NUM_REG_RE ; 93 sc_signal<Tcontrol_t > ** out_ISSUE_OUT_VAL ; 94 sc_signal<Tcontrol_t > ** in_ISSUE_OUT_ACK ; 95 sc_signal<Tcontext_t > ** out_ISSUE_OUT_CONTEXT_ID ; 96 sc_signal<Tcontext_t > ** out_ISSUE_OUT_FRONT_END_ID ; 97 sc_signal<Tpacket_t > ** out_ISSUE_OUT_PACKET_ID ; 98 sc_signal<Toperation_t > ** out_ISSUE_OUT_OPERATION ; 99 sc_signal<Ttype_t > ** out_ISSUE_OUT_TYPE ; 100 sc_signal<Tlsq_ptr_t > ** out_ISSUE_OUT_STORE_QUEUE_PTR_WRITE; 101 sc_signal<Tlsq_ptr_t > ** out_ISSUE_OUT_LOAD_QUEUE_PTR_WRITE ; 102 sc_signal<Tcontrol_t > ** out_ISSUE_OUT_HAS_IMMEDIAT ; 103 sc_signal<Tgeneral_data_t > ** out_ISSUE_OUT_IMMEDIAT ; 104 sc_signal<Tcontrol_t > ** out_ISSUE_OUT_READ_RA ; 105 sc_signal<Tgeneral_address_t> ** out_ISSUE_OUT_NUM_REG_RA ; 106 sc_signal<Tcontrol_t > ** out_ISSUE_OUT_READ_RB ; 107 sc_signal<Tgeneral_address_t> ** out_ISSUE_OUT_NUM_REG_RB ; 108 sc_signal<Tcontrol_t > ** out_ISSUE_OUT_READ_RC ; 109 sc_signal<Tspecial_address_t> ** out_ISSUE_OUT_NUM_REG_RC ; 110 sc_signal<Tcontrol_t > ** out_ISSUE_OUT_WRITE_RD ; 111 sc_signal<Tgeneral_address_t> ** out_ISSUE_OUT_NUM_REG_RD ; 112 sc_signal<Tcontrol_t > ** out_ISSUE_OUT_WRITE_RE ; 113 sc_signal<Tspecial_address_t> ** out_ISSUE_OUT_NUM_REG_RE ; 50 114 51 115 ALLOC2_SC_SIGNAL( in_ISSUE_IN_VAL ," in_ISSUE_IN_VAL ",Tcontrol_t ,_param->_nb_rename_unit,_param->_nb_inst_rename[it1]); … … 309 373 Ttype_t type = out_ISSUE_OUT_TYPE[i]->read(); 310 374 TEST(Ttype_t,type, tab_type[imm%NB_TYPE]); 311 TEST(bool ,_param->_table_issue_type[i][type],true);375 // TEST(bool ,_param->_table_issue_type[i][type],true); 312 376 } 313 377 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/include/Parameters.h
r111 r117 38 38 //public : uint32_t _size_store_queue_ptr ; 39 39 //public : uint32_t _size_load_queue_ptr ; 40 public : uint32_t _nb_inst_issue ;41 40 public : uint32_t * _nb_inst_rename ;//[nb_rename_unit] 42 41 public : uint32_t _nb_inst_reexecute ; … … 44 43 public : Tpriority_t _priority ; 45 44 public : Tload_balancing_t _load_balancing ; 46 47 45 //public : bool ** _table_routing ;//[nb_rename_unit][nb_inst_issue] 46 //public : bool ** _table_issue_type ;//[nb_inst_issue][nb_type] 48 47 public : uint32_t _size_reexecute_queue ; 49 48 49 public : uint32_t _nb_inst_issue ; 50 50 //public : uint32_t _nb_bank_select_out ; 51 51 public : uint32_t _max_nb_inst_rename ; … … 74 74 uint32_t size_store_queue_ptr , 75 75 uint32_t size_load_queue_ptr , 76 uint32_t nb_inst_issue ,76 // uint32_t nb_inst_issue , 77 77 uint32_t * nb_inst_rename , 78 78 uint32_t nb_inst_reexecute , … … 80 80 Tpriority_t priority , 81 81 Tload_balancing_t load_balancing , 82 bool ** table_routing ,83 bool ** table_issue_type ,82 // bool ** table_routing , 83 // bool ** table_issue_type , 84 84 bool is_toplevel=false); 85 85 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_function_in_order_genMealy_issue_out.cpp
r115 r117 30 30 Tcontrol_t val [_param->_nb_inst_issue]; 31 31 32 uint32_t index=0; 32 33 for (uint32_t i=0; i<_param->_nb_inst_issue; i++) 33 34 val [i] = 0; 34 35 36 //-------------------------------------- 35 37 // From Reexecute_queue 38 //-------------------------------------- 36 39 40 // scan all reexecute_queue slot ... 37 41 // uint32_t num_reexecute_entry = 0; 38 42 for (std::list<entry_t*>::iterator it=_reexecute_queue.begin(); … … 42 46 entry_t* entry = (*it); 43 47 44 for (uint32_t i=0; i<_param->_nb_inst_issue; i++) 45 // test if no previous transaction and can accept this type 46 if ((val[i] == 0) and _param->_table_issue_type [i][entry->_type]) 47 { 48 // find a issue port 49 val [i] = 1; 50 51 if (_param->_have_port_context_id) 52 PORT_WRITE(out_ISSUE_OUT_CONTEXT_ID [i], entry->_context_id ); 53 if (_param->_have_port_front_end_id) 54 PORT_WRITE(out_ISSUE_OUT_FRONT_END_ID [i], entry->_front_end_id ); 55 if (_param->_have_port_rob_ptr ) 56 PORT_WRITE(out_ISSUE_OUT_PACKET_ID [i], entry->_packet_id ); 57 PORT_WRITE(out_ISSUE_OUT_OPERATION [i], entry->_operation ); 58 PORT_WRITE(out_ISSUE_OUT_TYPE [i], entry->_type ); 59 PORT_WRITE(out_ISSUE_OUT_STORE_QUEUE_PTR_WRITE [i], entry->_store_queue_ptr_write); 60 if (_param->_have_port_load_queue_ptr) 61 PORT_WRITE(out_ISSUE_OUT_LOAD_QUEUE_PTR_WRITE [i], entry->_load_queue_ptr_write ); 62 PORT_WRITE(out_ISSUE_OUT_HAS_IMMEDIAT [i], entry->_has_immediat ); 63 PORT_WRITE(out_ISSUE_OUT_IMMEDIAT [i], entry->_immediat ); 64 PORT_WRITE(out_ISSUE_OUT_READ_RA [i], entry->_read_ra ); 65 PORT_WRITE(out_ISSUE_OUT_NUM_REG_RA [i], entry->_num_reg_ra ); 66 PORT_WRITE(out_ISSUE_OUT_READ_RB [i], entry->_read_rb ); 67 PORT_WRITE(out_ISSUE_OUT_NUM_REG_RB [i], entry->_num_reg_rb ); 68 PORT_WRITE(out_ISSUE_OUT_READ_RC [i], entry->_read_rc ); 69 PORT_WRITE(out_ISSUE_OUT_NUM_REG_RC [i], entry->_num_reg_rc ); 70 PORT_WRITE(out_ISSUE_OUT_WRITE_RD [i], entry->_write_rd ); 71 PORT_WRITE(out_ISSUE_OUT_NUM_REG_RD [i], entry->_num_reg_rd ); 72 PORT_WRITE(out_ISSUE_OUT_WRITE_RE [i], entry->_write_re ); 73 PORT_WRITE(out_ISSUE_OUT_NUM_REG_RE [i], entry->_num_reg_re ); 48 val [index] = 1; 49 50 if (_param->_have_port_context_id) 51 PORT_WRITE(out_ISSUE_OUT_CONTEXT_ID [index], entry->_context_id ); 52 if (_param->_have_port_front_end_id) 53 PORT_WRITE(out_ISSUE_OUT_FRONT_END_ID [index], entry->_front_end_id ); 54 if (_param->_have_port_rob_ptr ) 55 PORT_WRITE(out_ISSUE_OUT_PACKET_ID [index], entry->_packet_id ); 56 PORT_WRITE(out_ISSUE_OUT_OPERATION [index], entry->_operation ); 57 PORT_WRITE(out_ISSUE_OUT_TYPE [index], entry->_type ); 58 PORT_WRITE(out_ISSUE_OUT_STORE_QUEUE_PTR_WRITE [index], entry->_store_queue_ptr_write); 59 if (_param->_have_port_load_queue_ptr) 60 PORT_WRITE(out_ISSUE_OUT_LOAD_QUEUE_PTR_WRITE [index], entry->_load_queue_ptr_write ); 61 PORT_WRITE(out_ISSUE_OUT_HAS_IMMEDIAT [index], entry->_has_immediat ); 62 PORT_WRITE(out_ISSUE_OUT_IMMEDIAT [index], entry->_immediat ); 63 PORT_WRITE(out_ISSUE_OUT_READ_RA [index], entry->_read_ra ); 64 PORT_WRITE(out_ISSUE_OUT_NUM_REG_RA [index], entry->_num_reg_ra ); 65 PORT_WRITE(out_ISSUE_OUT_READ_RB [index], entry->_read_rb ); 66 PORT_WRITE(out_ISSUE_OUT_NUM_REG_RB [index], entry->_num_reg_rb ); 67 PORT_WRITE(out_ISSUE_OUT_READ_RC [index], entry->_read_rc ); 68 PORT_WRITE(out_ISSUE_OUT_NUM_REG_RC [index], entry->_num_reg_rc ); 69 PORT_WRITE(out_ISSUE_OUT_WRITE_RD [index], entry->_write_rd ); 70 PORT_WRITE(out_ISSUE_OUT_NUM_REG_RD [index], entry->_num_reg_rd ); 71 PORT_WRITE(out_ISSUE_OUT_WRITE_RE [index], entry->_write_re ); 72 PORT_WRITE(out_ISSUE_OUT_NUM_REG_RE [index], entry->_num_reg_re ); 74 73 75 internal_ISSUE_OUT_FROM_REEXECUTE [i] = true;76 // internal_ISSUE_OUT_NUM_BANK [i] = num_reexecute_entry;77 internal_ISSUE_OUT_ENTRY [i] = entry;74 internal_ISSUE_OUT_FROM_REEXECUTE [index] = true; 75 // internal_ISSUE_OUT_NUM_BANK [index] = num_reexecute_entry; 76 internal_ISSUE_OUT_ENTRY [index] = entry; 78 77 79 break; // stop scan 80 } 81 // num_reexecute_entry ++; 78 index ++; // next slot 82 79 } 80 81 //-------------------------------------- 82 // From Issue_queue 83 //-------------------------------------- 84 index = _param->_nb_inst_reexecute; 83 85 84 // From Issue_queue 86 log_printf(TRACE,Issue_queue,FUNCTION," * From Issue_queue"); 87 88 // for all instruction in issue_queue head ... 85 89 for (uint32_t i=0; i<_param->_nb_bank; ++i) 86 90 { … … 89 93 log_printf(TRACE,Issue_queue,FUNCTION," * Bank [%d]",num_bank); 90 94 91 bool find = false;95 // bool find = false; 92 96 93 // Have instruction ?97 // ... test if have an instruction 94 98 if (not _issue_queue [num_bank].empty()) 95 99 { 96 100 log_printf(TRACE,Issue_queue,FUNCTION," * Not Empty !!!"); 97 101 102 // read instruction 98 103 entry_t* entry = _issue_queue [num_bank].front(); 99 104 100 // have valid instruction, search a valid issue slot. 101 for (uint32_t j=0; j<_param->_nb_inst_issue; j++) 102 { 103 Tcontrol_t issue_ack = PORT_READ(in_ISSUE_OUT_ACK [j]); 105 // Tcontrol_t issue_ack = PORT_READ(in_ISSUE_OUT_ACK [index]); 106 107 log_printf(TRACE,Issue_queue,FUNCTION," * Issue [%d]",index); 108 // log_printf(TRACE,Issue_queue,FUNCTION," * issue_ack : %d",issue_ack); 109 // log_printf(TRACE,Issue_queue,FUNCTION," * previous transaction : %d",val[index]); 110 // log_printf(TRACE,Issue_queue,FUNCTION," * can issue type : %d",_param->_table_issue_type [index][entry->_type]); 104 111 105 log_printf(TRACE,Issue_queue,FUNCTION," * Issue [%d]",j); 106 log_printf(TRACE,Issue_queue,FUNCTION," * issue_ack : %d",issue_ack); 107 log_printf(TRACE,Issue_queue,FUNCTION," * previous transaction : %d",val[j]); 108 log_printf(TRACE,Issue_queue,FUNCTION," * can issue type : %d",_param->_table_issue_type [j][entry->_type]); 112 // in_order : test if find a valid read_unit 113 // if (issue_ack) 114 // { 115 // log_printf(TRACE,Issue_queue,FUNCTION," * find !!!"); 116 117 // find = true; 118 // } 109 119 110 // test if no previous transaction and can accept this type 111 if (not val[j] and 112 _param->_table_issue_type [j][entry->_type] and 113 issue_ack) 114 { 115 log_printf(TRACE,Issue_queue,FUNCTION," * find !!!"); 116 117 // find a issue port 118 val [j] = 1; 119 120 if (_param->_have_port_context_id) 121 PORT_WRITE(out_ISSUE_OUT_CONTEXT_ID [j], entry->_context_id ); 122 if (_param->_have_port_front_end_id) 123 PORT_WRITE(out_ISSUE_OUT_FRONT_END_ID [j], entry->_front_end_id ); 124 if (_param->_have_port_rob_ptr ) 125 PORT_WRITE(out_ISSUE_OUT_PACKET_ID [j], entry->_packet_id ); 126 PORT_WRITE(out_ISSUE_OUT_OPERATION [j], entry->_operation ); 127 PORT_WRITE(out_ISSUE_OUT_TYPE [j], entry->_type ); 128 PORT_WRITE(out_ISSUE_OUT_STORE_QUEUE_PTR_WRITE [j], entry->_store_queue_ptr_write); 129 if (_param->_have_port_load_queue_ptr) 130 PORT_WRITE(out_ISSUE_OUT_LOAD_QUEUE_PTR_WRITE [j], entry->_load_queue_ptr_write ); 131 PORT_WRITE(out_ISSUE_OUT_HAS_IMMEDIAT [j], entry->_has_immediat ); 132 PORT_WRITE(out_ISSUE_OUT_IMMEDIAT [j], entry->_immediat ); 133 PORT_WRITE(out_ISSUE_OUT_READ_RA [j], entry->_read_ra ); 134 PORT_WRITE(out_ISSUE_OUT_NUM_REG_RA [j], entry->_num_reg_ra ); 135 PORT_WRITE(out_ISSUE_OUT_READ_RB [j], entry->_read_rb ); 136 PORT_WRITE(out_ISSUE_OUT_NUM_REG_RB [j], entry->_num_reg_rb ); 137 PORT_WRITE(out_ISSUE_OUT_READ_RC [j], entry->_read_rc ); 138 PORT_WRITE(out_ISSUE_OUT_NUM_REG_RC [j], entry->_num_reg_rc ); 139 PORT_WRITE(out_ISSUE_OUT_WRITE_RD [j], entry->_write_rd ); 140 PORT_WRITE(out_ISSUE_OUT_NUM_REG_RD [j], entry->_num_reg_rd ); 141 PORT_WRITE(out_ISSUE_OUT_WRITE_RE [j], entry->_write_re ); 142 PORT_WRITE(out_ISSUE_OUT_NUM_REG_RE [j], entry->_num_reg_re ); 143 144 internal_ISSUE_OUT_FROM_REEXECUTE [j] = false; 145 internal_ISSUE_OUT_NUM_BANK [j] = num_bank; 146 internal_ISSUE_OUT_ENTRY [j] = entry; 147 148 find = true; 149 break; // find : stop scan 150 } 151 } 120 // find a issue port 121 val [index] = true; // instruction is valid 122 123 if (_param->_have_port_context_id) 124 PORT_WRITE(out_ISSUE_OUT_CONTEXT_ID [index], entry->_context_id ); 125 if (_param->_have_port_front_end_id) 126 PORT_WRITE(out_ISSUE_OUT_FRONT_END_ID [index], entry->_front_end_id ); 127 if (_param->_have_port_rob_ptr ) 128 PORT_WRITE(out_ISSUE_OUT_PACKET_ID [index], entry->_packet_id ); 129 PORT_WRITE(out_ISSUE_OUT_OPERATION [index], entry->_operation ); 130 PORT_WRITE(out_ISSUE_OUT_TYPE [index], entry->_type ); 131 PORT_WRITE(out_ISSUE_OUT_STORE_QUEUE_PTR_WRITE [index], entry->_store_queue_ptr_write); 132 if (_param->_have_port_load_queue_ptr) 133 PORT_WRITE(out_ISSUE_OUT_LOAD_QUEUE_PTR_WRITE [index], entry->_load_queue_ptr_write ); 134 PORT_WRITE(out_ISSUE_OUT_HAS_IMMEDIAT [index], entry->_has_immediat ); 135 PORT_WRITE(out_ISSUE_OUT_IMMEDIAT [index], entry->_immediat ); 136 PORT_WRITE(out_ISSUE_OUT_READ_RA [index], entry->_read_ra ); 137 PORT_WRITE(out_ISSUE_OUT_NUM_REG_RA [index], entry->_num_reg_ra ); 138 PORT_WRITE(out_ISSUE_OUT_READ_RB [index], entry->_read_rb ); 139 PORT_WRITE(out_ISSUE_OUT_NUM_REG_RB [index], entry->_num_reg_rb ); 140 PORT_WRITE(out_ISSUE_OUT_READ_RC [index], entry->_read_rc ); 141 PORT_WRITE(out_ISSUE_OUT_NUM_REG_RC [index], entry->_num_reg_rc ); 142 PORT_WRITE(out_ISSUE_OUT_WRITE_RD [index], entry->_write_rd ); 143 PORT_WRITE(out_ISSUE_OUT_NUM_REG_RD [index], entry->_num_reg_rd ); 144 PORT_WRITE(out_ISSUE_OUT_WRITE_RE [index], entry->_write_re ); 145 PORT_WRITE(out_ISSUE_OUT_NUM_REG_RE [index], entry->_num_reg_re ); 146 147 internal_ISSUE_OUT_FROM_REEXECUTE [index] = false; 148 internal_ISSUE_OUT_NUM_BANK [index] = num_bank; 149 internal_ISSUE_OUT_ENTRY [index] = entry; 150 151 index ++; // next slot 152 152 } 153 153 154 if (not find) 155 break; // stop scan (in order) 154 // if (not find) 155 // { 156 // log_printf(TRACE,Issue_queue,FUNCTION," * Not find. Stop Scan (in order)"); 157 158 // break; // stop scan (in order) 159 // } 156 160 } 157 161 162 // Output 158 163 for (uint32_t i=0; i<_param->_nb_inst_issue; i++) 159 164 { 160 165 internal_ISSUE_OUT_VAL [i] = val [i]; 161 166 PORT_WRITE(out_ISSUE_OUT_VAL [i], internal_ISSUE_OUT_VAL [i]); 167 168 // // Type invalid to the Core_Glue network 169 // if (not val [i]) // == empty 170 // PORT_WRITE(out_ISSUE_OUT_TYPE [i], TYPE_INVALID); 162 171 } 163 172 } -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_function_out_of_order_genMoore.cpp
r111 r117 109 109 for (uint32_t i=0; i<_param->_nb_inst_issue; i++) 110 110 // test if no previous transaction and can accept this type 111 if ((val[i] == 0) and _param->_table_issue_type [i][entry->_type]) 111 if ((val[i] == 0) 112 // and _param->_table_issue_type [i][entry->_type] 113 ) 112 114 { 113 115 // find a issue port … … 168 170 for (uint32_t i=0; i<_param->_nb_inst_issue; i++) 169 171 // test if no previous transaction and can accept this type 170 if ((val[i] == 0) and _param->_table_issue_type [i][entry->_type]) 172 if ((val[i] == 0) 173 // and _param->_table_issue_type [i][entry->_type] 174 ) 171 175 { 172 176 // find a issue port -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_transition.cpp
r111 r117 106 106 log_printf(TRACE,Issue_queue,FUNCTION," * Dump Issue_queue"); 107 107 108 if (_param->_queue_scheme == ISSUE_QUEUE_SCHEME_IN_ORDER) 109 { 110 log_printf(TRACE,Issue_queue,FUNCTION," * reg_NUM_BANK_HEAD : %d",reg_NUM_BANK_HEAD); 111 log_printf(TRACE,Issue_queue,FUNCTION," * reg_NUM_BANK_TAIL : %d",reg_NUM_BANK_TAIL); 112 } 113 108 114 for (uint32_t i=0; i<_param->_nb_bank; i++) 109 115 { -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Parameters.cpp
r111 r117 32 32 uint32_t size_store_queue_ptr , 33 33 uint32_t size_load_queue_ptr , 34 uint32_t nb_inst_issue ,34 // uint32_t nb_inst_issue , 35 35 uint32_t * nb_inst_rename , 36 36 uint32_t nb_inst_reexecute , … … 38 38 Tpriority_t priority , 39 39 Tload_balancing_t load_balancing , 40 bool ** table_routing ,41 bool ** table_issue_type ,40 // bool ** table_routing , 41 // bool ** table_issue_type , 42 42 bool is_toplevel ) 43 43 { … … 50 50 _queue_scheme = queue_scheme ; 51 51 _nb_bank = nb_bank ; 52 52 // _nb_inst_issue = nb_inst_issue ; 53 53 _nb_inst_rename = nb_inst_rename ; 54 54 _nb_inst_reexecute = nb_inst_reexecute ; … … 56 56 _priority = priority ; 57 57 _load_balancing = load_balancing ; 58 59 58 // _table_routing = table_routing ; 59 // _table_issue_type = table_issue_type ; 60 60 _size_reexecute_queue = nb_inst_reexecute ; 61 61 62 log_printf(TRACE,Issue_queue,FUNCTION," * table_routing [nb_rename_unit][nb_inst_issue]"); 63 for (uint32_t i=0; i<_nb_rename_unit; ++i) 64 for (uint32_t j=0; j<_nb_inst_issue; ++j) 65 if (_table_routing [i][j]) 66 log_printf(TRACE,Issue_queue,FUNCTION," [%d][%d] -> true",i,j); 62 _nb_inst_issue = _nb_inst_reexecute+_nb_bank; 63 64 // log_printf(TRACE,Issue_queue,FUNCTION," * table_routing [nb_rename_unit][nb_inst_issue]"); 65 // for (uint32_t i=0; i<_nb_rename_unit; ++i) 66 // for (uint32_t j=0; j<_nb_inst_issue; ++j) 67 // if (_table_routing [i][j]) 68 // log_printf(TRACE,Issue_queue,FUNCTION," [%d][%d] -> true",i,j); 67 69 68 log_printf(TRACE,Issue_queue,FUNCTION," * table_issue_type [nb_inst_issue][nb_type]");69 for (uint32_t i=0; i<_nb_inst_issue; ++i)70 for (uint32_t j=0; j<_nb_type; ++j)71 if (_table_issue_type [i][j])72 log_printf(TRACE,Issue_queue,FUNCTION," [%d][%d] -> true",i,j);70 // log_printf(TRACE,Issue_queue,FUNCTION," * table_issue_type [nb_inst_issue][nb_type]"); 71 // for (uint32_t i=0; i<_nb_inst_issue; ++i) 72 // for (uint32_t j=0; j<_nb_type; ++j) 73 // if (_table_issue_type [i][j]) 74 // log_printf(TRACE,Issue_queue,FUNCTION," [%d][%d] -> true",i,j); 73 75 74 76 _max_nb_inst_rename = max<uint32_t>(_nb_inst_rename,_nb_rename_unit); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Parameters_msg_error.cpp
r111 r117 48 48 test.error(toString(_("nb_bank (%d) must be a multiple of size_queue (%d).\n"),_nb_bank,_size_queue)); 49 49 50 if (not is_multiple(_nb_bank, _nb_inst_issue))51 test.error(toString(_("nb_inst_issue (%d) must be a multiple of nb_bank (%d) .\n"),_nb_inst_issue,_nb_bank));50 // if (not is_multiple(_nb_bank, _nb_inst_issue)) 51 // test.error(toString(_("nb_inst_issue (%d) must be a multiple of nb_bank (%d) .\n"),_nb_inst_issue,_nb_bank)); 52 52 53 53 if (_nb_rename_unit_select > _nb_rename_unit) … … 57 57 test.warning(_("For better performance, the bank's size (size_queue/nb_bank) must be > 1.\n")); 58 58 59 for (uint32_t i=0; i<_nb_rename_unit; i++)60 {61 bool type_present [_nb_type];59 // for (uint32_t i=0; i<_nb_rename_unit; i++) 60 // { 61 // bool type_present [_nb_type]; 62 62 63 for (uint32_t j=0; j<_nb_type; j++)64 type_present [j] = not is_type_valid(j);63 // for (uint32_t j=0; j<_nb_type; j++) 64 // type_present [j] = not is_type_valid(j); 65 65 66 bool find = false;67 for (uint32_t j=0; j<_nb_inst_issue; j++)68 if (_table_routing [i][j])69 {70 find = true;66 // bool find = false; 67 // for (uint32_t j=0; j<_nb_inst_issue; j++) 68 // if (_table_routing [i][j]) 69 // { 70 // find = true; 71 71 72 for (uint32_t k=0; k<_nb_type; k++)73 type_present [k] |= _table_issue_type [j][k];74 }72 // for (uint32_t k=0; k<_nb_type; k++) 73 // type_present [k] |= _table_issue_type [j][k]; 74 // } 75 75 76 if (not find)77 test.error(toString(_("Rename_unit [%d] is not connected with a issue slot.\n"),i));78 else79 for (uint32_t j=0; j<_nb_type; j++)80 if (not type_present [j] and not is_type_optionnal(j))81 test.error(toString(_("Rename_unit [%d] can't issue instruction's type \"%s\".\n"),i,toString(j).c_str()));82 }76 // if (not find) 77 // test.error(toString(_("Rename_unit [%d] is not connected with a issue slot.\n"),i)); 78 // else 79 // for (uint32_t j=0; j<_nb_type; j++) 80 // if (not type_present [j] and not is_type_optionnal(j)) 81 // test.error(toString(_("Rename_unit [%d] can't issue instruction's type \"%s\".\n"),i,toString(j).c_str())); 82 // } 83 83 84 84 if ((_priority != PRIORITY_ROUND_ROBIN)) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/SelfTest/src/test.cpp
r88 r117 153 153 ALLOC1_SC_SIGNAL( in_COMMIT_ACK ," in_COMMIT_ACK ",Tcontrol_t ,_param->_nb_inst_commit); 154 154 ALLOC1_SC_SIGNAL(out_COMMIT_WEN ,"out_COMMIT_WEN ",Tcontrol_t ,_param->_nb_inst_commit); 155 156 155 //ALLOC1_SC_SIGNAL(out_COMMIT_CONTEXT_ID ,"out_COMMIT_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_commit); 156 //ALLOC1_SC_SIGNAL(out_COMMIT_FRONT_END_ID ,"out_COMMIT_FRONT_END_ID ",Tcontext_t ,_param->_nb_inst_commit); 157 157 ALLOC1_SC_SIGNAL(out_COMMIT_PACKET_ID ,"out_COMMIT_PACKET_ID ",Tpacket_t ,_param->_nb_inst_commit); 158 158 //ALLOC1_SC_SIGNAL(out_COMMIT_OPERATION ,"out_COMMIT_OPERATION ",Toperation_t ,_param->_nb_inst_commit); … … 234 234 INSTANCE1_SC_SIGNAL(_Reexecute_unit, in_COMMIT_ACK ,_param->_nb_inst_commit); 235 235 INSTANCE1_SC_SIGNAL(_Reexecute_unit,out_COMMIT_WEN ,_param->_nb_inst_commit); 236 237 238 239 236 //if (_param->_have_port_context_id) 237 //INSTANCE1_SC_SIGNAL(_Reexecute_unit,out_COMMIT_CONTEXT_ID ,_param->_nb_inst_commit); 238 //if (_param->_have_port_front_end_id) 239 //INSTANCE1_SC_SIGNAL(_Reexecute_unit,out_COMMIT_FRONT_END_ID ,_param->_nb_inst_commit); 240 240 if (_param->_have_port_rob_ptr ) 241 241 INSTANCE1_SC_SIGNAL(_Reexecute_unit,out_COMMIT_PACKET_ID ,_param->_nb_inst_commit); … … 415 415 416 416 TEST(Tcontrol_t ,out_COMMIT_WEN [i]->read(),request[packet].commit_wen ); 417 if (_param->_have_port_context_id)418 TEST(Tcontext_t ,out_COMMIT_CONTEXT_ID [i]->read(),request[packet].context_id );419 if (_param->_have_port_front_end_id)420 TEST(Tcontext_t ,out_COMMIT_FRONT_END_ID [i]->read(),request[packet].front_end_id);417 // if (_param->_have_port_context_id) 418 // TEST(Tcontext_t ,out_COMMIT_CONTEXT_ID [i]->read(),request[packet].context_id ); 419 // if (_param->_have_port_front_end_id) 420 // TEST(Tcontext_t ,out_COMMIT_FRONT_END_ID [i]->read(),request[packet].front_end_id); 421 421 // TEST(Toperation_t ,out_COMMIT_OPERATION [i]->read(),request[packet].operation ); 422 422 // TEST(Ttype_t ,out_COMMIT_TYPE [i]->read(),request[packet].type ); … … 529 529 DELETE1_SC_SIGNAL( in_COMMIT_ACK ,_param->_nb_inst_commit); 530 530 DELETE1_SC_SIGNAL(out_COMMIT_WEN ,_param->_nb_inst_commit); 531 532 531 //DELETE1_SC_SIGNAL(out_COMMIT_CONTEXT_ID ,_param->_nb_inst_commit); 532 //DELETE1_SC_SIGNAL(out_COMMIT_FRONT_END_ID ,_param->_nb_inst_commit); 533 533 DELETE1_SC_SIGNAL(out_COMMIT_PACKET_ID ,_param->_nb_inst_commit); 534 534 //DELETE1_SC_SIGNAL(out_COMMIT_OPERATION ,_param->_nb_inst_commit); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/include/Reexecute_unit.h
r97 r117 87 87 public : SC_IN (Tcontrol_t ) ** in_COMMIT_ACK ;//[nb_inst_commit] 88 88 public : SC_OUT(Tcontrol_t ) ** out_COMMIT_WEN ;//[nb_inst_commit] 89 90 89 //public : SC_OUT(Tcontext_t ) ** out_COMMIT_CONTEXT_ID ;//[nb_inst_commit] 90 //public : SC_OUT(Tcontext_t ) ** out_COMMIT_FRONT_END_ID ;//[nb_inst_commit] 91 91 public : SC_OUT(Tpacket_t ) ** out_COMMIT_PACKET_ID ;//[nb_inst_commit] 92 92 //public : SC_OUT(Toperation_t ) ** out_COMMIT_OPERATION ;//[nb_inst_commit] -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_allocation.cpp
r112 r117 83 83 ALLOC1_VALACK_IN ( in_COMMIT_ACK ,ACK); 84 84 ALLOC1_SIGNAL_OUT(out_COMMIT_WEN ,"wen" ,Tcontrol_t ,1); 85 86 85 // ALLOC1_SIGNAL_OUT(out_COMMIT_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ); 86 // ALLOC1_SIGNAL_OUT(out_COMMIT_FRONT_END_ID ,"front_end_id",Tcontext_t ,_param->_size_front_end_id); 87 87 ALLOC1_SIGNAL_OUT(out_COMMIT_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_rob_ptr ); 88 88 // ALLOC1_SIGNAL_OUT(out_COMMIT_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_deallocation.cpp
r115 r117 44 44 DELETE1_SIGNAL( in_COMMIT_ACK ,_param->_nb_inst_commit,1); 45 45 DELETE1_SIGNAL(out_COMMIT_WEN ,_param->_nb_inst_commit,1); 46 47 46 // DELETE1_SIGNAL(out_COMMIT_CONTEXT_ID ,_param->_nb_inst_commit,_param->_size_context_id ); 47 // DELETE1_SIGNAL(out_COMMIT_FRONT_END_ID ,_param->_nb_inst_commit,_param->_size_front_end_id); 48 48 DELETE1_SIGNAL(out_COMMIT_PACKET_ID ,_param->_nb_inst_commit,_param->_size_rob_ptr ); 49 49 // DELETE1_SIGNAL(out_COMMIT_OPERATION ,_param->_nb_inst_commit,_param->_size_operation ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_genMealy_commit.cpp
r98 r117 101 101 if (commit_val) 102 102 { 103 if (_param->_have_port_context_id)104 PORT_WRITE(out_COMMIT_CONTEXT_ID [i], PORT_READ(in_EXECUTE_LOOP_CONTEXT_ID [x][y]));105 if (_param->_have_port_front_end_id)106 PORT_WRITE(out_COMMIT_FRONT_END_ID [i], PORT_READ(in_EXECUTE_LOOP_FRONT_END_ID [x][y]));103 // if (_param->_have_port_context_id) 104 // PORT_WRITE(out_COMMIT_CONTEXT_ID [i], PORT_READ(in_EXECUTE_LOOP_CONTEXT_ID [x][y])); 105 // if (_param->_have_port_front_end_id) 106 // PORT_WRITE(out_COMMIT_FRONT_END_ID [i], PORT_READ(in_EXECUTE_LOOP_FRONT_END_ID [x][y])); 107 107 if (_param->_have_port_rob_ptr ) 108 108 PORT_WRITE(out_COMMIT_PACKET_ID [i], PORT_READ(in_EXECUTE_LOOP_PACKET_ID [x][y])); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/SelfTest/src/test.cpp
r88 r117 77 77 sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET"); 78 78 79 sc_signal<Tcontrol_t > ** in_INSERT_VAL ; 80 sc_signal<Tcontrol_t > ** out_INSERT_ACK ; 81 sc_signal<Tcontext_t > ** in_INSERT_FRONT_END_ID ; 82 sc_signal<Tcontext_t > ** in_INSERT_CONTEXT_ID ; 83 sc_signal<Ttype_t > ** in_INSERT_TYPE ; 84 sc_signal<Toperation_t> ** in_INSERT_OPERATION ; 85 sc_signal<Tlsq_ptr_t > ** out_INSERT_STORE_QUEUE_PTR_WRITE; 86 sc_signal<Tlsq_ptr_t > ** out_INSERT_LOAD_QUEUE_PTR_WRITE ; 87 sc_signal<Tcontrol_t > ** in_RETIRE_VAL ; 88 sc_signal<Tcontrol_t > ** out_RETIRE_ACK ; 89 sc_signal<Tcontext_t > ** in_RETIRE_FRONT_END_ID ; 90 sc_signal<Tcontext_t > ** in_RETIRE_CONTEXT_ID ; 91 //sc_signal<Ttype_t > ** in_RETIRE_TYPE ; 92 //sc_signal<Toperation_t> ** in_RETIRE_OPERATION ; 93 sc_signal<Tcontrol_t > ** in_RETIRE_USE_STORE_QUEUE ; 94 sc_signal<Tcontrol_t > ** in_RETIRE_USE_LOAD_QUEUE ; 95 sc_signal<Tlsq_ptr_t > ** in_RETIRE_STORE_QUEUE_PTR_WRITE; 96 sc_signal<Tlsq_ptr_t > ** in_RETIRE_LOAD_QUEUE_PTR_WRITE ; 97 79 98 ALLOC1_SC_SIGNAL( in_INSERT_VAL ," in_INSERT_VAL ",Tcontrol_t ,_param->_nb_inst_insert); 80 99 ALLOC1_SC_SIGNAL(out_INSERT_ACK ,"out_INSERT_ACK ",Tcontrol_t ,_param->_nb_inst_insert); … … 89 108 ALLOC1_SC_SIGNAL( in_RETIRE_FRONT_END_ID ," in_RETIRE_FRONT_END_ID ",Tcontext_t ,_param->_nb_inst_retire); 90 109 ALLOC1_SC_SIGNAL( in_RETIRE_CONTEXT_ID ," in_RETIRE_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_retire); 91 // 92 // 110 //ALLOC1_SC_SIGNAL( in_RETIRE_TYPE ," in_RETIRE_TYPE ",Ttype_t ,_param->_nb_inst_retire); 111 //ALLOC1_SC_SIGNAL( in_RETIRE_OPERATION ," in_RETIRE_OPERATION ",Toperation_t,_param->_nb_inst_retire); 93 112 ALLOC1_SC_SIGNAL( in_RETIRE_USE_STORE_QUEUE ," in_RETIRE_USE_STORE_QUEUE ",Tcontrol_t ,_param->_nb_inst_retire); 94 113 ALLOC1_SC_SIGNAL( in_RETIRE_USE_LOAD_QUEUE ," in_RETIRE_USE_LOAD_QUEUE ",Tcontrol_t ,_param->_nb_inst_retire); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/SelfTest/src/test.cpp
r98 r117 79 79 ALLOC1_SC_SIGNAL( in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RE_PHY_NEW," in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RE_PHY_NEW",Tspecial_address_t,_param->_nb_inst_insert); 80 80 81 82 83 84 85 86 81 //ALLOC1_SC_SIGNAL(out_INSERT_STAT_LIST_READ_RA ,"out_INSERT_STAT_LIST_READ_RA ",Tcontrol_t ,_param->_nb_inst_insert); 82 //ALLOC1_SC_SIGNAL(out_INSERT_STAT_LIST_NUM_REG_RA_PHY ,"out_INSERT_STAT_LIST_NUM_REG_RA_PHY ",Tgeneral_address_t,_param->_nb_inst_insert); 83 //ALLOC1_SC_SIGNAL(out_INSERT_STAT_LIST_READ_RB ,"out_INSERT_STAT_LIST_READ_RB ",Tcontrol_t ,_param->_nb_inst_insert); 84 //ALLOC1_SC_SIGNAL(out_INSERT_STAT_LIST_NUM_REG_RB_PHY ,"out_INSERT_STAT_LIST_NUM_REG_RB_PHY ",Tgeneral_address_t,_param->_nb_inst_insert); 85 //ALLOC1_SC_SIGNAL(out_INSERT_STAT_LIST_READ_RC ,"out_INSERT_STAT_LIST_READ_RC ",Tcontrol_t ,_param->_nb_inst_insert); 86 //ALLOC1_SC_SIGNAL(out_INSERT_STAT_LIST_NUM_REG_RC_PHY ,"out_INSERT_STAT_LIST_NUM_REG_RC_PHY ",Tspecial_address_t,_param->_nb_inst_insert); 87 87 ALLOC1_SC_SIGNAL(out_INSERT_STAT_LIST_WRITE_RD ,"out_INSERT_STAT_LIST_WRITE_RD ",Tcontrol_t ,_param->_nb_inst_insert); 88 ALLOC1_SC_SIGNAL(out_INSERT_STAT_LIST_NUM_REG_RD_PHY_OLD ,"out_INSERT_STAT_LIST_NUM_REG_RD_PHY_OLD ",Tgeneral_address_t,_param->_nb_inst_insert); 88 89 ALLOC1_SC_SIGNAL(out_INSERT_STAT_LIST_NUM_REG_RD_PHY_NEW ,"out_INSERT_STAT_LIST_NUM_REG_RD_PHY_NEW ",Tgeneral_address_t,_param->_nb_inst_insert); 89 90 ALLOC1_SC_SIGNAL(out_INSERT_STAT_LIST_WRITE_RE ,"out_INSERT_STAT_LIST_WRITE_RE ",Tcontrol_t ,_param->_nb_inst_insert); 91 ALLOC1_SC_SIGNAL(out_INSERT_STAT_LIST_NUM_REG_RE_PHY_OLD ,"out_INSERT_STAT_LIST_NUM_REG_RE_PHY_OLD ",Tspecial_address_t,_param->_nb_inst_insert); 90 92 ALLOC1_SC_SIGNAL(out_INSERT_STAT_LIST_NUM_REG_RE_PHY_NEW ,"out_INSERT_STAT_LIST_NUM_REG_RE_PHY_NEW ",Tspecial_address_t,_param->_nb_inst_insert); 91 93 … … 157 159 INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue, in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RE_PHY_NEW,_param->_nb_inst_insert); 158 160 159 160 161 162 163 164 161 //INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_STAT_LIST_READ_RA ,_param->_nb_inst_insert); 162 //INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_STAT_LIST_NUM_REG_RA_PHY ,_param->_nb_inst_insert); 163 //INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_STAT_LIST_READ_RB ,_param->_nb_inst_insert); 164 //INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_STAT_LIST_NUM_REG_RB_PHY ,_param->_nb_inst_insert); 165 //INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_STAT_LIST_READ_RC ,_param->_nb_inst_insert); 166 //INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_STAT_LIST_NUM_REG_RC_PHY ,_param->_nb_inst_insert); 165 167 INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_STAT_LIST_WRITE_RD ,_param->_nb_inst_insert); 168 INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_STAT_LIST_NUM_REG_RD_PHY_OLD ,_param->_nb_inst_insert); 166 169 INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_STAT_LIST_NUM_REG_RD_PHY_NEW ,_param->_nb_inst_insert); 167 170 INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_STAT_LIST_WRITE_RE ,_param->_nb_inst_insert); 171 INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_STAT_LIST_NUM_REG_RE_PHY_OLD ,_param->_nb_inst_insert); 168 172 INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_STAT_LIST_NUM_REG_RE_PHY_NEW ,_param->_nb_inst_insert); 169 173 … … 331 335 DELETE1_SC_SIGNAL( in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RE_PHY_NEW,_param->_nb_inst_insert); 332 336 333 334 335 336 337 338 337 //DELETE1_SC_SIGNAL(out_INSERT_STAT_LIST_READ_RA ,_param->_nb_inst_insert); 338 //DELETE1_SC_SIGNAL(out_INSERT_STAT_LIST_NUM_REG_RA_PHY ,_param->_nb_inst_insert); 339 //DELETE1_SC_SIGNAL(out_INSERT_STAT_LIST_READ_RB ,_param->_nb_inst_insert); 340 //DELETE1_SC_SIGNAL(out_INSERT_STAT_LIST_NUM_REG_RB_PHY ,_param->_nb_inst_insert); 341 //DELETE1_SC_SIGNAL(out_INSERT_STAT_LIST_READ_RC ,_param->_nb_inst_insert); 342 //DELETE1_SC_SIGNAL(out_INSERT_STAT_LIST_NUM_REG_RC_PHY ,_param->_nb_inst_insert); 339 343 DELETE1_SC_SIGNAL(out_INSERT_STAT_LIST_WRITE_RD ,_param->_nb_inst_insert); 344 DELETE1_SC_SIGNAL(out_INSERT_STAT_LIST_NUM_REG_RD_PHY_OLD ,_param->_nb_inst_insert); 340 345 DELETE1_SC_SIGNAL(out_INSERT_STAT_LIST_NUM_REG_RD_PHY_NEW ,_param->_nb_inst_insert); 341 346 DELETE1_SC_SIGNAL(out_INSERT_STAT_LIST_WRITE_RE ,_param->_nb_inst_insert); 347 DELETE1_SC_SIGNAL(out_INSERT_STAT_LIST_NUM_REG_RE_PHY_OLD ,_param->_nb_inst_insert); 342 348 DELETE1_SC_SIGNAL(out_INSERT_STAT_LIST_NUM_REG_RE_PHY_NEW ,_param->_nb_inst_insert); 343 349 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/include/Register_translation_unit_Glue.h
r110 r117 108 108 public : SC_OUT(Tspecial_address_t) ** out_INSERT_STAT_LIST_NUM_REG_RC_PHY ;//[nb_inst_insert] 109 109 public : SC_OUT(Tcontrol_t ) ** out_INSERT_STAT_LIST_WRITE_RD ;//[nb_inst_insert] 110 public : SC_OUT(Tgeneral_address_t) ** out_INSERT_STAT_LIST_NUM_REG_RD_PHY_OLD ;//[nb_inst_insert] 110 111 public : SC_OUT(Tgeneral_address_t) ** out_INSERT_STAT_LIST_NUM_REG_RD_PHY_NEW ;//[nb_inst_insert] 111 112 public : SC_OUT(Tcontrol_t ) ** out_INSERT_STAT_LIST_WRITE_RE ;//[nb_inst_insert] 113 public : SC_OUT(Tspecial_address_t) ** out_INSERT_STAT_LIST_NUM_REG_RE_PHY_OLD ;//[nb_inst_insert] 112 114 public : SC_OUT(Tspecial_address_t) ** out_INSERT_STAT_LIST_NUM_REG_RE_PHY_NEW ;//[nb_inst_insert] 113 115 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/src/Register_translation_unit_Glue_allocation.cpp
r112 r117 97 97 ALLOC1_SIGNAL_OUT(out_INSERT_STAT_LIST_NUM_REG_RC_PHY ,"STAT_LIST_NUM_REG_RC_PHY" ,Tspecial_address_t,_param->_size_special_register ); 98 98 ALLOC1_SIGNAL_OUT(out_INSERT_STAT_LIST_WRITE_RD ,"STAT_LIST_WRITE_RD" ,Tcontrol_t ,1); 99 ALLOC1_SIGNAL_OUT(out_INSERT_STAT_LIST_NUM_REG_RD_PHY_OLD ,"STAT_LIST_NUM_REG_RD_PHY_OLD" ,Tgeneral_address_t,_param->_size_general_register ); 99 100 ALLOC1_SIGNAL_OUT(out_INSERT_STAT_LIST_NUM_REG_RD_PHY_NEW ,"STAT_LIST_NUM_REG_RD_PHY_NEW" ,Tgeneral_address_t,_param->_size_general_register ); 100 101 ALLOC1_SIGNAL_OUT(out_INSERT_STAT_LIST_WRITE_RE ,"STAT_LIST_WRITE_RE" ,Tcontrol_t ,1); 102 ALLOC1_SIGNAL_OUT(out_INSERT_STAT_LIST_NUM_REG_RE_PHY_OLD ,"STAT_LIST_NUM_REG_RE_PHY_OLD" ,Tspecial_address_t,_param->_size_special_register ); 101 103 ALLOC1_SIGNAL_OUT(out_INSERT_STAT_LIST_NUM_REG_RE_PHY_NEW ,"STAT_LIST_NUM_REG_RE_PHY_NEW" ,Tspecial_address_t,_param->_size_special_register ); 102 104 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/src/Register_translation_unit_Glue_deallocation.cpp
r110 r117 59 59 DELETE1_SIGNAL( in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RE_PHY_NEW,_param->_nb_inst_insert,_param->_size_special_register ); 60 60 61 DELETE1_SIGNAL(out_INSERT_STAT_LIST_READ_RA ,_param->_nb_inst_insert,1);62 DELETE1_SIGNAL(out_INSERT_STAT_LIST_NUM_REG_RA_PHY ,_param->_nb_inst_insert,_param->_size_general_register );63 DELETE1_SIGNAL(out_INSERT_STAT_LIST_READ_RB ,_param->_nb_inst_insert,1);64 DELETE1_SIGNAL(out_INSERT_STAT_LIST_NUM_REG_RB_PHY ,_param->_nb_inst_insert,_param->_size_general_register );65 DELETE1_SIGNAL(out_INSERT_STAT_LIST_READ_RC ,_param->_nb_inst_insert,1);66 DELETE1_SIGNAL(out_INSERT_STAT_LIST_NUM_REG_RC_PHY ,_param->_nb_inst_insert,_param->_size_special_register );61 DELETE1_SIGNAL(out_INSERT_STAT_LIST_READ_RA ,_param->_nb_inst_insert,1); 62 DELETE1_SIGNAL(out_INSERT_STAT_LIST_NUM_REG_RA_PHY ,_param->_nb_inst_insert,_param->_size_general_register ); 63 DELETE1_SIGNAL(out_INSERT_STAT_LIST_READ_RB ,_param->_nb_inst_insert,1); 64 DELETE1_SIGNAL(out_INSERT_STAT_LIST_NUM_REG_RB_PHY ,_param->_nb_inst_insert,_param->_size_general_register ); 65 DELETE1_SIGNAL(out_INSERT_STAT_LIST_READ_RC ,_param->_nb_inst_insert,1); 66 DELETE1_SIGNAL(out_INSERT_STAT_LIST_NUM_REG_RC_PHY ,_param->_nb_inst_insert,_param->_size_special_register ); 67 67 DELETE1_SIGNAL(out_INSERT_STAT_LIST_WRITE_RD ,_param->_nb_inst_insert,1); 68 DELETE1_SIGNAL(out_INSERT_STAT_LIST_NUM_REG_RD_PHY_OLD ,_param->_nb_inst_insert,_param->_size_general_register ); 68 69 DELETE1_SIGNAL(out_INSERT_STAT_LIST_NUM_REG_RD_PHY_NEW ,_param->_nb_inst_insert,_param->_size_general_register ); 69 70 DELETE1_SIGNAL(out_INSERT_STAT_LIST_WRITE_RE ,_param->_nb_inst_insert,1); 71 DELETE1_SIGNAL(out_INSERT_STAT_LIST_NUM_REG_RE_PHY_OLD ,_param->_nb_inst_insert,_param->_size_special_register ); 70 72 DELETE1_SIGNAL(out_INSERT_STAT_LIST_NUM_REG_RE_PHY_NEW ,_param->_nb_inst_insert,_param->_size_special_register ); 71 73 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/src/Register_translation_unit_Glue_genMealy_insert.cpp
r101 r117 49 49 PORT_WRITE(out_INSERT_FREE_LIST_SPR_VAL [i], WRITE_RE ); 50 50 51 PORT_WRITE(out_INSERT_STAT_LIST_READ_RA [i], READ_RA );52 PORT_WRITE(out_INSERT_STAT_LIST_NUM_REG_RA_PHY [i], NUM_REG_RA_PHY );53 PORT_WRITE(out_INSERT_STAT_LIST_READ_RB [i], READ_RB );54 PORT_WRITE(out_INSERT_STAT_LIST_NUM_REG_RB_PHY [i], NUM_REG_RB_PHY );55 PORT_WRITE(out_INSERT_STAT_LIST_READ_RC [i], READ_RC );56 PORT_WRITE(out_INSERT_STAT_LIST_NUM_REG_RC_PHY [i], NUM_REG_RC_PHY );51 PORT_WRITE(out_INSERT_STAT_LIST_READ_RA [i], READ_RA ); 52 PORT_WRITE(out_INSERT_STAT_LIST_NUM_REG_RA_PHY [i], NUM_REG_RA_PHY ); 53 PORT_WRITE(out_INSERT_STAT_LIST_READ_RB [i], READ_RB ); 54 PORT_WRITE(out_INSERT_STAT_LIST_NUM_REG_RB_PHY [i], NUM_REG_RB_PHY ); 55 PORT_WRITE(out_INSERT_STAT_LIST_READ_RC [i], READ_RC ); 56 PORT_WRITE(out_INSERT_STAT_LIST_NUM_REG_RC_PHY [i], NUM_REG_RC_PHY ); 57 57 PORT_WRITE(out_INSERT_STAT_LIST_WRITE_RD [i], WRITE_RD ); 58 PORT_WRITE(out_INSERT_STAT_LIST_NUM_REG_RD_PHY_OLD [i], NUM_REG_RD_PHY_OLD); 58 59 PORT_WRITE(out_INSERT_STAT_LIST_NUM_REG_RD_PHY_NEW [i], NUM_REG_RD_PHY_NEW); 59 60 PORT_WRITE(out_INSERT_STAT_LIST_WRITE_RE [i], WRITE_RE ); 61 PORT_WRITE(out_INSERT_STAT_LIST_NUM_REG_RE_PHY_OLD [i], NUM_REG_RE_PHY_OLD); 60 62 PORT_WRITE(out_INSERT_STAT_LIST_NUM_REG_RE_PHY_NEW [i], NUM_REG_RE_PHY_NEW); 61 63 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/SelfTest/src/test.cpp
r113 r117 63 63 sc_signal<Tcontrol_t > ** in_INSERT_VAL ;//[nb_inst_insert] 64 64 sc_signal<Tcontrol_t > ** out_INSERT_ACK ;//[nb_inst_insert] 65 66 67 68 69 70 65 //sc_signal<Tcontrol_t > ** in_INSERT_READ_RA ;//[nb_inst_insert] 66 //sc_signal<Tgeneral_address_t> ** in_INSERT_NUM_REG_RA_PHY ;//[nb_inst_insert] 67 //sc_signal<Tcontrol_t > ** in_INSERT_READ_RB ;//[nb_inst_insert] 68 //sc_signal<Tgeneral_address_t> ** in_INSERT_NUM_REG_RB_PHY ;//[nb_inst_insert] 69 //sc_signal<Tcontrol_t > ** in_INSERT_READ_RC ;//[nb_inst_insert] 70 //sc_signal<Tspecial_address_t> ** in_INSERT_NUM_REG_RC_PHY ;//[nb_inst_insert] 71 71 sc_signal<Tcontrol_t > ** in_INSERT_WRITE_RD ;//[nb_inst_insert] 72 sc_signal<Tgeneral_address_t> ** in_INSERT_NUM_REG_RD_PHY_OLD;//[nb_inst_insert] 72 73 sc_signal<Tgeneral_address_t> ** in_INSERT_NUM_REG_RD_PHY_NEW;//[nb_inst_insert] 73 74 sc_signal<Tcontrol_t > ** in_INSERT_WRITE_RE ;//[nb_inst_insert] 75 sc_signal<Tspecial_address_t> ** in_INSERT_NUM_REG_RE_PHY_OLD;//[nb_inst_insert] 74 76 sc_signal<Tspecial_address_t> ** in_INSERT_NUM_REG_RE_PHY_NEW;//[nb_inst_insert] 75 77 sc_signal<Tcontrol_t > ** in_RETIRE_VAL ;//[nb_inst_retire] 76 78 sc_signal<Tcontrol_t > ** out_RETIRE_ACK ;//[nb_inst_retire] 77 79 sc_signal<Tcontrol_t > ** in_RETIRE_RESTORE ;//[nb_inst_retire] 78 79 80 81 82 83 80 //sc_signal<Tcontrol_t > ** in_RETIRE_READ_RA ;//[nb_inst_retire] 81 //sc_signal<Tgeneral_address_t> ** in_RETIRE_NUM_REG_RA_PHY ;//[nb_inst_retire] 82 //sc_signal<Tcontrol_t > ** in_RETIRE_READ_RB ;//[nb_inst_retire] 83 //sc_signal<Tgeneral_address_t> ** in_RETIRE_NUM_REG_RB_PHY ;//[nb_inst_retire] 84 //sc_signal<Tcontrol_t > ** in_RETIRE_READ_RC ;//[nb_inst_retire] 85 //sc_signal<Tspecial_address_t> ** in_RETIRE_NUM_REG_RC_PHY ;//[nb_inst_retire] 84 86 sc_signal<Tcontrol_t > ** in_RETIRE_WRITE_RD ;//[nb_inst_retire] 85 87 sc_signal<Tcontrol_t > ** in_RETIRE_RESTORE_RD_PHY_OLD;//[nb_inst_retire] … … 99 101 ALLOC1_SC_SIGNAL( in_INSERT_VAL ," in_INSERT_VAL ",Tcontrol_t ,_param->_nb_inst_insert); 100 102 ALLOC1_SC_SIGNAL(out_INSERT_ACK ,"out_INSERT_ACK ",Tcontrol_t ,_param->_nb_inst_insert); 101 102 103 104 105 106 103 //ALLOC1_SC_SIGNAL( in_INSERT_READ_RA ," in_INSERT_READ_RA ",Tcontrol_t ,_param->_nb_inst_insert); 104 //ALLOC1_SC_SIGNAL( in_INSERT_NUM_REG_RA_PHY ," in_INSERT_NUM_REG_RA_PHY ",Tgeneral_address_t,_param->_nb_inst_insert); 105 //ALLOC1_SC_SIGNAL( in_INSERT_READ_RB ," in_INSERT_READ_RB ",Tcontrol_t ,_param->_nb_inst_insert); 106 //ALLOC1_SC_SIGNAL( in_INSERT_NUM_REG_RB_PHY ," in_INSERT_NUM_REG_RB_PHY ",Tgeneral_address_t,_param->_nb_inst_insert); 107 //ALLOC1_SC_SIGNAL( in_INSERT_READ_RC ," in_INSERT_READ_RC ",Tcontrol_t ,_param->_nb_inst_insert); 108 //ALLOC1_SC_SIGNAL( in_INSERT_NUM_REG_RC_PHY ," in_INSERT_NUM_REG_RC_PHY ",Tspecial_address_t,_param->_nb_inst_insert); 107 109 ALLOC1_SC_SIGNAL( in_INSERT_WRITE_RD ," in_INSERT_WRITE_RD ",Tcontrol_t ,_param->_nb_inst_insert); 110 ALLOC1_SC_SIGNAL( in_INSERT_NUM_REG_RD_PHY_OLD," in_INSERT_NUM_REG_RD_PHY_OLD",Tgeneral_address_t,_param->_nb_inst_insert); 108 111 ALLOC1_SC_SIGNAL( in_INSERT_NUM_REG_RD_PHY_NEW," in_INSERT_NUM_REG_RD_PHY_NEW",Tgeneral_address_t,_param->_nb_inst_insert); 109 112 ALLOC1_SC_SIGNAL( in_INSERT_WRITE_RE ," in_INSERT_WRITE_RE ",Tcontrol_t ,_param->_nb_inst_insert); 113 ALLOC1_SC_SIGNAL( in_INSERT_NUM_REG_RE_PHY_OLD," in_INSERT_NUM_REG_RE_PHY_OLD",Tspecial_address_t,_param->_nb_inst_insert); 110 114 ALLOC1_SC_SIGNAL( in_INSERT_NUM_REG_RE_PHY_NEW," in_INSERT_NUM_REG_RE_PHY_NEW",Tspecial_address_t,_param->_nb_inst_insert); 111 115 ALLOC1_SC_SIGNAL( in_RETIRE_VAL ," in_RETIRE_VAL ",Tcontrol_t ,_param->_nb_inst_retire); 112 116 ALLOC1_SC_SIGNAL(out_RETIRE_ACK ,"out_RETIRE_ACK ",Tcontrol_t ,_param->_nb_inst_retire); 113 117 ALLOC1_SC_SIGNAL( in_RETIRE_RESTORE ," in_RETIRE_RESTORE ",Tcontrol_t ,_param->_nb_inst_retire); 114 115 116 117 118 119 118 //ALLOC1_SC_SIGNAL( in_RETIRE_READ_RA ," in_RETIRE_READ_RA ",Tcontrol_t ,_param->_nb_inst_retire); 119 //ALLOC1_SC_SIGNAL( in_RETIRE_NUM_REG_RA_PHY ," in_RETIRE_NUM_REG_RA_PHY ",Tgeneral_address_t,_param->_nb_inst_retire); 120 //ALLOC1_SC_SIGNAL( in_RETIRE_READ_RB ," in_RETIRE_READ_RB ",Tcontrol_t ,_param->_nb_inst_retire); 121 //ALLOC1_SC_SIGNAL( in_RETIRE_NUM_REG_RB_PHY ," in_RETIRE_NUM_REG_RB_PHY ",Tgeneral_address_t,_param->_nb_inst_retire); 122 //ALLOC1_SC_SIGNAL( in_RETIRE_READ_RC ," in_RETIRE_READ_RC ",Tcontrol_t ,_param->_nb_inst_retire); 123 //ALLOC1_SC_SIGNAL( in_RETIRE_NUM_REG_RC_PHY ," in_RETIRE_NUM_REG_RC_PHY ",Tspecial_address_t,_param->_nb_inst_retire); 120 124 ALLOC1_SC_SIGNAL( in_RETIRE_WRITE_RD ," in_RETIRE_WRITE_RD ",Tcontrol_t ,_param->_nb_inst_retire); 121 125 ALLOC1_SC_SIGNAL( in_RETIRE_RESTORE_RD_PHY_OLD," in_RETIRE_RESTORE_RD_PHY_OLD",Tcontrol_t ,_param->_nb_inst_retire); … … 145 149 INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_INSERT_VAL ,_param->_nb_inst_insert); 146 150 INSTANCE1_SC_SIGNAL(_Stat_List_unit,out_INSERT_ACK ,_param->_nb_inst_insert); 147 148 149 150 151 152 151 //INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_INSERT_READ_RA ,_param->_nb_inst_insert); 152 //INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_INSERT_NUM_REG_RA_PHY ,_param->_nb_inst_insert); 153 //INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_INSERT_READ_RB ,_param->_nb_inst_insert); 154 //INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_INSERT_NUM_REG_RB_PHY ,_param->_nb_inst_insert); 155 //INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_INSERT_READ_RC ,_param->_nb_inst_insert); 156 //INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_INSERT_NUM_REG_RC_PHY ,_param->_nb_inst_insert); 153 157 INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_INSERT_WRITE_RD ,_param->_nb_inst_insert); 158 INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_INSERT_NUM_REG_RD_PHY_OLD,_param->_nb_inst_insert); 154 159 INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_INSERT_NUM_REG_RD_PHY_NEW,_param->_nb_inst_insert); 155 160 INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_INSERT_WRITE_RE ,_param->_nb_inst_insert); 161 INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_INSERT_NUM_REG_RE_PHY_OLD,_param->_nb_inst_insert); 156 162 INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_INSERT_NUM_REG_RE_PHY_NEW,_param->_nb_inst_insert); 157 163 … … 159 165 INSTANCE1_SC_SIGNAL(_Stat_List_unit,out_RETIRE_ACK ,_param->_nb_inst_retire); 160 166 INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_RETIRE_RESTORE ,_param->_nb_inst_retire); 161 162 163 164 165 166 167 //INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_RETIRE_READ_RA ,_param->_nb_inst_retire); 168 //INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_RETIRE_NUM_REG_RA_PHY ,_param->_nb_inst_retire); 169 //INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_RETIRE_READ_RB ,_param->_nb_inst_retire); 170 //INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_RETIRE_NUM_REG_RB_PHY ,_param->_nb_inst_retire); 171 //INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_RETIRE_READ_RC ,_param->_nb_inst_retire); 172 //INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_RETIRE_NUM_REG_RC_PHY ,_param->_nb_inst_retire); 167 173 INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_RETIRE_WRITE_RD ,_param->_nb_inst_retire); 168 174 INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_RETIRE_RESTORE_RD_PHY_OLD,_param->_nb_inst_retire); … … 348 354 349 355 in_INSERT_VAL [i]->write((rand()%100) < percent_transaction_insert); 350 in_INSERT_READ_RA [i]->write(read_ra );351 in_INSERT_NUM_REG_RA_PHY [i]->write(ra);352 in_INSERT_READ_RB [i]->write(read_rb );353 in_INSERT_NUM_REG_RB_PHY [i]->write(rb);354 in_INSERT_READ_RC [i]->write(read_rc );355 in_INSERT_NUM_REG_RC_PHY [i]->write(rc);356 // in_INSERT_READ_RA [i]->write(read_ra ); 357 // in_INSERT_NUM_REG_RA_PHY [i]->write(ra); 358 // in_INSERT_READ_RB [i]->write(read_rb ); 359 // in_INSERT_NUM_REG_RB_PHY [i]->write(rb); 360 // in_INSERT_READ_RC [i]->write(read_rc ); 361 // in_INSERT_NUM_REG_RC_PHY [i]->write(rc); 356 362 in_INSERT_WRITE_RD [i]->write(write_rd); 357 363 in_INSERT_NUM_REG_RD_PHY_NEW [i]->write(rd); … … 394 400 395 401 in_RETIRE_VAL [i]->write((rand()%100) < percent_transaction_retire); 396 in_RETIRE_READ_RA [i]->write(read_ra );397 in_RETIRE_RESTORE [i]->write(0);398 in_RETIRE_NUM_REG_RA_PHY [i]->write(ra);399 in_RETIRE_READ_RB [i]->write(read_rb );400 in_RETIRE_NUM_REG_RB_PHY [i]->write(rb);401 in_RETIRE_READ_RC [i]->write(read_rc );402 in_RETIRE_NUM_REG_RC_PHY [i]->write(rc);402 // in_RETIRE_READ_RA [i]->write(read_ra ); 403 // in_RETIRE_RESTORE [i]->write(0); 404 // in_RETIRE_NUM_REG_RA_PHY [i]->write(ra); 405 // in_RETIRE_READ_RB [i]->write(read_rb ); 406 // in_RETIRE_NUM_REG_RB_PHY [i]->write(rb); 407 // in_RETIRE_READ_RC [i]->write(read_rc ); 408 // in_RETIRE_NUM_REG_RC_PHY [i]->write(rc); 403 409 in_RETIRE_WRITE_RD [i]->write(write_rd); 404 410 in_RETIRE_RESTORE_RD_PHY_OLD [i]->write(0); … … 454 460 if (in_INSERT_VAL [i]->read() and out_INSERT_ACK [i]->read()) 455 461 { 456 Tcontrol_t read_ra = in_INSERT_READ_RA [i]->read();457 Tgeneral_address_t ra = in_INSERT_NUM_REG_RA_PHY [i]->read();458 Tcontrol_t read_rb = in_INSERT_READ_RB [i]->read();459 Tgeneral_address_t rb = in_INSERT_NUM_REG_RB_PHY [i]->read();460 Tcontrol_t read_rc = in_INSERT_READ_RC [i]->read();461 Tspecial_address_t rc = in_INSERT_NUM_REG_RC_PHY [i]->read();462 // Tcontrol_t read_ra = in_INSERT_READ_RA [i]->read(); 463 // Tgeneral_address_t ra = in_INSERT_NUM_REG_RA_PHY [i]->read(); 464 // Tcontrol_t read_rb = in_INSERT_READ_RB [i]->read(); 465 // Tgeneral_address_t rb = in_INSERT_NUM_REG_RB_PHY [i]->read(); 466 // Tcontrol_t read_rc = in_INSERT_READ_RC [i]->read(); 467 // Tspecial_address_t rc = in_INSERT_NUM_REG_RC_PHY [i]->read(); 462 468 Tgeneral_address_t rd_new = in_INSERT_NUM_REG_RD_PHY_NEW [i]->read(); 463 469 Tspecial_address_t re_new = in_INSERT_NUM_REG_RE_PHY_NEW [i]->read(); 464 470 465 471 LABEL("INSERT [%d] - Accepted",i); 466 LABEL(" * read_ra : %d",read_ra );467 LABEL(" * reg_ra : %d",ra );468 LABEL(" * status[%d]._is_free : %d",ra,spr_status[ra]._is_free );469 LABEL(" * status[%d]._is_link : %d",ra,spr_status[ra]._is_link );470 LABEL(" * status[%d]._is_valid : %d",ra,spr_status[ra]._is_valid);471 LABEL(" * status[%d]._counter : %d",ra,spr_status[ra]._counter );472 LABEL(" * read_rb : %d",read_rb );473 LABEL(" * reg_rb : %d",rb );474 LABEL(" * status[%d]._is_free : %d",rb,spr_status[rb]._is_free );475 LABEL(" * status[%d]._is_link : %d",rb,spr_status[rb]._is_link );476 LABEL(" * status[%d]._is_valid : %d",rb,spr_status[rb]._is_valid);477 LABEL(" * status[%d]._counter : %d",rb,spr_status[rb]._counter );478 LABEL(" * read_rc : %d",read_rc );479 LABEL(" * reg_rc : %d",rc );480 LABEL(" * status[%d]._is_free : %d",rc,spr_status[rc]._is_free );481 LABEL(" * status[%d]._is_link : %d",rc,spr_status[rc]._is_link );482 LABEL(" * status[%d]._is_valid : %d",rc,spr_status[rc]._is_valid);483 LABEL(" * status[%d]._counter : %d",rc,spr_status[rc]._counter );472 // LABEL(" * read_ra : %d",read_ra ); 473 // LABEL(" * reg_ra : %d",ra ); 474 // LABEL(" * status[%d]._is_free : %d",ra,spr_status[ra]._is_free ); 475 // LABEL(" * status[%d]._is_link : %d",ra,spr_status[ra]._is_link ); 476 // LABEL(" * status[%d]._is_valid : %d",ra,spr_status[ra]._is_valid); 477 // LABEL(" * status[%d]._counter : %d",ra,spr_status[ra]._counter ); 478 // LABEL(" * read_rb : %d",read_rb ); 479 // LABEL(" * reg_rb : %d",rb ); 480 // LABEL(" * status[%d]._is_free : %d",rb,spr_status[rb]._is_free ); 481 // LABEL(" * status[%d]._is_link : %d",rb,spr_status[rb]._is_link ); 482 // LABEL(" * status[%d]._is_valid : %d",rb,spr_status[rb]._is_valid); 483 // LABEL(" * status[%d]._counter : %d",rb,spr_status[rb]._counter ); 484 // LABEL(" * read_rc : %d",read_rc ); 485 // LABEL(" * reg_rc : %d",rc ); 486 // LABEL(" * status[%d]._is_free : %d",rc,spr_status[rc]._is_free ); 487 // LABEL(" * status[%d]._is_link : %d",rc,spr_status[rc]._is_link ); 488 // LABEL(" * status[%d]._is_valid : %d",rc,spr_status[rc]._is_valid); 489 // LABEL(" * status[%d]._counter : %d",rc,spr_status[rc]._counter ); 484 490 LABEL(" * read_rd : %d",write_rd); 485 491 LABEL(" * reg_rd_new : %d",rd_new ); … … 495 501 LABEL(" * status[%d]._counter : %d",re_new,spr_status[re_new]._counter ); 496 502 497 if (read_ra)498 {499 gpr_status[ra]._counter ++;500 }501 if (read_rb)502 {503 gpr_status[rb]._counter ++;504 }505 if (read_rc)506 {507 spr_status[rc]._counter ++;508 }503 // if (read_ra) 504 // { 505 // gpr_status[ra]._counter ++; 506 // } 507 // if (read_rb) 508 // { 509 // gpr_status[rb]._counter ++; 510 // } 511 // if (read_rc) 512 // { 513 // spr_status[rc]._counter ++; 514 // } 509 515 if (write_rd) 510 516 { … … 544 550 { 545 551 Tcontrol_t restore = in_RETIRE_RESTORE [i]->read(); 546 Tcontrol_t read_ra = in_RETIRE_READ_RA [i]->read();547 Tgeneral_address_t ra = in_RETIRE_NUM_REG_RA_PHY [i]->read();548 Tcontrol_t read_rb = in_RETIRE_READ_RB [i]->read();549 Tgeneral_address_t rb = in_RETIRE_NUM_REG_RB_PHY [i]->read();550 Tcontrol_t read_rc = in_RETIRE_READ_RC [i]->read();551 Tspecial_address_t rc = in_RETIRE_NUM_REG_RC_PHY [i]->read();552 // Tcontrol_t read_ra = in_RETIRE_READ_RA [i]->read(); 553 // Tgeneral_address_t ra = in_RETIRE_NUM_REG_RA_PHY [i]->read(); 554 // Tcontrol_t read_rb = in_RETIRE_READ_RB [i]->read(); 555 // Tgeneral_address_t rb = in_RETIRE_NUM_REG_RB_PHY [i]->read(); 556 // Tcontrol_t read_rc = in_RETIRE_READ_RC [i]->read(); 557 // Tspecial_address_t rc = in_RETIRE_NUM_REG_RC_PHY [i]->read(); 552 558 Tcontrol_t write_rd = in_RETIRE_WRITE_RD [i]->read(); 553 559 Tcontrol_t restore_rd_old = in_RETIRE_RESTORE_RD_PHY_OLD [i]->read(); … … 561 567 LABEL("RETIRE [%d] - Accepted",i); 562 568 LABEL(" * restore : %d",restore); 563 LABEL(" * read_ra : %d",read_ra );564 LABEL(" * reg_ra : %d",ra );565 LABEL(" * status[%d]._is_free : %d",ra,spr_status[ra]._is_free );566 LABEL(" * status[%d]._is_link : %d",ra,spr_status[ra]._is_link );567 LABEL(" * status[%d]._is_valid : %d",ra,spr_status[ra]._is_valid);568 LABEL(" * status[%d]._counter : %d",ra,spr_status[ra]._counter );569 LABEL(" * read_rb : %d",read_rb );570 LABEL(" * reg_rb : %d",rb );571 LABEL(" * status[%d]._is_free : %d",rb,spr_status[rb]._is_free );572 LABEL(" * status[%d]._is_link : %d",rb,spr_status[rb]._is_link );573 LABEL(" * status[%d]._is_valid : %d",rb,spr_status[rb]._is_valid);574 LABEL(" * status[%d]._counter : %d",rb,spr_status[rb]._counter );575 LABEL(" * read_rc : %d",read_rc );576 LABEL(" * reg_rc : %d",rc );577 LABEL(" * status[%d]._is_free : %d",rc,spr_status[rc]._is_free );578 LABEL(" * status[%d]._is_link : %d",rc,spr_status[rc]._is_link );579 LABEL(" * status[%d]._is_valid : %d",rc,spr_status[rc]._is_valid);580 LABEL(" * status[%d]._counter : %d",rc,spr_status[rc]._counter );569 // LABEL(" * read_ra : %d",read_ra ); 570 // LABEL(" * reg_ra : %d",ra ); 571 // LABEL(" * status[%d]._is_free : %d",ra,spr_status[ra]._is_free ); 572 // LABEL(" * status[%d]._is_link : %d",ra,spr_status[ra]._is_link ); 573 // LABEL(" * status[%d]._is_valid : %d",ra,spr_status[ra]._is_valid); 574 // LABEL(" * status[%d]._counter : %d",ra,spr_status[ra]._counter ); 575 // LABEL(" * read_rb : %d",read_rb ); 576 // LABEL(" * reg_rb : %d",rb ); 577 // LABEL(" * status[%d]._is_free : %d",rb,spr_status[rb]._is_free ); 578 // LABEL(" * status[%d]._is_link : %d",rb,spr_status[rb]._is_link ); 579 // LABEL(" * status[%d]._is_valid : %d",rb,spr_status[rb]._is_valid); 580 // LABEL(" * status[%d]._counter : %d",rb,spr_status[rb]._counter ); 581 // LABEL(" * read_rc : %d",read_rc ); 582 // LABEL(" * reg_rc : %d",rc ); 583 // LABEL(" * status[%d]._is_free : %d",rc,spr_status[rc]._is_free ); 584 // LABEL(" * status[%d]._is_link : %d",rc,spr_status[rc]._is_link ); 585 // LABEL(" * status[%d]._is_valid : %d",rc,spr_status[rc]._is_valid); 586 // LABEL(" * status[%d]._counter : %d",rc,spr_status[rc]._counter ); 581 587 LABEL(" * read_rd : %d",write_rd); 582 588 LABEL(" * restore_rd_old : %d",restore_rd_old); … … 604 610 LABEL(" * status[%d]._counter : %d",re_new,spr_status[re_new]._counter ); 605 611 606 if (read_ra)607 {608 gpr_status[ra]._counter --;609 }610 if (read_rb)611 {612 gpr_status[rb]._counter --;613 }614 if (read_rc)615 {616 spr_status[rc]._counter --;617 }612 // if (read_ra) 613 // { 614 // gpr_status[ra]._counter --; 615 // } 616 // if (read_rb) 617 // { 618 // gpr_status[rb]._counter --; 619 // } 620 // if (read_rc) 621 // { 622 // spr_status[rc]._counter --; 623 // } 618 624 if (write_rd) 619 625 { … … 721 727 delete [] in_INSERT_VAL ; 722 728 delete [] out_INSERT_ACK ; 723 724 725 726 727 728 729 //delete [] in_INSERT_READ_RA ; 730 //delete [] in_INSERT_NUM_REG_RA_PHY ; 731 //delete [] in_INSERT_READ_RB ; 732 //delete [] in_INSERT_NUM_REG_RB_PHY ; 733 //delete [] in_INSERT_READ_RC ; 734 //delete [] in_INSERT_NUM_REG_RC_PHY ; 729 735 delete [] in_INSERT_WRITE_RD ; 736 delete [] in_INSERT_NUM_REG_RD_PHY_OLD; 730 737 delete [] in_INSERT_NUM_REG_RD_PHY_NEW; 731 738 delete [] in_INSERT_WRITE_RE ; 739 delete [] in_INSERT_NUM_REG_RE_PHY_OLD; 732 740 delete [] in_INSERT_NUM_REG_RE_PHY_NEW; 733 741 delete [] in_RETIRE_VAL ; 734 742 delete [] out_RETIRE_ACK ; 735 743 delete [] in_RETIRE_RESTORE ; 736 737 738 739 740 741 744 //delete [] in_RETIRE_READ_RA ; 745 //delete [] in_RETIRE_NUM_REG_RA_PHY ; 746 //delete [] in_RETIRE_READ_RB ; 747 //delete [] in_RETIRE_NUM_REG_RB_PHY ; 748 //delete [] in_RETIRE_READ_RC ; 749 //delete [] in_RETIRE_NUM_REG_RC_PHY ; 742 750 delete [] in_RETIRE_WRITE_RD ; 743 751 delete [] in_RETIRE_RESTORE_RD_PHY_OLD; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/include/Stat_List_unit.h
r112 r117 72 72 public : SC_IN (Tspecial_address_t) ** in_INSERT_NUM_REG_RC_PHY ;//[nb_inst_insert] 73 73 public : SC_IN (Tcontrol_t ) ** in_INSERT_WRITE_RD ;//[nb_inst_insert] 74 public : SC_IN (Tgeneral_address_t) ** in_INSERT_NUM_REG_RD_PHY_OLD;//[nb_inst_insert] 74 75 public : SC_IN (Tgeneral_address_t) ** in_INSERT_NUM_REG_RD_PHY_NEW;//[nb_inst_insert] 75 76 public : SC_IN (Tcontrol_t ) ** in_INSERT_WRITE_RE ;//[nb_inst_insert] 77 public : SC_IN (Tspecial_address_t) ** in_INSERT_NUM_REG_RE_PHY_OLD;//[nb_inst_insert] 76 78 public : SC_IN (Tspecial_address_t) ** in_INSERT_NUM_REG_RE_PHY_NEW;//[nb_inst_insert] 77 79 78 80 // ~~~~~[ Interface "retire" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 79 81 public : SC_IN (Tcontrol_t ) ** in_RETIRE_VAL ;//[nb_inst_retire] -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/include/Types.h
r112 r117 23 23 class stat_list_entry_t 24 24 { 25 public : bool _is_free ; // set = is present in free list 26 public : bool _is_link ; // set = is present in rat 27 //public : bool _is_valid; // set = an instruction have write in this register 28 //public : uint32_t _counter ; // number of register that must read this register 25 public : bool _is_free ; // set = is present in free list 26 public : bool _is_link ; // set = is present in rat 27 public : bool _is_use ; // set = is present in ROB (used by an instruction as destination) 28 // not necesseray in single thread mode : because an thread can't rename when they have an event 29 // in multi thread, the renaming continue and an old register can be reused 29 30 30 31 public : stat_list_entry_t (void) {}; … … 35 36 _is_free = 0; 36 37 _is_link = is_link; 37 // _is_valid = 1; 38 // _counter = 0; 38 _is_use = is_link; 39 39 } 40 40 41 // public : void insert_read (void) 42 // { 43 // _counter ++; 44 // } 41 public : void insert_write_old (void) 42 { 43 // old is not in the rat, but is already used (if miss prediction or event) 44 _is_link = 0; 45 } 45 46 46 public : void insert_write (void)47 public : void insert_write_new (void) 47 48 { 48 49 _is_free = 0; 49 50 _is_link = 1; 50 // _is_valid = 0;51 _is_use = 1; 51 52 } 52 53 // public : void retire_read (void)54 // {55 // _counter --;56 // }57 53 58 54 public : void retire_write_old (bool restore, bool restore_old) … … 62 58 // 1 0 0 - event and previous update 63 59 // 1 1 1 - event and first update 64 65 _is_link = restore and restore_old; 60 61 if (restore and restore_old) 62 { 63 _is_link = 1; 64 // _is_use = 1; // already set 65 } 66 else 67 { 68 // _is_link = 0; // already unset 69 _is_use = 0; 70 } 71 66 72 } 67 73 … … 73 79 74 80 if (restore) 75 _is_link = 0; 81 { 82 // test if is the actual mapping (in RAT) 83 if (_is_link) 84 _is_use = 0; 76 85 77 // in all case78 // _is_valid = 1; 86 _is_link = 0; 87 } 79 88 } 80 89 … … 84 93 } 85 94 86 // public : bool can_insert_read (uint32_t max_reader)87 // {88 // return ((_counter+1) < max_reader);89 // }90 91 95 public : bool can_free (void) 92 96 { 93 97 return ((_is_free == 0) and 94 (_is_link == 0) // and 95 // (_is_valid == 1) and // if is_link <- 0, then retire_write_old or reset 96 // (_counter == 0) 97 ); 98 (_is_link == 0) and 99 (_is_use == 0)); 98 100 } 99 101 … … 102 104 { 103 105 output << x._is_free << " " 104 << x._is_link // << " " 105 // << x._is_valid << " " 106 // << x._counter 107 ; 106 << x._is_link << " " 107 << x._is_use ; 108 108 109 109 return output; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/src/Stat_List_unit_allocation.cpp
r112 r117 69 69 ALLOC1_SIGNAL_IN ( in_INSERT_NUM_REG_RC_PHY ,"num_reg_rc_phy" ,Tspecial_address_t,_param->_size_special_register); 70 70 ALLOC1_SIGNAL_IN ( in_INSERT_WRITE_RD ,"write_rd" ,Tcontrol_t ,1 ); 71 ALLOC1_SIGNAL_IN ( in_INSERT_NUM_REG_RD_PHY_OLD,"num_reg_rd_phy_old",Tgeneral_address_t,_param->_size_general_register); 71 72 ALLOC1_SIGNAL_IN ( in_INSERT_NUM_REG_RD_PHY_NEW,"num_reg_rd_phy_new",Tgeneral_address_t,_param->_size_general_register); 72 73 ALLOC1_SIGNAL_IN ( in_INSERT_WRITE_RE ,"write_re" ,Tcontrol_t ,1 ); 74 ALLOC1_SIGNAL_IN ( in_INSERT_NUM_REG_RE_PHY_OLD,"num_reg_re_phy_old",Tspecial_address_t,_param->_size_special_register); 73 75 ALLOC1_SIGNAL_IN ( in_INSERT_NUM_REG_RE_PHY_NEW,"num_reg_re_phy_new",Tspecial_address_t,_param->_size_special_register); 74 76 75 77 ALLOC1_INTERFACE_END(_param->_nb_inst_insert); 76 78 } 77 79 78 80 // ~~~~~[ Interface "retire" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 79 81 { 80 82 ALLOC1_INTERFACE_BEGIN("retire",IN,NORTH,_("Retire a renaming result"),_param->_nb_inst_retire); 81 83 82 84 ALLOC1_VALACK_IN ( in_RETIRE_VAL ,VAL); 83 85 ALLOC1_VALACK_OUT(out_RETIRE_ACK ,ACK); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/src/Stat_List_unit_deallocation.cpp
r112 r117 39 39 DELETE1_SIGNAL( in_INSERT_NUM_REG_RC_PHY ,_param->_nb_inst_insert,_param->_size_special_register); 40 40 DELETE1_SIGNAL( in_INSERT_WRITE_RD ,_param->_nb_inst_insert,1 ); 41 DELETE1_SIGNAL( in_INSERT_NUM_REG_RD_PHY_OLD,_param->_nb_inst_insert,_param->_size_general_register); 41 42 DELETE1_SIGNAL( in_INSERT_NUM_REG_RD_PHY_NEW,_param->_nb_inst_insert,_param->_size_general_register); 42 43 DELETE1_SIGNAL( in_INSERT_WRITE_RE ,_param->_nb_inst_insert,1 ); 44 DELETE1_SIGNAL( in_INSERT_NUM_REG_RE_PHY_OLD,_param->_nb_inst_insert,_param->_size_special_register); 43 45 DELETE1_SIGNAL( in_INSERT_NUM_REG_RE_PHY_NEW,_param->_nb_inst_insert,_param->_size_special_register); 44 46 45 47 DELETE1_SIGNAL( in_RETIRE_VAL ,_param->_nb_inst_retire,1); 46 48 DELETE1_SIGNAL(out_RETIRE_ACK ,_param->_nb_inst_retire,1); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/src/Stat_List_unit_transition.cpp
r112 r117 86 86 if (PORT_READ(in_INSERT_WRITE_RD [i])) 87 87 { 88 Tgeneral_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RD_PHY_NEW [i]); 89 90 log_printf(TRACE,Stat_List_unit,FUNCTION," * WRITE_RD - num_reg new : %d",num_reg); 91 92 uint32_t bank = num_reg >> _param->_shift_gpr; 93 uint32_t reg = num_reg & _param->_mask_gpr ; 94 gpr_stat_list [bank][reg].insert_write(); 88 { 89 Tgeneral_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RD_PHY_OLD [i]); 90 91 log_printf(TRACE,Stat_List_unit,FUNCTION," * WRITE_RD - num_reg old : %d",num_reg); 92 93 uint32_t bank = num_reg >> _param->_shift_gpr; 94 uint32_t reg = num_reg & _param->_mask_gpr ; 95 gpr_stat_list [bank][reg].insert_write_old(); 96 } 97 { 98 Tgeneral_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RD_PHY_NEW [i]); 99 100 log_printf(TRACE,Stat_List_unit,FUNCTION," * WRITE_RD - num_reg new : %d",num_reg); 101 102 uint32_t bank = num_reg >> _param->_shift_gpr; 103 uint32_t reg = num_reg & _param->_mask_gpr ; 104 gpr_stat_list [bank][reg].insert_write_new(); 105 } 95 106 } 96 107 97 108 if (PORT_READ(in_INSERT_WRITE_RE [i])) 98 109 { 99 Tspecial_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RE_PHY_NEW [i]); 100 101 log_printf(TRACE,Stat_List_unit,FUNCTION," * WRITE_RE - num_reg new : %d",num_reg); 102 103 uint32_t bank = num_reg >> _param->_shift_spr; 104 uint32_t reg = num_reg & _param->_mask_spr ; 105 spr_stat_list [bank][reg].insert_write(); 106 } 110 { 111 Tspecial_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RE_PHY_OLD [i]); 112 113 log_printf(TRACE,Stat_List_unit,FUNCTION," * WRITE_RE - num_reg old : %d",num_reg); 114 115 uint32_t bank = num_reg >> _param->_shift_spr; 116 uint32_t reg = num_reg & _param->_mask_spr ; 117 spr_stat_list [bank][reg].insert_write_old(); 118 } 119 { 120 Tspecial_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RE_PHY_NEW [i]); 121 122 log_printf(TRACE,Stat_List_unit,FUNCTION," * WRITE_RE - num_reg new : %d",num_reg); 123 124 uint32_t bank = num_reg >> _param->_shift_spr; 125 uint32_t reg = num_reg & _param->_mask_spr ; 126 spr_stat_list [bank][reg].insert_write_new(); 127 } 128 } 107 129 } 108 130 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/src/Register_translation_unit_allocation.cpp
r112 r117 638 638 COMPONENT_MAP(_component,src , "in_INSERT_"+toString(i)+"_WRITE_RD" , 639 639 dest,"out_INSERT_"+toString(i)+"_STAT_LIST_WRITE_RD" ); 640 COMPONENT_MAP(_component,src , "in_INSERT_"+toString(i)+"_NUM_REG_RD_PHY_OLD", 641 dest,"out_INSERT_"+toString(i)+"_STAT_LIST_NUM_REG_RD_PHY_OLD"); 640 642 COMPONENT_MAP(_component,src , "in_INSERT_"+toString(i)+"_NUM_REG_RD_PHY_NEW", 641 643 dest,"out_INSERT_"+toString(i)+"_STAT_LIST_NUM_REG_RD_PHY_NEW"); 642 644 COMPONENT_MAP(_component,src , "in_INSERT_"+toString(i)+"_WRITE_RE" , 643 645 dest,"out_INSERT_"+toString(i)+"_STAT_LIST_WRITE_RE" ); 646 COMPONENT_MAP(_component,src , "in_INSERT_"+toString(i)+"_NUM_REG_RE_PHY_OLD", 647 dest,"out_INSERT_"+toString(i)+"_STAT_LIST_NUM_REG_RE_PHY_OLD"); 644 648 COMPONENT_MAP(_component,src , "in_INSERT_"+toString(i)+"_NUM_REG_RE_PHY_NEW", 645 649 dest,"out_INSERT_"+toString(i)+"_STAT_LIST_NUM_REG_RE_PHY_NEW"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/configuration.cfg
r112 r117 7 7 1 1 +1 # nb_inst_insert [0] [nb_rename_unit] 8 8 1 1 +1 # nb_inst_retire [0] [nb_rename_unit] 9 1 1 +1 # nb_inst_issue10 9 1 1 +1 # nb_inst_execute [0] [nb_execute_loop] 11 10 1 1 +1 # nb_inst_reexecute … … 28 27 1 1 +1 # issue_priority 29 28 1 1 +1 # issue_load_balancing 30 1 1 +1 # table_routing [0][0] [nb_rename_unit][nb_inst_issue]31 1 1 +1 # table_issue_type [0][TYPE_ALU ] [nb_inst_issue][nb_type]32 1 1 +1 # table_issue_type [0][TYPE_SHIFT ] [nb_inst_issue][nb_type]33 1 1 +1 # table_issue_type [0][TYPE_MOVE ] [nb_inst_issue][nb_type]34 1 1 +1 # table_issue_type [0][TYPE_TEST ] [nb_inst_issue][nb_type]35 1 1 +1 # table_issue_type [0][TYPE_MUL ] [nb_inst_issue][nb_type]36 1 1 +1 # table_issue_type [0][TYPE_DIV ] [nb_inst_issue][nb_type]37 1 1 +1 # table_issue_type [0][TYPE_EXTEND ] [nb_inst_issue][nb_type]38 1 1 +1 # table_issue_type [0][TYPE_FIND ] [nb_inst_issue][nb_type]39 1 1 +1 # table_issue_type [0][TYPE_SPECIAL] [nb_inst_issue][nb_type]40 1 1 +1 # table_issue_type [0][TYPE_CUSTOM ] [nb_inst_issue][nb_type]41 1 1 +1 # table_issue_type [0][TYPE_BRANCH ] [nb_inst_issue][nb_type]42 1 1 +1 # table_issue_type [0][TYPE_MEMORY ] [nb_inst_issue][nb_type]43 29 1 1 +1 # size_reexecute_queue 44 30 1 1 +1 # reexecute_priority -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/src/main.cpp
r112 r117 9 9 #include "Behavioural/include/Allocation.h" 10 10 11 #define NB_PARAMS 2 411 #define NB_PARAMS 23 12 12 13 13 void usage (int argc, char * argv[]) … … 22 22 err (_(" * nb_inst_insert [nb_rename_unit] (uint32_t )\n")); 23 23 err (_(" * nb_inst_retire [nb_rename_unit] (uint32_t )\n")); 24 24 //err (_(" * nb_inst_issue (uint32_t )\n")); 25 25 err (_(" * nb_inst_execute [nb_execute_loop] (uint32_t )\n")); 26 26 err (_(" * nb_inst_reexecute (uint32_t )\n")); … … 43 43 err (_(" * issue_priority (Tpriority_t )\n")); 44 44 err (_(" * issue_load_balancing (Tload_balancing_t )\n")); 45 err (_(" * table_routing [nb_rename_unit][nb_inst_issue] (bool )\n"));46 err (_(" * table_issue_type [nb_inst_issue][nb_type] (bool )\n"));47 err (_(" * TYPE_ALU \n"));48 err (_(" * TYPE_SHIFT \n"));49 err (_(" * TYPE_MOVE \n"));50 err (_(" * TYPE_TEST \n"));51 err (_(" * TYPE_MUL \n"));52 err (_(" * TYPE_DIV \n"));53 err (_(" * TYPE_EXTEND \n"));54 err (_(" * TYPE_FIND \n"));55 err (_(" * TYPE_SPECIAL\n"));56 err (_(" * TYPE_CUSTOM \n"));57 err (_(" * TYPE_BRANCH \n"));58 err (_(" * TYPE_MEMORY \n"));45 // err (_(" * table_routing [nb_rename_unit][nb_inst_issue] (bool )\n")); 46 // err (_(" * table_issue_type [nb_inst_issue][nb_type] (bool )\n")); 47 // err (_(" * TYPE_ALU \n")); 48 // err (_(" * TYPE_SHIFT \n")); 49 // err (_(" * TYPE_MOVE \n")); 50 // err (_(" * TYPE_TEST \n")); 51 // err (_(" * TYPE_MUL \n")); 52 // err (_(" * TYPE_DIV \n")); 53 // err (_(" * TYPE_EXTEND \n")); 54 // err (_(" * TYPE_FIND \n")); 55 // err (_(" * TYPE_SPECIAL\n")); 56 // err (_(" * TYPE_CUSTOM \n")); 57 // err (_(" * TYPE_BRANCH \n")); 58 // err (_(" * TYPE_MEMORY \n")); 59 59 err (_(" * size_reexecute_queue (uint32_t )\n")); 60 60 err (_(" * reexecute_priority (Tpriority_t )\n")); … … 120 120 _nb_inst_retire [i] = fromString<uint32_t>(argv[x++]); 121 121 122 122 //uint32_t _nb_inst_issue = fromString<uint32_t >(argv[x++]); 123 123 uint32_t * _nb_inst_execute = new uint32_t [_nb_execute_loop]; 124 124 for (uint32_t i=0; i<_nb_execute_loop; i++) … … 152 152 Tpriority_t _issue_priority = fromString<Tpriority_t >(argv[x++]); 153 153 Tload_balancing_t _issue_load_balancing = fromString<Tload_balancing_t>(argv[x++]); 154 bool ** _table_routing = new bool * [_nb_rename_unit]; 155 for (uint32_t i=0; i<_nb_rename_unit; i++) 156 { 157 _table_routing [i] = new bool [_nb_inst_issue]; 158 for (uint32_t j=0; j<_nb_inst_issue; j++) 159 _table_routing [i][j] = fromString<bool>(argv[x++]); 160 } 161 162 if (argc <= static_cast<int>(2+NB_PARAMS+3*_nb_front_end+2*_sum_nb_context+10*_nb_rename_unit+_nb_execute_loop+_nb_rename_unit*_nb_inst_issue+12*_nb_inst_issue)) 154 // bool ** _table_routing = new bool * [_nb_rename_unit]; 155 // for (uint32_t i=0; i<_nb_rename_unit; i++) 156 // { 157 // _table_routing [i] = new bool [_nb_inst_issue]; 158 // for (uint32_t j=0; j<_nb_inst_issue; j++) 159 // _table_routing [i][j] = fromString<bool>(argv[x++]); 160 // } 161 162 if (argc <= static_cast<int>(2+NB_PARAMS+3*_nb_front_end+2*_sum_nb_context+10*_nb_rename_unit+_nb_execute_loop//+_nb_rename_unit*_nb_inst_issue+12*_nb_inst_issue 163 )) 163 164 usage (argc, argv); 164 165 165 bool ** _table_issue_type = new bool * [_nb_inst_issue];166 for (uint32_t i=0; i<_nb_inst_issue; i++)167 {168 _table_issue_type [i] = new bool [MAX_TYPE];169 for (uint32_t j=0; j<MAX_TYPE; j++)170 _table_issue_type [i][j] = false;171 172 _table_issue_type [i][TYPE_ALU ] = fromString<bool>(argv[x++]);173 _table_issue_type [i][TYPE_SHIFT ] = fromString<bool>(argv[x++]);174 _table_issue_type [i][TYPE_MOVE ] = fromString<bool>(argv[x++]);175 _table_issue_type [i][TYPE_TEST ] = fromString<bool>(argv[x++]);176 _table_issue_type [i][TYPE_MUL ] = fromString<bool>(argv[x++]);177 _table_issue_type [i][TYPE_DIV ] = fromString<bool>(argv[x++]);178 _table_issue_type [i][TYPE_EXTEND ] = fromString<bool>(argv[x++]);179 _table_issue_type [i][TYPE_FIND ] = fromString<bool>(argv[x++]);180 _table_issue_type [i][TYPE_SPECIAL] = fromString<bool>(argv[x++]);181 _table_issue_type [i][TYPE_CUSTOM ] = fromString<bool>(argv[x++]);182 _table_issue_type [i][TYPE_BRANCH ] = fromString<bool>(argv[x++]);183 _table_issue_type [i][TYPE_MEMORY ] = fromString<bool>(argv[x++]);184 }166 // bool ** _table_issue_type = new bool * [_nb_inst_issue]; 167 // for (uint32_t i=0; i<_nb_inst_issue; i++) 168 // { 169 // _table_issue_type [i] = new bool [MAX_TYPE]; 170 // for (uint32_t j=0; j<MAX_TYPE; j++) 171 // _table_issue_type [i][j] = false; 172 173 // _table_issue_type [i][TYPE_ALU ] = fromString<bool>(argv[x++]); 174 // _table_issue_type [i][TYPE_SHIFT ] = fromString<bool>(argv[x++]); 175 // _table_issue_type [i][TYPE_MOVE ] = fromString<bool>(argv[x++]); 176 // _table_issue_type [i][TYPE_TEST ] = fromString<bool>(argv[x++]); 177 // _table_issue_type [i][TYPE_MUL ] = fromString<bool>(argv[x++]); 178 // _table_issue_type [i][TYPE_DIV ] = fromString<bool>(argv[x++]); 179 // _table_issue_type [i][TYPE_EXTEND ] = fromString<bool>(argv[x++]); 180 // _table_issue_type [i][TYPE_FIND ] = fromString<bool>(argv[x++]); 181 // _table_issue_type [i][TYPE_SPECIAL] = fromString<bool>(argv[x++]); 182 // _table_issue_type [i][TYPE_CUSTOM ] = fromString<bool>(argv[x++]); 183 // _table_issue_type [i][TYPE_BRANCH ] = fromString<bool>(argv[x++]); 184 // _table_issue_type [i][TYPE_MEMORY ] = fromString<bool>(argv[x++]); 185 // } 185 186 186 187 uint32_t _size_reexecute_queue = fromString<uint32_t >(argv[x++]); … … 220 221 } 221 222 222 if (argc != static_cast<int>(2+NB_PARAMS+3*_nb_front_end+2*_sum_nb_context+10*_nb_rename_unit+_nb_execute_loop+_nb_rename_unit*_nb_inst_issue+12*_nb_inst_issue+3*_sum_nb_load_store_queue)) 223 if (argc != static_cast<int>(2+NB_PARAMS+3*_nb_front_end+2*_sum_nb_context+10*_nb_rename_unit+_nb_execute_loop+// _nb_rename_unit*_nb_inst_issue+12*_nb_inst_issue 224 3*_sum_nb_load_store_queue)) 223 225 usage (argc, argv); 224 226 … … 294 296 _nb_inst_insert , 295 297 _nb_inst_retire , 296 298 // _nb_inst_issue , 297 299 _nb_inst_execute , 298 300 _nb_inst_reexecute , … … 315 317 _issue_priority , 316 318 _issue_load_balancing , 317 _table_routing ,318 _table_issue_type ,319 // _table_routing , 320 // _table_issue_type , 319 321 _size_reexecute_queue , 320 322 _reexecute_priority , … … 400 402 delete [] _rename_select_priority ; 401 403 402 for (uint32_t i=0; i<_nb_inst_issue; i++)403 delete [] _table_issue_type [i];404 delete [] _table_issue_type;405 406 for (uint32_t i=0; i<_nb_rename_unit; i++)407 delete [] _table_routing [i];408 delete [] _table_routing;404 // for (uint32_t i=0; i<_nb_inst_issue; i++) 405 // delete [] _table_issue_type [i]; 406 // delete [] _table_issue_type; 407 408 // for (uint32_t i=0; i<_nb_rename_unit; i++) 409 // delete [] _table_routing [i]; 410 // delete [] _table_routing; 409 411 410 412 delete [] _link_rename_unit_with_front_end; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/src/test.cpp
r112 r117 52 52 sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5); 53 53 sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET"); 54 55 sc_signal<Tcontrol_t > *** in_RENAME_VAL ; 56 sc_signal<Tcontrol_t > *** out_RENAME_ACK ; 57 sc_signal<Tcontext_t > *** in_RENAME_FRONT_END_ID ; 58 sc_signal<Tcontext_t > *** in_RENAME_CONTEXT_ID ; 59 sc_signal<Tdepth_t > *** in_RENAME_DEPTH ; 60 sc_signal<Ttype_t > *** in_RENAME_TYPE ; 61 sc_signal<Toperation_t > *** in_RENAME_OPERATION ; 62 sc_signal<Tcontrol_t > *** in_RENAME_NO_EXECUTE ; 63 sc_signal<Tcontrol_t > *** in_RENAME_IS_DELAY_SLOT ; 64 sc_signal<Taddress_t > *** in_RENAME_ADDRESS ; 65 sc_signal<Taddress_t > *** in_RENAME_ADDRESS_NEXT ; 66 sc_signal<Tcontrol_t > *** in_RENAME_HAS_IMMEDIAT ; 67 sc_signal<Tgeneral_data_t > *** in_RENAME_IMMEDIAT ; 68 sc_signal<Tcontrol_t > *** in_RENAME_READ_RA ; 69 sc_signal<Tgeneral_address_t> *** in_RENAME_NUM_REG_RA ; 70 sc_signal<Tcontrol_t > *** in_RENAME_READ_RB ; 71 sc_signal<Tgeneral_address_t> *** in_RENAME_NUM_REG_RB ; 72 sc_signal<Tcontrol_t > *** in_RENAME_READ_RC ; 73 sc_signal<Tspecial_address_t> *** in_RENAME_NUM_REG_RC ; 74 sc_signal<Tcontrol_t > *** in_RENAME_WRITE_RD ; 75 sc_signal<Tgeneral_address_t> *** in_RENAME_NUM_REG_RD ; 76 sc_signal<Tcontrol_t > *** in_RENAME_WRITE_RE ; 77 sc_signal<Tspecial_address_t> *** in_RENAME_NUM_REG_RE ; 78 sc_signal<Texception_t > *** in_RENAME_EXCEPTION_USE ; 79 sc_signal<Texception_t > *** in_RENAME_EXCEPTION ; 80 81 sc_signal<Tcontrol_t > ** out_ISSUE_VAL ; 82 sc_signal<Tcontrol_t > ** in_ISSUE_ACK ; 83 sc_signal<Tcontext_t > ** out_ISSUE_FRONT_END_ID ; 84 sc_signal<Tcontext_t > ** out_ISSUE_CONTEXT_ID ; 85 sc_signal<Tpacket_t > ** out_ISSUE_PACKET_ID ; 86 sc_signal<Ttype_t > ** out_ISSUE_TYPE ; 87 sc_signal<Toperation_t > ** out_ISSUE_OPERATION ; 88 sc_signal<Tlsq_ptr_t > ** out_ISSUE_STORE_QUEUE_PTR_WRITE ; 89 sc_signal<Tlsq_ptr_t > ** out_ISSUE_LOAD_QUEUE_PTR_WRITE ; 90 sc_signal<Tcontrol_t > ** out_ISSUE_HAS_IMMEDIAT ; 91 sc_signal<Tgeneral_data_t > ** out_ISSUE_IMMEDIAT ; 92 sc_signal<Tcontrol_t > ** out_ISSUE_READ_RA ; 93 sc_signal<Tgeneral_address_t> ** out_ISSUE_NUM_REG_RA ; 94 sc_signal<Tcontrol_t > ** out_ISSUE_READ_RB ; 95 sc_signal<Tgeneral_address_t> ** out_ISSUE_NUM_REG_RB ; 96 sc_signal<Tcontrol_t > ** out_ISSUE_READ_RC ; 97 sc_signal<Tspecial_address_t> ** out_ISSUE_NUM_REG_RC ; 98 sc_signal<Tcontrol_t > ** out_ISSUE_WRITE_RD ; 99 sc_signal<Tgeneral_address_t> ** out_ISSUE_NUM_REG_RD ; 100 sc_signal<Tcontrol_t > ** out_ISSUE_WRITE_RE ; 101 sc_signal<Tspecial_address_t> ** out_ISSUE_NUM_REG_RE ; 102 103 sc_signal<Tcontrol_t > *** in_EXECUTE_LOOP_VAL ; 104 sc_signal<Tcontrol_t > *** out_EXECUTE_LOOP_ACK ; 105 sc_signal<Tcontext_t > *** in_EXECUTE_LOOP_FRONT_END_ID ; 106 sc_signal<Tcontext_t > *** in_EXECUTE_LOOP_CONTEXT_ID ; 107 sc_signal<Tpacket_t > *** in_EXECUTE_LOOP_PACKET_ID ; 108 //sc_signal<Ttype_t > *** in_EXECUTE_LOOP_TYPE ; 109 //sc_signal<Toperation_t > *** in_EXECUTE_LOOP_OPERATION ; 110 sc_signal<Tspecial_data_t > *** in_EXECUTE_LOOP_FLAGS ; 111 sc_signal<Texception_t > *** in_EXECUTE_LOOP_EXCEPTION ; 112 sc_signal<Tcontrol_t > *** in_EXECUTE_LOOP_NO_SEQUENCE ; 113 sc_signal<Taddress_t > *** in_EXECUTE_LOOP_ADDRESS ; 114 sc_signal<Tgeneral_data_t > *** in_EXECUTE_LOOP_DATA ; 115 116 sc_signal<Tcontrol_t > ** out_INSERT_VAL ; 117 sc_signal<Tcontrol_t > ** in_INSERT_ACK ; 118 sc_signal<Tcontrol_t > ** out_INSERT_RD_USE ; 119 sc_signal<Tgeneral_address_t> ** out_INSERT_RD_NUM_REG ; 120 sc_signal<Tcontrol_t > ** out_INSERT_RE_USE ; 121 sc_signal<Tspecial_address_t> ** out_INSERT_RE_NUM_REG ; 122 123 //sc_signal<Tcontrol_t > ** out_RETIRE_VAL ; 124 //sc_signal<Tcontrol_t > ** in_RETIRE_ACK ; 125 //sc_signal<Tcontrol_t > ** out_RETIRE_RD_OLD_USE ; 126 //sc_signal<Tgeneral_address_t> ** out_RETIRE_RD_OLD_NUM_REG ; 127 //sc_signal<Tcontrol_t > ** out_RETIRE_RD_NEW_USE ; 128 //sc_signal<Tgeneral_address_t> ** out_RETIRE_RD_NEW_NUM_REG ; 129 //sc_signal<Tcontrol_t > ** out_RETIRE_RE_OLD_USE ; 130 //sc_signal<Tspecial_address_t> ** out_RETIRE_RE_OLD_NUM_REG ; 131 //sc_signal<Tcontrol_t > ** out_RETIRE_RE_NEW_USE ; 132 //sc_signal<Tspecial_address_t> ** out_RETIRE_RE_NEW_NUM_REG ; 133 134 sc_signal<Tcontrol_t > ** out_BRANCH_COMPLETE_VAL ; 135 sc_signal<Tcontrol_t > ** in_BRANCH_COMPLETE_ACK ; 136 sc_signal<Tcontext_t > ** out_BRANCH_COMPLETE_FRONT_END_ID ; 137 sc_signal<Tcontext_t > ** out_BRANCH_COMPLETE_CONTEXT_ID ; 138 sc_signal<Tdepth_t > ** out_BRANCH_COMPLETE_DEPTH ; 139 sc_signal<Taddress_t > ** out_BRANCH_COMPLETE_ADDRESS ; 140 sc_signal<Tcontrol_t > ** out_BRANCH_COMPLETE_NO_SEQUENCE ; 141 sc_signal<Tcontrol_t > ** in_BRANCH_COMPLETE_MISS_PREDICTION ; 142 143 sc_signal<Tcontrol_t > * out_COMMIT_EVENT_VAL ; 144 sc_signal<Tcontrol_t > * in_COMMIT_EVENT_ACK ; 145 sc_signal<Tcontext_t > * out_COMMIT_EVENT_FRONT_END_ID ; 146 sc_signal<Tcontext_t > * out_COMMIT_EVENT_CONTEXT_ID ; 147 sc_signal<Tdepth_t > * out_COMMIT_EVENT_DEPTH ; 148 sc_signal<Tevent_type_t > * out_COMMIT_EVENT_TYPE ; 149 sc_signal<Tcontrol_t > * out_COMMIT_EVENT_IS_DELAY_SLOT ; 150 sc_signal<Taddress_t > * out_COMMIT_EVENT_ADDRESS ; 151 sc_signal<Tcontrol_t > * out_COMMIT_EVENT_ADDRESS_EPCR_VAL ; 152 sc_signal<Taddress_t > * out_COMMIT_EVENT_ADDRESS_EPCR ; 153 sc_signal<Tcontrol_t > * out_COMMIT_EVENT_ADDRESS_EEAR_VAL ; 154 sc_signal<Tgeneral_data_t > * out_COMMIT_EVENT_ADDRESS_EEAR ; 155 156 sc_signal<Tcontrol_t > *** in_EVENT_VAL ; 157 sc_signal<Tcontrol_t > *** out_EVENT_ACK ; 158 sc_signal<Taddress_t > *** in_EVENT_ADDRESS ; 159 sc_signal<Taddress_t > *** in_EVENT_ADDRESS_NEXT ; 160 sc_signal<Tcontrol_t > *** in_EVENT_ADDRESS_NEXT_VAL ; 161 sc_signal<Tcontrol_t > *** in_EVENT_IS_DS_TAKE ; 162 163 sc_signal<Tcontrol_t > *** in_SPR_EVENT_VAL ; 164 sc_signal<Tcontrol_t > *** out_SPR_EVENT_ACK ; 165 sc_signal<Tspr_t > *** in_SPR_EVENT_EPCR ; 166 sc_signal<Tcontrol_t > *** in_SPR_EVENT_EEAR_WEN ; 167 sc_signal<Tspr_t > *** in_SPR_EVENT_EEAR ; 168 sc_signal<Tcontrol_t > *** in_SPR_EVENT_SR_DSX ; 169 sc_signal<Tcontrol_t > *** in_SPR_EVENT_SR_TO_ESR ; 170 171 sc_signal<Tcounter_t > *** out_NB_INST_COMMIT_ALL ; 172 sc_signal<Tcounter_t > *** out_NB_INST_COMMIT_MEM ; 173 sc_signal<Tcounter_t > *** in_NB_INST_DECOD_ALL ; 174 175 sc_signal<Tdepth_t > *** in_DEPTH_MIN ; 176 sc_signal<Tdepth_t > *** in_DEPTH_MAX ; 177 sc_signal<Tcontrol_t > *** in_DEPTH_FULL ; 178 179 sc_signal<Tcontrol_t > *** out_SPR_SR_IEE ; 180 sc_signal<Tcontrol_t > *** out_SPR_SR_EPH ; 54 181 55 182 ALLOC2_SC_SIGNAL( in_RENAME_VAL ," in_RENAME_VAL ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/SelfTest/src/main.cpp
r115 r117 61 61 } 62 62 63 uint32_t num_thread = 0; 64 uint32_t ** _translate_num_context_to_num_thread = new uint32_t * [_nb_front_end]; 65 for (uint32_t i=0; i<_nb_front_end; i++) 66 { 67 _translate_num_context_to_num_thread [i] = new uint32_t [_nb_context[i]]; 68 for (uint32_t j=0; j<_nb_context[i]; j++) 69 _translate_num_context_to_num_thread [i][j] = num_thread ++; 70 } 71 63 72 int _return = EXIT_SUCCESS; 64 73 try … … 70 79 _nb_inst_reexecute , 71 80 _implement_group , 81 _translate_num_context_to_num_thread, 72 82 true //is_toplevel 73 83 ); … … 100 110 for (uint32_t i=0; i<_nb_front_end; i++) 101 111 { 112 delete [] _translate_num_context_to_num_thread [i]; 113 } 114 delete [] _translate_num_context_to_num_thread; 115 116 117 for (uint32_t i=0; i<_nb_front_end; i++) 118 { 102 119 for (uint32_t j=0; j<_nb_context[i]; j++) 103 120 delete [] _implement_group [i][j]; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/include/Parameters.h
r88 r117 27 27 public : uint32_t _nb_inst_reexecute ; 28 28 public : bool *** _implement_group ;//[nb_front_end][nb_context][NB_GROUP] 29 public : uint32_t ** _translate_num_context_to_num_thread; //[nb_front_end][nb_context] 29 30 30 31 public : uint32_t _max_nb_context ; … … 41 42 uint32_t nb_inst_reexecute , 42 43 bool *** implement_group , 44 uint32_t ** translate_num_context_to_num_thread, //[nb_front_end][nb_context] 43 45 bool is_toplevel=false 44 46 ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/include/SPR.h
r101 r117 545 545 // [0][21] CID 546 546 //---------------------------------------------------------- 547 class CID : public GENERIC 548 { 549 public : CID (uint32_t num_front_end=0, uint32_t num_context=0,const Parameters * param=NULL) : GENERIC (num_front_end,num_context,param) {}; 550 }; 551 552 //---------------------------------------------------------- 553 // [0][22] TID 554 //---------------------------------------------------------- 555 class TID : public GENERIC 556 { 557 public : TID (uint32_t num_front_end=0, uint32_t num_context=0,const Parameters * param=NULL) : GENERIC (num_front_end,num_context,param) {}; 558 }; 559 560 //---------------------------------------------------------- 561 // [0][23] TSR 547 class CID : public morpheo::behavioural::SPR 548 { 549 private: const Tspr_t _cpu_id : 32; // cpu_id reset value 550 public : Tspr_t cpu_id : 32; 551 552 public : CID (uint32_t num_front_end=0, uint32_t num_context=0,const Parameters * param=NULL): 553 _cpu_id ((param==NULL)?0:param->_translate_num_context_to_num_thread[num_front_end][num_context]) 554 {}; 555 public : void reset (void ) 556 { 557 cpu_id = _cpu_id; 558 }; 559 public : Tspr_t read (void ) 560 { 561 return ((cpu_id << 0)); 562 }; 563 public : void write (Tspr_t x) 564 { 565 cpu_id = x >> 0; 566 }; 567 }; 568 569 //---------------------------------------------------------- 570 // [0][22] TID - Thread Id 571 //---------------------------------------------------------- 572 class TID : public morpheo::behavioural::SPR 573 { 574 public : Tspr_t thread_id : 32; 575 576 public : TID (uint32_t num_front_end=0, uint32_t num_context=0,const Parameters * param=NULL) 577 {}; 578 public : void reset (void ) 579 { 580 }; 581 public : Tspr_t read (void ) 582 { 583 return ((thread_id << 0)); 584 }; 585 public : void write (Tspr_t x) 586 { 587 thread_id = x >> 0; 588 }; 589 }; 590 591 //---------------------------------------------------------- 592 // [0][23] TSR - Thread Status Register 562 593 //---------------------------------------------------------- 563 594 class TSR : public GENERIC -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Parameters.cpp
r88 r117 23 23 uint32_t nb_inst_reexecute , 24 24 bool *** implement_group , 25 uint32_t ** translate_num_context_to_num_thread, //[nb_front_end][nb_context] 25 26 bool is_toplevel 26 27 ) … … 32 33 _nb_inst_reexecute = nb_inst_reexecute; 33 34 _implement_group = implement_group ; 35 _translate_num_context_to_num_thread = translate_num_context_to_num_thread; 34 36 35 37 _max_nb_context = max<uint32_t>(_nb_context,_nb_front_end); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_allocation.cpp
r112 r117 236 236 for (uint32_t j=0; j<_param->_nb_context[i]; j++) 237 237 for (uint32_t k=0; k<NB_GROUP; k++) 238 238 if (_param->_implement_group [i][j][k]) 239 239 { 240 240 241 for (uint32_t l=0; l<NB_REG_GROUP[k]; l++) 241 242 if (_spr [i][j][k][l] == NULL) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/include/Parameters.h
r112 r117 62 62 public : Tpriority_t _issue_priority ; 63 63 public : Tload_balancing_t _issue_load_balancing ; 64 public : bool ** _table_routing ;//[nb_rename_unit][nb_inst_issue]65 public : bool ** _table_issue_type ;//[nb_inst_issue][nb_type]64 // public : bool ** _table_routing ;//[nb_rename_unit][nb_inst_issue] 65 // public : bool ** _table_issue_type ;//[nb_inst_issue][nb_type] 66 66 // Reexecute 67 67 public : uint32_t _size_reexecute_queue ; … … 135 135 uint32_t * nb_inst_insert ,//[nb_rename_unit] 136 136 uint32_t * nb_inst_retire ,//[nb_rename_unit] 137 137 // uint32_t nb_inst_issue , 138 138 uint32_t * nb_inst_execute ,//[nb_execute_loop] 139 139 uint32_t nb_inst_reexecute , … … 159 159 Tpriority_t issue_priority , 160 160 Tload_balancing_t issue_load_balancing , 161 bool ** table_routing ,//[nb_rename_unit][nb_inst_issue]162 bool ** table_issue_type ,//[nb_inst_issue][nb_type]161 // bool ** table_routing ,//[nb_rename_unit][nb_inst_issue] 162 // bool ** table_issue_type ,//[nb_inst_issue][nb_type] 163 163 // Reexecute 164 164 uint32_t size_reexecute_queue , … … 173 173 uint32_t * nb_reg_free ,//[nb_rename_unit] 174 174 uint32_t * nb_rename_unit_bank ,//[nb_rename_unit] 175 // 175 // uint32_t * size_read_counter ,//[nb_rename_unit] 176 176 uint32_t * nb_load_store_queue ,//[nb_rename_unit] 177 177 uint32_t ** size_store_queue ,//[nb_rename_unit][nb_load_store_queue] -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_allocation.cpp
r112 r117 674 674 COMPONENT_MAP(_component,src , "in_RETIRE_EVENT_"+toString(x)+"_"+toString(k)+"_STATE", 675 675 dest,"out_RETIRE_EVENT_"+toString(j)+"_"+toString(k)+"_STATE"); 676 x++;677 ++it;678 676 } 677 x++; 678 ++it; 679 679 } 680 680 } … … 885 885 COMPONENT_MAP(_component,src , "in_COMMIT_"+toString(i)+"_WEN" , 886 886 dest,"out_COMMIT_"+toString(i)+"_WEN" ); 887 // if (_param->_have_port_context_id) 888 // COMPONENT_MAP(_component,src , "in_COMMIT_"+toString(i)+"_CONTEXT_ID" , 889 // dest,"out_COMMIT_"+toString(i)+"_CONTEXT_ID" ); 890 // if (_param->_have_port_front_end_id) 891 // COMPONENT_MAP(_component,src , "in_COMMIT_"+toString(i)+"_FRONT_END_ID", 892 // dest,"out_COMMIT_"+toString(i)+"_FRONT_END_ID"); 887 893 if (_param->_have_port_rob_ptr) 888 894 COMPONENT_MAP(_component,src , "in_COMMIT_"+toString(i)+"_PACKET_ID" , -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/Parameters.cpp
r112 r117 25 25 uint32_t * nb_inst_insert ,//[nb_rename_unit] 26 26 uint32_t * nb_inst_retire ,//[nb_rename_unit] 27 27 // uint32_t nb_inst_issue , 28 28 uint32_t * nb_inst_execute ,//[nb_execute_loop] 29 29 uint32_t nb_inst_reexecute , … … 49 49 Tpriority_t issue_priority , 50 50 Tload_balancing_t issue_load_balancing , 51 bool ** table_routing ,//[nb_rename_unit][nb_inst_issue]52 bool ** table_issue_type ,//[nb_inst_issue][nb_type]51 // bool ** table_routing ,//[nb_rename_unit][nb_inst_issue] 52 // bool ** table_issue_type ,//[nb_inst_issue][nb_type] 53 53 // Reexecute 54 54 uint32_t size_reexecute_queue , … … 63 63 uint32_t * nb_reg_free ,//[nb_rename_unit] 64 64 uint32_t * nb_rename_unit_bank ,//[nb_rename_unit] 65 // 65 // uint32_t * size_read_counter ,//[nb_rename_unit] 66 66 uint32_t * nb_load_store_queue ,//[nb_rename_unit] 67 67 uint32_t ** size_store_queue ,//[nb_rename_unit][nb_load_store_queue] … … 87 87 _nb_inst_insert = nb_inst_insert ; 88 88 _nb_inst_retire = nb_inst_retire ; 89 89 // _nb_inst_issue = nb_inst_issue ; 90 90 _nb_inst_execute = nb_inst_execute ; 91 91 _nb_inst_reexecute = nb_inst_reexecute ; … … 107 107 _issue_priority = issue_priority ; 108 108 _issue_load_balancing = issue_load_balancing ; 109 _table_routing = table_routing ;110 _table_issue_type = table_issue_type ;109 // _table_routing = table_routing ; 110 // _table_issue_type = table_issue_type ; 111 111 _size_reexecute_queue = size_reexecute_queue ; 112 112 _reexecute_priority = reexecute_priority ; … … 265 265 _commit_load_balancing , 266 266 _nb_rename_unit_select , 267 _nb_thread 267 _nb_thread , 268 268 _translate_num_context_to_num_thread 269 269 ); … … 284 284 size_store_queue_ptr , 285 285 size_load_queue_ptr , 286 286 // _nb_inst_issue , 287 287 _nb_inst_insert , 288 288 _nb_inst_reexecute , 289 289 _nb_rename_unit_select , 290 290 _issue_priority , 291 _issue_load_balancing ,292 _table_routing ,293 _table_issue_type291 _issue_load_balancing // , 292 // _table_routing , 293 // _table_issue_type 294 294 ); 295 296 _nb_inst_issue = _param_issue_queue->_nb_inst_issue; 295 297 296 298 _param_reexecute_unit = new morpheo::behavioural::core::multi_ooo_engine::ooo_engine::reexecute_unit::Parameters … … 319 321 _nb_context , 320 322 _nb_inst_reexecute , 321 _implement_group 323 _implement_group , 324 _translate_num_context_to_num_thread 322 325 ); 323 326 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/Parameters_print.cpp
r112 r117 58 58 str+= toString(MSG_INFORMATION)+" * issue_priority : "+toString<Tpriority_t >(_issue_priority )+"\n"; 59 59 str+= toString(MSG_INFORMATION)+" * issue_load_balancing : "+toString<Tload_balancing_t>(_issue_load_balancing )+"\n"; 60 61 62 63 64 65 60 // for (uint32_t i=0; i<_nb_rename_unit; ++i) 61 // for (uint32_t j=0; j<_nb_inst_issue ; ++j) 62 // str+= toString(MSG_INFORMATION)+" * table_routing ["+toString(i)+"]["+toString(j)+"] : "+toString<bool >(_table_routing [i][j] )+"\n";//[nb_rename_unit][nb_inst_issue] 63 // for (uint32_t i=0; i<_nb_inst_issue ; ++i) 64 // for (uint32_t j=0; j<_nb_type; ++j) 65 // str+= toString(MSG_INFORMATION)+" * table_issue_type ["+toString(i)+"]["+toString(j)+"] : "+toString<bool >(_table_issue_type [i][j] )+"\n";//[nb_inst_issue][nb_type] 66 66 str+= toString(MSG_INFORMATION)+" * size_reexecute_queue : "+toString<uint32_t >(_size_reexecute_queue )+"\n"; 67 67 str+= toString(MSG_INFORMATION)+" * reexecute_priority : "+toString<Tpriority_t >(_reexecute_priority )+"\n"; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/SelfTest/src/test.cpp
r110 r117 52 52 sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5); 53 53 sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET"); 54 55 sc_signal<Tcontrol_t > ** out_ICACHE_REQ_VAL ; 56 sc_signal<Tcontrol_t > ** in_ICACHE_REQ_ACK ; 57 sc_signal<Tcontext_t > ** out_ICACHE_REQ_THREAD_ID ; 58 sc_signal<Tpacket_t > ** out_ICACHE_REQ_PACKET_ID ; 59 sc_signal<Ticache_address_t > ** out_ICACHE_REQ_ADDRESS ; 60 sc_signal<Ticache_type_t > ** out_ICACHE_REQ_TYPE ; 61 62 sc_signal<Tcontrol_t > ** in_ICACHE_RSP_VAL ; 63 sc_signal<Tcontrol_t > ** out_ICACHE_RSP_ACK ; 64 sc_signal<Tcontext_t > ** in_ICACHE_RSP_THREAD_ID ; 65 sc_signal<Tpacket_t > ** in_ICACHE_RSP_PACKET_ID ; 66 sc_signal<Ticache_instruction_t> *** in_ICACHE_RSP_INSTRUCTION ; 67 sc_signal<Ticache_error_t > ** in_ICACHE_RSP_ERROR ; 68 69 sc_signal<Tcontrol_t > ** out_DCACHE_REQ_VAL ; 70 sc_signal<Tcontrol_t > ** in_DCACHE_REQ_ACK ; 71 sc_signal<Tcontext_t > ** out_DCACHE_REQ_THREAD_ID ; 72 sc_signal<Tpacket_t > ** out_DCACHE_REQ_PACKET_ID ; 73 sc_signal<Tdcache_address_t > ** out_DCACHE_REQ_ADDRESS ; 74 sc_signal<Tdcache_data_t > ** out_DCACHE_REQ_WDATA ; 75 sc_signal<Tdcache_type_t > ** out_DCACHE_REQ_TYPE ; 76 77 sc_signal<Tcontrol_t > ** in_DCACHE_RSP_VAL ; 78 sc_signal<Tcontrol_t > ** out_DCACHE_RSP_ACK ; 79 sc_signal<Tcontext_t > ** in_DCACHE_RSP_THREAD_ID ; 80 sc_signal<Tpacket_t > ** in_DCACHE_RSP_PACKET_ID ; 81 sc_signal<Tdcache_data_t > ** in_DCACHE_RSP_RDATA ; 82 sc_signal<Tdcache_error_t > ** in_DCACHE_RSP_ERROR ; 83 84 sc_signal<Tcontrol_t > ** in_INTERRUPT_ENABLE ; 54 85 55 86 ALLOC1_SC_SIGNAL(out_ICACHE_REQ_VAL ,"out_ICACHE_REQ_VAL ",Tcontrol_t ,_param->_nb_icache_port); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/include/Parameters.h
r115 r117 135 135 public : uint32_t _nb_ooo_engine ; 136 136 public : uint32_t * _nb_rename_unit ;//[nb_ooo_engine] 137 public : uint32_t * _nb_inst_issue ;//[nb_ooo_engine] 137 public : uint32_t * _nb_inst_issue_queue ;//[nb_ooo_engine] 138 public : uint32_t * _nb_inst_issue_slot ;//[nb_ooo_engine] 138 139 public : uint32_t * _nb_inst_reexecute ;//[nb_ooo_engine] 139 140 public : uint32_t * _nb_inst_commit ;//[nb_ooo_engine] … … 148 149 public : multi_ooo_engine::ooo_engine::issue_queue::Tissue_queue_scheme_t 149 150 * _issue_queue_scheme ;//[nb_ooo_engine] 151 public : bool * _issue_queue_in_order ;//[nb_ooo_engine] 150 152 public : uint32_t * _nb_issue_queue_bank ;//[nb_ooo_engine] 151 153 public : Tpriority_t * _issue_priority ;//[nb_ooo_engine] … … 179 181 public : uint32_t * _link_decod_bloc_with_thread ;//[nb_thread] 180 182 public : uint32_t * _link_rename_bloc_with_front_end ;//[nb_front_end] 181 public : bool *** _table_dispatch ;//[nb_ooo_engine][nb_inst_issue ][nb_read_bloc]183 public : bool *** _table_dispatch ;//[nb_ooo_engine][nb_inst_issue_slot][nb_read_bloc] 182 184 public : bool ** _link_read_bloc_and_load_store_unit ;//[nb_read_bloc][nb_load_store_unit] 183 185 public : bool ** _link_read_bloc_and_functionnal_unit ;//[nb_read_bloc][nb_functionnal_unit] … … 251 253 public : uint32_t ** _ooo_engine_nb_reg_free ;//[nb_ooo_engine][nb_rename_unit] 252 254 public : uint32_t ** _ooo_engine_nb_rename_unit_bank ;//[nb_ooo_engine][nb_rename_unit] 253 // 254 public : bool *** _ooo_engine_table_routing ;//[nb_ooo_engine][nb_rename_unit][nb_inst_issue]255 public : bool *** _ooo_engine_table_issue_type ;//[nb_ooo_engine][nb_inst_issue][nb_type]255 //public : uint32_t ** _ooo_engine_size_read_counter ;//[nb_ooo_engine][nb_rename_unit] 256 //public : bool *** _ooo_engine_table_routing ;//[nb_ooo_engine][nb_rename_unit][nb_inst_issue_slot] 257 //public : bool *** _ooo_engine_table_issue_type ;//[nb_ooo_engine][nb_inst_issue_slot][nb_type] 256 258 public : uint32_t ** _ooo_engine_nb_load_store_unit ;//[nb_ooo_engine][nb_rename_unit] 257 259 public : uint32_t *** _ooo_engine_size_store_queue ;//[nb_ooo_engine][nb_rename_unit][ooo_engine_nb_load_store_unit] … … 331 333 332 334 333 public : bool **** _network_table_dispatch ;//[nb_ooo_engine][nb_inst_issue][nb_execute_loop][nb_read_unit] 335 public : bool **** _network_table_dispatch ;//[nb_ooo_engine][nb_inst_issue_slot][nb_execute_loop][nb_read_unit] 336 public : bool *** _network_table_issue_type ;// [nb_execute_loop][nb_read_unit][nb_type] 334 337 335 338 … … 450 453 uint32_t nb_ooo_engine , 451 454 uint32_t * nb_rename_unit ,//[nb_ooo_engine] 452 uint32_t * nb_inst_issue 455 uint32_t * nb_inst_issue_slot ,//[nb_ooo_engine] 453 456 uint32_t * nb_inst_reexecute ,//[nb_ooo_engine] 454 457 uint32_t * nb_inst_commit ,//[nb_ooo_engine] … … 494 497 uint32_t * link_decod_bloc_with_thread ,//[nb_thread] 495 498 uint32_t * link_rename_bloc_with_front_end ,//[nb_front_end] 496 bool *** table_dispatch ,//[nb_ooo_engine][nb_inst_issue ][nb_read_bloc]499 bool *** table_dispatch ,//[nb_ooo_engine][nb_inst_issue_slot][nb_read_bloc] 497 500 bool ** link_read_bloc_and_load_store_unit ,//[nb_read_bloc][nb_load_store_unit] 498 501 bool ** link_read_bloc_and_functionnal_unit ,//[nb_read_bloc][nb_functionnal_unit] -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Core_allocation.cpp
r112 r117 701 701 702 702 // ~~~~~[ Interface : "issue" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 703 for (uint32_t j=0; j<_param->_nb_inst_issue [i]; ++j)703 for (uint32_t j=0; j<_param->_nb_inst_issue_queue [i]; ++j) 704 704 { 705 705 dest = _name+"_glue"; … … 1210 1210 if (_param->_have_port_dcache_thread_id) 1211 1211 COMPONENT_MAP(_component,src , "in_LSQ_REQ_" +toString(i)+"_"+toString(j)+"_"+toString(k)+"_THREAD_ID", 1212 dest,"out_DCACHE_REQ_" +toString(j)+"_"+toString(k)+"_ THREAD_ID");1212 dest,"out_DCACHE_REQ_" +toString(j)+"_"+toString(k)+"_CONTEXT_ID"); 1213 1213 if (_param->_have_port_dcache_packet_id) 1214 1214 COMPONENT_MAP(_component,src , "in_LSQ_REQ_" +toString(i)+"_"+toString(j)+"_"+toString(k)+"_PACKET_ID", … … 1239 1239 if (_param->_have_port_dcache_thread_id) 1240 1240 COMPONENT_MAP(_component,src ,"out_LSQ_RSP_" +toString(i)+"_"+toString(j)+"_"+toString(k)+"_THREAD_ID", 1241 dest, "in_DCACHE_RSP_" +toString(j)+"_"+toString(k)+"_ THREAD_ID");1241 dest, "in_DCACHE_RSP_" +toString(j)+"_"+toString(k)+"_CONTEXT_ID"); 1242 1242 if (_param->_have_port_dcache_packet_id) 1243 1243 COMPONENT_MAP(_component,src ,"out_LSQ_RSP_" +toString(i)+"_"+toString(j)+"_"+toString(k)+"_PACKET_ID", -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Parameters.cpp
r115 r117 107 107 uint32_t * nb_reg_free ,//[nb_rename_bloc] 108 108 uint32_t * nb_rename_unit_bank ,//[nb_rename_bloc] 109 // 109 //uint32_t * size_read_counter ,//[nb_rename_bloc] 110 110 111 111 // Read bloc … … 173 173 uint32_t nb_ooo_engine , 174 174 uint32_t * nb_rename_unit ,//[nb_ooo_engine] 175 uint32_t * nb_inst_issue 175 uint32_t * nb_inst_issue_slot ,//[nb_ooo_engine] 176 176 uint32_t * nb_inst_reexecute ,//[nb_ooo_engine] 177 177 uint32_t * nb_inst_commit ,//[nb_ooo_engine] … … 217 217 uint32_t * link_decod_bloc_with_thread ,//[nb_thread] 218 218 uint32_t * link_rename_bloc_with_front_end ,//[nb_front_end] 219 bool *** table_dispatch ,//[nb_ooo_engine][nb_inst_issue ][nb_read_bloc]219 bool *** table_dispatch ,//[nb_ooo_engine][nb_inst_issue_slot][nb_read_bloc] 220 220 bool ** link_read_bloc_and_load_store_unit ,//[nb_read_bloc][nb_load_store_unit] 221 221 bool ** link_read_bloc_and_functionnal_unit ,//[nb_read_bloc][nb_functionnal_unit] … … 319 319 _nb_ooo_engine = nb_ooo_engine ; 320 320 _nb_rename_unit = nb_rename_unit ; 321 _nb_inst_issue = nb_inst_issue;321 _nb_inst_issue_slot = nb_inst_issue_slot ; 322 322 _nb_inst_reexecute = nb_inst_reexecute ; 323 323 _nb_inst_commit = nb_inst_commit ; … … 868 868 for (uint32_t i=0; i<_nb_ooo_engine; ++i) 869 869 { 870 for (uint32_t j=0; j<_nb_inst_issue [i]; ++j)870 for (uint32_t j=0; j<_nb_inst_issue_slot[i]; ++j) 871 871 for (uint32_t k=0; k<_nb_read_bloc; ++k) 872 872 { … … 1003 1003 } 1004 1004 1005 ALLOC4(_network_table_dispatch ,bool ,_nb_ooo_engine,_nb_inst_issue [it1],_nb_execute_loop,_nb_read_unit[it3]);1006 ALLOC3(_ooo_engine_table_routing ,bool ,_nb_ooo_engine,_nb_rename_unit[it1],_nb_inst_issue[it1]);1007 ALLOC3(_ooo_engine_table_issue_type ,bool ,_nb_ooo_engine,_nb_inst_issue[it1],_nb_type);1005 ALLOC4(_network_table_dispatch ,bool ,_nb_ooo_engine,_nb_inst_issue_slot[it1],_nb_execute_loop,_nb_read_unit[it3]); 1006 // ALLOC3(_ooo_engine_table_routing ,bool ,_nb_ooo_engine,_nb_rename_unit[it1],_nb_inst_issue_slot[it1]); 1007 // ALLOC3(_ooo_engine_table_issue_type ,bool ,_nb_ooo_engine,_nb_inst_issue_slot[it1],_nb_type); 1008 1008 ALLOC2(_list_functionnal_unit_with_rename_unit ,std::vector<uint32_t>,_nb_ooo_engine,_nb_rename_unit[it1]); 1009 1009 ALLOC2(_list_load_store_unit_with_rename_unit ,std::vector<uint32_t>,_nb_ooo_engine,_nb_rename_unit[it1]); … … 1011 1011 for (uint32_t i=0; i<_nb_ooo_engine; ++i) 1012 1012 { 1013 log_printf(TRACE,Core,FUNCTION,_(" * ooo_engine_table_issue_type [%d]"),i); 1014 1013 // log_printf(TRACE,Core,FUNCTION,_(" * ooo_engine_table_issue_type [%d]"),i); 1015 1014 1016 1015 // Init 1017 for (uint32_t j=0; j<_nb_inst_issue [i]; ++j)1016 for (uint32_t j=0; j<_nb_inst_issue_slot[i]; ++j) 1018 1017 { 1019 1018 for (uint32_t k=0; k<_nb_execute_loop; ++k) 1020 1019 for (uint32_t l=0; l<_nb_read_unit[k]; ++l) 1021 1020 _network_table_dispatch [i][j][k][l] = false; 1022 for (uint32_t k=0; k<_nb_rename_unit[i]; ++k)1023 _ooo_engine_table_routing [i][k][j] = false;1024 for (uint32_t k=0; k<_nb_type; ++k)1025 _ooo_engine_table_issue_type [i][j][k] = false;1021 // for (uint32_t k=0; k<_nb_rename_unit[i]; ++k) 1022 // _ooo_engine_table_routing [i][k][j] = false; 1023 // for (uint32_t k=0; k<_nb_type; ++k) 1024 // _ooo_engine_table_issue_type [i][j][k] = false; 1026 1025 } 1027 1026 1028 std::vector<uint32_t> list_thread_with_inst_issue [_nb_inst_issue [i]];1027 std::vector<uint32_t> list_thread_with_inst_issue [_nb_inst_issue_slot[i]]; 1029 1028 1030 for (uint32_t j=0; j<_nb_inst_issue [i]; ++j)1029 for (uint32_t j=0; j<_nb_inst_issue_slot[i]; ++j) 1031 1030 { 1032 1031 for (uint32_t k=0; k<_nb_read_bloc; ++k) … … 1044 1043 { 1045 1044 // Scan timing table, test if have an instruction 1046 for (uint32_t m=0; m<_nb_type; ++m)1047 for (uint32_t n=0; n<_nb_operation; ++n)1048 if (_timing[l][m][n]._latence > 0)1049 {1050 log_printf(TRACE,Core,FUNCTION,_(" [%d][%d] -> true"),j,m);1045 // for (uint32_t m=0; m<_nb_type; ++m) 1046 // for (uint32_t n=0; n<_nb_operation; ++n) 1047 // if (_timing[l][m][n]._latence > 0) 1048 // { 1049 // log_printf(TRACE,Core,FUNCTION,_(" [%d][%d] -> true"),j,m); 1051 1050 1052 _ooo_engine_table_issue_type [i][j][m] = true;1053 break;1054 }1051 // _ooo_engine_table_issue_type [i][j][m] = true; 1052 // break; 1053 // } 1055 1054 1056 1055 for (uint32_t m=0; m<_nb_thread; ++m) … … 1073 1072 if (_link_read_bloc_and_load_store_unit [k][l]) 1074 1073 { 1075 1074 // _ooo_engine_table_issue_type [i][j][TYPE_MEMORY] = true; 1076 1075 // _ooo_engine_table_issue_type [i][j][instruction_information(INSTRUCTION_L_LBS)._type] |= (_timing[l][instruction_information(INSTRUCTION_L_LBS)._type][instruction_information(INSTRUCTION_L_LBS)._operation]._latence > 0); 1077 1076 // _ooo_engine_table_issue_type [i][j][instruction_information(INSTRUCTION_L_LBZ)._type] |= (_timing[l][instruction_information(INSTRUCTION_L_LBZ)._type][instruction_information(INSTRUCTION_L_LBZ)._operation]._latence > 0); … … 1131 1130 } 1132 1131 1133 uint32_t num_rename_bloc = _link_rename_bloc_with_rename_unit[i][j];1134 1135 for (uint32_t k=0; k<_nb_front_end; ++k)1136 // test if this front_end is connected with this rename_bloc1137 if (_link_rename_bloc_with_front_end[k] == num_rename_bloc)1138 // the front end is connected with rename_bloc. Now test all slot issue that it can accepted this front_end1139 for (uint32_t l=0; l<_nb_inst_issue[i]; ++l)1140 for (std::vector<uint32_t>::iterator it = list_thread_with_inst_issue [l].begin();1141 it != list_thread_with_inst_issue [l].end();1142 ++it)1143 // Test if the this is in front_end [k]1144 if (_link_context_with_thread[*it].first == k)1145 {1146 _ooo_engine_table_routing [i][j][l] |= true;1147 log_printf(TRACE,Core,FUNCTION,_(" [%d][%d] -> true"),j,l);1148 }1132 // uint32_t num_rename_bloc = _link_rename_bloc_with_rename_unit[i][j]; 1133 1134 // for (uint32_t k=0; k<_nb_front_end; ++k) 1135 // // test if this front_end is connected with this rename_bloc 1136 // if (_link_rename_bloc_with_front_end[k] == num_rename_bloc) 1137 // // the front end is connected with rename_bloc. Now test all slot issue that it can accepted this front_end 1138 // for (uint32_t l=0; l<_nb_inst_issue_slot[i]; ++l) 1139 // for (std::vector<uint32_t>::iterator it = list_thread_with_inst_issue [l].begin(); 1140 // it != list_thread_with_inst_issue [l].end(); 1141 // ++it) 1142 // // Test if the this is in front_end [k] 1143 // if (_link_context_with_thread[*it].first == k) 1144 // { 1145 // _ooo_engine_table_routing [i][j][l] |= true; 1146 // log_printf(TRACE,Core,FUNCTION,_(" [%d][%d] -> true"),j,l); 1147 // } 1149 1148 } 1150 1149 } 1151 1150 1152 log_printf(TRACE,Core,FUNCTION,_(" * network_table_dispatch [nb_ooo_engine][nb_inst_issue][nb_execute_loop][nb_read_unit]"));1151 log_printf(TRACE,Core,FUNCTION,_(" * network_table_dispatch [nb_ooo_engine][nb_inst_issue_slot][nb_execute_loop][nb_read_unit]")); 1153 1152 for (uint32_t i=0; i<_nb_ooo_engine; ++i) 1154 for (uint32_t j=0; j<_nb_inst_issue [i]; ++j)1153 for (uint32_t j=0; j<_nb_inst_issue_slot[i]; ++j) 1155 1154 for (uint32_t k=0; k<_nb_execute_loop; ++k) 1156 1155 for (uint32_t l=0; l<_nb_read_unit[k]; ++l) 1157 1156 if (_network_table_dispatch [i][j][k][l] == true) 1158 1157 log_printf(TRACE,Core,FUNCTION,_(" Issue Slot [%d][%d] is connected with Read_unit [%d][%d]"),i,j,k,l); 1158 1159 ALLOC3(_network_table_issue_type,bool,_nb_execute_loop,_nb_read_unit[it1],_nb_type); 1160 1161 log_printf(TRACE,Core,FUNCTION,_(" * network_table_issue_type")); 1162 for (uint32_t i=0; i<_nb_execute_loop; ++i) 1163 for (uint32_t j=0; j<_nb_read_unit[i]; ++j) 1164 { 1165 // init 1166 for (uint32_t t=0; t<_nb_type; ++t) 1167 _network_table_issue_type [i][j][t] = false; 1168 1169 // get number of read bloc 1170 uint32_t num_read_bloc = _link_read_bloc_with_read_unit[i][j]; 1171 1172 // for each functionnal unit : test if the read bloc is connected with the functionnal unit 1173 for (uint32_t k=0; k<_nb_functionnal_unit; ++k) 1174 if (_link_read_bloc_and_functionnal_unit [num_read_bloc][k]) 1175 // Scan timing table, test if have an instruction 1176 for (uint32_t t=0; t<_nb_type; ++t) 1177 for (uint32_t o=0; o<_nb_operation; ++o) 1178 if (_timing[k][t][o]._latence > 0) 1179 { 1180 log_printf(TRACE,Core,FUNCTION,_(" [%d][%d][%d] -> true"),i,j,t); 1181 1182 _network_table_issue_type [i][j][t] = true; 1183 break; // operation 1184 } 1185 1186 // Test load store unit connected with this read bloc 1187 for (uint32_t k=0; k<_nb_load_store_unit; ++k) 1188 // Test load store unit connected with this read bloc 1189 if (_link_read_bloc_and_load_store_unit [num_read_bloc][k]) 1190 { 1191 uint32_t t = TYPE_MEMORY; 1192 1193 log_printf(TRACE,Core,FUNCTION,_(" [%d][%d][%d] -> true"),i,j,t); 1194 1195 _network_table_issue_type [i][j][t] = true; 1196 break; // load_store_unit 1197 } 1198 } 1159 1199 1160 1200 ALLOC2(_ooo_engine_nb_load_store_unit ,uint32_t ,_nb_ooo_engine,_nb_rename_unit[it1]); … … 1787 1827 } 1788 1828 1829 ALLOC1(_issue_queue_in_order,bool,_nb_ooo_engine); 1830 for (uint32_t i=0; i<_nb_ooo_engine; ++i) 1831 _issue_queue_in_order [i] = (_issue_queue_scheme [i] == core::multi_ooo_engine::ooo_engine::issue_queue::ISSUE_QUEUE_SCHEME_IN_ORDER); 1832 1789 1833 // parameters depends 1790 1834 _size_ooo_engine_id = log2(_nb_ooo_engine); … … 1838 1882 for (uint32_t i=0; i<_nb_front_end; ++i) 1839 1883 _param_front_end [i]= new core::multi_front_end::front_end::Parameters 1840 (1884 ( 1841 1885 _nb_context [i], 1842 1886 _nb_decod_unit [i], … … 1877 1921 ); 1878 1922 1923 ALLOC1(_nb_inst_issue_queue,uint32_t,_nb_ooo_engine); 1924 1879 1925 _param_ooo_engine = new core::multi_ooo_engine::ooo_engine::Parameters * [_nb_ooo_engine]; 1880 1926 1881 1927 for (uint32_t i=0; i<_nb_ooo_engine; ++i) 1928 { 1882 1929 _param_ooo_engine [i] = new core::multi_ooo_engine::ooo_engine::Parameters 1883 1930 ( … … 1889 1936 _ooo_engine_nb_inst_insert [i], 1890 1937 _ooo_engine_nb_inst_retire [i], 1891 _nb_inst_issue [i],1938 // _nb_inst_issue [i], 1892 1939 _ooo_engine_nb_inst_execute [i], 1893 1940 _nb_inst_reexecute [i], … … 1910 1957 _issue_priority [i], 1911 1958 _issue_load_balancing [i], 1912 _ooo_engine_table_routing [i],1913 _ooo_engine_table_issue_type [i],1959 // _ooo_engine_table_routing [i], 1960 // _ooo_engine_table_issue_type [i], 1914 1961 _size_reexecute_queue [i], 1915 1962 _reexecute_priority [i], … … 1922 1969 _ooo_engine_nb_reg_free [i], 1923 1970 _ooo_engine_nb_rename_unit_bank [i], 1924 // 1971 // _ooo_engine_size_read_counter [i], 1925 1972 _ooo_engine_nb_load_store_unit [i], 1926 1973 _ooo_engine_size_store_queue [i], … … 1932 1979 _ooo_engine_translate_num_context_to_num_thread[i] 1933 1980 ); 1981 _nb_inst_issue_queue [i] = _param_ooo_engine [i]->_nb_inst_issue; 1982 } 1934 1983 1935 1984 _param_execute_loop = new core::multi_execute_loop::execute_loop::Parameters * [_nb_execute_loop]; … … 2045 2094 _nb_inst_branch_complete ,//[nb_ooo_engine] 2046 2095 _ooo_engine_nb_inst_insert_rob ,//[nb_ooo_engine] 2047 _nb_inst_issue ,//[nb_ooo_engine] 2096 _nb_inst_reexecute ,//[nb_ooo_engine] 2097 _nb_inst_issue_queue ,//[nb_ooo_engine] 2098 _nb_inst_issue_slot ,//[nb_ooo_engine] 2048 2099 _ooo_engine_nb_inst_execute ,//[nb_ooo_engine][ooo_engine_nb_execute_loop] 2100 _issue_queue_in_order ,//[nb_ooo_engine] 2049 2101 _nb_read_unit ,//[nb_execute_loop] 2050 2102 _nb_write_unit ,//[nb_execute_loop] … … 2059 2111 _dispatch_priority , 2060 2112 _dispatch_load_balancing , 2061 _network_table_dispatch ,//[nb_ooo_engine][nb_inst_issue][nb_execute_loop][nb_read_unit] 2113 _network_table_dispatch ,//[nb_ooo_engine][nb_inst_issue_slot][nb_execute_loop][nb_read_unit] 2114 _network_table_issue_type ,// [nb_execute_loop][nb_read_unit][nb_type] 2062 2115 _translate_ooo_engine_num_front_end ,//[nb_ooo_engine][ooo_engine_nb_front_end] 2063 2116 _translate_ooo_engine_num_execute_loop,//[nb_ooo_engine][ooo_engine_nb_execute_loop] 2064 _translate_execute_loop_num_ooo_engine // *[nb_execute_loop][execute_loop_nb_ooo_engine]2117 _translate_execute_loop_num_ooo_engine //[nb_execute_loop][execute_loop_nb_ooo_engine] 2065 2118 ); 2066 2119 … … 2146 2199 DELETE2(_list_load_store_unit_with_rename_unit ,_nb_ooo_engine,_nb_rename_unit[it1]); 2147 2200 DELETE2(_list_functionnal_unit_with_rename_unit ,_nb_ooo_engine,_nb_rename_unit[it1]); 2148 DELETE3(_ooo_engine_table_issue_type ,_nb_ooo_engine,_nb_inst_issue[it1],_nb_type); 2149 DELETE3(_ooo_engine_table_routing ,_nb_ooo_engine,_nb_rename_unit[it1],_nb_inst_issue[it1]); 2150 DELETE4(_network_table_dispatch ,_nb_ooo_engine,_nb_inst_issue[it1],_nb_execute_loop,_nb_read_unit[it3]); 2151 // DELETE2(_ooo_engine_size_read_counter ,_nb_ooo_engine,_nb_rename_unit[it1]); 2201 // DELETE3(_ooo_engine_table_issue_type ,_nb_ooo_engine,_nb_inst_issue_slot[it1],_nb_type); 2202 // DELETE3(_ooo_engine_table_routing ,_nb_ooo_engine,_nb_rename_unit[it1],_nb_inst_issue_slot[it1]); 2203 DELETE3(_network_table_issue_type ,_nb_execute_loop,_nb_read_unit[it1],_nb_type); 2204 DELETE4(_network_table_dispatch ,_nb_ooo_engine,_nb_inst_issue_slot[it1],_nb_execute_loop,_nb_read_unit[it3]); 2205 // DELETE2(_ooo_engine_size_read_counter ,_nb_ooo_engine,_nb_rename_unit[it1]); 2152 2206 DELETE2(_ooo_engine_nb_rename_unit_bank ,_nb_ooo_engine,_nb_rename_unit[it1]); 2153 2207 DELETE2(_ooo_engine_nb_reg_free ,_nb_ooo_engine,_nb_rename_unit[it1]); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Parameters_msg_error.cpp
r109 r117 206 206 { 207 207 // initialisation 208 uint32_t nb_link_slot [_nb_ooo_engine][max<uint32_t>(_nb_inst_issue ,_nb_ooo_engine)];208 uint32_t nb_link_slot [_nb_ooo_engine][max<uint32_t>(_nb_inst_issue_slot,_nb_ooo_engine)]; 209 209 uint32_t nb_link_read_bloc [_nb_read_bloc]; 210 210 211 211 // initialisation 212 212 for (uint32_t i=0; i<_nb_ooo_engine; ++i) 213 for (uint32_t j=0; j<_nb_inst_issue [i]; ++j)213 for (uint32_t j=0; j<_nb_inst_issue_slot[i]; ++j) 214 214 nb_link_slot [i][j] = 0; 215 215 for (uint32_t i=0; i<_nb_read_bloc; ++i) … … 218 218 // set link 219 219 for (uint32_t i=0; i<_nb_ooo_engine; ++i) 220 for (uint32_t j=0; j<_nb_inst_issue [i]; ++j)220 for (uint32_t j=0; j<_nb_inst_issue_slot[i]; ++j) 221 221 for (uint32_t k=0; k<_nb_read_bloc; ++k) 222 222 if (_table_dispatch [i][j][k]) … … 228 228 // test 229 229 for (uint32_t i=0; i<_nb_ooo_engine; ++i) 230 for (uint32_t j=0; j<_nb_inst_issue [i]; ++j)230 for (uint32_t j=0; j<_nb_inst_issue_slot[i]; ++j) 231 231 if (nb_link_slot [i][j] == 0) 232 232 test.error(toString(_("In Out Of Order Engine [%d], the slot issue [%d] is not link with a read_bloc.\n"),i,j)); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Parameters_print.cpp
r112 r117 173 173 str+= toString(MSG_INFORMATION)+" * OOO_ENGINE ["+toString<uint32_t>(i)+"]\n"; 174 174 str+= toString(MSG_INFORMATION)+" * nb_rename_unit : "+toString<uint32_t >(_nb_rename_unit [i])+"\n"; 175 str+= toString(MSG_INFORMATION)+" * nb_inst_issue : "+toString<uint32_t >(_nb_inst_issue [i])+"\n"; 175 str+= toString(MSG_INFORMATION)+" * nb_inst_issue_queue : "+toString<uint32_t >(_nb_inst_issue_queue [i])+"\n"; 176 str+= toString(MSG_INFORMATION)+" * nb_inst_issue_slot : "+toString<uint32_t >(_nb_inst_issue_slot [i])+"\n"; 176 177 str+= toString(MSG_INFORMATION)+" * nb_inst_reexecute : "+toString<uint32_t >(_nb_inst_reexecute [i])+"\n"; 177 178 str+= toString(MSG_INFORMATION)+" * nb_inst_commit : "+toString<uint32_t >(_nb_inst_commit [i])+"\n"; … … 261 262 262 263 for (uint32_t i=0; i<_nb_ooo_engine; ++i) 263 for (uint32_t j=0; j<_nb_inst_issue [i]; ++j)264 for (uint32_t j=0; j<_nb_inst_issue_slot[i]; ++j) 264 265 for (uint32_t k=0; k<_nb_read_bloc; ++k) 265 266 str+= toString(MSG_INFORMATION)+" * table_dispatch ["+toString(i)+"]["+toString(j)+"]["+toString(k)+"] : "+toString(_table_dispatch [i][j][k])+"\n";//[nb_ooo_engine][nb_inst_issue][nb_read_bloc] -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/SelfTest/src/main.cpp
r115 r117 25 25 delete my_top; 26 26 27 delete param;28 27 } 29 28 catch (morpheo::ErrorMorpheo & error) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.Common
r113 r117 22 22 endif 23 23 24 ##-----[ Entity ]-------------------------------------------25 #ENTITY = $$($(BASENAME) $$PWD)26 27 24 #-----[ Directory ]---------------------------------------- 28 #DIR_TMP = .29 25 DIR_TMP = $(MORPHEO_TMP) 30 26 DIR_INC = include … … 35 31 36 32 #-----[ Compilation ]-------------------------------------- 37 INCDIR = $(SYSTEMC_INCDIR_$(SIMULATOR )) \33 INCDIR = $(SYSTEMC_INCDIR_$(SIMULATOR_SYSTEMC)) \ 38 34 -I. \ 39 35 -I$(DIR_MORPHEO) 40 36 41 37 LIBDIR = -L$(DIR_LIB) \ 42 $(SYSTEMC_LIBDIR_$(SIMULATOR ))38 $(SYSTEMC_LIBDIR_$(SIMULATOR_SYSTEMC)) 43 39 # $(OR1K_LIBDIR) 44 40 45 FLAGS_COMMON = $(SYSTEMC_CFLAGS_$(SIMULATOR )) \41 FLAGS_COMMON = $(SYSTEMC_CFLAGS_$(SIMULATOR_SYSTEMC)) \ 46 42 $(CXX_FLAGS) 47 43 … … 62 58 @$(ECHO) "-------------------| $(ENTITY)" 63 59 64 test :65 @echo $(DIR_LIBRARY);66 67 60 $(DIR_OBJ)/$(ENTITY)_%.o : $(DIR_SRC)/%.cpp $(HEADERS) 68 61 @\ 69 62 $(ECHO) "Compilation : $*";\ 70 $(SYSTEMC_CXX_$(SIMULATOR )) $(CFLAGS) -c -o $@ $<;63 $(SYSTEMC_CXX_$(SIMULATOR_SYSTEMC)) $(CFLAGS) -c -o $@ $<; 71 64 72 65 $(DIR_OBJ) : -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.Component
r113 r117 18 18 $(DIR_LIB)/%.a : $(SOURCES) $(HEADERS) 19 19 @\ 20 case "${SIMULATOR }" in \20 case "${SIMULATOR_SYSTEMC}" in \ 21 21 "modelsim") \ 22 22 $(MODELTECH_VLIB) $@; \ … … 25 25 *) \ 26 26 $(MAKE) $(OBJECTS); \ 27 $(ECHO) "Archive : $*"; \ 28 $(AR) -r $@ $(OBJECTS); \ 29 $(RANLIB) $@; \ 27 if $(TEST) $$? -eq 0; then \ 28 $(ECHO) "Archive : $*"; \ 29 $(AR) -r $@ $(OBJECTS); \ 30 $(RANLIB) $@; \ 31 fi; \ 30 32 ;; \ 31 33 esac; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.Selftest
r115 r117 19 19 OBJECTS = $(OBJECTS_COMMON) 20 20 21 LIBS = -lm $(SYSTEMC_LIBNAME_$(SIMULATOR ))21 LIBS = -lm $(SYSTEMC_LIBNAME_$(SIMULATOR_SYSTEMC)) 22 22 # $(OR1K_LIBNAME) -lbfd 23 23 … … 27 27 EXEC_PREFIX = 28 28 #$(VALGRIND) 29 EXEC_PARAMS = $(SYSTEMC_EXEC_PARAMS_$(SIMULATOR ))29 EXEC_PARAMS = $(SYSTEMC_EXEC_PARAMS_$(SIMULATOR_SYSTEMC)) 30 30 EXEC_LOG = $(patsubst $(DIR_CFG_GEN)/%.cfg,$(DIR_LOG)/%.exec.log,$(wildcard $(DIR_CFG_GEN)/*.cfg)) \ 31 31 $(patsubst $(DIR_CFG_USER)/%.cfg,$(DIR_LOG)/%.exec.log,$(wildcard $(DIR_CFG_USER)/*.cfg)) … … 35 35 .PRECIOUS : $(DIR_BIN)/%.x $(DIR_LOG)/%.exec.log 36 36 #.NOTPARALLEL : clean clean_all help 37 38 vpath %.cfg $(DIR_CFG_USER):$(DIR_CFG_GEN) 39 vpath %.x $(DIR_BIN) 37 40 38 41 all_selftest : test_env $(DIR_OBJ) $(DIR_BIN) $(DIR_LOG) … … 168 171 done; 169 172 170 $(DIR_LOG)/%.exec.log : $(DIR_CFG_GEN)/%.cfg $(DIR_BIN)/$(EXEC).x173 $(DIR_LOG)/%.exec.log : %.cfg $(EXEC).x 171 174 @\ 172 175 $(ECHO) "Execute : $*";\ 173 export SYSTEMC=$(SYSTEMC_$(SIMULATOR )); $(EXEC_PREFIX) $(DIR_BIN)/$(EXEC).x $(EXEC_PARAMS) $* `$(CAT) $<` &> $@; \176 export SYSTEMC=$(SYSTEMC_$(SIMULATOR_SYSTEMC)); $(EXEC_PREFIX) $(DIR_BIN)/$(EXEC).x $(EXEC_PARAMS) $* `$(CAT) $<` &> $@; \ 174 177 declare timing=`$(GREP) -h "Timing" $@`; \ 175 178 $(GREP) -q "Timing" $@; \ … … 189 192 fi; 190 193 191 $(DIR_LOG)/%.exec.log : $(DIR_CFG_USER)/%.cfg $(DIR_BIN)/$(EXEC).x192 @\193 $(ECHO) "Execute : $*";\194 export SYSTEMC=$(SYSTEMC_$(SIMULATOR)); $(EXEC_PREFIX) $(DIR_BIN)/$(EXEC).x $(EXEC_PARAMS) $* `$(CAT) $<` &> $@; \195 declare timing=`$(GREP) -h "Timing" $@`; \196 $(GREP) -q "Timing" $@; \197 declare -i test_timing=$$?; \198 $(GREP) -q "Test OK" $@; \199 declare -i test_ok=$$?; \200 $(GREP) -q "Test KO" $@; \201 declare -i test_ko=$$?; \202 if $(TEST) $$test_ko -ne 0 -a $$test_ok -eq 0 -a $$test_timing -eq 0; \203 then $(ECHO) -e " $* ... OK\t$$timing";\204 else $(ECHO) " $* ... KO"; \205 fi;206 207 194 $(DIR_BIN)/%.x : $(SOURCES) $(HEADERS) $(DIR_OBJ) $(DIR_BIN) 208 195 @\ 209 196 $(ECHO) "Linkage : $*";\ 210 case "${SIMULATOR }" in \197 case "${SIMULATOR_SYSTEMC}" in \ 211 198 "modelsim") \ 212 199 $(MAKE) vhdl_package; \ … … 226 213 *) \ 227 214 $(MAKE) $(OBJECTS); \ 228 $(SYSTEMC_CXX_$(SIMULATOR )) $(LFLAGS) -o $@ $(OBJECTS) $(LIBRARY) $(LIBS);\215 $(SYSTEMC_CXX_$(SIMULATOR_SYSTEMC)) $(LFLAGS) -o $@ $(OBJECTS) $(LIBRARY) $(LIBS);\ 229 216 ;; \ 230 217 esac; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.Synthesis
r116 r117 11 11 DIR_VHDL = . 12 12 WORK_NAME = work 13 DIR_WORK = $( MORPHEO_TMP)/$(WORK_NAME)13 DIR_WORK = $(DIR_TMP)/$(WORK_NAME) 14 14 15 15 FPGA_CFG_FILE_LOCAL = mkf.info … … 95 95 $(XILINX_ENV); $(MAKE) -f Makefile.mkf $*.ngc &> $@; 96 96 97 $(DIR_WORK) : $(XILINX_CORELIB)97 $(DIR_WORK) : 98 98 @\ 99 99 $(ECHO) "Create work-space : $@"; \ 100 mkdir -p $@; \ 100 101 $(MODELTECH_VLIB) $@; \ 101 102 $(MODELTECH_VMAP) $(XILINX_LIBNAME) $(XILINX_LIBDIR); \ … … 104 105 $(ECHO) "Run manualy \"$(XILINX_COMPXLIB)\" with $(XILINX_CORELIB) directory"; \ 105 106 fi; 106 107 $(XILINX_CORELIB) :108 @\109 $(ECHO) "Create Corelib : $@"; \110 $(MODELTECH_ENV); $(XILINX_COMPXLIB)111 112 # $(MODELTECH_ENV); $(XILINX_COMPXLIB) -s mti_se -arch all -lib all -l vhdl -dir $(XILINX_CORELIB) -w -p $(MODELTECH_BIN) -smartmodel_setup113 114 107 115 108 $(DIR_LOG)/%.sim.log : $(DIR_VHDL)/%.vhdl $(DIR_LOG)/%.vhdl.log -
trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Constants.h
r116 r117 39 39 typedef enum 40 40 { 41 TYPE_ALU = 0x0, // 00000 - unit multiple 42 TYPE_SHIFT = 0x1, // 00001 - unit multiple 43 TYPE_MOVE = 0x2, // 00010 - unit multiple 44 TYPE_TEST = 0x3, // 00011 - unit multiple 45 TYPE_MUL = 0x4, // 00100 - unit multiple 46 TYPE_DIV = 0x5, // 00101 - unit multiple, type optionnal 47 TYPE_EXTEND = 0x6, // 00110 - unit multiple, type optionnal 48 TYPE_FIND = 0x7, // 00111 - unit multiple, type optionnal 49 TYPE_SPECIAL = 0x8, // 01000 - unit uniq 50 TYPE_CUSTOM = 0x9, // 01001 - unit uniq , type optionnal 51 TYPE_BRANCH = 0xa, // 01010 - unit multiple 52 TYPE_MEMORY = 0xb // 01011 - unit uniq 41 TYPE_ALU = 0x0, // 0000 - unit multiple 42 TYPE_SHIFT = 0x1, // 0000 - unit multiple 43 TYPE_MOVE = 0x2, // 0000 - unit multiple 44 TYPE_TEST = 0x3, // 0000 - unit multiple 45 TYPE_MUL = 0x4, // 0000 - unit multiple 46 TYPE_DIV = 0x5, // 0000 - unit multiple, type optionnal 47 TYPE_EXTEND = 0x6, // 0000 - unit multiple, type optionnal 48 TYPE_FIND = 0x7, // 0000 - unit multiple, type optionnal 49 TYPE_SPECIAL = 0x8, // 0000 - unit uniq 50 TYPE_CUSTOM = 0x9, // 0000 - unit uniq , type optionnal 51 TYPE_BRANCH = 0xa, // 0000 - unit multiple 52 TYPE_MEMORY = 0xb, // 0000 - unit uniq , type exclusive 53 TYPE_INVALID = 0xf // 1111 - none 53 54 } type_t; 54 55 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Parameters.h
r113 r117 113 113 114 114 public : uint32_t _size_store_queue_ptr ; 115 //public : bool _have_port_store_queue_ptr ; // always true (min = 1)115 public : bool _have_port_store_queue_ptr ; // always true (min = 1) 116 116 117 117 public : uint32_t _size_general_data ; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Version.h
r116 r117 10 10 #define MORPHEO_MAJOR_VERSION "0" 11 11 #define MORPHEO_MINOR_VERSION "2" 12 #define MORPHEO_REVISION "11 6"12 #define MORPHEO_REVISION "117" 13 13 #define MORPHEO_CODENAME "Castor" 14 14 15 #define MORPHEO_DATE_DAY " 30"16 #define MORPHEO_DATE_MONTH "0 4"15 #define MORPHEO_DATE_DAY "16" 16 #define MORPHEO_DATE_MONTH "05" 17 17 #define MORPHEO_DATE_YEAR "2009" 18 18 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Parameters.cpp
r113 r117 2 2 * $Id$ 3 3 * 4 * [ 4 * [ Description ] 5 5 * 6 6 */ -
trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Parameters_copy.cpp
r88 r117 58 58 59 59 param->_size_store_queue_ptr = _size_store_queue_ptr ; 60 //param->_have_port_store_queue_ptr = _have_port_store_queue_ptr ; // always true (min = 1)60 param->_have_port_store_queue_ptr = _have_port_store_queue_ptr ; // always true (min = 1) 61 61 62 62 param->_size_general_data = _size_general_data ; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/src/SPR_access_mode_implement_group.cpp
r97 r117 32 32 _spr_generic [GROUP_SYSTEM_AND_CONTROL ][ 20]._user_access_mode = SPR_ACCESS_MODE_READ_ONLY_COND; 33 33 _spr_generic [GROUP_SYSTEM_AND_CONTROL ][ 20]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE; 34 35 // new register : CID, TID, TSR 36 _spr_generic [GROUP_SYSTEM_AND_CONTROL ][ 21]._user_access_mode = SPR_ACCESS_MODE_READ_ONLY; 37 _spr_generic [GROUP_SYSTEM_AND_CONTROL ][ 21]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE; 38 _spr_generic [GROUP_SYSTEM_AND_CONTROL ][ 22]._user_access_mode = SPR_ACCESS_MODE_READ_ONLY; 39 _spr_generic [GROUP_SYSTEM_AND_CONTROL ][ 22]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE; 40 _spr_generic [GROUP_SYSTEM_AND_CONTROL ][ 23]._user_access_mode = SPR_ACCESS_MODE_READ_ONLY; 41 _spr_generic [GROUP_SYSTEM_AND_CONTROL ][ 23]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE; 34 42 35 43 const uint32_t nb_shadow = 1; // max 16 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Simulation_test_end.cpp
r113 r117 15 15 bool simulation_test_end (void) 16 16 { 17 msg ("##########[ cycle %d ]\n",static_cast<uint32_t>(simulation_cycle()));17 msgInformation("##########[ cycle %.0f ]\n",static_cast<double>(simulation_cycle())); 18 18 19 19 // Test if a stop condition is activate -
trunk/IPs/systemC/processor/Morpheo/Common/include/ErrorMorpheo.h
r88 r117 22 22 class ErrorMorpheo : public std::exception 23 23 { 24 // -----[ 24 // -----[ fields ]---------------------------------------------------- 25 25 private : std::string _msg; 26 26 27 // -----[ 27 // -----[ methods ]--------------------------------------------------- 28 28 public : ErrorMorpheo () throw() {_msg = toString("%s ",MSG_ERROR); _msg+="Exception detected ...";} 29 29 public : ErrorMorpheo (std::string msg) throw() {_msg = toString("%s ",MSG_ERROR); _msg+=msg;} … … 34 34 { 35 35 #ifdef DEBUG 36 _msg = toString(_("%s <%s> at line %d, in file %s : %s"),MSG_ERROR,funcname.c_str(),line,file.c_str(),msg.c_str()); 36 _msg = toString(_("\n%s at line %d, in file %s"),MSG_ERROR,line,file.c_str()); 37 _msg = toString(_("\n%s <%s> %s"),MSG_ERROR,funcname.c_str(),msg.c_str()); 37 38 #else 38 _msg = toString(_(" %s %s"),MSG_ERROR,msg.c_str());39 _msg = toString(_("\n%s %s"),MSG_ERROR,msg.c_str()); 39 40 #endif 40 41 } … … 44 45 }; 45 46 46 class TestMorpheo : public std::exception47 {48 // -----[ fields ]----------------------------------------------------49 private : std::string _msg;47 // class TestMorpheo : public std::exception 48 // { 49 // // -----[ fields ]---------------------------------------------------- 50 // private : std::string _msg; 50 51 51 // -----[ methods ]---------------------------------------------------52 public : TestMorpheo () throw() {_msg=_("Test error ...");}53 public : TestMorpheo (std::string msg) throw() {_msg=msg;}54 public : ~TestMorpheo (void) throw() {}55 public : const char* what () const throw() { return ( _msg.c_str() );}56 };52 // // -----[ methods ]--------------------------------------------------- 53 // public : TestMorpheo () throw() {_msg=_("Test error ...");} 54 // public : TestMorpheo (std::string msg) throw() {_msg=msg;} 55 // public : ~TestMorpheo (void) throw() {} 56 // public : const char* what () const throw() { return ( _msg.c_str() );} 57 // }; 57 58 58 59 }; // end namespace morpheo -
trunk/IPs/systemC/processor/Morpheo/Common/src/MemCheck.cpp
r115 r117 14 14 15 15 // Global flags set by macros in MemCheck.h 16 bool traceFlag = true;16 bool traceFlag = false; 17 17 bool activeFlag = false; 18 18 … … 137 137 void operator delete(void* p) 138 138 { 139 memMap_it it = findPtr(p);139 bool can_free = true; 140 140 141 if ( it != memMap.end())141 if (activeFlag) 142 142 { 143 memMap_it it = findPtr(p); 144 145 if (it != memMap.end()) 146 { 147 // this pointer is previously allocated 148 delPtr(p); 149 150 } 151 else 152 { 153 // this pointer is not previously allocated 154 155 can_free = false; 156 msgError("Attempt to delete unknown pointer: %p\n", p); 157 } 158 } 159 160 161 if (can_free) 162 { 163 if(traceFlag) 164 msgInformation("Deleted memory at address %p\n", p); 165 143 166 free(p); 144 delPtr(p);145 146 if(traceFlag)147 msgInformation("Deleted memory at address %p\n", p);148 167 } 149 else150 if(!p && activeFlag)151 msgError("Attempt to delete unknown pointer: %p\n", p);152 168 } 153 169 -
trunk/IPs/systemC/processor/Morpheo/Files/Instance_x1_w1_0.cfg
r115 r117 74 74 75 75 <front_end id="0"> 76 <parameter name="nb_context" value="1" /> 76 77 <parameter name="nb_decod_unit" value="1" /> 77 78 <parameter name="nb_inst_branch_predict" value="1" /> … … 156 157 <parameter name="dcache_port_load_balancing" value="1" /> 157 158 159 <link name="link_context_with_thread" src="0" dest="0.0" /> 158 160 <link name="link_decod_unit_with_decod_bloc" src="0" dest="0.0" /> 159 161 <link name="link_rename_unit_with_rename_bloc" src="0" dest="0.0" /> -
trunk/IPs/systemC/processor/Morpheo/Files/Instance_x1_w1_1.cfg
r112 r117 1 1 <?xml version="1.0" encoding="ISO-8859-1" ?> 2 2 3 <core name="Instance_ scalar_1">3 <core name="Instance_x1_w1_1"> 4 4 5 5 <thread id="0"> … … 17 17 <decod_bloc id="0"> 18 18 <parameter name="size_decod_queue" value="2" /> 19 <parameter name="decod_queue_scheme" value="0" /> 19 20 <parameter name="nb_inst_decod" value="1" /> 20 21 <parameter name="nb_context_select" value="1" /> … … 30 31 <parameter name="rename_select_nb_front_end_select" value="1" /> 31 32 <parameter name="nb_general_register" value="64"/> 32 <parameter name="nb_special_register" value=" 4" />33 <parameter name="nb_special_register" value="16" /> 33 34 <parameter name="nb_reg_free" value="1" /> 34 35 <parameter name="nb_rename_unit_bank" value="1" /> … … 61 62 <parameter name="nb_inst_functionnal_unit" value="1" /> 62 63 63 <timing type="0" latence="1" delay="1" /> 64 <timing type="0" latence="1" delay="1" /> 65 <timing type="1" latence="1" delay="1" /> 66 <timing type="2" latence="1" delay="1" /> 67 <timing type="3" latence="1" delay="1" /> 68 <timing type="4" latence="1" delay="1" /> 69 <timing type="6" latence="1" delay="1" /> 70 <timing type="7" latence="1" delay="1" /> 71 <timing type="8" latence="1" delay="1" /> 72 <timing type="10" latence="1" delay="1" /> 64 73 </functionnal_unit> 65 74 66 75 <front_end id="0"> 76 <parameter name="nb_context" value="1" /> 67 77 <parameter name="nb_decod_unit" value="1" /> 68 78 <parameter name="nb_inst_branch_predict" value="1" /> … … 74 84 <parameter name="btb_victim_scheme" value="1" /> 75 85 <parameter name="dir_predictor_scheme" value="1" /> 86 87 <predictor id="0"> 88 <parameter name="dir_have_bht" value="0" /> 89 <parameter name="dir_have_pht" value="0" /> 90 </predictor> 91 92 <predictor id="1"> 93 <parameter name="dir_have_bht" value="0" /> 94 <parameter name="dir_have_pht" value="0" /> 95 </predictor> 96 97 <predictor id="2"> 98 <parameter name="dir_have_bht" value="0" /> 99 <parameter name="dir_have_pht" value="0" /> 100 </predictor> 76 101 </front_end> 77 102 … … 90 115 <parameter name="size_issue_queue" value="4" /> 91 116 <parameter name="nb_issue_queue_bank" value="1" /> 117 <parameter name="issue_queue_scheme" value="0" /> 92 118 <parameter name="issue_priority" value="1" /> 93 119 <parameter name="issue_load_balancing" value="1" /> … … 101 127 <parameter name="nb_write_unit" value="1" /> 102 128 <parameter name="nb_gpr_bank" value="1" /> 103 <parameter name="nb_gpr_port_read_by_bank" value=" 1" />129 <parameter name="nb_gpr_port_read_by_bank" value="2" /> 104 130 <parameter name="nb_gpr_port_write_by_bank" value="1" /> 105 131 <parameter name="nb_spr_bank" value="1" /> … … 131 157 <parameter name="dcache_port_load_balancing" value="1" /> 132 158 159 <link name="link_context_with_thread" src="0" dest="0.0" /> 133 160 <link name="link_decod_unit_with_decod_bloc" src="0" dest="0.0" /> 134 161 <link name="link_rename_unit_with_rename_bloc" src="0" dest="0.0" /> -
trunk/IPs/systemC/processor/Morpheo/Files/Instance_x1_w1_2.cfg
r112 r117 1 1 <?xml version="1.0" encoding="ISO-8859-1" ?> 2 2 3 <core name="Instance_ scalar_2">3 <core name="Instance_x1_w1_2"> 4 4 5 5 <thread id="0"> … … 17 17 <decod_bloc id="0"> 18 18 <parameter name="size_decod_queue" value="4" /> 19 <parameter name="decod_queue_scheme" value="0" /> 19 20 <parameter name="nb_inst_decod" value="1" /> 20 21 <parameter name="nb_context_select" value="1" /> … … 30 31 <parameter name="rename_select_nb_front_end_select" value="1" /> 31 32 <parameter name="nb_general_register" value="64"/> 32 <parameter name="nb_special_register" value=" 4" />33 <parameter name="nb_special_register" value="16" /> 33 34 <parameter name="nb_reg_free" value="1" /> 34 35 <parameter name="nb_rename_unit_bank" value="1" /> … … 61 62 <parameter name="nb_inst_functionnal_unit" value="1" /> 62 63 63 <timing type="0" latence="1" delay="1" /> 64 <timing type="0" latence="1" delay="1" /> 65 <timing type="1" latence="1" delay="1" /> 66 <timing type="2" latence="1" delay="1" /> 67 <timing type="3" latence="1" delay="1" /> 68 <timing type="4" latence="1" delay="1" /> 69 <timing type="6" latence="1" delay="1" /> 70 <timing type="7" latence="1" delay="1" /> 71 <timing type="8" latence="1" delay="1" /> 72 <timing type="10" latence="1" delay="1" /> 64 73 </functionnal_unit> 65 74 66 75 <front_end id="0"> 76 <parameter name="nb_context" value="1" /> 67 77 <parameter name="nb_decod_unit" value="1" /> 68 78 <parameter name="nb_inst_branch_predict" value="1" /> … … 74 84 <parameter name="btb_victim_scheme" value="3" /> 75 85 <parameter name="dir_predictor_scheme" value="1" /> 86 87 <predictor id="0"> 88 <parameter name="dir_have_bht" value="0" /> 89 <parameter name="dir_have_pht" value="0" /> 90 </predictor> 91 92 <predictor id="1"> 93 <parameter name="dir_have_bht" value="0" /> 94 <parameter name="dir_have_pht" value="0" /> 95 </predictor> 96 97 <predictor id="2"> 98 <parameter name="dir_have_bht" value="0" /> 99 <parameter name="dir_have_pht" value="0" /> 100 </predictor> 76 101 </front_end> 77 102 … … 90 115 <parameter name="size_issue_queue" value="8" /> 91 116 <parameter name="nb_issue_queue_bank" value="2" /> 117 <parameter name="issue_queue_scheme" value="0" /> 92 118 <parameter name="issue_priority" value="1" /> 93 119 <parameter name="issue_load_balancing" value="1" /> … … 100 126 <parameter name="nb_read_unit" value="1" /> 101 127 <parameter name="nb_write_unit" value="1" /> 102 <parameter name="nb_gpr_bank" value=" 2" />103 <parameter name="nb_gpr_port_read_by_bank" value=" 1" />128 <parameter name="nb_gpr_bank" value="1" /> 129 <parameter name="nb_gpr_port_read_by_bank" value="2" /> 104 130 <parameter name="nb_gpr_port_write_by_bank" value="1" /> 105 131 <parameter name="nb_spr_bank" value="2" /> … … 131 157 <parameter name="dcache_port_load_balancing" value="1" /> 132 158 159 <link name="link_context_with_thread" src="0" dest="0.0" /> 133 160 <link name="link_decod_unit_with_decod_bloc" src="0" dest="0.0" /> 134 161 <link name="link_rename_unit_with_rename_bloc" src="0" dest="0.0" /> -
trunk/IPs/systemC/processor/Morpheo/Files/Instance_x1_w1_3.cfg
r112 r117 1 1 <?xml version="1.0" encoding="ISO-8859-1" ?> 2 2 3 <core name="Instance_ scalar_2">3 <core name="Instance_x1_w1_3"> 4 4 5 5 <thread id="0"> … … 17 17 <decod_bloc id="0"> 18 18 <parameter name="size_decod_queue" value="4" /> 19 <parameter name="decod_queue_scheme" value="0" /> 19 20 <parameter name="nb_inst_decod" value="1" /> 20 21 <parameter name="nb_context_select" value="1" /> … … 30 31 <parameter name="rename_select_nb_front_end_select" value="1" /> 31 32 <parameter name="nb_general_register" value="64"/> 32 <parameter name="nb_special_register" value=" 4" />33 <parameter name="nb_special_register" value="16" /> 33 34 <parameter name="nb_reg_free" value="1" /> 34 35 <parameter name="nb_rename_unit_bank" value="1" /> 35 36 </rename_bloc> 36 37 37 <read_bloc id="0"> 38 <parameter name="size_read_queue" value="4" /> 39 <parameter name="size_reservation_station" value="4" /> 40 <parameter name="nb_inst_retire_reservation_station" value="1" /> 41 </read_bloc> 42 43 <read_bloc id="1"> 38 <read_bloc id="0,1"> 44 39 <parameter name="size_read_queue" value="4" /> 45 40 <parameter name="size_reservation_station" value="4" /> … … 47 42 </read_bloc> 48 43 49 <write_bloc id="0"> 50 <parameter name="size_write_queue" value="4" /> 51 <parameter name="size_execute_queue" value="4" /> 52 <parameter name="nb_bypass_write" value="0" /> 53 </write_bloc> 54 55 <write_bloc id="1"> 44 <write_bloc id="0,1"> 56 45 <parameter name="size_write_queue" value="4" /> 57 46 <parameter name="size_execute_queue" value="4" /> … … 73 62 <parameter name="nb_inst_functionnal_unit" value="1" /> 74 63 75 <timing type="0" latence="1" delay="1" /> 64 <timing type="0" latence="1" delay="1" /> 65 <timing type="1" latence="1" delay="1" /> 66 <timing type="2" latence="1" delay="1" /> 67 <timing type="3" latence="1" delay="1" /> 68 <timing type="4" latence="1" delay="1" /> 69 <timing type="6" latence="1" delay="1" /> 70 <timing type="7" latence="1" delay="1" /> 71 <timing type="8" latence="1" delay="1" /> 72 <timing type="10" latence="1" delay="1" /> 76 73 </functionnal_unit> 77 74 78 75 <front_end id="0"> 76 <parameter name="nb_context" value="1" /> 79 77 <parameter name="nb_decod_unit" value="1" /> 80 78 <parameter name="nb_inst_branch_predict" value="1" /> … … 86 84 <parameter name="btb_victim_scheme" value="3" /> 87 85 <parameter name="dir_predictor_scheme" value="1" /> 86 87 <predictor id="0"> 88 <parameter name="dir_have_bht" value="0" /> 89 <parameter name="dir_have_pht" value="0" /> 90 </predictor> 91 92 <predictor id="1"> 93 <parameter name="dir_have_bht" value="0" /> 94 <parameter name="dir_have_pht" value="0" /> 95 </predictor> 96 97 <predictor id="2"> 98 <parameter name="dir_have_bht" value="0" /> 99 <parameter name="dir_have_pht" value="0" /> 100 </predictor> 88 101 </front_end> 89 102 … … 102 115 <parameter name="size_issue_queue" value="8" /> 103 116 <parameter name="nb_issue_queue_bank" value="2" /> 117 <parameter name="issue_queue_scheme" value="0" /> 104 118 <parameter name="issue_priority" value="1" /> 105 119 <parameter name="issue_load_balancing" value="1" /> … … 110 124 111 125 <execute_loop id="0"> 112 <parameter name="nb_read_unit" value=" 1" />113 <parameter name="nb_write_unit" value=" 1" />126 <parameter name="nb_read_unit" value="2" /> 127 <parameter name="nb_write_unit" value="2" /> 114 128 <parameter name="nb_gpr_bank" value="2" /> 115 <parameter name="nb_gpr_port_read_by_bank" value=" 1" />129 <parameter name="nb_gpr_port_read_by_bank" value="2" /> 116 130 <parameter name="nb_gpr_port_write_by_bank" value="1" /> 117 131 <parameter name="nb_spr_bank" value="2" /> … … 143 157 <parameter name="dcache_port_load_balancing" value="1" /> 144 158 159 <link name="link_context_with_thread" src="0" dest="0.0" /> 145 160 <link name="link_decod_unit_with_decod_bloc" src="0" dest="0.0" /> 146 161 <link name="link_rename_unit_with_rename_bloc" src="0" dest="0.0" /> … … 157 172 158 173 <link name="table_dispatch" src="0.0.0" dest="1" /> 159 <link name="link_read_bloc_and_load_store_unit" src="0.0" dest="0" /> 160 <link name="link_read_bloc_and_load_store_unit" src="1.0" dest="1" /> 161 <link name="link_read_bloc_and_functionnal_unit" src="0.0" dest="1" /> 162 <link name="link_read_bloc_and_functionnal_unit" src="1.0" dest="0" /> 163 <link name="link_write_bloc_and_load_store_unit" src="0.0" dest="0" /> 174 <link name="table_dispatch" src="0.0.1" dest="1" /> 175 176 <link name="link_read_bloc_and_load_store_unit" src="0.0" dest="1" /> 177 <link name="link_read_bloc_and_load_store_unit" src="1.0" dest="0" /> 178 <link name="link_read_bloc_and_functionnal_unit" src="0.0" dest="0" /> 179 <link name="link_read_bloc_and_functionnal_unit" src="1.0" dest="1" /> 180 181 <link name="link_write_bloc_and_load_store_unit" src="0.0" dest="1" /> 164 182 <link name="link_write_bloc_and_load_store_unit" src="1.0" dest="1" /> 165 <link name="link_write_bloc_and_functionnal_unit" src="0.0" dest=" 0" />183 <link name="link_write_bloc_and_functionnal_unit" src="0.0" dest="1" /> 166 184 <link name="link_write_bloc_and_functionnal_unit" src="1.0" dest="1" /> 185 167 186 <link name="link_thread_and_functionnal_unit" src="0.0" dest="1" /> 168 187 -
trunk/IPs/systemC/processor/Morpheo/Files/Instance_x1_w1_4.cfg
r112 r117 1 1 <?xml version="1.0" encoding="ISO-8859-1" ?> 2 2 3 <core name="Instance_ scalar_2">3 <core name="Instance_x1_w1_4"> 4 4 5 5 <thread id="0"> … … 17 17 <decod_bloc id="0"> 18 18 <parameter name="size_decod_queue" value="4" /> 19 <parameter name="decod_queue_scheme" value="0" /> 19 20 <parameter name="nb_inst_decod" value="1" /> 20 21 <parameter name="nb_context_select" value="1" /> … … 30 31 <parameter name="rename_select_nb_front_end_select" value="1" /> 31 32 <parameter name="nb_general_register" value="64"/> 32 <parameter name="nb_special_register" value=" 4" />33 <parameter name="nb_special_register" value="16" /> 33 34 <parameter name="nb_reg_free" value="1" /> 34 35 <parameter name="nb_rename_unit_bank" value="1" /> 35 36 </rename_bloc> 36 37 37 <read_bloc id="0 ">38 <read_bloc id="0,1,2"> 38 39 <parameter name="size_read_queue" value="4" /> 39 40 <parameter name="size_reservation_station" value="4" /> 40 41 <parameter name="nb_inst_retire_reservation_station" value="1" /> 41 42 </read_bloc> 42 43 <read_bloc id="1"> 44 <parameter name="size_read_queue" value="4" /> 45 <parameter name="size_reservation_station" value="4" /> 46 <parameter name="nb_inst_retire_reservation_station" value="1" /> 47 </read_bloc> 48 49 <write_bloc id="0"> 50 <parameter name="size_write_queue" value="4" /> 51 <parameter name="size_execute_queue" value="4" /> 52 <parameter name="nb_bypass_write" value="0" /> 53 </write_bloc> 54 55 <write_bloc id="1"> 43 44 <write_bloc id="0,1,2"> 56 45 <parameter name="size_write_queue" value="4" /> 57 46 <parameter name="size_execute_queue" value="4" /> … … 72 61 <functionnal_unit id="0"> 73 62 <parameter name="nb_inst_functionnal_unit" value="1" /> 63 64 <timing type="0" latence="1" delay="1" /> 65 <timing type="1" latence="1" delay="1" /> 66 <timing type="2" latence="1" delay="1" /> 67 <timing type="3" latence="1" delay="1" /> 68 <timing type="4" latence="1" delay="1" /> 69 <timing type="6" latence="1" delay="1" /> 70 <timing type="7" latence="1" delay="1" /> 71 <timing type="8" latence="1" delay="1" /> 72 <timing type="10" latence="1" delay="1" /> 74 73 </functionnal_unit> 75 74 76 75 <functionnal_unit id="1"> 77 76 <parameter name="nb_inst_functionnal_unit" value="1" /> 77 78 <timing type="0" latence="1" delay="1" /> 79 <timing type="1" latence="1" delay="1" /> 80 <timing type="2" latence="1" delay="1" /> 81 <timing type="3" latence="1" delay="1" /> 82 <timing type="4" latence="1" delay="1" /> 83 <timing type="6" latence="1" delay="1" /> 84 <timing type="7" latence="1" delay="1" /> 85 86 <timing type="10" latence="1" delay="1" /> 78 87 </functionnal_unit> 79 88 80 89 <front_end id="0"> 90 <parameter name="nb_context" value="1" /> 81 91 <parameter name="nb_decod_unit" value="1" /> 82 92 <parameter name="nb_inst_branch_predict" value="1" /> … … 99 109 <parameter name="nb_execute_loop_select" value="1" /> 100 110 <parameter name="size_re_order_buffer" value="32"/> 101 <parameter name="nb_re_order_buffer_bank" value=" 2" />111 <parameter name="nb_re_order_buffer_bank" value="8" /> 102 112 <parameter name="commit_priority" value="1" /> 103 113 <parameter name="commit_load_balancing" value="1" /> 104 114 <parameter name="size_issue_queue" value="8" /> 105 115 <parameter name="nb_issue_queue_bank" value="2" /> 116 <parameter name="issue_queue_scheme" value="0" /> 106 117 <parameter name="issue_priority" value="1" /> 107 118 <parameter name="issue_load_balancing" value="1" /> … … 112 123 113 124 <execute_loop id="0"> 114 <parameter name="nb_read_unit" value=" 1" />115 <parameter name="nb_write_unit" value=" 1" />125 <parameter name="nb_read_unit" value="3" /> 126 <parameter name="nb_write_unit" value="3" /> 116 127 <parameter name="nb_gpr_bank" value="2" /> 117 <parameter name="nb_gpr_port_read_by_bank" value=" 1" />128 <parameter name="nb_gpr_port_read_by_bank" value="2" /> 118 129 <parameter name="nb_gpr_port_write_by_bank" value="1" /> 119 130 <parameter name="nb_spr_bank" value="2" /> … … 148 159 <parameter name="dcache_port_load_balancing" value="1" /> 149 160 161 <link name="link_context_with_thread" src="0" dest="0.0" /> 150 162 <link name="link_decod_unit_with_decod_bloc" src="0" dest="0.0" /> 151 163 <link name="link_rename_unit_with_rename_bloc" src="0" dest="0.0" /> 164 152 165 <link name="link_read_unit_with_read_bloc" src="0" dest="0.0" /> 153 166 <link name="link_read_unit_with_read_bloc" src="1" dest="0.1" /> 167 <link name="link_read_unit_with_read_bloc" src="2" dest="0.2" /> 154 168 <link name="link_write_unit_with_write_bloc" src="0" dest="0.0" /> 155 169 <link name="link_write_unit_with_write_bloc" src="1" dest="0.1" /> 170 <link name="link_write_unit_with_write_bloc" src="2" dest="0.2" /> 171 156 172 <link name="link_decod_bloc_with_thread" src="0" dest="0" /> 157 173 <link name="link_rename_bloc_with_front_end" src="0" dest="0" /> … … 162 178 163 179 <link name="table_dispatch" src="0.0.0" dest="1" /> 164 <link name="link_read_bloc_and_load_store_unit" src="0.0" dest="0" /> 165 <link name="link_read_bloc_and_load_store_unit" src="1.0" dest="1" /> 166 <link name="link_read_bloc_and_functionnal_unit" src="0.0" dest="1" /> 167 <link name="link_read_bloc_and_functionnal_unit" src="0.1" dest="1" /> 168 <link name="link_read_bloc_and_functionnal_unit" src="1.0" dest="0" /> 180 <link name="table_dispatch" src="0.0.1" dest="1" /> 181 <link name="table_dispatch" src="0.0.2" dest="1" /> 182 183 <link name="link_read_bloc_and_load_store_unit" src="0.0" dest="1" /> 184 <link name="link_read_bloc_and_load_store_unit" src="1.0" dest="0" /> 185 <link name="link_read_bloc_and_load_store_unit" src="2.0" dest="0" /> 186 187 <link name="link_read_bloc_and_functionnal_unit" src="0.0" dest="0" /> 188 <link name="link_read_bloc_and_functionnal_unit" src="0.1" dest="0" /> 189 <link name="link_read_bloc_and_functionnal_unit" src="1.0" dest="1" /> 169 190 <link name="link_read_bloc_and_functionnal_unit" src="1.1" dest="0" /> 170 <link name="link_write_bloc_and_load_store_unit" src="0.0" dest="0" /> 191 <link name="link_read_bloc_and_functionnal_unit" src="2.0" dest="0" /> 192 <link name="link_read_bloc_and_functionnal_unit" src="2.1" dest="1" /> 193 194 <link name="link_write_bloc_and_load_store_unit" src="0.0" dest="1" /> 171 195 <link name="link_write_bloc_and_load_store_unit" src="1.0" dest="1" /> 172 <link name="link_write_bloc_and_functionnal_unit" src="0.0" dest="0" /> 173 <link name="link_write_bloc_and_functionnal_unit" src="0.1" dest="0" /> 196 <link name="link_write_bloc_and_load_store_unit" src="2.0" dest="1" /> 197 <link name="link_write_bloc_and_functionnal_unit" src="0.0" dest="1" /> 198 <link name="link_write_bloc_and_functionnal_unit" src="0.1" dest="1" /> 174 199 <link name="link_write_bloc_and_functionnal_unit" src="1.0" dest="1" /> 175 200 <link name="link_write_bloc_and_functionnal_unit" src="1.1" dest="1" /> 201 <link name="link_write_bloc_and_functionnal_unit" src="2.0" dest="1" /> 202 <link name="link_write_bloc_and_functionnal_unit" src="2.1" dest="1" /> 203 176 204 <link name="link_thread_and_functionnal_unit" src="0.0" dest="1" /> 205 <link name="link_thread_and_functionnal_unit" src="0.1" dest="1" /> 177 206 178 207 </core> -
trunk/IPs/systemC/processor/Morpheo/Files/Instance_x1_w2_1.cfg
r112 r117 1 1 <?xml version="1.0" encoding="ISO-8859-1" ?> 2 2 3 <core name="Instance_ scalar_2">3 <core name="Instance_x1_w2_1"> 4 4 5 5 <thread id="0"> … … 17 17 <decod_bloc id="0"> 18 18 <parameter name="size_decod_queue" value="4" /> 19 <parameter name="decod_queue_scheme" value="0" /> 19 20 <parameter name="nb_inst_decod" value="2" /> 20 21 <parameter name="nb_context_select" value="1" /> … … 30 31 <parameter name="rename_select_nb_front_end_select" value="1" /> 31 32 <parameter name="nb_general_register" value="64"/> 32 <parameter name="nb_special_register" value=" 4"/>33 <parameter name="nb_special_register" value="16"/> 33 34 <parameter name="nb_reg_free" value="1" /> 34 <parameter name="nb_rename_unit_bank" value=" 1" />35 <parameter name="nb_rename_unit_bank" value="2" /> 35 36 </rename_bloc> 36 37 37 <read_bloc id="0 ">38 <read_bloc id="0,1,2"> 38 39 <parameter name="size_read_queue" value="4" /> 39 40 <parameter name="size_reservation_station" value="4" /> 40 <parameter name="nb_inst_retire_reservation_station" value=" 2" />41 <parameter name="nb_inst_retire_reservation_station" value="1" /> 41 42 </read_bloc> 42 43 <read_bloc id="1"> 44 <parameter name="size_read_queue" value="4" /> 45 <parameter name="size_reservation_station" value="4" /> 46 <parameter name="nb_inst_retire_reservation_station" value="2" /> 47 </read_bloc> 48 49 <write_bloc id="0"> 50 <parameter name="size_write_queue" value="4" /> 51 <parameter name="size_execute_queue" value="4" /> 52 <parameter name="nb_bypass_write" value="0" /> 53 </write_bloc> 54 55 <write_bloc id="1"> 43 44 <write_bloc id="0,1,2"> 56 45 <parameter name="size_write_queue" value="4" /> 57 46 <parameter name="size_execute_queue" value="4" /> … … 72 61 <functionnal_unit id="0"> 73 62 <parameter name="nb_inst_functionnal_unit" value="1" /> 63 64 <timing type="0" latence="1" delay="1" /> 65 <timing type="1" latence="1" delay="1" /> 66 <timing type="2" latence="1" delay="1" /> 67 <timing type="3" latence="1" delay="1" /> 68 <timing type="4" latence="1" delay="1" /> 69 <timing type="6" latence="1" delay="1" /> 70 <timing type="7" latence="1" delay="1" /> 71 72 <timing type="10" latence="1" delay="1" /> 74 73 </functionnal_unit> 75 74 76 75 <functionnal_unit id="1"> 77 76 <parameter name="nb_inst_functionnal_unit" value="1" /> 77 78 <timing type="0" latence="1" delay="1" /> 79 <timing type="1" latence="1" delay="1" /> 80 <timing type="2" latence="1" delay="1" /> 81 <timing type="3" latence="1" delay="1" /> 82 <timing type="4" latence="1" delay="1" /> 83 <timing type="6" latence="1" delay="1" /> 84 <timing type="7" latence="1" delay="1" /> 85 <timing type="8" latence="1" delay="1" /> 86 <timing type="10" latence="1" delay="1" /> 78 87 </functionnal_unit> 79 88 80 89 <front_end id="0"> 90 <parameter name="nb_context" value="1" /> 81 91 <parameter name="nb_decod_unit" value="1" /> 82 92 <parameter name="nb_inst_branch_predict" value="1" /> … … 87 97 <parameter name="btb_size_counter" value="2" /> 88 98 <parameter name="btb_victim_scheme" value="3" /> 89 <parameter name="dir_predictor_scheme" value=" 1" />99 <parameter name="dir_predictor_scheme" value="2" /> 90 100 </front_end> 91 101 … … 104 114 <parameter name="size_issue_queue" value="8" /> 105 115 <parameter name="nb_issue_queue_bank" value="2" /> 116 <parameter name="issue_queue_scheme" value="0" /> 106 117 <parameter name="issue_priority" value="1" /> 107 118 <parameter name="issue_load_balancing" value="1" /> … … 112 123 113 124 <execute_loop id="0"> 114 <parameter name="nb_read_unit" value=" 1" />115 <parameter name="nb_write_unit" value=" 1" />125 <parameter name="nb_read_unit" value="3" /> 126 <parameter name="nb_write_unit" value="3" /> 116 127 <parameter name="nb_gpr_bank" value="2" /> 117 <parameter name="nb_gpr_port_read_by_bank" value=" 1" />118 <parameter name="nb_gpr_port_write_by_bank" value=" 1" />128 <parameter name="nb_gpr_port_read_by_bank" value="2" /> 129 <parameter name="nb_gpr_port_write_by_bank" value="2" /> 119 130 <parameter name="nb_spr_bank" value="2" /> 120 <parameter name="nb_spr_port_read_by_bank" value=" 1" />121 <parameter name="nb_spr_port_write_by_bank" value=" 1" />131 <parameter name="nb_spr_port_read_by_bank" value="2" /> 132 <parameter name="nb_spr_port_write_by_bank" value="2" /> 122 133 <parameter name="execution_unit_to_write_unit_priority" value="1" /> 123 134 <parameter name="read_unit_to_execution_unit_priority" value="1" /> … … 148 159 <parameter name="dcache_port_load_balancing" value="1" /> 149 160 161 <link name="link_context_with_thread" src="0" dest="0.0" /> 150 162 <link name="link_decod_unit_with_decod_bloc" src="0" dest="0.0" /> 151 163 <link name="link_rename_unit_with_rename_bloc" src="0" dest="0.0" /> 164 152 165 <link name="link_read_unit_with_read_bloc" src="0" dest="0.0" /> 153 166 <link name="link_read_unit_with_read_bloc" src="1" dest="0.1" /> 167 <link name="link_read_unit_with_read_bloc" src="2" dest="0.2" /> 154 168 <link name="link_write_unit_with_write_bloc" src="0" dest="0.0" /> 155 169 <link name="link_write_unit_with_write_bloc" src="1" dest="0.1" /> 170 <link name="link_write_unit_with_write_bloc" src="2" dest="0.2" /> 171 156 172 <link name="link_decod_bloc_with_thread" src="0" dest="0" /> 157 173 <link name="link_rename_bloc_with_front_end" src="0" dest="0" /> … … 162 178 163 179 <link name="table_dispatch" src="0.0.0" dest="1" /> 164 <link name="link_read_bloc_and_load_store_unit" src="0.0" dest="0" /> 165 <link name="link_read_bloc_and_load_store_unit" src="1.0" dest="1" /> 166 <link name="link_read_bloc_and_functionnal_unit" src="0.0" dest="1" /> 167 <link name="link_read_bloc_and_functionnal_unit" src="0.1" dest="1" /> 168 <link name="link_read_bloc_and_functionnal_unit" src="1.0" dest="0" /> 180 <link name="table_dispatch" src="0.0.1" dest="1" /> 181 <link name="table_dispatch" src="0.0.2" dest="1" /> 182 <link name="table_dispatch" src="0.1.0" dest="1" /> 183 <link name="table_dispatch" src="0.1.1" dest="1" /> 184 <link name="table_dispatch" src="0.1.2" dest="1" /> 185 186 <link name="link_read_bloc_and_load_store_unit" src="0.0" dest="1" /> 187 <link name="link_read_bloc_and_load_store_unit" src="1.0" dest="0" /> 188 <link name="link_read_bloc_and_load_store_unit" src="2.0" dest="0" /> 189 190 <link name="link_read_bloc_and_functionnal_unit" src="0.0" dest="0" /> 191 <link name="link_read_bloc_and_functionnal_unit" src="0.1" dest="0" /> 192 <link name="link_read_bloc_and_functionnal_unit" src="1.0" dest="1" /> 169 193 <link name="link_read_bloc_and_functionnal_unit" src="1.1" dest="0" /> 170 <link name="link_write_bloc_and_load_store_unit" src="0.0" dest="0" /> 194 <link name="link_read_bloc_and_functionnal_unit" src="2.0" dest="0" /> 195 <link name="link_read_bloc_and_functionnal_unit" src="2.1" dest="1" /> 196 197 <link name="link_write_bloc_and_load_store_unit" src="0.0" dest="1" /> 171 198 <link name="link_write_bloc_and_load_store_unit" src="1.0" dest="1" /> 172 <link name="link_write_bloc_and_functionnal_unit" src="0.0" dest="0" /> 173 <link name="link_write_bloc_and_functionnal_unit" src="0.1" dest="0" /> 199 <link name="link_write_bloc_and_load_store_unit" src="2.0" dest="1" /> 200 <link name="link_write_bloc_and_functionnal_unit" src="0.0" dest="1" /> 201 <link name="link_write_bloc_and_functionnal_unit" src="0.1" dest="1" /> 174 202 <link name="link_write_bloc_and_functionnal_unit" src="1.0" dest="1" /> 175 203 <link name="link_write_bloc_and_functionnal_unit" src="1.1" dest="1" /> 204 <link name="link_write_bloc_and_functionnal_unit" src="2.0" dest="1" /> 205 <link name="link_write_bloc_and_functionnal_unit" src="2.1" dest="1" /> 206 176 207 <link name="link_thread_and_functionnal_unit" src="0.0" dest="1" /> 208 <link name="link_thread_and_functionnal_unit" src="0.1" dest="1" /> 177 209 178 210 </core> -
trunk/IPs/systemC/processor/Morpheo/Files/Instance_x1_w4_1.cfg
r114 r117 1 1 <?xml version="1.0" encoding="ISO-8859-1" ?> 2 2 3 <core name="Instance_ debug">3 <core name="Instance_x1_w4_1"> 4 4 5 5 <thread id="0"> … … 7 7 <parameter name="nb_inst_fetch" value="8" /> 8 8 <parameter name="ras_size_queue" value="8" /> 9 <parameter name="upt_size_queue" value=" 8" />9 <parameter name="upt_size_queue" value="4" /> 10 10 <parameter name="ufpt_size_queue" value="4" /> 11 11 … … 31 31 <parameter name="rename_select_nb_front_end_select" value="1" /> 32 32 <parameter name="nb_general_register" value="256"/> 33 <parameter name="nb_special_register" value="128" 33 <parameter name="nb_special_register" value="128"/> 34 34 <parameter name="nb_reg_free" value="8" /> 35 35 <parameter name="nb_rename_unit_bank" value="8" /> … … 79 79 80 80 <front_end id="0"> 81 <parameter name="nb_context" value="1" /> 81 82 <parameter name="nb_decod_unit" value="1" /> 82 83 <parameter name="nb_inst_branch_predict" value="1" /> … … 165 166 <parameter name="dcache_port_load_balancing" value="1" /> 166 167 168 <link name="link_context_with_thread" src="0" dest="0.0" /> 167 169 <link name="link_decod_unit_with_decod_bloc" src="0" dest="0.0" /> 168 170 <link name="link_rename_unit_with_rename_bloc" src="0" dest="0.0" /> … … 226 228 <link name="link_read_bloc_and_functionnal_unit" src="2.2" dest="0" /> 227 229 <link name="link_read_bloc_and_functionnal_unit" src="3.2" dest="1" /> 230 228 231 <link name="link_write_bloc_and_load_store_unit" src="0.0" dest="1" /> 229 232 <link name="link_write_bloc_and_load_store_unit" src="1.0" dest="1" /> -
trunk/IPs/systemC/processor/Morpheo/Files/Morpheo.gen
r115 r117 108 108 <parameter name="nb_read_unit" min="1" max="8" step="+ 1" default="1" level="..." description="..." /> 109 109 <parameter name="nb_execute_unit" min="1" max="8" step="+ 1" default="1" level="..." description="..." /> 110 <parameter name="nb_write_unit" min="1" max=" 8"step="+ 1" default="1" level="..." description="..." />110 <parameter name="nb_write_unit" min="1" max="16" step="+ 1" default="1" level="..." description="..." /> 111 111 <parameter name="nb_gpr_bank" min="1" max="8" step="* 2" default="1" level="..." description="..." /> 112 112 <parameter name="nb_gpr_port_read_by_bank" min="1" max="16" step="+ 1" default="1" level="..." description="..." /> -
trunk/IPs/systemC/processor/Morpheo/Files/Morpheo.sim
r115 r117 10 10 <parameter name="use_statistics" value="1" /> 11 11 <parameter name="use_information" value="0" /> 12 <parameter name="use_header" value=" 1" />12 <parameter name="use_header" value="0" /> 13 13 14 14 <parameter name="statistics_cycle_start" value="5" /> 15 15 <parameter name="statistics_period" value="0" /> 16 16 17 <<<<<<< .mine 18 <parameter name="simulation_nb_cycle" value="1000000" /> 19 ======= 20 <parameter name="simulation_nb_cycle" value="10000000"/> 21 >>>>>>> .r114 17 <parameter name="simulation_nb_cycle" value="1000000000"/> 22 18 <parameter name="simulation_nb_instruction" value="0" /> 23 19 … … 25 21 <parameter name="directory_vhdl" value="." /> 26 22 <parameter name="directory_position" value="." /> 27 <parameter name="directory_log" value=" ." />23 <parameter name="directory_log" value="/dsk/l1/misc/Morpheo/log/" /> 28 24 29 25 <parameter name="debug_level" value="0" /> 30 <<<<<<< .mine 31 <parameter name="debug_cycle_start" value="0" /> 32 <parameter name="debug_cycle_stop" value="2" /> 33 ======= 34 <parameter name="debug_cycle_start" value="600" /> 35 <parameter name="debug_cycle_stop" value="827" /> 36 >>>>>>> .r114 26 <parameter name="debug_cycle_start" value="4250" /> 27 <parameter name="debug_cycle_stop" value="4400" /> 37 28 <parameter name="debug_have_log_file" value="0" /> 38 <parameter name="debug_idle_cycle" value="100 "/>39 <parameter name="debug_idle_time" value=" 5"/>29 <parameter name="debug_idle_cycle" value="1000" /> 30 <parameter name="debug_idle_time" value="10" /> 40 31 41 32 <component name="Comparator" model="systemc" debug="0" /> -
trunk/IPs/systemC/processor/Morpheo/Script/instruction_flow_dump.sh
r114 r117 20 20 { 21 21 if test ${#} -ne 2; then 22 usage ${*}; 23 fi; 24 25 if test ! -f ${1} -o ! -f ${2}; then 22 26 usage ${*}; 23 27 fi;
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