- Timestamp:
- Jul 5, 2007, 5:50:19 PM (17 years ago)
- Location:
- trunk/IPs/systemC/processor/Morpheo
- Files:
-
- 40 added
- 31 deleted
- 140 edited
- 12 moved
Legend:
- Unmodified
- Added
- Removed
-
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/SelfTest/src/test.cpp
r2 r42 43 43 *********************************************************************/ 44 44 sc_clock CLOCK ("clock", 1.0, 0.5); 45 sc_signal<Tcontrol_t> RESET; 45 46 sc_signal<Tdata_t> DATA_IN [param._nb_port]; 46 47 sc_signal<Tcontrol_t> ADDSUB [param._nb_port]; … … 53 54 cout << "<" << name << "> Instanciation of _Counter" << endl; 54 55 55 #if defined(STATISTICS) or defined(VHDL_TESTBENCH)56 56 (*(_Counter->in_CLOCK)) (CLOCK); 57 #endif 57 (*(_Counter->in_NRESET)) (RESET); 58 58 59 59 for (uint32_t i=0; i<param._nb_port; i++) … … 79 79 80 80 sc_start(0); 81 _Counter->vhdl_testbench_label("Initialisation"); 81 82 RESET.write(1); 83 82 84 cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} Initialisation" << endl; 83 85 84 _Counter->vhdl_testbench_label("Loop of Test");85 86 cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} Loop of Test" << endl; 86 87 87 88 for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++) 88 89 { 89 _Counter->vhdl_testbench_label("Iteration "+toString(iteration));90 90 cout << "{" << static_cast<uint32_t>(sc_simulation_time()) << "} Itération " << iteration << endl; 91 91 for (uint32_t i=0; i<param._nb_port; i++) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/include/Counter.h
r2 r42 25 25 #include "Behavioural/include/Vhdl.h" 26 26 #endif 27 #ifdef VHDL_TESTBENCH 28 #include "Behavioural/include/Vhdl_Testbench.h" 29 #endif 27 #include "Behavioural/include/Component.h" 30 28 31 29 using namespace std; 32 30 33 namespace morpheo 31 namespace morpheo { 34 32 namespace behavioural { 35 33 namespace generic { 36 34 namespace counter { 37 38 35 39 36 class Counter … … 55 52 #endif 56 53 57 #ifdef VHDL_TESTBENCH 58 private : Vhdl_Testbench * _vhdl_testbench; 59 #endif 54 public : Component * _component; 55 private : Interfaces * _interfaces; 60 56 61 57 #ifdef SYSTEMC … … 63 59 // Interface 64 60 public : SC_CLOCK * in_CLOCK ; 65 61 public : SC_IN (Tcontrol_t) * in_NRESET ; 66 62 public : SC_IN (Tdata_t) ** in_COUNTER_DATA ; 67 63 public : SC_IN (Tcontrol_t) ** in_COUNTER_ADDSUB ; … … 107 103 #if VHDL 108 104 public : void vhdl (void); 109 private : void vhdl_port (Vhdl & vhdl);110 private : void vhdl_declaration (Vhdl & vhdl);111 private : void vhdl_body (Vhdl & vhdl);105 private : void vhdl_port (Vhdl * & vhdl); 106 private : void vhdl_declaration (Vhdl * & vhdl); 107 private : void vhdl_body (Vhdl * & vhdl); 112 108 #endif 113 109 114 110 #ifdef VHDL_TESTBENCH 115 private : void vhdl_testbench_port (void);116 111 private : void vhdl_testbench_transition (void); 117 112 #endif 118 public : void vhdl_testbench_label (string label);119 113 }; 120 114 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Counter.cpp
r2 r42 31 31 log_printf(FUNC,Counter,"Counter","Begin"); 32 32 33 #ifdef SYSTEMC 34 allocation (); 35 #endif 36 33 37 #ifdef STATISTICS 34 38 // Allocation of statistics … … 36 40 param_statistics , 37 41 param); 38 #endif39 40 #ifdef VHDL_TESTBENCH41 // Creation of a testbench42 // -> port43 // -> clock's signals44 _vhdl_testbench = new Vhdl_Testbench (_name);45 vhdl_testbench_port ();46 _vhdl_testbench->set_clock ("in_CLOCK",false);47 42 #endif 48 43 … … 53 48 54 49 #ifdef SYSTEMC 55 allocation ();56 57 50 SC_METHOD (transition); 58 51 dont_initialize (); … … 85 78 #endif 86 79 87 #ifdef VHDL_TESTBENCH88 // generate the test bench89 _vhdl_testbench->generate_file();90 delete _vhdl_testbench;91 #endif92 93 80 #ifdef STATISTICS 94 81 _stat->generate_file(statistics(0)); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Counter_allocation.cpp
r2 r42 21 21 log_printf(FUNC,Counter,"allocation","Begin"); 22 22 23 #if defined(STATISTICS) or defined(VHDL_TESTBENCH) 24 in_CLOCK = new SC_CLOCK ("in_CLOCK"); 23 _component = new Component (); 24 25 Entity * entity = _component->set_entity (_name 26 ,"Counter" 27 #ifdef POSITION 28 ,COMBINATORY 25 29 #endif 30 ); 31 32 _interfaces = entity->set_interfaces(); 26 33 27 in_COUNTER_DATA = new SC_IN (Tdata_t) * [_param._nb_port]; 28 in_COUNTER_ADDSUB= new SC_IN (Tcontrol_t) * [_param._nb_port]; 29 out_COUNTER_DATA = new SC_OUT(Tdata_t) * [_param._nb_port]; 30 31 for (uint32_t i=0; i<_param._nb_port; i++) 32 { 33 rename = " in_COUNTER_DATA_" +toString(i); 34 in_COUNTER_DATA [i] = new SC_IN (Tdata_t) (rename.c_str()); 34 // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 35 { 36 Interface * interface = _interfaces->set_interface("" 37 #ifdef POSITION 38 , IN 39 , SOUTH 40 , "Generalist interface" 41 #endif 42 ); 43 44 in_CLOCK = interface->set_signal_clk ("clock" ,1,CLOCK_VHDL_NO); 45 in_NRESET = interface->set_signal_in <Tcontrol_t> ("nreset",1,RESET_VHDL_NO); 46 } 35 47 36 rename = " in_COUNTER_ADDSUB_"+toString(i); 37 in_COUNTER_ADDSUB[i] = new SC_IN (Tcontrol_t) (rename.c_str()); 38 39 rename = "out_COUNTER_DATA_" +toString(i); 40 out_COUNTER_DATA [i] = new SC_OUT(Tdata_t) (rename.c_str()); 41 } 48 // ~~~~~[ Interface : "counter" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 49 { 50 in_COUNTER_DATA = new SC_IN (Tdata_t) * [_param._nb_port]; 51 in_COUNTER_ADDSUB= new SC_IN (Tcontrol_t) * [_param._nb_port]; 52 out_COUNTER_DATA = new SC_OUT(Tdata_t) * [_param._nb_port]; 53 54 for (uint32_t i=0; i<_param._nb_port; i++) 55 { 56 Interface_fifo * interface = _interfaces->set_interface("counter_"+toString(i) 57 #ifdef POSITION 58 , IN 59 , SOUTH 60 , "Counter interface" 61 #endif 62 ); 63 64 in_COUNTER_DATA [i] = interface->set_signal_in <Tdata_t > ("data" , _param._size_data); 65 in_COUNTER_ADDSUB [i] = interface->set_signal_in <Tcontrol_t> ("addsub", 1 ); 66 out_COUNTER_DATA [i] = interface->set_signal_out <Tdata_t > ("data" , _param._size_data); 67 } 68 } 69 #ifdef POSITION 70 _component->generate_file(); 71 #endif 42 72 43 73 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Counter_deallocation.cpp
r2 r42 19 19 log_printf(FUNC,Counter,"deallocation","Begin"); 20 20 21 #if defined(STATISTICS) or defined(VHDL_TESTBENCH) 22 delete in_CLOCK; 23 #endif 21 delete in_CLOCK; 22 delete in_NRESET; 24 23 25 for (uint32_t i=0; i<_param._nb_port; i++) 26 { 27 delete in_COUNTER_DATA [i]; 28 delete in_COUNTER_ADDSUB[i]; 29 delete out_COUNTER_DATA [i]; 30 } 31 delete in_COUNTER_DATA ; 32 delete in_COUNTER_ADDSUB; 33 delete out_COUNTER_DATA ; 24 delete [] in_COUNTER_DATA ; 25 delete [] in_COUNTER_ADDSUB; 26 delete [] out_COUNTER_DATA ; 34 27 35 28 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 29 30 delete _component; 36 31 37 32 log_printf(FUNC,Counter,"deallocation","End"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Counter_genMealy.cpp
r3 r42 1 1 #ifdef SYSTEMC 2 #if defined(STATISTICS) or defined(VHDL_TESTBENCH)3 2 /* 4 3 * $Id$ … … 51 50 }; // end namespace morpheo 52 51 #endif 53 #endif -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Counter_vhdl.cpp
r2 r42 19 19 { 20 20 log_printf(FUNC,Counter,"vhdl","Begin"); 21 Vhdl vhdl (_name);21 Vhdl * vhdl = new Vhdl (_name); 22 22 23 vhdl .set_library_work (_name + "_Pack");23 vhdl->set_library_work (_name + "_Pack"); 24 24 25 25 vhdl_port (vhdl); … … 27 27 vhdl_body (vhdl); 28 28 29 vhdl.generate_file(); 29 vhdl->generate_file(); 30 31 delete vhdl; 30 32 log_printf(FUNC,Counter,"vhdl","End"); 31 33 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Counter_vhdl_body.cpp
r2 r42 14 14 namespace counter { 15 15 16 17 void Counter::vhdl_body (Vhdl & vhdl) 16 void Counter::vhdl_body (Vhdl * & vhdl) 18 17 { 19 18 log_printf(FUNC,Counter,"vhdl_body","Begin"); 20 vhdl .set_body ("");19 vhdl->set_body (""); 21 20 22 21 for (uint32_t i=0; i<_param._nb_port; i++) … … 26 25 if (_param._size_data > 1) 27 26 { 28 counter_inc = "in_COUNTER_ DATA_"+toString(i)+"+1";29 counter_dec = "in_COUNTER_ DATA_"+toString(i)+"-1";27 counter_inc = "in_COUNTER_"+toString(i)+"_DATA+1"; 28 counter_dec = "in_COUNTER_"+toString(i)+"_DATA-1"; 30 29 } 31 30 else 32 31 { 33 counter_inc = "in_COUNTER_ DATA_"+toString(i)+"+1";34 counter_dec = "in_COUNTER_ DATA_"+toString(i)+"-1";32 counter_inc = "in_COUNTER_"+toString(i)+"_DATA+1"; 33 counter_dec = "in_COUNTER_"+toString(i)+"_DATA-1"; 35 34 } 36 35 37 vhdl .set_body ("out_COUNTER_DATA_"+toString(i)+"<=");36 vhdl->set_body ("out_COUNTER_"+toString(i)+"_DATA <="); 38 37 if (_param._size_data > 1) 39 38 { 40 vhdl .set_body ("\tin_COUNTER_DATA_"+toString(i)+"+1 when in_COUNTER_ADDSUB_"+toString(i)+" = '1' and in_COUNTER_DATA_"+toString(i)+"< cst_max else");41 vhdl .set_body ("\tin_COUNTER_DATA_"+toString(i)+"-1 when in_COUNTER_ADDSUB_"+toString(i)+" = '0' and in_COUNTER_DATA_"+toString(i)+"> cst_min else");42 vhdl .set_body ("\tin_COUNTER_DATA_"+toString(i)+";");39 vhdl->set_body ("\tin_COUNTER_"+toString(i)+"_DATA+1 when in_COUNTER_"+toString(i)+"_ADDSUB = '1' and in_COUNTER_"+toString(i)+"_DATA < cst_max else"); 40 vhdl->set_body ("\tin_COUNTER_"+toString(i)+"_DATA-1 when in_COUNTER_"+toString(i)+"_ADDSUB = '0' and in_COUNTER_"+toString(i)+"_DATA > cst_min else"); 41 vhdl->set_body ("\tin_COUNTER_"+toString(i)+"_DATA;"); 43 42 } 44 43 else 45 44 { 46 vhdl .set_body ("\tin_COUNTER_ADDSUB_"+toString(i)+";");45 vhdl->set_body ("\tin_COUNTER_"+toString(i)+"_ADDSUB;"); 47 46 } 48 47 } -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Counter_vhdl_declaration.cpp
r2 r42 15 15 16 16 17 void Counter::vhdl_declaration (Vhdl & vhdl)17 void Counter::vhdl_declaration (Vhdl * & vhdl) 18 18 { 19 19 log_printf(FUNC,Counter,"vhdl_declaration","Begin"); … … 21 21 if (_param._size_data > 1) 22 22 { 23 vhdl .set_constant ("cst_min",_param._size_data,std_logic_others(_param._size_data,0));24 vhdl .set_constant ("cst_max",_param._size_data,std_logic_others(_param._size_data,1));23 vhdl->set_constant ("cst_min",_param._size_data,std_logic_others(_param._size_data,0)); 24 vhdl->set_constant ("cst_max",_param._size_data,std_logic_others(_param._size_data,1)); 25 25 } 26 26 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Counter_vhdl_port.cpp
r2 r42 15 15 16 16 17 void Counter::vhdl_port (Vhdl & vhdl)17 void Counter::vhdl_port (Vhdl * & vhdl) 18 18 { 19 19 log_printf(FUNC,Counter,"vhdl_port","Begin"); 20 20 21 for (uint32_t i=0; i<_param._nb_port; i++) 22 { 23 vhdl.set_port (" in_COUNTER_DATA_" +toString(i), IN, _param._size_data); 24 vhdl.set_port (" in_COUNTER_ADDSUB_"+toString(i), IN, 1 ); 25 vhdl.set_port ("out_COUNTER_DATA_" +toString(i),OUT, _param._size_data); 26 } 27 21 _interfaces->set_port(vhdl); 22 28 23 log_printf(FUNC,Counter,"vhdl_port","End"); 29 24 }; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Counter_vhdl_testbench_transition.cpp
r2 r42 21 21 sc_start(0); 22 22 23 // In order with file Counter_vhdl_testbench_port.cpp 24 // Warning : if a output depend of a subcomponent, take directly the port of subcomponent 25 // (because we have no control on the ordonnancer's policy) 26 27 for (uint32_t i=0; i<_param._nb_port; i++) 28 { 29 _vhdl_testbench->add_input (PORT_READ( in_COUNTER_DATA [i])); 30 _vhdl_testbench->add_input (PORT_READ( in_COUNTER_ADDSUB[i])); 31 _vhdl_testbench->add_output(PORT_READ(out_COUNTER_DATA [i])); 32 } 33 34 // add_test : 35 // - True : the cycle must be compare with the output of systemC 36 // - False : no test 37 _vhdl_testbench->add_test(true); 38 39 _vhdl_testbench->new_cycle (); // always at the end 23 _interfaces->testbench(); 40 24 41 25 log_printf(FUNC,Counter,"vhdl_testbench_transition","End"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/src/test.cpp
r15 r42 94 94 READ_VAL [i] .write (0); 95 95 96 NRESET.write(0); 97 96 98 sc_start(5); 99 100 NRESET.write(1); 97 101 98 102 cout << "<" << name << "> Write the RegisterFile (no read)" << endl; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/include/RegisterFile_Monolithic.h
r41 r42 23 23 #include "Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/include/Statistics.h" 24 24 #endif 25 #ifdef POSITION 26 #include "Behavioural/include/Position.h" 27 #else 28 #include "Behavioural/include/Interfaces.h" 29 #endif 25 #include "Behavioural/include/Component.h" 30 26 #ifdef VHDL 31 27 #include "Behavioural/include/Vhdl.h" … … 57 53 #endif 58 54 59 #ifdef POSITION 60 private : Position * _position; 61 #endif 62 55 public : Component * _component; 63 56 private : Interfaces * _interfaces; 64 57 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_allocation.cpp
r41 r42 17 17 void RegisterFile_Monolithic::allocation (void) 18 18 { 19 _component = new Component (); 20 21 Entity * entity = _component->set_entity (_name 22 ,"RegisterFile_Monolithic" 19 23 #ifdef POSITION 20 _position = new Position (); 21 22 Entity * entity = _position->set_entity (_name , 23 "RegisterFile_Monolithic", 24 REGISTER ); 24 ,REGISTER 25 #endif 26 ); 25 27 26 28 _interfaces = entity->set_interfaces(); 27 #else28 _interfaces = new Interfaces();29 #endif30 29 31 30 // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 32 Interface * interface_ = _interfaces->set_interface("", IN ,SOUTH, "Generalist interface"); 33 34 in_CLOCK = interface_->set_signal_clk ("clock" ,1); 35 in_NRESET = interface_->set_signal_in <Tcontrol_t> ("nreset",1); 36 31 { 32 Interface * interface = _interfaces->set_interface("" 33 #ifdef POSITION 34 , IN 35 ,SOUTH 36 , "Generalist interface" 37 #endif 38 ); 39 40 in_CLOCK = interface->set_signal_clk ("clock" ,1); 41 in_NRESET = interface->set_signal_in <Tcontrol_t> ("nreset",1, RESET_VHDL_YES); 42 } 37 43 // ~~~~~[ Interface : "read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 38 44 … … 44 50 for (uint32_t i=0; i<_param._nb_port_read; i++) 45 51 { 46 Interface_fifo * interface_read = _interfaces->set_interface("read_"+toString(i), IN ,WEST, "Interface Read"); 52 Interface_fifo * interface = _interfaces->set_interface("read_"+toString(i) 53 #ifdef POSITION 54 , IN 55 ,WEST 56 , "Interface Read" 57 #endif 58 ); 47 59 48 in_READ_VAL [i] = interface _read->set_signal_valack_in ("val" , VAL);49 out_READ_ACK [i] = interface _read->set_signal_valack_out ("ack" , ACK);50 in_READ_ADDRESS [i] = interface _read->set_signal_in <Taddress_t> ("address", static_cast<uint32_t>(log2(_param._nb_word)));51 out_READ_DATA [i] = interface _read->set_signal_out <Tdata_t > ("data" , _param._size_word);60 in_READ_VAL [i] = interface->set_signal_valack_in ("val" , VAL); 61 out_READ_ACK [i] = interface->set_signal_valack_out ("ack" , ACK); 62 in_READ_ADDRESS [i] = interface->set_signal_in <Taddress_t> ("address", static_cast<uint32_t>(log2(_param._nb_word))); 63 out_READ_DATA [i] = interface->set_signal_out <Tdata_t > ("data" , _param._size_word); 52 64 } 53 65 … … 61 73 for (uint32_t i=0; i<_param._nb_port_write; i++) 62 74 { 63 Interface_fifo * interface_write = _interfaces->set_interface("write_"+toString(i), IN ,EAST, "Interface Write"); 75 Interface_fifo * interface = _interfaces->set_interface("write_"+toString(i) 76 #ifdef POSITION 77 , IN 78 ,EAST 79 , "Interface Write" 80 #endif 81 ); 64 82 65 in_WRITE_VAL [i] = interface _write->set_signal_valack_in ("val" , VAL);66 out_WRITE_ACK [i] = interface _write->set_signal_valack_out ("ack" , ACK);67 in_WRITE_ADDRESS [i] = interface _write->set_signal_in <Taddress_t> ("address", static_cast<uint32_t>(log2(_param._nb_word)));68 in_WRITE_DATA [i] = interface _write->set_signal_in <Tdata_t > ("data" , _param._size_word);83 in_WRITE_VAL [i] = interface->set_signal_valack_in ("val" , VAL); 84 out_WRITE_ACK [i] = interface->set_signal_valack_out ("ack" , ACK); 85 in_WRITE_ADDRESS [i] = interface->set_signal_in <Taddress_t> ("address", static_cast<uint32_t>(log2(_param._nb_word))); 86 in_WRITE_DATA [i] = interface->set_signal_in <Tdata_t > ("data" , _param._size_word); 69 87 } 70 88 … … 79 97 80 98 #ifdef POSITION 81 _ position->generate_file();99 _component->generate_file(); 82 100 #endif 83 101 }; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_deallocation.cpp
r41 r42 17 17 void RegisterFile_Monolithic::deallocation (void) 18 18 { 19 delete _component; 20 19 21 delete in_CLOCK; 20 22 delete in_NRESET; … … 33 35 // ----- Register 34 36 delete [] reg_DATA; 35 36 #ifdef POSITION37 delete _position;38 #else39 delete _interfaces;40 #endif41 37 }; 42 38 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/include/Select_Priority_Fixed.h
r41 r42 22 22 #include "Behavioural/Generic/Select/Select_Priority_Fixed/include/Statistics.h" 23 23 #endif 24 #ifdef POSITION 25 #include "Behavioural/include/Position.h" 26 #else 27 #include "Behavioural/include/Interfaces.h" 28 #endif 24 #include "Behavioural/include/Component.h" 29 25 #ifdef VHDL 30 26 #include "Behavioural/include/Vhdl.h" … … 58 54 #endif 59 55 60 #ifdef POSITION 61 private : Position * _position; 62 #endif 63 56 private : Component * _component; 64 57 private : Interfaces * _interfaces; 65 58 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/src/Select_Priority_Fixed.cpp
r41 r42 71 71 sensitive << *(in_VAL [i]); 72 72 73 # ifdef SYSTEMCASS_SPECIFIC73 # ifdef SYSTEMCASS_SPECIFIC 74 74 // List dependency information 75 75 … … 85 85 } 86 86 87 # endif87 # endif 88 88 #endif 89 89 log_printf(FUNC,Select_Priority_Fixed,"Select_Priority_Fixed","End"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/src/Select_Priority_Fixed_allocation.cpp
r41 r42 19 19 log_printf(FUNC,Select_Priority_Fixed,"allocation","Begin"); 20 20 21 _component = new Component (); 22 23 Entity * entity = _component->set_entity (_name 21 24 #ifdef POSITION 22 _position = new Position (); 23 24 Entity * entity = _position->set_entity (_name , 25 "Select_Priority_Fixed", 26 COMBINATORY ); 25 ,"Select_Priority_Fixed" 26 ,COMBINATORY 27 #endif 28 ); 27 29 28 30 _interfaces = entity->set_interfaces(); 29 #else30 _interfaces = new Interfaces();31 #endif32 31 33 32 // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 34 33 35 Interface_fifo * interface_ = _interfaces->set_interface("", IN ,WEST, "Generalist interface"); 34 Interface_fifo * interface = _interfaces->set_interface("" 35 #ifdef POSITION 36 ,IN 37 ,WEST 38 ,"Generalist interface" 39 #endif 40 ); 36 41 37 in_CLOCK = interface _->set_signal_clk ("clock" ,1, CLOCK_VHDL_NO);38 in_NRESET = interface _->set_signal_in <Tcontrol_t> ("nreset",1);42 in_CLOCK = interface->set_signal_clk ("clock" ,1, CLOCK_VHDL_NO); 43 in_NRESET = interface->set_signal_in <Tcontrol_t> ("nreset",1); 39 44 in_VAL = new SC_IN (Tcontrol_t) * [_param._nb_entity]; 40 45 if (_param._encoding_one_hot) … … 43 48 for (uint32_t i=0; i<_param._nb_entity; i++) 44 49 { 45 in_VAL [i] = interface _->set_signal_in <Tcontrol_t> ("val_"+toString(i),1);50 in_VAL [i] = interface->set_signal_in <Tcontrol_t> ("val_"+toString(i),1); 46 51 if (_param._encoding_one_hot) 47 out_ACK [i] = interface _->set_signal_out <Tcontrol_t> ("ack_"+toString(i),1);52 out_ACK [i] = interface->set_signal_out <Tcontrol_t> ("ack_"+toString(i),1); 48 53 } 49 54 50 55 if (_param._encoding_compact) 51 56 { 52 out_ENTITY = interface _->set_signal_out <Tentity_t > ("entity" , _param._size_entity);53 out_ENTITY_ACK = interface _->set_signal_out <Tcontrol_t> ("entity_ack", 1);57 out_ENTITY = interface->set_signal_out <Tentity_t > ("entity" , _param._size_entity); 58 out_ENTITY_ACK = interface->set_signal_out <Tcontrol_t> ("entity_ack", 1); 54 59 } 55 60 … … 57 62 58 63 #ifdef POSITION 59 _ position->generate_file();64 _component->generate_file(); 60 65 #endif 61 66 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/src/Select_Priority_Fixed_deallocation.cpp
r41 r42 34 34 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 35 35 36 #ifdef POSITION 37 delete _position; 38 #else 39 delete _interfaces; 40 #endif 36 delete _component; 37 41 38 log_printf(FUNC,Select_Priority_Fixed,"deallocation","End"); 42 39 }; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/SelfTest/src/test.cpp
r2 r42 44 44 *********************************************************************/ 45 45 sc_clock CLOCK ("clock", 1.0, 0.5); 46 sc_signal <Tdirection_t> NRESET("nreset"); 46 47 sc_signal <Tdata_t > SHIFTER_DATA_IN [param._nb_port]; 47 48 sc_signal <Tshift_t > SHIFTER_SHIFT [param._nb_port]; … … 61 62 #if (defined(STATISTICS) || defined (VHDL_TESTBENCH)) 62 63 (*(_Shifter->in_CLOCK)) (CLOCK); 64 (*(_Shifter->in_NRESET)) (NRESET); 63 65 #endif 64 66 for (uint32_t i=0; i<param._nb_port; i++) … … 116 118 117 119 sc_start(0); 120 121 NRESET.write(1); 118 122 119 123 for (uint32_t x=0; x<6; x++) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/include/Shifter.h
r2 r42 24 24 #include "Behavioural/include/Vhdl.h" 25 25 #endif 26 #ifdef VHDL_TESTBENCH 27 #include "Behavioural/include/Vhdl_Testbench.h" 28 #endif 26 #include "Behavioural/include/Component.h" 29 27 30 28 using namespace std; … … 50 48 #endif 51 49 52 #ifdef VHDL_TESTBENCH 53 private : Vhdl_Testbench * _vhdl_testbench; 54 #endif 50 public : Component * _component; 51 private : Interfaces * _interfaces; 55 52 56 53 #ifdef SYSTEMC 57 54 // ~~~~~[ Interface ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 58 55 public : SC_CLOCK * in_CLOCK ; 56 public : SC_IN (Tcontrol_t) * in_NRESET ; 57 59 58 // Interface "shifter" 60 59 public : SC_IN (Tdata_t) ** in_SHIFTER_DATA ; … … 104 103 #if VHDL 105 104 public : void vhdl (void); 106 private : void vhdl_port (Vhdl & vhdl);107 private : void vhdl_declaration (Vhdl & vhdl);108 private : void vhdl_body (Vhdl & vhdl);105 private : void vhdl_port (Vhdl * & vhdl); 106 private : void vhdl_declaration (Vhdl * & vhdl); 107 private : void vhdl_body (Vhdl * & vhdl); 109 108 #endif 110 109 #ifdef STATISTICS … … 113 112 114 113 #ifdef VHDL_TESTBENCH 115 private : void vhdl_testbench (Vhdl_Testbench & vhdl_testbench); 116 private : void vhdl_testbench_port (Vhdl_Testbench & vhdl_testbench); 117 private : void vhdl_testbench_transition (Vhdl_Testbench & vhdl_testbench); 114 private : void vhdl_testbench_transition (void); 118 115 #endif 119 116 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Shifter.cpp
r2 r42 15 15 16 16 #ifdef SYSTEMC 17 Shifter::Shifter (sc_module_name name ,17 Shifter::Shifter (sc_module_name name 18 18 #else 19 Shifter::Shifter (string name ,19 Shifter::Shifter (string name 20 20 #endif 21 21 #ifdef STATISTICS 22 morpheo::behavioural::Parameters_Statistics param_statistics,22 ,morpheo::behavioural::Parameters_Statistics param_statistics 23 23 #endif 24 morpheo::behavioural::generic::shifter::Parameters param ):24 ,morpheo::behavioural::generic::shifter::Parameters param ): 25 25 _name (name) 26 26 ,_param (param) 27 27 { 28 #ifdef SYSTEMC 29 allocation (); 30 #endif 31 28 32 #ifdef STATISTICS 29 33 // Allocation of statistics … … 31 35 param_statistics , 32 36 param); 33 #endif34 35 #ifdef VHDL_TESTBENCH36 // Creation of a testbench37 // -> port38 // -> clock's signals39 _vhdl_testbench = new Vhdl_Testbench (_name);40 vhdl_testbench_port (*_vhdl_testbench);41 _vhdl_testbench->set_clock ("in_CLOCK",false);42 37 #endif 43 38 … … 48 43 49 44 #ifdef SYSTEMC 50 allocation ();51 52 45 #if (defined(STATISTICS) || defined (VHDL_TESTBENCH)) 53 46 SC_METHOD (transition); … … 107 100 #endif 108 101 109 #ifdef VHDL_TESTBENCH110 // generate the test bench111 _vhdl_testbench->generate_file();112 delete _vhdl_testbench;113 #endif114 115 102 #ifdef STATISTICS 116 103 _stat->generate_file(statistics(0)); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Shifter_allocation.cpp
r2 r42 17 17 void Shifter::allocation (void) 18 18 { 19 string rename; 19 _component = new Component (); 20 21 Entity * entity = _component->set_entity (_name 22 ,"Shifter" 23 #ifdef POSITION 24 ,COMBINATORY 25 #endif 26 ); 27 28 _interfaces = entity->set_interfaces(); 20 29 21 30 #if (defined(STATISTICS) || defined (VHDL_TESTBENCH)) 22 in_CLOCK = new SC_CLOCK ("SC_CLOCK"); 31 { 32 Interface_fifo * interface = _interfaces->set_interface("" 33 #ifdef POSITION 34 , IN 35 , SOUTH 36 , "Generalist interface" 23 37 #endif 24 // Interface "shifter" 25 in_SHIFTER_DATA = new SC_IN (Tdata_t) * [_param._nb_port]; 26 if (_param._shift_value == 0) 27 in_SHIFTER_SHIFT = new SC_IN (Tshift_t) * [_param._nb_port]; 28 if (_param._direction == external_direction) 29 in_SHIFTER_DIRECTION = new SC_IN (Tdirection_t) * [_param._nb_port]; 30 if (_param._rotate == external_rotate) 31 in_SHIFTER_TYPE = new SC_IN (Ttype_t) * [_param._nb_port]; 32 if (_param._carry == external_carry) 33 in_SHIFTER_CARRY = new SC_IN (Tcarry_t) * [_param._nb_port]; 34 if (_param._carry == external_completion) 35 if (_param._type_completion_bool == true) 36 in_SHIFTER_CARRY_IN = new SC_IN (Tcontrol_t) * [_param._nb_port]; 37 else 38 in_SHIFTER_COMPLETION= new SC_IN (Tdata_t) * [_param._nb_port]; 39 out_SHIFTER_DATA = new SC_OUT(Tdata_t) * [_param._nb_port]; 38 ); 39 40 in_CLOCK = interface->set_signal_clk ("clock" ,1, CLOCK_VHDL_NO); 41 in_NRESET = interface->set_signal_in <Tcontrol_t> ("nreset",1, RESET_VHDL_NO); 42 } 43 #endif 40 44 41 for (uint32_t i=0; i<_param._nb_port; i++) 42 { 43 rename = "in_SHIFTER_DATA[" + toString(i) + "]"; 44 in_SHIFTER_DATA [i] = new SC_IN (Tdata_t) (rename.c_str()); 45 { 46 // Interface "shifter" 47 in_SHIFTER_DATA = new SC_IN (Tdata_t) * [_param._nb_port]; 48 if (_param._shift_value == 0) 49 in_SHIFTER_SHIFT = new SC_IN (Tshift_t) * [_param._nb_port]; 50 if (_param._direction == external_direction) 51 in_SHIFTER_DIRECTION = new SC_IN (Tdirection_t) * [_param._nb_port]; 52 if (_param._rotate == external_rotate) 53 in_SHIFTER_TYPE = new SC_IN (Ttype_t) * [_param._nb_port]; 54 if (_param._carry == external_carry) 55 in_SHIFTER_CARRY = new SC_IN (Tcarry_t) * [_param._nb_port]; 56 if (_param._carry == external_completion) 57 if (_param._type_completion_bool == true) 58 in_SHIFTER_CARRY_IN = new SC_IN (Tcontrol_t) * [_param._nb_port]; 59 else 60 in_SHIFTER_COMPLETION= new SC_IN (Tdata_t) * [_param._nb_port]; 61 out_SHIFTER_DATA = new SC_OUT(Tdata_t) * [_param._nb_port]; 62 63 for (uint32_t i=0; i<_param._nb_port; i++) 64 { 65 Interface_fifo * interface = _interfaces->set_interface("shifter_"+toString(i) 66 #ifdef POSITION 67 , IN 68 , SOUTH 69 , "Generalist interface" 70 #endif 71 ); 72 73 in_SHIFTER_DATA [i] = interface->set_signal_in <Tdata_t > ("data" ,_param._size_data); 74 if (_param._shift_value == 0) 75 in_SHIFTER_SHIFT [i] = interface->set_signal_in <Tshift_t > ("shift" ,static_cast<uint32_t>(ceil(log2(_param._size_data)))); 76 if (_param._direction == external_direction) 77 in_SHIFTER_DIRECTION [i] = interface->set_signal_in <Tdirection_t> ("direction" ,1); 78 if (_param._rotate == external_rotate) 79 in_SHIFTER_TYPE [i] = interface->set_signal_in <Ttype_t > ("type" ,1); 80 if (_param._carry == external_carry) 81 in_SHIFTER_CARRY [i] = interface->set_signal_in <Tcarry_t > ("carry" ,1); 82 if (_param._carry == external_completion) 83 if (_param._type_completion_bool == true) 84 in_SHIFTER_CARRY_IN [i] = interface->set_signal_in <Tcontrol_t > ("carry_in" ,1); 85 else 86 in_SHIFTER_COMPLETION [i] = interface->set_signal_in <Tdata_t > ("completion",_param._size_data_completion); 87 out_SHIFTER_DATA [i] = interface->set_signal_out <Tdata_t > ("data" ,_param._size_data); 88 } 89 } 45 90 46 if (_param._shift_value == 0) 47 { 48 rename = "in_SHIFTER_SHIFT[" + toString(i) + "]"; 49 in_SHIFTER_SHIFT [i] = new SC_IN (Tshift_t) (rename.c_str()); 50 } 51 if (_param._direction == external_direction) 52 { 53 rename = "in_SHIFTER_DIRECTION[" + toString(i) + "]"; 54 in_SHIFTER_DIRECTION [i] = new SC_IN (Tdirection_t) (rename.c_str()); 55 } 56 if (_param._rotate == external_rotate) 57 { 58 rename = "in_SHIFTER_TYPE[" + toString(i) + "]"; 59 in_SHIFTER_TYPE [i] = new SC_IN (Ttype_t) (rename.c_str()); 60 } 61 if (_param._carry == external_carry) 62 { 63 rename = "in_SHIFTER_CARRY[" + toString(i) + "]"; 64 in_SHIFTER_CARRY [i] = new SC_IN (Tcarry_t) (rename.c_str()); 65 } 91 #ifdef POSITION 92 _component->generate_file(); 93 #endif 66 94 67 if (_param._carry == external_completion)68 if (_param._type_completion_bool == true)69 {70 rename = "in_SHIFTER_CARRY_IN[" + toString(i) + "]";71 in_SHIFTER_CARRY_IN [i] = new SC_IN (Tcontrol_t) (rename.c_str());72 }73 else74 {75 rename = "in_SHIFTER_COMPLETION[" + toString(i) + "]";76 in_SHIFTER_COMPLETION [i] = new SC_IN (Tdata_t) (rename.c_str());77 }78 79 rename = "out_SHIFTER_DATA[" + toString(i) + "]";80 out_SHIFTER_DATA [i] = new SC_OUT(Tdata_t) (rename.c_str());81 }82 95 }; 83 96 84 97 }; // end namespace shifter 85 98 }; // end namespace generic -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Shifter_deallocation.cpp
r2 r42 18 18 { 19 19 #if (defined(STATISTICS) || defined (VHDL_TESTBENCH)) 20 delete in_CLOCK;20 delete in_CLOCK; 21 21 #endif 22 22 23 // Interface "shifter" 24 for (uint32_t i=0; i<_param._nb_port; i++) 25 { 26 delete in_SHIFTER_DATA [i]; 27 if (_param._shift_value == 0) 28 delete in_SHIFTER_SHIFT [i]; 29 if (_param._direction == external_direction) 30 delete in_SHIFTER_DIRECTION [i]; 31 if (_param._rotate == external_rotate) 32 delete in_SHIFTER_TYPE [i]; 33 if (_param._carry == external_carry) 34 delete in_SHIFTER_CARRY [i]; 35 if (_param._carry == external_completion) 36 if (_param._type_completion_bool == true) 37 delete in_SHIFTER_CARRY_IN [i]; 38 else 39 delete in_SHIFTER_COMPLETION[i]; 40 delete out_SHIFTER_DATA [i]; 41 } 23 delete [] in_SHIFTER_DATA ; 24 if (_param._shift_value == 0) 25 delete [] in_SHIFTER_SHIFT ; 26 if (_param._direction == external_direction ) 27 delete [] in_SHIFTER_DIRECTION ; 28 if (_param._rotate == external_rotate ) 29 delete [] in_SHIFTER_TYPE ; 30 if (_param._carry == external_carry ) 31 delete [] in_SHIFTER_CARRY ; 32 if (_param._carry == external_completion) 33 if (_param._type_completion_bool == true) 34 delete [] in_SHIFTER_CARRY_IN ; 35 else 36 delete [] in_SHIFTER_COMPLETION; 37 delete [] out_SHIFTER_DATA ; 42 38 43 delete in_SHIFTER_DATA ; 44 if (_param._shift_value == 0) 45 delete in_SHIFTER_SHIFT ; 46 if (_param._direction == external_direction ) 47 delete in_SHIFTER_DIRECTION ; 48 if (_param._rotate == external_rotate ) 49 delete in_SHIFTER_TYPE ; 50 if (_param._carry == external_carry ) 51 delete in_SHIFTER_CARRY ; 52 if (_param._carry == external_completion) 53 if (_param._type_completion_bool == true) 54 delete in_SHIFTER_CARRY_IN ; 55 else 56 delete in_SHIFTER_COMPLETION; 57 delete out_SHIFTER_DATA ; 39 delete _component; 40 58 41 }; 59 42 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Shifter_transition.cpp
r2 r42 23 23 24 24 #ifdef VHDL_TESTBENCH 25 vhdl_testbench_transition ( *_vhdl_testbench);25 vhdl_testbench_transition (); 26 26 #endif 27 27 }; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Shifter_vhdl.cpp
r2 r42 18 18 void Shifter::vhdl (void) 19 19 { 20 Vhdl vhdl (_name);20 Vhdl * vhdl = new Vhdl (_name); 21 21 22 vhdl .set_library_work (_name + "_Pack");22 vhdl->set_library_work (_name + "_Pack"); 23 23 24 24 vhdl_port (vhdl); … … 26 26 vhdl_body (vhdl); 27 27 28 vhdl.generate_file(); 28 vhdl->generate_file(); 29 30 delete vhdl; 29 31 }; 30 32 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Shifter_vhdl_body.cpp
r2 r42 15 15 16 16 17 void Shifter::vhdl_body (Vhdl & vhdl)17 void Shifter::vhdl_body (Vhdl * & vhdl) 18 18 { 19 19 //uint32_t log2_size_data = static_cast<uint32_t>(ceil(log2(_param._size_data))); 20 20 21 vhdl .set_body ("-- Compute all case of shift");21 vhdl->set_body ("-- Compute all case of shift"); 22 22 23 23 for (uint32_t i=0; i<_param._nb_port; i++) … … 25 25 //-----[ Shift logic Left ]-------------------------------------------- 26 26 if (_param._have_shift_logic_left) 27 vhdl .set_body ("shift_logic_left_"+toString(i)+" <= TO_STDLOGICVECTOR(TO_BITVECTOR(in_SHIFTER_DATA_"+toString(i)+") sll CONV_INTEGER(shift_"+toString(i)+"));");27 vhdl->set_body ("shift_logic_left_"+toString(i)+" <= TO_STDLOGICVECTOR(TO_BITVECTOR(in_SHIFTER_"+toString(i)+"_DATA) sll CONV_INTEGER(shift_"+toString(i)+"));"); 28 28 //-----[ Shift logic Right ]------------------------------------------- 29 29 if (_param._have_shift_logic_right) 30 vhdl .set_body ("shift_logic_right_"+toString(i)+" <= TO_STDLOGICVECTOR(TO_BITVECTOR(in_SHIFTER_DATA_"+toString(i)+") srl CONV_INTEGER(shift_"+toString(i)+"));");30 vhdl->set_body ("shift_logic_right_"+toString(i)+" <= TO_STDLOGICVECTOR(TO_BITVECTOR(in_SHIFTER_"+toString(i)+"_DATA) srl CONV_INTEGER(shift_"+toString(i)+"));"); 31 31 //-----[ Shift arithmetic Left ]--------------------------------------- 32 32 if (_param._have_shift_arithmetic_left) 33 vhdl .set_body ("shift_arithmetic_left_"+toString(i)+" <= TO_STDLOGICVECTOR(TO_BITVECTOR(in_SHIFTER_DATA_"+toString(i)+") sla CONV_INTEGER(shift_"+toString(i)+"));");33 vhdl->set_body ("shift_arithmetic_left_"+toString(i)+" <= TO_STDLOGICVECTOR(TO_BITVECTOR(in_SHIFTER_"+toString(i)+"_DATA) sla CONV_INTEGER(shift_"+toString(i)+"));"); 34 34 //-----[ Shift arithmetic Right ]-------------------------------------- 35 35 if (_param._have_shift_arithmetic_right) 36 vhdl .set_body ("shift_arithmetic_right_"+toString(i)+" <= TO_STDLOGICVECTOR(TO_BITVECTOR(in_SHIFTER_DATA_"+toString(i)+") sra CONV_INTEGER(shift_"+toString(i)+"));");36 vhdl->set_body ("shift_arithmetic_right_"+toString(i)+" <= TO_STDLOGICVECTOR(TO_BITVECTOR(in_SHIFTER_"+toString(i)+"_DATA) sra CONV_INTEGER(shift_"+toString(i)+"));"); 37 37 //-----[ Rotate Left ]------------------------------------------------- 38 38 if (_param._have_rotate_left) 39 vhdl .set_body ("rotate_left_"+toString(i)+" <= TO_STDLOGICVECTOR(TO_BITVECTOR(in_SHIFTER_DATA_"+toString(i)+") rol CONV_INTEGER(shift_"+toString(i)+"));");39 vhdl->set_body ("rotate_left_"+toString(i)+" <= TO_STDLOGICVECTOR(TO_BITVECTOR(in_SHIFTER_"+toString(i)+"_DATA) rol CONV_INTEGER(shift_"+toString(i)+"));"); 40 40 //-----[ Rotate Right ]------------------------------------------------ 41 41 if (_param._have_rotate_right) 42 vhdl .set_body ("rotate_right_"+toString(i)+" <= TO_STDLOGICVECTOR(TO_BITVECTOR(in_SHIFTER_DATA_"+toString(i)+") ror CONV_INTEGER(shift_"+toString(i)+"));");42 vhdl->set_body ("rotate_right_"+toString(i)+" <= TO_STDLOGICVECTOR(TO_BITVECTOR(in_SHIFTER_"+toString(i)+"_DATA) ror CONV_INTEGER(shift_"+toString(i)+"));"); 43 43 } 44 44 45 45 if (_param._size_data_completion > 0) 46 46 { 47 vhdl .set_body ("");48 vhdl .set_body ("-- Mask");47 vhdl->set_body (""); 48 vhdl->set_body ("-- Mask"); 49 49 50 50 for (uint32_t i=0; i<_param._nb_port; i++) … … 53 53 54 54 if (_param._type_completion_bool == true) 55 print_shifter_completion = "in_SHIFTER_ CARRY_IN";55 print_shifter_completion = "in_SHIFTER_"+toString(i)+"_CARRY_IN"; 56 56 else 57 print_shifter_completion = "in_SHIFTER_ COMPLETION";57 print_shifter_completion = "in_SHIFTER_"+toString(i)+"_COMPLETION"; 58 58 59 59 if (_param._size_data == _param._size_data_completion) 60 60 { 61 vhdl .set_body ("shifter_completion_left_"+toString(i)+" <= "+print_shifter_completion+"_"+toString(i)+";");62 vhdl .set_body ("shifter_completion_right_"+toString(i)+" <= "+print_shifter_completion+"_"+toString(i)+";");61 vhdl->set_body ("shifter_completion_left_"+toString(i)+" <= "+print_shifter_completion+";"); 62 vhdl->set_body ("shifter_completion_right_"+toString(i)+" <= "+print_shifter_completion+";"); 63 63 } 64 64 else 65 65 { 66 vhdl .set_body ("shifter_completion_left_"+toString(i)+std_logic_range(_param._size_data-1,_param._size_data_completion)+" <= "+std_logic_others(_param._size_data-_param._size_data_completion,0)+";");67 vhdl .set_body ("shifter_completion_left_"+toString(i)+std_logic_range(_param._size_data_completion )+" <= "+print_shifter_completion+"_"+toString(i)+";");68 69 vhdl .set_body ("shifter_completion_right_"+toString(i)+std_logic_range(_param._size_data-1,_param._size_data-_param._size_data_completion)+" <= "+print_shifter_completion+"_"+toString(i)+";");70 vhdl .set_body ("shifter_completion_right_"+toString(i)+std_logic_range(_param._size_data-_param._size_data_completion )+" <= "+std_logic_others(_param._size_data-_param._size_data_completion,0)+";");71 } 72 73 vhdl .set_body ("mask_completion_left_"+toString(i)+" <= TO_STDLOGICVECTOR(TO_BITVECTOR(cst_completion) sll CONV_INTEGER(shift_"+toString(i)+"));");74 vhdl .set_body ("mask_completion_right_"+toString(i)+" <= TO_STDLOGICVECTOR(TO_BITVECTOR(cst_completion) srl CONV_INTEGER(shift_"+toString(i)+"));");66 vhdl->set_body ("shifter_completion_left_"+toString(i)+std_logic_range(_param._size_data-1,_param._size_data_completion)+" <= "+std_logic_others(_param._size_data-_param._size_data_completion,0)+";"); 67 vhdl->set_body ("shifter_completion_left_"+toString(i)+std_logic_range(_param._size_data_completion )+" <= "+print_shifter_completion+";"); 68 69 vhdl->set_body ("shifter_completion_right_"+toString(i)+std_logic_range(_param._size_data-1,_param._size_data-_param._size_data_completion)+" <= "+print_shifter_completion+";"); 70 vhdl->set_body ("shifter_completion_right_"+toString(i)+std_logic_range(_param._size_data-_param._size_data_completion )+" <= "+std_logic_others(_param._size_data-_param._size_data_completion,0)+";"); 71 } 72 73 vhdl->set_body ("mask_completion_left_"+toString(i)+" <= TO_STDLOGICVECTOR(TO_BITVECTOR(cst_completion) sll CONV_INTEGER(shift_"+toString(i)+"));"); 74 vhdl->set_body ("mask_completion_right_"+toString(i)+" <= TO_STDLOGICVECTOR(TO_BITVECTOR(cst_completion) srl CONV_INTEGER(shift_"+toString(i)+"));"); 75 75 } 76 76 } 77 77 78 78 79 vhdl .set_body ("");80 vhdl .set_body ("-- Multiplexor");79 vhdl->set_body (""); 80 vhdl->set_body ("-- Multiplexor"); 81 81 82 82 for (uint32_t i=0; i<_param._nb_port; i++) 83 83 { 84 vhdl .set_body ("out_SHIFTER_DATA_"+toString(i)+"<=");84 vhdl->set_body ("out_SHIFTER_"+toString(i)+"_DATA <="); 85 85 string print_else = " "; 86 86 … … 95 95 { 96 96 have_when = true; 97 print_when += " in_SHIFTER_ DIRECTION_"+toString(i)+"= cst_is_direction_left ";98 print_and = " and "; 99 } 100 if (_param._rotate == external_rotate) 101 { 102 have_when = true; 103 print_when += print_and+" in_SHIFTER_ TYPE_"+toString(i)+"= cst_is_type_shift ";97 print_when += " in_SHIFTER_"+toString(i)+"_DIRECTION = cst_is_direction_left "; 98 print_and = " and "; 99 } 100 if (_param._rotate == external_rotate) 101 { 102 have_when = true; 103 print_when += print_and+" in_SHIFTER_"+toString(i)+"_TYPE = cst_is_type_shift "; 104 104 print_and = " and "; 105 105 } … … 107 107 { 108 108 have_when = true; 109 print_when += print_and+" in_SHIFTER_ CARRY_"+toString(i)+"= cst_is_carry_arithmetic";110 } 111 112 if (have_when) 113 print_when = "when " + print_when; 114 115 vhdl .set_body ("\t"+print_else+" shift_arithmetic_left_"+toString(i)+" "+print_when);109 print_when += print_and+" in_SHIFTER_"+toString(i)+"_CARRY = cst_is_carry_arithmetic"; 110 } 111 112 if (have_when) 113 print_when = "when " + print_when; 114 115 vhdl->set_body ("\t"+print_else+" shift_arithmetic_left_"+toString(i)+" "+print_when); 116 116 print_else = "else"; 117 117 } … … 126 126 { 127 127 have_when = true; 128 print_when += " in_SHIFTER_ DIRECTION_"+toString(i)+"= cst_is_direction_right";129 print_and = " and "; 130 } 131 if (_param._rotate == external_rotate) 132 { 133 have_when = true; 134 print_when += print_and+" in_SHIFTER_ TYPE_"+toString(i)+"= cst_is_type_shift ";128 print_when += " in_SHIFTER_"+toString(i)+"_DIRECTION = cst_is_direction_right"; 129 print_and = " and "; 130 } 131 if (_param._rotate == external_rotate) 132 { 133 have_when = true; 134 print_when += print_and+" in_SHIFTER_"+toString(i)+"_TYPE = cst_is_type_shift "; 135 135 print_and = " and "; 136 136 } … … 138 138 { 139 139 have_when = true; 140 print_when += print_and+" in_SHIFTER_ CARRY_"+toString(i)+"= cst_is_carry_arithmetic";141 } 142 143 if (have_when) 144 print_when = "when " + print_when; 145 146 vhdl .set_body ("\t"+print_else+" shift_arithmetic_right_"+toString(i)+" "+print_when);140 print_when += print_and+" in_SHIFTER_"+toString(i)+"_CARRY = cst_is_carry_arithmetic"; 141 } 142 143 if (have_when) 144 print_when = "when " + print_when; 145 146 vhdl->set_body ("\t"+print_else+" shift_arithmetic_right_"+toString(i)+" "+print_when); 147 147 print_else = "else"; 148 148 } … … 157 157 { 158 158 have_when = true; 159 print_when += " in_SHIFTER_ DIRECTION_"+toString(i)+"= cst_is_direction_left ";160 print_and = " and "; 161 } 162 if (_param._rotate == external_rotate) 163 { 164 have_when = true; 165 print_when += print_and+" in_SHIFTER_ TYPE_"+toString(i)+"= cst_is_type_shift ";159 print_when += " in_SHIFTER_"+toString(i)+"_DIRECTION = cst_is_direction_left "; 160 print_and = " and "; 161 } 162 if (_param._rotate == external_rotate) 163 { 164 have_when = true; 165 print_when += print_and+" in_SHIFTER_"+toString(i)+"_TYPE = cst_is_type_shift "; 166 166 print_and = " and "; 167 167 } … … 169 169 { 170 170 have_when = true; 171 print_when += print_and+" in_SHIFTER_ CARRY_"+toString(i)+"= cst_is_carry_logic ";171 print_when += print_and+" in_SHIFTER_"+toString(i)+"_CARRY = cst_is_carry_logic "; 172 172 } 173 173 … … 182 182 print_expr_completion = "(shift_logic_left_"+toString(i)+" and mask_completion_left_"+toString(i)+" ) or ( shifter_completion_left_"+toString(i)+" and not mask_completion_left_"+toString(i)+" )"; 183 183 184 vhdl .set_body ("\t"+print_else+" "+print_expr_completion+" "+print_when);184 vhdl->set_body ("\t"+print_else+" "+print_expr_completion+" "+print_when); 185 185 print_else = "else"; 186 186 } … … 195 195 { 196 196 have_when = true; 197 print_when += " in_SHIFTER_ DIRECTION_"+toString(i)+"= cst_is_direction_right";198 print_and = " and "; 199 } 200 if (_param._rotate == external_rotate) 201 { 202 have_when = true; 203 print_when += print_and+" in_SHIFTER_ TYPE_"+toString(i)+"= cst_is_type_shift ";197 print_when += " in_SHIFTER_"+toString(i)+"_DIRECTION = cst_is_direction_right"; 198 print_and = " and "; 199 } 200 if (_param._rotate == external_rotate) 201 { 202 have_when = true; 203 print_when += print_and+" in_SHIFTER_"+toString(i)+"_TYPE = cst_is_type_shift "; 204 204 print_and = " and "; 205 205 } … … 207 207 { 208 208 have_when = true; 209 print_when += print_and+" in_SHIFTER_ CARRY_"+toString(i)+"= cst_is_carry_logic ";209 print_when += print_and+" in_SHIFTER_"+toString(i)+"_CARRY = cst_is_carry_logic "; 210 210 } 211 211 … … 220 220 print_expr_completion = "(shift_logic_right_"+toString(i)+" and mask_completion_right_"+toString(i)+") or ( shifter_completion_right_"+toString(i)+" and not mask_completion_right_"+toString(i)+")"; 221 221 222 vhdl .set_body ("\t"+print_else+" "+print_expr_completion+" "+print_when);222 vhdl->set_body ("\t"+print_else+" "+print_expr_completion+" "+print_when); 223 223 print_else = "else"; 224 224 } … … 233 233 { 234 234 have_when = true; 235 print_when += " in_SHIFTER_ DIRECTION_"+toString(i)+"= cst_is_direction_left ";236 print_and = " and "; 237 } 238 if (_param._rotate == external_rotate) 239 { 240 have_when = true; 241 print_when += print_and+" in_SHIFTER_ TYPE_"+toString(i)+"= cst_is_type_rotate";242 print_and = " and "; 243 } 244 245 if (have_when) 246 print_when = "when " + print_when; 247 248 vhdl .set_body ("\t"+print_else+" rotate_left_"+toString(i)+" "+print_when);235 print_when += " in_SHIFTER_"+toString(i)+"_DIRECTION = cst_is_direction_left "; 236 print_and = " and "; 237 } 238 if (_param._rotate == external_rotate) 239 { 240 have_when = true; 241 print_when += print_and+" in_SHIFTER_"+toString(i)+"_TYPE = cst_is_type_rotate"; 242 print_and = " and "; 243 } 244 245 if (have_when) 246 print_when = "when " + print_when; 247 248 vhdl->set_body ("\t"+print_else+" rotate_left_"+toString(i)+" "+print_when); 249 249 print_else = "else"; 250 250 } … … 259 259 { 260 260 have_when = true; 261 print_when += " in_SHIFTER_ DIRECTION_"+toString(i)+"= cst_is_direction_right";262 print_and = " and "; 263 } 264 if (_param._rotate == external_rotate) 265 { 266 have_when = true; 267 print_when += print_and+" in_SHIFTER_ TYPE_"+toString(i)+"= cst_is_type_rotate";268 print_and = " and "; 269 } 270 271 if (have_when) 272 print_when = "when " + print_when; 273 274 vhdl .set_body ("\t"+print_else+" rotate_right_"+toString(i)+" "+print_when);275 print_else = "else"; 276 } 277 vhdl .set_body (";");261 print_when += " in_SHIFTER_"+toString(i)+"_DIRECTION = cst_is_direction_right"; 262 print_and = " and "; 263 } 264 if (_param._rotate == external_rotate) 265 { 266 have_when = true; 267 print_when += print_and+" in_SHIFTER_"+toString(i)+"_TYPE = cst_is_type_rotate"; 268 print_and = " and "; 269 } 270 271 if (have_when) 272 print_when = "when " + print_when; 273 274 vhdl->set_body ("\t"+print_else+" rotate_right_"+toString(i)+" "+print_when); 275 print_else = "else"; 276 } 277 vhdl->set_body (";"); 278 278 } 279 279 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Shifter_vhdl_declaration.cpp
r2 r42 15 15 16 16 17 void Shifter::vhdl_declaration (Vhdl & vhdl)17 void Shifter::vhdl_declaration (Vhdl * & vhdl) 18 18 { 19 19 uint32_t log2_size_data = static_cast<uint32_t>(ceil(log2(_param._size_data))); 20 20 21 vhdl .set_constant("cst_is_direction_left ",1,_left );22 vhdl .set_constant("cst_is_direction_right ",1,_right );23 vhdl .set_constant("cst_is_type_shift ",1,_shift );24 vhdl .set_constant("cst_is_type_rotate ",1,_rotate );25 vhdl .set_constant("cst_is_carry_arithmetic",1,_arithmetic);26 vhdl .set_constant("cst_is_carry_logic ",1,_logic );27 vhdl .set_constant("cst_completion ",_param._size_data,"(others => '1')");21 vhdl->set_constant("cst_is_direction_left ",1,_left ); 22 vhdl->set_constant("cst_is_direction_right ",1,_right ); 23 vhdl->set_constant("cst_is_type_shift ",1,_shift ); 24 vhdl->set_constant("cst_is_type_rotate ",1,_rotate ); 25 vhdl->set_constant("cst_is_carry_arithmetic",1,_arithmetic); 26 vhdl->set_constant("cst_is_carry_logic ",1,_logic ); 27 vhdl->set_constant("cst_completion ",_param._size_data,"(others => '1')"); 28 28 29 29 for (uint32_t i=0; i<_param._nb_port; i++) 30 30 { 31 31 if (_param._shift_value != 0) 32 vhdl .set_constant("shift_"+toString(i),log2_size_data, _param._shift_value);32 vhdl->set_constant("shift_"+toString(i),log2_size_data, _param._shift_value); 33 33 else 34 vhdl .set_alias ("shift_"+toString(i),std_logic(log2_size_data), "in_SHIFTER_SHIFT_"+toString(i),std_logic_range(log2_size_data));34 vhdl->set_alias ("shift_"+toString(i),std_logic(log2_size_data), "in_SHIFTER_"+toString(i)+"_SHIFT",std_logic_range(log2_size_data)); 35 35 36 36 if (_param._size_data_completion > 0) 37 37 { 38 vhdl .set_signal ("shifter_completion_left_"+toString(i)+" ",_param._size_data);39 vhdl .set_signal ("shifter_completion_right_"+toString(i)+"",_param._size_data);40 vhdl .set_signal ("mask_completion_left_"+toString(i)+" ",_param._size_data);41 vhdl .set_signal ("mask_completion_right_"+toString(i)+" ",_param._size_data);38 vhdl->set_signal ("shifter_completion_left_"+toString(i)+" ",_param._size_data); 39 vhdl->set_signal ("shifter_completion_right_"+toString(i)+"",_param._size_data); 40 vhdl->set_signal ("mask_completion_left_"+toString(i)+" ",_param._size_data); 41 vhdl->set_signal ("mask_completion_right_"+toString(i)+" ",_param._size_data); 42 42 } 43 43 44 44 //-----[ Shift logic Left ]-------------------------------------------- 45 45 if (_param._have_shift_logic_left) 46 vhdl .set_signal ("shift_logic_left_"+toString(i)+" ",_param._size_data);46 vhdl->set_signal ("shift_logic_left_"+toString(i)+" ",_param._size_data); 47 47 48 48 //-----[ Shift logic Right ]------------------------------------------- 49 49 if (_param._have_shift_logic_right) 50 vhdl .set_signal ("shift_logic_right_"+toString(i)+" ",_param._size_data);50 vhdl->set_signal ("shift_logic_right_"+toString(i)+" ",_param._size_data); 51 51 52 52 //-----[ Shift arithmetic Left ]--------------------------------------- 53 53 if (_param._have_shift_arithmetic_left) 54 vhdl .set_signal ("shift_arithmetic_left_"+toString(i)+" ",_param._size_data);54 vhdl->set_signal ("shift_arithmetic_left_"+toString(i)+" ",_param._size_data); 55 55 56 56 //-----[ Shift arithmetic Right ]-------------------------------------- 57 57 if (_param._have_shift_arithmetic_right) 58 vhdl .set_signal ("shift_arithmetic_right_"+toString(i)+"",_param._size_data);58 vhdl->set_signal ("shift_arithmetic_right_"+toString(i)+"",_param._size_data); 59 59 60 60 //-----[ Rotate Left ]------------------------------------------------- 61 61 if (_param._have_rotate_left) 62 vhdl .set_signal ("rotate_left_"+toString(i)+" ",_param._size_data);62 vhdl->set_signal ("rotate_left_"+toString(i)+" ",_param._size_data); 63 63 64 64 //-----[ Rotate Right ]------------------------------------------------ 65 65 if (_param._have_rotate_right) 66 vhdl .set_signal ("rotate_right_"+toString(i)+" ",_param._size_data);66 vhdl->set_signal ("rotate_right_"+toString(i)+" ",_param._size_data); 67 67 } 68 68 }; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Shifter_vhdl_port.cpp
r2 r42 15 15 16 16 17 void Shifter::vhdl_port (Vhdl & vhdl)17 void Shifter::vhdl_port (Vhdl * & vhdl) 18 18 { 19 for (uint32_t i=0; i<_param._nb_port; i++) 20 { 21 vhdl.set_port (" in_SHIFTER_DATA_"+toString(i)+" ", IN, _param._size_data); 22 if (_param._shift_value == 0) 23 vhdl.set_port (" in_SHIFTER_SHIFT_"+toString(i)+" ", IN, static_cast<uint32_t>(ceil(log2(_param._size_data)))); 24 if (_param._direction == external_direction) 25 vhdl.set_port (" in_SHIFTER_DIRECTION_"+toString(i)+" ", IN, 1); 26 if (_param._rotate == external_rotate) 27 vhdl.set_port (" in_SHIFTER_TYPE_"+toString(i)+" ", IN, 1); 28 if (_param._carry == external_carry) 29 vhdl.set_port (" in_SHIFTER_CARRY_"+toString(i)+" ", IN, 1); 30 if (_param._carry == external_completion) 31 if (_param._type_completion_bool == true) 32 vhdl.set_port (" in_SHIFTER_CARRY_IN_"+toString(i)+" ", IN, 1); 33 else 34 vhdl.set_port (" in_SHIFTER_COMPLETION_"+toString(i)+"", IN, _param._size_data_completion); 35 36 vhdl.set_port ("out_SHIFTER_DATA_"+toString(i)+" ",OUT, _param._size_data); 37 } 19 _interfaces->set_port(vhdl); 38 20 }; 39 21 }; // end namespace shifter -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Shifter_vhdl_testbench_transition.cpp
r2 r42 15 15 16 16 17 void Shifter::vhdl_testbench_transition ( Vhdl_Testbench & vhdl_testbench)17 void Shifter::vhdl_testbench_transition (void) 18 18 { 19 #ifndef SYSTEMCASS_SPECIFIC 20 sc_cycle(0); 21 #endif 19 sc_start(0); 22 20 23 // In order with file Shifter_vhdl_testbench_port.cpp 24 25 for (uint32_t i=0; i<_param._nb_port; i++) 26 { 27 vhdl_testbench.add_input (PORT_READ( in_SHIFTER_DATA [i])); 28 if (_param._shift_value == 0) 29 vhdl_testbench.add_input (PORT_READ( in_SHIFTER_SHIFT [i])); 30 if (_param._direction == external_direction) 31 vhdl_testbench.add_input (PORT_READ( in_SHIFTER_DIRECTION [i])); 32 if (_param._rotate == external_rotate) 33 vhdl_testbench.add_input (PORT_READ( in_SHIFTER_TYPE [i])); 34 if (_param._carry == external_carry) 35 vhdl_testbench.add_input (PORT_READ( in_SHIFTER_CARRY [i])); 36 if (_param._carry == external_completion) 37 if (_param._type_completion_bool == true) 38 vhdl_testbench.add_input (PORT_READ( in_SHIFTER_CARRY_IN [i])); 39 else 40 vhdl_testbench.add_input (PORT_READ( in_SHIFTER_COMPLETION[i])); 41 vhdl_testbench.add_output (PORT_READ(out_SHIFTER_DATA [i])); 42 } 43 44 // add_test : 45 // - True : the cycle must be compare with the output of systemC 46 // - False : no test 47 vhdl_testbench.add_test(true); 48 49 vhdl_testbench.new_cycle (); // always at the end 21 _interfaces->testbench(); 50 22 }; 51 23 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/SelfTest/configuration.cfg
r15 r42 1 1 Victim_Pseudo_LRU 2 4 4*2 # nb_entity3 1 1 +2 # nb_access4 1 1 +2 # nb_update5 1 1 2 4 16 *2 # nb_entity 3 1 4 *2 # nb_access 4 1 4 *2 # nb_update 5 1 16 *2 # size_table -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/include/Victim_Pseudo_LRU.h
r15 r42 40 40 #include "Behavioural/include/Vhdl.h" 41 41 #endif 42 #ifdef VHDL_TESTBENCH 43 #include "Behavioural/include/Vhdl_Testbench.h" 42 #ifdef POSITION 43 #include "Behavioural/include/Component.h" 44 #else 45 #include "Behavioural/include/Interfaces.h" 44 46 #endif 45 47 … … 175 177 #endif 176 178 177 #ifdef VHDL_TESTBENCH 178 private : Vhdl_Testbench * _vhdl_testbench; 179 #endif 179 #ifdef POSITION 180 private : Component * _component; 181 #endif 182 private : Interfaces * _interfaces; 180 183 181 184 #ifdef SYSTEMC … … 237 240 #if VHDL 238 241 public : void vhdl (void); 239 private : void vhdl_port (Vhdl & vhdl);240 private : void vhdl_declaration (Vhdl & vhdl);241 private : void vhdl_body (Vhdl & vhdl);242 private : void vhdl_port (Vhdl * & vhdl); 243 private : void vhdl_declaration (Vhdl * & vhdl); 244 private : void vhdl_body (Vhdl * & vhdl); 242 245 #endif 243 246 244 247 #ifdef VHDL_TESTBENCH 245 private : void vhdl_testbench (Vhdl_Testbench & vhdl_testbench); 246 private : void vhdl_testbench_port (Vhdl_Testbench & vhdl_testbench); 247 private : void vhdl_testbench_transition (Vhdl_Testbench & vhdl_testbench); 248 private : void vhdl_testbench_transition (void); 248 249 #endif 249 250 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/src/Victim_Pseudo_LRU.cpp
r15 r42 28 28 log_printf(FUNC,Victim_Pseudo_LRU,"Victim_Pseudo_LRU","Begin"); 29 29 30 #ifdef SYSTEMC 31 log_printf(TRACE,Victim_Pseudo_LRU,"Victim_Pseudo_LRU","Allocation"); 32 allocation (); 33 #endif 34 30 35 #ifdef STATISTICS 31 36 log_printf(TRACE,Victim_Pseudo_LRU,"Victim_Pseudo_LRU","Allocation of statistics"); … … 37 42 #endif 38 43 39 #ifdef VHDL_TESTBENCH40 // Creation of a testbench41 // -> port42 // -> clock's signals43 log_printf(TRACE,Victim_Pseudo_LRU,"Victim_Pseudo_LRU","Creation of Testbench");44 _vhdl_testbench = new Vhdl_Testbench (_name);45 vhdl_testbench_port (*_vhdl_testbench);46 _vhdl_testbench->set_clock ("in_CLOCK",true);47 #endif48 49 44 #ifdef VHDL 50 45 // generate the vhdl … … 54 49 55 50 #ifdef SYSTEMC 56 log_printf(TRACE,Victim_Pseudo_LRU,"Victim_Pseudo_LRU","Allocation");57 allocation ();58 59 51 log_printf(TRACE,Victim_Pseudo_LRU,"Victim_Pseudo_LRU","Definition of sc_method"); 60 52 SC_METHOD (transition); … … 100 92 #endif 101 93 102 #ifdef VHDL_TESTBENCH103 // generate the test bench104 _vhdl_testbench->generate_file();105 delete _vhdl_testbench;106 #endif107 108 94 #ifdef STATISTICS 109 95 _stat->generate_file(statistics(0)); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/src/Victim_Pseudo_LRU_allocation.cpp
r15 r42 17 17 void Victim_Pseudo_LRU::allocation (void) 18 18 { 19 in_CLOCK = new SC_CLOCK ("in_CLOCK"); 20 in_NRESET = new SC_IN (Tcontrol_t) ("in_NRESET");19 #ifdef POSITION 20 _component = new Component (); 21 21 22 // -----[ Interface access ]------------------------------------------- 23 in_ACCESS_VAL = new SC_IN (Tcontrol_t) * [_param._nb_access]; 24 out_ACCESS_ACK = new SC_OUT(Tcontrol_t) * [_param._nb_access]; 25 if (_param._size_table>1) 26 in_ACCESS_ADDRESS = new SC_IN (Taddress_t) * [_param._nb_access]; 27 out_ACCESS_ENTITY = new SC_OUT(Tentity_t ) * [_param._nb_access]; 22 Entity * entity = _component->set_entity (_name , 23 "Select_Priority_Fixed", 24 COMBINATORY ); 28 25 29 for (uint32_t i=0; i<_param._nb_access; i++) 30 { 31 string rename; 26 _interfaces = entity->set_interfaces(); 27 #else 28 _interfaces = new Interfaces(); 29 #endif 32 30 33 rename = "in_ACCESS_VAL[" + toString(i) + "]"; 34 in_ACCESS_VAL [i] = new SC_IN (Tcontrol_t) (rename.c_str()); 31 // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 32 { 33 Interface_fifo * interface = _interfaces->set_interface("", IN ,WEST, "Generalist interface"); 34 35 in_CLOCK = interface->set_signal_clk ("clock" ,1); 36 in_NRESET = interface->set_signal_in <Tcontrol_t> ("nreset",1); 37 } 35 38 36 rename = "out_ACCESS_ACK[" + toString(i) + "]"; 37 out_ACCESS_ACK [i] = new SC_OUT(Tcontrol_t) (rename.c_str()); 39 // ~~~~~[ Interface : "access" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 40 { 41 in_ACCESS_VAL = new SC_IN (Tcontrol_t) * [_param._nb_access]; 42 out_ACCESS_ACK = new SC_OUT(Tcontrol_t) * [_param._nb_access]; 43 if (_param._size_table>1) 44 in_ACCESS_ADDRESS = new SC_IN (Taddress_t) * [_param._nb_access]; 45 out_ACCESS_ENTITY = new SC_OUT(Tentity_t ) * [_param._nb_access]; 46 47 for (uint32_t i=0; i<_param._nb_access; i++) 48 { 49 Interface_fifo * interface = _interfaces->set_interface("access_"+toString(i), IN ,WEST, "Access"); 38 50 39 if (_param._size_table>1)40 {41 rename = "in_ACCESS_ADDRESS[" + toString(i) + "]";42 in_ACCESS_ADDRESS [i] = new SC_IN (Taddress_t) (rename.c_str());43 }44 rename = "out_ACCESS_ENTITY[" + toString(i) + "]";45 out_ACCESS_ENTITY [i] = new SC_OUT(Tentity_t ) (rename.c_str());46 51 in_ACCESS_VAL [i] = interface->set_signal_valack_in ("val" , VAL); 52 out_ACCESS_ACK [i] = interface->set_signal_valack_out ("ack" , ACK); 53 54 if (_param._size_table>1) 55 in_ACCESS_ADDRESS [i] = interface->set_signal_in <Taddress_t> ("address",static_cast<uint32_t>(log2(_param._size_table))); 56 out_ACCESS_ENTITY [i] = interface->set_signal_out <Tentity_t> ("entity" ,static_cast<uint32_t>(log2(_param._nb_entity ))); 57 } 58 } 47 59 48 // -----[ Interface update ]------------------------------------------- 49 in_UPDATE_VAL = new SC_IN (Tcontrol_t) * [_param._nb_update]; 50 out_UPDATE_ACK = new SC_OUT(Tcontrol_t) * [_param._nb_update]; 51 if (_param._size_table>1) 52 in_UPDATE_ADDRESS = new SC_IN (Taddress_t) * [_param._nb_update]; 53 in_UPDATE_ENTITY = new SC_IN (Tentity_t ) * [_param._nb_update]; 60 // ~~~~~[ Interface : "update" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 61 62 { 63 in_UPDATE_VAL = new SC_IN (Tcontrol_t) * [_param._nb_update]; 64 out_UPDATE_ACK = new SC_OUT(Tcontrol_t) * [_param._nb_update]; 65 if (_param._size_table>1) 66 in_UPDATE_ADDRESS = new SC_IN (Taddress_t) * [_param._nb_update]; 67 in_UPDATE_ENTITY = new SC_IN (Tentity_t ) * [_param._nb_update]; 68 69 for (uint32_t i=0; i<_param._nb_update; i++) 70 { 71 Interface_fifo * interface = _interfaces->set_interface("update_"+toString(i), IN ,EAST, "Update"); 54 72 55 for (uint32_t i=0; i<_param._nb_update; i++) 56 { 57 string rename; 58 59 rename = "in_UPDATE_VAL[" + toString(i) + "]"; 60 in_UPDATE_VAL [i] = new SC_IN (Tcontrol_t) (rename.c_str()); 61 62 rename = "out_UPDATE_ACK[" + toString(i) + "]";; 63 out_UPDATE_ACK [i] = new SC_OUT(Tcontrol_t) (rename.c_str()); 64 65 if (_param._size_table>1) 66 { 67 rename = "in_UPDATE_ADDRESS[" + toString(i) + "]"; 68 in_UPDATE_ADDRESS [i] = new SC_IN (Taddress_t) (rename.c_str()); 69 } 70 71 rename = "in_UPDATE_ENTITY[" + toString(i) + "]"; 72 in_UPDATE_ENTITY [i] = new SC_IN (Tentity_t ) (rename.c_str()); 73 } 74 73 in_UPDATE_VAL [i] = interface->set_signal_valack_in ("val" , VAL); 74 out_UPDATE_ACK [i] = interface->set_signal_valack_out ("ack" , ACK); 75 if (_param._size_table>1) 76 in_UPDATE_ADDRESS [i] = interface->set_signal_in <Taddress_t> ("address",static_cast<uint32_t>(log2(_param._size_table))); 77 in_UPDATE_ENTITY [i] = interface->set_signal_in <Tentity_t> ("entity" ,static_cast<uint32_t>(log2(_param._nb_entity ))); 78 } 79 } 75 80 // -----[ Register ]--------------------------------------------------- 76 81 reg_TABLE = new entry_t * [_param._size_table]; … … 81 86 // -----[ Internal ]--------------------------------------------------- 82 87 internal_ACCESS_ENTITY = new Tentity_t [_param._nb_entity]; 88 89 #ifdef POSITION 90 _component->generate_file(); 91 #endif 83 92 }; 84 93 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/src/Victim_Pseudo_LRU_deallocation.cpp
r15 r42 17 17 void Victim_Pseudo_LRU::deallocation (void) 18 18 { 19 delete in_CLOCK;20 delete in_NRESET;19 delete in_CLOCK; 20 delete in_NRESET; 21 21 // -----[ Interface access ]------------------------------------------- 22 for (uint32_t i=0; i<_param._nb_access; i++) 23 { 24 delete in_ACCESS_VAL [i]; 25 delete out_ACCESS_ACK [i]; 26 if (_param._size_table>1) 27 delete in_ACCESS_ADDRESS [i]; 28 delete out_ACCESS_ENTITY [i]; 29 } 30 31 delete in_ACCESS_VAL ; 32 delete out_ACCESS_ACK ; 22 delete [] in_ACCESS_VAL ; 23 delete [] out_ACCESS_ACK ; 33 24 if (_param._size_table>1) 34 delete in_ACCESS_ADDRESS;35 delete out_ACCESS_ENTITY ;25 delete [] in_ACCESS_ADDRESS; 26 delete [] out_ACCESS_ENTITY ; 36 27 37 28 // -----[ Interface update ]------------------------------------------- 38 for (uint32_t i=0; i<_param._nb_update; i++) 39 { 40 delete in_UPDATE_VAL [i]; 41 delete out_UPDATE_ACK [i]; 42 if (_param._size_table>1) 43 delete in_UPDATE_ADDRESS [i]; 44 delete in_UPDATE_ENTITY [i]; 45 } 46 delete in_UPDATE_VAL ; 47 delete out_UPDATE_ACK ; 29 delete [] in_UPDATE_VAL ; 30 delete [] out_UPDATE_ACK ; 48 31 if (_param._size_table>1) 49 delete in_UPDATE_ADDRESS;50 delete in_UPDATE_ENTITY ;32 delete [] in_UPDATE_ADDRESS; 33 delete [] in_UPDATE_ENTITY ; 51 34 52 35 // -----[ Register ]--------------------------------------------------- 53 for (uint32_t i=0; i<_param._size_table; i++) 54 { 55 delete reg_TABLE [i]; 56 } 57 delete reg_TABLE; 36 delete [] reg_TABLE; 58 37 59 38 // -----[ Internal ]--------------------------------------------------- 60 delete internal_ACCESS_ENTITY; 39 delete [] internal_ACCESS_ENTITY; 40 41 #ifdef POSITION 42 delete _component; 43 #else 44 delete _interfaces; 45 #endif 61 46 }; 62 47 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/src/Victim_Pseudo_LRU_transition.cpp
r15 r42 67 67 68 68 #ifdef VHDL_TESTBENCH 69 vhdl_testbench_transition ( *_vhdl_testbench);69 vhdl_testbench_transition (); 70 70 #endif 71 71 }; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/src/Victim_Pseudo_LRU_vhdl.cpp
r15 r42 22 22 23 23 log_printf(TRACE,Victim_Pseudo_LRU,"vhdl","Construction of vhdl"); 24 Vhdl vhdl (_name);24 Vhdl * vhdl = new Vhdl (_name); 25 25 26 26 log_printf(TRACE,Victim_Pseudo_LRU,"vhdl","Set library"); 27 vhdl .set_library_work (_name + "_Pack");27 vhdl->set_library_work (_name + "_Pack"); 28 28 29 29 log_printf(TRACE,Victim_Pseudo_LRU,"vhdl","Set port"); … … 34 34 vhdl_body (vhdl); 35 35 log_printf(TRACE,Victim_Pseudo_LRU,"vhdl","Generate File"); 36 vhdl.generate_file(); 36 vhdl->generate_file(); 37 38 delete vhdl; 37 39 log_printf(FUNC,Victim_Pseudo_LRU,"vhdl","End"); 38 40 }; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/src/Victim_Pseudo_LRU_vhdl_body.cpp
r15 r42 15 15 namespace victim_pseudo_lru { 16 16 17 void Victim_Pseudo_LRU::vhdl_body (Vhdl & vhdl)17 void Victim_Pseudo_LRU::vhdl_body (Vhdl * & vhdl) 18 18 { 19 vhdl .set_body ("");20 vhdl .set_body ("-----------------------------------------------------------------------------");21 vhdl .set_body ("-- Access");22 vhdl .set_body ("-----------------------------------------------------------------------------");23 vhdl .set_body ("");24 vhdl .set_body ("-- Tree of Pseudo-LRU - example to 8 entity");25 vhdl .set_body ("--");26 vhdl .set_body ("-- 4-5-6-7? ");27 vhdl .set_body ("-- 0_______|_______1 ");28 vhdl .set_body ("-- | | ");29 vhdl .set_body ("-- 2-3? 6-7? ");30 vhdl .set_body ("-- 0___|___1 0___|___1 ");31 vhdl .set_body ("-- | | | | ");32 vhdl .set_body ("-- 1? 3? 5? 7? ");33 vhdl .set_body ("-- 0_|_1 0_|_1 0_|_1 0_|_1 ");34 vhdl .set_body ("-- | | | | | | | | ");35 vhdl .set_body ("-- Way Way Way Way Way Way Way Way ");36 vhdl .set_body ("-- 0 1 2 3 4 5 6 7 ");37 for (uint32_t i=0; i<_param._nb_access; i++) 38 { 39 vhdl .set_body ("");19 vhdl->set_body (""); 20 vhdl->set_body ("-----------------------------------------------------------------------------"); 21 vhdl->set_body ("-- Access"); 22 vhdl->set_body ("-----------------------------------------------------------------------------"); 23 vhdl->set_body (""); 24 vhdl->set_body ("-- Tree of Pseudo-LRU - example to 8 entity"); 25 vhdl->set_body ("--"); 26 vhdl->set_body ("-- 4-5-6-7? "); 27 vhdl->set_body ("-- 0_______|_______1 "); 28 vhdl->set_body ("-- | | "); 29 vhdl->set_body ("-- 2-3? 6-7? "); 30 vhdl->set_body ("-- 0___|___1 0___|___1 "); 31 vhdl->set_body ("-- | | | | "); 32 vhdl->set_body ("-- 1? 3? 5? 7? "); 33 vhdl->set_body ("-- 0_|_1 0_|_1 0_|_1 0_|_1 "); 34 vhdl->set_body ("-- | | | | | | | | "); 35 vhdl->set_body ("-- Way Way Way Way Way Way Way Way "); 36 vhdl->set_body ("-- 0 1 2 3 4 5 6 7 "); 37 for (uint32_t i=0; i<_param._nb_access; i++) 38 { 39 vhdl->set_body (""); 40 40 // Read the table 41 41 … … 43 43 44 44 if (_param._size_table>1) 45 access_address = "conv_integer(in_ACCESS_ ADDRESS_"+toString(i)+")";45 access_address = "conv_integer(in_ACCESS_"+toString(i)+"_ADDRESS)"; 46 46 else 47 47 access_address = "0"; 48 48 49 vhdl .set_body ("access_entry_"+toString(i)+" <= reg_TABLE ("+access_address+");");50 vhdl .set_body ("");49 vhdl->set_body ("access_entry_"+toString(i)+" <= reg_TABLE ("+access_address+");"); 50 vhdl->set_body (""); 51 51 52 52 for (int32_t j=static_cast<uint32_t>(log2(_param._nb_entity)-1); j>=0; j--) 53 53 { 54 vhdl .set_body ("access_entity_"+toString(i)+"("+toString(j)+") <= ");54 vhdl->set_body ("access_entity_"+toString(i)+"("+toString(j)+") <= "); 55 55 56 56 uint32_t cpt=0; … … 72 72 string print_else = (k==(1<<j)-1)?" ":"else "; 73 73 74 vhdl .set_body ("\t"+print_else+"access_entry_"+toString(i)+"("+toString(k)+") "+cond);74 vhdl->set_body ("\t"+print_else+"access_entry_"+toString(i)+"("+toString(k)+") "+cond); 75 75 cpt ++; 76 76 } 77 vhdl .set_body ("\t;");77 vhdl->set_body ("\t;"); 78 78 } 79 79 } 80 80 81 vhdl .set_body ("");82 vhdl .set_body ("-----------------------------------------------------------------------------");83 vhdl .set_body ("-- Update");84 vhdl .set_body ("-----------------------------------------------------------------------------");85 vhdl .set_body ("");86 vhdl .set_body ("-- port access");81 vhdl->set_body (""); 82 vhdl->set_body ("-----------------------------------------------------------------------------"); 83 vhdl->set_body ("-- Update"); 84 vhdl->set_body ("-----------------------------------------------------------------------------"); 85 vhdl->set_body (""); 86 vhdl->set_body ("-- port access"); 87 87 for (uint32_t i=0; i<_param._nb_access; i++) 88 88 for (int32_t j=static_cast<uint32_t>(log2(_param._nb_entity)-1); j>=0; j--) … … 107 107 } 108 108 109 vhdl .set_body ("access_next_entry_"+toString(i)+"("+toString(k)+") <=");110 vhdl .set_body ("\tnot access_entity_"+toString(i)+"("+toString(j)+") "+cond);109 vhdl->set_body ("access_next_entry_"+toString(i)+"("+toString(k)+") <="); 110 vhdl->set_body ("\tnot access_entity_"+toString(i)+"("+toString(j)+") "+cond); 111 111 if (have_cond == true) 112 vhdl .set_body ("\telse access_entry_"+toString(i)+"("+toString(k)+")");113 vhdl .set_body ("\t;");112 vhdl->set_body ("\telse access_entry_"+toString(i)+"("+toString(k)+")"); 113 vhdl->set_body ("\t;"); 114 114 cpt ++; 115 115 } 116 116 } 117 117 118 vhdl .set_body ("");119 vhdl .set_body ("-- port update");118 vhdl->set_body (""); 119 vhdl->set_body ("-- port update"); 120 120 for (uint32_t i=0; i<_param._nb_update; i++) 121 121 for (int32_t j=static_cast<uint32_t>(log2(_param._nb_entity)-1); j>=0; j--) … … 137 137 else 138 138 cond += " and"; 139 cond += " in_UPDATE_ ENTITY_"+toString(i)+"("+toString(l)+")='"+toString((cpt>>(l-(j+1)))&1)+"'";139 cond += " in_UPDATE_"+toString(i)+"_ENTITY("+toString(l)+")='"+toString((cpt>>(l-(j+1)))&1)+"'"; 140 140 } 141 141 142 vhdl .set_body ("update_next_entry_"+toString(i)+"("+toString(k)+") <=");143 vhdl .set_body ("\tnot in_UPDATE_ENTITY_"+toString(i)+"("+toString(j)+") "+cond);142 vhdl->set_body ("update_next_entry_"+toString(i)+"("+toString(k)+") <="); 143 vhdl->set_body ("\tnot in_UPDATE_"+toString(i)+"_ENTITY("+toString(j)+") "+cond); 144 144 if (have_cond == true) 145 145 { … … 147 147 148 148 if (_param._size_table>1) 149 update_address = "conv_integer(in_UPDATE_ ADDRESS_"+toString(i)+")";149 update_address = "conv_integer(in_UPDATE_"+toString(i)+"_ADDRESS)"; 150 150 else 151 151 update_address = "0"; 152 152 153 vhdl .set_body ("\telse reg_TABLE ("+update_address+")("+toString(k)+")");153 vhdl->set_body ("\telse reg_TABLE ("+update_address+")("+toString(k)+")"); 154 154 } 155 vhdl .set_body ("\t;");155 vhdl->set_body ("\t;"); 156 156 cpt ++; 157 157 } 158 158 } 159 159 160 vhdl .set_body ("");161 vhdl .set_body ("-----------------------------------------------------------------------------");162 vhdl .set_body ("-- Transition");163 vhdl .set_body ("-----------------------------------------------------------------------------");164 vhdl .set_body ("");165 166 vhdl .set_body ("reg_TABLE_write: process (in_CLOCK)");167 vhdl .set_body ("begin");168 vhdl .set_body ("\tif in_CLOCK'event and in_CLOCK = '1' then");169 vhdl .set_body ("\t\t-- Access port");160 vhdl->set_body (""); 161 vhdl->set_body ("-----------------------------------------------------------------------------"); 162 vhdl->set_body ("-- Transition"); 163 vhdl->set_body ("-----------------------------------------------------------------------------"); 164 vhdl->set_body (""); 165 166 vhdl->set_body ("reg_TABLE_write: process (in_CLOCK)"); 167 vhdl->set_body ("begin"); 168 vhdl->set_body ("\tif in_CLOCK'event and in_CLOCK = '1' then"); 169 vhdl->set_body ("\t\t-- Access port"); 170 170 for (uint32_t i=0; i<_param._nb_access; i++) 171 171 { … … 173 173 174 174 if (_param._size_table>1) 175 access_address = "conv_integer(in_ACCESS_ ADDRESS_"+toString(i)+")";175 access_address = "conv_integer(in_ACCESS_"+toString(i)+"_ADDRESS)"; 176 176 else 177 177 access_address = "0"; 178 178 179 vhdl .set_body ("\t\tif (in_ACCESS_VAL_"+toString(i)+"= '1') then");180 vhdl .set_body ("\t\t\treg_TABLE ("+access_address+") <= access_next_entry_"+toString(i)+";");181 vhdl .set_body ("\t\tend if;");182 } 183 184 vhdl .set_body ("\t\t-- Update port");179 vhdl->set_body ("\t\tif (in_ACCESS_"+toString(i)+"_VAL = '1') then"); 180 vhdl->set_body ("\t\t\treg_TABLE ("+access_address+") <= access_next_entry_"+toString(i)+";"); 181 vhdl->set_body ("\t\tend if;"); 182 } 183 184 vhdl->set_body ("\t\t-- Update port"); 185 185 for (uint32_t i=0; i<_param._nb_update; i++) 186 186 { … … 188 188 189 189 if (_param._size_table>1) 190 update_address = "conv_integer(in_UPDATE_ ADDRESS_"+toString(i)+")";190 update_address = "conv_integer(in_UPDATE_"+toString(i)+"_ADDRESS)"; 191 191 else 192 192 update_address = "0"; 193 193 194 vhdl .set_body ("\t\tif (in_UPDATE_VAL_"+toString(i)+"= '1') then");195 vhdl .set_body ("\t\t\treg_TABLE ("+update_address+") <= update_next_entry_"+toString(i)+";");196 vhdl .set_body ("\t\tend if;");197 } 198 199 vhdl .set_body ("\tend if;");200 vhdl .set_body ("end process reg_TABLE_write;");201 202 vhdl .set_body ("");203 vhdl .set_body ("-----------------------------------------------------------------------------");204 vhdl .set_body ("-- Output");205 vhdl .set_body ("-----------------------------------------------------------------------------");206 vhdl .set_body ("");207 vhdl .set_body ("-- Ack is always ");208 vhdl .set_body ("");209 for (uint32_t i=0; i<_param._nb_access; i++) 210 { 211 vhdl .set_body ("out_ACCESS_ACK_"+toString(i)+"<= '1';");212 vhdl .set_body ("out_ACCESS_ENTITY_"+toString(i)+" <= access_entity_"+toString(i)+" when in_ACCESS_VAL_"+toString(i)+"= '1' else (others => '0');");213 } 214 vhdl .set_body ("");194 vhdl->set_body ("\t\tif (in_UPDATE_"+toString(i)+"_VAL = '1') then"); 195 vhdl->set_body ("\t\t\treg_TABLE ("+update_address+") <= update_next_entry_"+toString(i)+";"); 196 vhdl->set_body ("\t\tend if;"); 197 } 198 199 vhdl->set_body ("\tend if;"); 200 vhdl->set_body ("end process reg_TABLE_write;"); 201 202 vhdl->set_body (""); 203 vhdl->set_body ("-----------------------------------------------------------------------------"); 204 vhdl->set_body ("-- Output"); 205 vhdl->set_body ("-----------------------------------------------------------------------------"); 206 vhdl->set_body (""); 207 vhdl->set_body ("-- Ack is always "); 208 vhdl->set_body (""); 209 for (uint32_t i=0; i<_param._nb_access; i++) 210 { 211 vhdl->set_body ("out_ACCESS_"+toString(i)+"_ACK <= '1';"); 212 vhdl->set_body ("out_ACCESS_"+toString(i)+"_ENTITY <= access_entity_"+toString(i)+" when in_ACCESS_"+toString(i)+"_VAL = '1' else (others => '0');"); 213 } 214 vhdl->set_body (""); 215 215 for (uint32_t i=0; i<_param._nb_update; i++) 216 216 { 217 vhdl .set_body ("out_UPDATE_ACK_"+toString(i)+"<= '1';");217 vhdl->set_body ("out_UPDATE_"+toString(i)+"_ACK <= '1';"); 218 218 } 219 219 }; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/src/Victim_Pseudo_LRU_vhdl_declaration.cpp
r15 r42 16 16 17 17 18 void Victim_Pseudo_LRU::vhdl_declaration (Vhdl & vhdl)18 void Victim_Pseudo_LRU::vhdl_declaration (Vhdl * & vhdl) 19 19 { 20 vhdl .set_type ("Ttable", "array (" + toString(_param._size_table-1) + " downto 0) of "+std_logic(_param._nb_entity-1));20 vhdl->set_type ("Ttable", "array (" + toString(_param._size_table-1) + " downto 0) of "+std_logic(_param._nb_entity-1)); 21 21 22 22 23 vhdl .set_signal ("reg_TABLE", "Ttable");23 vhdl->set_signal ("reg_TABLE", "Ttable"); 24 24 for (uint32_t i=0; i<_param._nb_access; i++) 25 25 { 26 vhdl .set_signal ("access_entry_"+toString(i)+" ",std_logic(_param._nb_entity-1));27 vhdl .set_signal ("access_next_entry_"+toString(i)+"",std_logic(_param._nb_entity-1));28 vhdl .set_signal ("access_entity_"+toString(i)+" ",std_logic(static_cast<uint32_t>(log2(_param._nb_entity))));26 vhdl->set_signal ("access_entry_"+toString(i)+" ",std_logic(_param._nb_entity-1)); 27 vhdl->set_signal ("access_next_entry_"+toString(i)+"",std_logic(_param._nb_entity-1)); 28 vhdl->set_signal ("access_entity_"+toString(i)+" ",std_logic(static_cast<uint32_t>(log2(_param._nb_entity)))); 29 29 } 30 30 31 31 for (uint32_t i=0; i<_param._nb_update; i++) 32 32 { 33 vhdl .set_signal ("update_next_entry_"+toString(i)+"",std_logic(_param._nb_entity-1));33 vhdl->set_signal ("update_next_entry_"+toString(i)+"",std_logic(_param._nb_entity-1)); 34 34 } 35 35 }; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/src/Victim_Pseudo_LRU_vhdl_port.cpp
r15 r42 16 16 17 17 18 void Victim_Pseudo_LRU::vhdl_port (Vhdl & vhdl)18 void Victim_Pseudo_LRU::vhdl_port (Vhdl * & vhdl) 19 19 { 20 vhdl.set_port ("in_CLOCK ", IN, 1); 21 vhdl.set_port ("in_NRESET", IN, 1); 22 23 for (uint32_t i = 0; i < _param._nb_access; i ++) 24 { 25 vhdl.set_port (" in_ACCESS_VAL_"+toString(i)+" ",IN ,std_logic(1)); 26 vhdl.set_port ("out_ACCESS_ACK_"+toString(i)+" ",OUT,std_logic(1)); 27 if (_param._size_table>1) 28 vhdl.set_port (" in_ACCESS_ADDRESS_"+toString(i)+" ",IN ,std_logic(static_cast<uint32_t>(log2(_param._size_table)))); 29 vhdl.set_port ("out_ACCESS_ENTITY_"+toString(i)+" ",OUT,std_logic(static_cast<uint32_t>(log2(_param._nb_entity)))); 30 } 31 32 for (uint32_t i = 0; i < _param._nb_update; i ++) 33 { 34 vhdl.set_port (" in_UPDATE_VAL_"+toString(i)+" ",IN ,std_logic(1)); 35 vhdl.set_port ("out_UPDATE_ACK_"+toString(i)+" ",OUT,std_logic(1)); 36 if (_param._size_table>1) 37 vhdl.set_port (" in_UPDATE_ADDRESS_"+toString(i)+" ",IN ,std_logic(static_cast<uint32_t>(log2(_param._size_table)))); 38 vhdl.set_port (" in_UPDATE_ENTITY_"+toString(i)+" ",IN ,std_logic(static_cast<uint32_t>(log2(_param._nb_entity)))); 39 } 20 _interfaces->set_port(vhdl); 40 21 }; 41 22 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/src/Victim_Pseudo_LRU_vhdl_testbench_transition.cpp
r15 r42 16 16 17 17 18 void Victim_Pseudo_LRU::vhdl_testbench_transition ( Vhdl_Testbench & vhdl_testbench)18 void Victim_Pseudo_LRU::vhdl_testbench_transition (void) 19 19 { 20 #ifndef SYSTEMCASS_SPECIFIC 21 sc_cycle(0); 22 #endif 23 vhdl_testbench.add_input (PORT_READ(in_NRESET)); 20 // Evaluation before read the ouput signal 21 sc_start(0); 24 22 25 for (uint32_t i = 0; i < _param._nb_access; i ++) 26 { 27 vhdl_testbench.add_input (PORT_READ( in_ACCESS_VAL [i])); 28 vhdl_testbench.add_output (PORT_READ(out_ACCESS_ACK [i])); 29 if (_param._size_table>1) 30 vhdl_testbench.add_input (PORT_READ( in_ACCESS_ADDRESS [i])); 31 vhdl_testbench.add_output (PORT_READ(out_ACCESS_ENTITY [i])); 32 } 33 34 for (uint32_t i = 0; i < _param._nb_update; i ++) 35 { 36 vhdl_testbench.add_input (PORT_READ( in_UPDATE_VAL [i])); 37 vhdl_testbench.add_output (PORT_READ(out_UPDATE_ACK [i])); 38 if (_param._size_table>1) 39 vhdl_testbench.add_input (PORT_READ( in_UPDATE_ADDRESS [i])); 40 vhdl_testbench.add_input (PORT_READ( in_UPDATE_ENTITY [i])); 41 } 42 43 vhdl_testbench.add_test(true); 44 45 vhdl_testbench.new_cycle (); // always at the end 23 _interfaces->testbench(); 46 24 }; 47 25 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.Selftest
r40 r42 96 96 $(DIR_LOG)/%.exec.log : $(DIR_CFG_GEN)/%.cfg $(DIR_BIN)/$(EXEC).x 97 97 @$(ECHO) "Execute : $*" 98 @$(EXPORT) SYSTEMC=$(SYSTEMC_$(SIMULATOR)) ; $(VALGRIND)./$(DIR_BIN)/$(EXEC).x $(EXEC_PARAMS) $* `$(CAT) $<` &> $@99 declare -i count=`$(GREP) -ch "Test KO" $@`; \100 if $(TEST) $$count - eq0; \98 @$(EXPORT) SYSTEMC=$(SYSTEMC_$(SIMULATOR)) ; ./$(DIR_BIN)/$(EXEC).x $(EXEC_PARAMS) $* `$(CAT) $<` &> $@ 99 declare -i count=`$(GREP) -ch "Test OK" $@`; \ 100 if $(TEST) $$count -ne 0; \ 101 101 then echo " $* ... OK"; \ 102 102 else echo " $* ... KO"; exit 1; \ … … 119 119 @$(MKDIR) $@ 120 120 121 selftest_clean_all : library_clean config_clean121 selftest_clean_all : library_clean 122 122 123 selftest_clean : 123 selftest_clean : config_clean 124 124 @$(RM) $(DIR_LOG) \ 125 125 $(DIR_CFG_USER)/*~ \ -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.Synthesis
r40 r42 69 69 @$(ECHO) "VHDL's Simulation : $*" 70 70 @$(MODELTECH_VSIM) "$(DIR_WORK).`$(BASENAME) $* |$(UPPERtoLOWER)`" &> $@ 71 declare -i count=`$(GREP) -ch "Test KO" $@`; \72 if $(TEST) $$count - eq0; \71 declare -i count=`$(GREP) -ch "Test OK" $@`; \ 72 if $(TEST) $$count -ne 0; \ 73 73 then echo " $* ... OK"; \ 74 74 else echo " $* ... KO"; exit 1; \ -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.flags
r40 r42 17 17 -DVHDL \ 18 18 -DVHDL_TESTBENCH \ 19 -DCONFIGURATION \ 20 -DPOSITION \ 21 -DSTATISTICS \ 19 -DVHDL_TESTBENCH_ASSERT \ 22 20 -DDEBUG=DEBUG_NONE 23 21 22 # -DCONFIGURATION \ 23 # -DSTATISTICS \ 24 # -DPOSITION \ 25 24 26 # Flags : 25 # DEBUG={level} - Print Debug Message 26 # SYSTEMC - To generate a systemc's model 27 # VHDL - To generate a vhdl's models 28 # VHDL_TESTBENCH (need SYSTEMC) - In the simulation, generate two testbench's file (input and ouput) to validate the vhdl's model 29 # STATISTICS (need SYSTEMC) - In the simulation, generate a statistics's file 30 # POSITION - To generate a position's files (it's input of viewer) 31 # CONFIGURATION - To generate a configuration's file (it's input of viewer and generator) 27 # DEBUG={level} - Print Debug Message 28 # SYSTEMC - To generate a systemc's model 29 # VHDL - To generate a vhdl's models 30 # VHDL_TESTBENCH (need SYSTEMC) - In the simulation, generate two testbench's file (input and ouput) to validate the vhdl's model 31 # VHDL_TESTBENCH_ASSERT (need SYSTEMC) - In the simulation, generate in testbench's file an serie of assert 32 # STATISTICS (need SYSTEMC) - In the simulation, generate a statistics's file 33 # POSITION - To generate a position's files (it's input of viewer) 34 # CONFIGURATION - To generate a configuration's file (it's input of viewer and generator) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.mkf
r23 r42 3 3 # 4 4 5 all: _Generic/RegisterFile/RegisterFile_Monolithic/SelfTest Generic/Select/Priority_Fixed/SelfTest 5 all: _Generic/RegisterFile/RegisterFile_Monolithic/SelfTest Generic/Select/Priority_Fixed/SelfTest _Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/SelfTest 6 6 7 7 _Generic/RegisterFile/RegisterFile_Monolithic/SelfTest: … … 10 10 Generic/Select/Priority_Fixed/SelfTest: 11 11 12 _Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/SelfTest: 13 gmake all -C Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/SelfTest 14 12 15 clean: 13 16 gmake clean -C Generic/RegisterFile/RegisterFile_Monolithic/SelfTest 17 gmake clean -C Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/SelfTest 14 18 15 19 re: clean all … … 17 21 install: 18 22 gmake install -C Generic/RegisterFile/RegisterFile_Monolithic/SelfTest 23 gmake install -C Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/SelfTest 19 24 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/include/New_Component.h
r41 r42 22 22 #include "Behavioural/@DIRECTORY/include/Statistics.h" 23 23 #endif 24 #ifdef POSITION 25 #include "Behavioural/include/Position.h" 26 #else 27 #include "Behavioural/include/Interfaces.h" 28 #endif 24 #include "Behavioural/include/Component.h" 29 25 #ifdef VHDL 30 26 #include "Behavioural/include/Vhdl.h" … … 55 51 #endif 56 52 57 #ifdef POSITION 58 private : Position * _position; 59 #endif 60 53 public : Component * _component; 61 54 private : Interfaces * _interfaces; 62 55 … … 107 100 #if VHDL 108 101 public : void vhdl (void); 109 private : void vhdl_port (Vhdl & vhdl);110 102 private : void vhdl_declaration (Vhdl & vhdl); 111 103 private : void vhdl_body (Vhdl & vhdl); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/New_Component_allocation.cpp
r40 r42 19 19 log_printf(FUNC,@COMPONENT,"allocation","Begin"); 20 20 21 _component = new Component (); 22 23 Entity * entity = _component->set_entity (_name 21 24 #ifdef POSITION 22 _position = new Position (); 23 24 Entity * entity = _position->set_entity (_name , 25 "@COMPONENT", 26 COMBINATORY ); 25 ,"@COMPONENT" 26 ,COMBINATORY 27 #endif 28 ); 27 29 28 30 _interfaces = entity->set_interfaces(); 29 #else30 _interfaces = new Interfaces();31 #endif32 31 33 32 // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 34 33 35 Interface * interface_ = _interfaces->set_interface("", IN ,WEST, "Generalist interface"); 34 Interface * interface = _interfaces->set_interface("" 35 #ifdef POSITION 36 ,IN 37 ,SOUTH, 38 "Generalist interface" 39 #endif 40 ); 36 41 37 in_CLOCK = interface _->set_signal_clk ("clock" ,1, PORT_VHDL_YES_TESTBENCH_NO);38 in_NRESET = interface _->set_signal_in <Tcontrol_t> ("nreset",1);42 in_CLOCK = interface->set_signal_clk ("clock" ,1, PORT_VHDL_YES_TESTBENCH_NO); 43 in_NRESET = interface->set_signal_in <Tcontrol_t> ("nreset",1); 39 44 40 45 … … 42 47 43 48 #ifdef POSITION 44 _ position->generate_file();49 _component->generate_file(); 45 50 #endif 46 51 47 log_printf(FUNC,@COMPONENT,"allocation","End");52 Log_printf(FUNC,@COMPONENT,"allocation","End"); 48 53 }; 49 54 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/New_Component_deallocation.cpp
r40 r42 24 24 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 25 25 26 #ifdef POSITION 27 delete _position; 28 #else 29 delete _interfaces; 30 #endif 26 delete _component; 31 27 32 28 log_printf(FUNC,@COMPONENT,"deallocation","End"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/New_Component_vhdl.cpp
r40 r42 20 20 Vhdl vhdl (_name); 21 21 22 vhdl.set_library_work (_name + "_Pack"); 22 _interfaces->set_port(vhdl); 23 _component->vhdl_instance(vhdl); 23 24 24 vhdl_port (vhdl);25 25 vhdl_declaration (vhdl); 26 26 vhdl_body (vhdl); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component/src/New_Component_vhdl_port.cpp
r41 r42 13 13 @NAMESPACE_BEGIN 14 14 15 void @COMPONENT::vhdl_port (Vhdl & vhdl)16 {17 log_printf(FUNC,@COMPONENT,"vhdl_port","Begin");15 // void @COMPONENT::vhdl_port (Vhdl & vhdl) 16 // { 17 // log_printf(FUNC,@COMPONENT,"vhdl_port","Begin"); 18 18 19 _interfaces->set_port(vhdl);19 // _interfaces->set_port(vhdl); 20 20 21 log_printf(FUNC,@COMPONENT,"vhdl_port","End");22 };21 // Log_printf(FUNC,@COMPONENT,"vhdl_port","End"); 22 // }; 23 23 24 24 @NAMESPACE_END -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/SelfTest/src/test.cpp
r15 r42 96 96 97 97 98 _Branch_History_Table->vhdl_testbench_label("Initialisation");99 98 cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} Initialisation" << endl; 100 99 … … 129 128 sc_start(0); 130 129 131 _Branch_History_Table->vhdl_testbench_label("Loop of Test");132 130 cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} Loop of Test" << endl; 133 131 134 132 for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++) 135 133 { 136 _Branch_History_Table->vhdl_testbench_label("Iteration "+toString(iteration));137 134 num_port_branch_complete = rand() % param._nb_branch_complete; 138 135 num_port_predict = rand() % param._nb_prediction ; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/include/Branch_History_Table.h
r15 r42 27 27 #include "Behavioural/include/Vhdl.h" 28 28 #endif 29 #ifdef VHDL_TESTBENCH 30 #include "Behavioural/include/Vhdl_Testbench.h" 31 #endif 29 #include "Behavioural/include/Component.h" 32 30 33 31 using namespace std; … … 59 57 #endif 60 58 61 #ifdef VHDL_TESTBENCH 62 private : Vhdl_Testbench * _vhdl_testbench; 63 #endif 59 public : Component * _component; 60 private : Interfaces * _interfaces; 64 61 65 62 #ifdef SYSTEMC … … 83 80 84 81 // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 85 public : SC_SIGNAL(Thistory_t) ** signal_BRANCH_COMPLETE_HISTORY;86 82 #endif 87 83 … … 118 114 #endif 119 115 120 #if VHDL121 public : void vhdl (void);122 private : void vhdl_port (Vhdl & vhdl);123 private : void vhdl_type (Vhdl & vhdl);124 private : void vhdl_signal (Vhdl & vhdl);125 private : void vhdl_body (Vhdl & vhdl);126 #endif127 116 #ifdef STATISTICS 128 117 public : string statistics (uint32_t depth); 129 118 #endif 130 119 #if VHDL 120 public : void vhdl (void); 121 private : void vhdl_port (Vhdl * & vhdl); 122 private : void vhdl_type (Vhdl * & vhdl); 123 private : void vhdl_signal (Vhdl * & vhdl); 124 private : void vhdl_body (Vhdl * & vhdl); 125 #endif 131 126 #ifdef VHDL_TESTBENCH 132 private : void vhdl_testbench_port (void);133 127 private : void vhdl_testbench_transition (void); 134 128 #endif 135 public : void vhdl_testbench_label (string label);136 129 }; 137 130 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table.cpp
r15 r42 32 32 #endif 33 33 { 34 35 #ifdef SYSTEMC 36 allocation (); 37 #endif 38 34 39 #ifdef STATISTICS 35 40 // Allocation of statistics … … 39 44 #endif 40 45 41 #ifdef VHDL_TESTBENCH42 // Creation of a testbench43 // -> port44 // -> clock's signals45 _vhdl_testbench = new Vhdl_Testbench (_name);46 vhdl_testbench_port ();47 _vhdl_testbench->set_clock ("in_CLOCK",true);48 #endif49 50 46 #ifdef VHDL 51 47 // generate the vhdl … … 53 49 #endif 54 50 51 55 52 #ifdef SYSTEMC 56 allocation ();57 58 53 // // Constant 59 54 // for (uint32_t i=0; i<_param._nb_prediction ; i++) … … 77 72 Branch_History_Table::~Branch_History_Table (void) 78 73 { 79 #ifdef VHDL_TESTBENCH80 // generate the test bench81 _vhdl_testbench->generate_file();82 delete _vhdl_testbench;83 #endif84 85 74 #ifdef STATISTICS 86 75 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_allocation.cpp
r15 r42 20 20 void Branch_History_Table::allocation (void) 21 21 { 22 string rename; 23 24 in_CLOCK = new SC_CLOCK ("in_CLOCK"); 25 in_NRESET = new SC_IN (Tcontrol_t) ("in_NRESET"); 26 22 _component = new Component (); 23 24 Entity * entity = _component->set_entity (_name 25 ,"Branch_History_Table" 26 #ifdef POSITION 27 ,MIXTE 28 #endif 29 ); 30 31 _interfaces = entity->set_interfaces(); 32 33 // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 34 { 35 Interface * interface = _interfaces->set_interface("" 36 #ifdef POSITION 37 , IN 38 , SOUTH 39 , "Generalist interface" 40 #endif 41 ); 42 43 in_CLOCK = interface->set_signal_clk ("clock" ,1); 44 in_NRESET = interface->set_signal_in <Tcontrol_t> ("nreset",1,RESET_VHDL_YES); 45 } 46 47 // ~~~~~[ Interface : "predict" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 27 48 in_PREDICT_VAL = new SC_IN (Tcontrol_t) * [_param._nb_prediction]; 28 49 out_PREDICT_ACK = new SC_OUT(Tcontrol_t) * [_param._nb_prediction]; … … 32 53 for (uint32_t i=0; i<_param._nb_prediction; i++) 33 54 { 34 rename = "in_PREDICT_VAL[" +toString(i)+"]"; 35 in_PREDICT_VAL [i] = new SC_IN (Tcontrol_t) (rename.c_str()); 36 37 rename = "out_PREDICT_ACK[" +toString(i)+"]"; 38 out_PREDICT_ACK [i] = new SC_OUT(Tcontrol_t) (rename.c_str()); 39 40 rename = "in_PREDICT_ADDRESS["+toString(i)+"]"; 41 in_PREDICT_ADDRESS [i] = new SC_IN (Taddress_t) (rename.c_str()); 42 43 rename = "out_PREDICT_HISTORY["+toString(i)+"]"; 44 out_PREDICT_HISTORY [i] = new SC_OUT(Thistory_t) (rename.c_str()); 45 } 46 47 in_BRANCH_COMPLETE_VAL = new SC_IN (Tcontrol_t) * [_param._nb_branch_complete]; 48 out_BRANCH_COMPLETE_ACK = new SC_OUT (Tcontrol_t) * [_param._nb_branch_complete]; 49 in_BRANCH_COMPLETE_ADDRESS = new SC_IN (Taddress_t) * [_param._nb_branch_complete]; 50 in_BRANCH_COMPLETE_HISTORY = new SC_IN (Thistory_t) * [_param._nb_branch_complete]; 51 in_BRANCH_COMPLETE_DIRECTION= new SC_IN (Tcontrol_t) * [_param._nb_branch_complete]; 52 signal_BRANCH_COMPLETE_HISTORY = new SC_SIGNAL (Thistory_t) * [_param._nb_branch_complete]; 55 Interface_fifo * interface = _interfaces->set_interface("predict_"+toString(i) 56 #ifdef POSITION 57 , IN 58 , WEST 59 , "Interface Predict" 60 #endif 61 ); 62 63 in_PREDICT_VAL [i] = interface->set_signal_valack_in ("val" , VAL); 64 out_PREDICT_ACK [i] = interface->set_signal_valack_out ("ack" , ACK); 65 in_PREDICT_ADDRESS [i] = interface->set_signal_in <Taddress_t> ("address", static_cast<uint32_t>(ceil(log2(_param._nb_shifter)))); 66 out_PREDICT_HISTORY [i] = interface->set_signal_out <Thistory_t> ("history", _param._size_shifter); 67 } 68 69 // ~~~~~[ Interface : "branch_complete" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 70 71 in_BRANCH_COMPLETE_VAL = new SC_IN (Tcontrol_t) * [_param._nb_branch_complete]; 72 out_BRANCH_COMPLETE_ACK = new SC_OUT (Tcontrol_t) * [_param._nb_branch_complete]; 73 in_BRANCH_COMPLETE_ADDRESS = new SC_IN (Taddress_t) * [_param._nb_branch_complete]; 74 in_BRANCH_COMPLETE_HISTORY = new SC_IN (Thistory_t) * [_param._nb_branch_complete]; 75 in_BRANCH_COMPLETE_DIRECTION = new SC_IN (Tcontrol_t) * [_param._nb_branch_complete]; 53 76 54 77 for (uint32_t i=0; i<_param._nb_branch_complete; i++) 55 78 { 56 rename = "in_BRANCH_COMPLETE_VAL[" +toString(i)+"]"; 57 in_BRANCH_COMPLETE_VAL [i] = new SC_IN (Tcontrol_t) (rename.c_str()); 58 59 rename = "out_BRANCH_COMPLETE_ACK[" +toString(i)+"]"; 60 out_BRANCH_COMPLETE_ACK [i] = new SC_OUT(Tcontrol_t) (rename.c_str()); 61 62 rename = "in_BRANCH_COMPLETE_ADDRESS["+toString(i)+"]"; 63 in_BRANCH_COMPLETE_ADDRESS [i] = new SC_IN (Taddress_t) (rename.c_str()); 64 65 rename = "in_BRANCH_COMPLETE_HISTORY["+toString(i)+"]"; 66 in_BRANCH_COMPLETE_HISTORY [i] = new SC_IN (Thistory_t) (rename.c_str()); 67 68 rename = "in_BRANCH_COMPLETE_DIRECTION[" +toString(i)+"]"; 69 in_BRANCH_COMPLETE_DIRECTION[i] = new SC_IN (Tcontrol_t) (rename.c_str()); 70 71 rename = "signal_BRANCH_COMPLETE_HISTORY["+toString(i)+"]"; 72 signal_BRANCH_COMPLETE_HISTORY [i] = new SC_SIGNAL (Thistory_t) (rename.c_str()); 73 79 Interface_fifo * interface = _interfaces->set_interface("branch_complete_"+toString(i) 80 #ifdef POSITION 81 , IN 82 , EAST 83 , "Interface branch complete" 84 #endif 85 ); 86 87 in_BRANCH_COMPLETE_VAL [i] = interface->set_signal_valack_in ("val" , VAL); 88 out_BRANCH_COMPLETE_ACK [i] = interface->set_signal_valack_out ("ack" , ACK); 89 in_BRANCH_COMPLETE_ADDRESS [i] = interface->set_signal_in <Taddress_t> ("address" , static_cast<uint32_t>(ceil(log2(_param._nb_shifter)))); 90 in_BRANCH_COMPLETE_HISTORY [i] = interface->set_signal_in <Thistory_t> ("history" , _param._size_shifter); 91 in_BRANCH_COMPLETE_DIRECTION [i] = interface->set_signal_in <Tcontrol_t> ("direction", 1); 74 92 } 75 93 76 94 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 77 95 string name_component; 96 78 97 // =====[ component_Shifter ]========================================= 79 98 80 99 name_component = _name+"_Shifter"; 81 100 82 component_Shifter = new morpheo::behavioural::generic::shifter::Shifter (name_component.c_str() ,101 component_Shifter = new morpheo::behavioural::generic::shifter::Shifter (name_component.c_str() 83 102 #ifdef STATISTICS 84 _param_statistics , 85 #endif 86 *(_param._param_shifter) ); 87 88 89 // Instantiation 90 #if (defined(STATISTICS) || defined (VHDL_TESTBENCH)) 91 (*(component_Shifter->in_CLOCK)) (*(in_CLOCK)); 92 #endif 93 94 for (uint32_t i=0; i<_param._nb_branch_complete; i++) 95 { 96 (*(component_Shifter-> in_SHIFTER_DATA [i])) (*( in_BRANCH_COMPLETE_HISTORY [i])); 97 (*(component_Shifter-> in_SHIFTER_CARRY_IN [i])) (*( in_BRANCH_COMPLETE_DIRECTION[i])); 98 (*(component_Shifter->out_SHIFTER_DATA [i])) (*(signal_BRANCH_COMPLETE_HISTORY [i])); 99 } 100 103 ,_param_statistics 104 #endif 105 ,*(_param._param_shifter)); 106 107 _component->set_component (component_Shifter->_component 108 #ifdef POSITION 109 , 25 110 , 25 111 , 10 112 , 10 113 #endif 114 ); 115 101 116 // =====[ component_RegisterFile ]==================================== 102 117 … … 105 120 component_RegisterFile = new morpheo::behavioural::generic::registerfile::registerfile_monolithic::RegisterFile_Monolithic(name_component.c_str(), 106 121 #ifdef STATISTICS 107 _param_statistics , 108 #endif 109 *(_param._param_registerfile)); 122 _param_statistics , 123 #endif 124 *(_param._param_registerfile)); 125 126 _component->set_component (component_RegisterFile->_component 127 #ifdef POSITION 128 , 75 129 , 75 130 , 10 131 , 10 132 #endif 133 ); 110 134 111 // Instantiation 112 (*(component_RegisterFile->in_CLOCK )) (*(in_CLOCK )); 113 (*(component_RegisterFile->in_NRESET)) (*(in_NRESET)); 135 // ~~~~~[ Component - Instanciation ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 136 137 // =====[ component_RegisterFile - Instanciation ]==================== 138 139 #ifdef POSITION 140 _component->interface_map (_name+"_RegisterFile","", 141 _name ,""); 142 #endif 143 144 _component->port_map(_name+"_RegisterFile", "in_CLOCK" , _name,"in_CLOCK" ); 145 _component->port_map(_name+"_RegisterFile", "in_NRESET", _name,"in_NRESET"); 114 146 115 147 for (uint32_t i=0; i<_param._nb_prediction; i++) 116 148 { 117 (*(component_RegisterFile-> in_READ_VAL [i])) (*( in_PREDICT_VAL [i])); 118 (*(component_RegisterFile->out_READ_ACK [i])) (*(out_PREDICT_ACK [i])); 119 (*(component_RegisterFile-> in_READ_ADDRESS [i])) (*( in_PREDICT_ADDRESS [i])); 120 (*(component_RegisterFile->out_READ_DATA [i])) (*(out_PREDICT_HISTORY [i])); 149 #ifdef POSITION 150 _component->interface_map (_name+"_RegisterFile","read_" +toString(i), 151 _name ,"predict_"+toString(i)); 152 #endif 153 154 _component->port_map(_name+"_RegisterFile", "in_READ_"+toString(i)+"_VAL" , _name, "in_PREDICT_"+toString(i)+"_VAL" ); 155 _component->port_map(_name+"_RegisterFile","out_READ_"+toString(i)+"_ACK" , _name,"out_PREDICT_"+toString(i)+"_ACK" ); 156 _component->port_map(_name+"_RegisterFile", "in_READ_"+toString(i)+"_ADDRESS", _name, "in_PREDICT_"+toString(i)+"_ADDRESS"); 157 _component->port_map(_name+"_RegisterFile","out_READ_"+toString(i)+"_DATA" , _name,"out_PREDICT_"+toString(i)+"_HISTORY"); 121 158 } 122 159 123 160 for (uint32_t i=0; i<_param._nb_branch_complete; i++) 124 161 { 125 (*(component_RegisterFile-> in_WRITE_VAL [i])) (*( in_BRANCH_COMPLETE_VAL [i])); 126 (*(component_RegisterFile->out_WRITE_ACK [i])) (*( out_BRANCH_COMPLETE_ACK [i])); 127 (*(component_RegisterFile-> in_WRITE_ADDRESS [i])) (*( in_BRANCH_COMPLETE_ADDRESS [i])); 128 (*(component_RegisterFile-> in_WRITE_DATA [i])) (*(signal_BRANCH_COMPLETE_HISTORY [i])); 129 } 162 #ifdef POSITION 163 _component->interface_map (_name+"_RegisterFile","write_" +toString(i), 164 _name+"_Shifter" ,"shifter_"+toString(i)); 165 #endif 166 167 _component->port_map(_name+"_RegisterFile", "in_WRITE_"+toString(i)+"_VAL" , _name , "in_BRANCH_COMPLETE_"+toString(i)+"_VAL" ); 168 _component->port_map(_name+"_RegisterFile","out_WRITE_"+toString(i)+"_ACK" , _name ,"out_BRANCH_COMPLETE_"+toString(i)+"_ACK" ); 169 _component->port_map(_name+"_RegisterFile", "in_WRITE_"+toString(i)+"_ADDRESS", _name , "in_BRANCH_COMPLETE_"+toString(i)+"_ADDRESS"); 170 _component->port_map(_name+"_RegisterFile", "in_WRITE_"+toString(i)+"_DATA" , _name+"_Shifter","out_SHIFTER_" +toString(i)+"_DATA"); 171 } 172 173 // =====[ component_Shifter - Instanciation ]========================= 174 175 #if (defined(STATISTICS) || defined (VHDL_TESTBENCH)) 176 177 #ifdef POSITION 178 _component->interface_map (_name+"_Shifter","", 179 _name ,""); 180 #endif 181 182 _component->port_map(_name+"_Shifter", "in_CLOCK" , _name,"in_CLOCK" ); 183 _component->port_map(_name+"_Shifter", "in_NRESET", _name,"in_NRESET"); 184 185 #endif 186 187 for (uint32_t i=0; i<_param._nb_branch_complete; i++) 188 { 189 #ifdef POSITION 190 _component->interface_map (_name+"_Shifter","shifter_"+toString(i), 191 _name ,"branch_complete_"+toString(i)); 192 193 #endif 194 195 _component->port_map(_name+"_Shifter", "in_SHIFTER_" +toString(i)+"_DATA" , _name , "in_BRANCH_COMPLETE_"+toString(i)+"_HISTORY"); 196 _component->port_map(_name+"_Shifter", "in_SHIFTER_" +toString(i)+"_CARRY_IN", _name , "in_BRANCH_COMPLETE_"+toString(i)+"_DIRECTION"); 197 _component->port_map(_name+"_Shifter", "out_SHIFTER_"+toString(i)+"_DATA" , _name+"_RegisterFile", "in_WRITE_"+toString(i)+"_DATA"); 198 } 199 200 #ifdef POSITION 201 _component->generate_file(); 202 #endif 130 203 }; 131 204 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_deallocation.cpp
r15 r42 19 19 void Branch_History_Table::deallocation (void) 20 20 { 21 delete in_CLOCK;22 delete in_NRESET;21 delete in_CLOCK; 22 delete in_NRESET; 23 23 24 for (uint32_t i=0; i<_param._nb_prediction; i++) 25 { 26 delete in_PREDICT_VAL [i]; 27 delete out_PREDICT_ACK [i]; 28 delete in_PREDICT_ADDRESS [i]; 29 delete out_PREDICT_HISTORY [i]; 30 } 24 delete [] in_PREDICT_VAL ; 25 delete [] out_PREDICT_ACK ; 26 delete [] in_PREDICT_ADDRESS; 27 delete [] out_PREDICT_HISTORY; 31 28 32 delete in_PREDICT_VAL ; 33 delete out_PREDICT_ACK ; 34 delete in_PREDICT_ADDRESS; 35 delete out_PREDICT_HISTORY; 36 37 for (uint32_t i=0; i<_param._nb_branch_complete; i++) 38 { 39 delete in_BRANCH_COMPLETE_VAL [i]; 40 delete out_BRANCH_COMPLETE_ACK [i]; 41 delete in_BRANCH_COMPLETE_ADDRESS [i]; 42 delete in_BRANCH_COMPLETE_HISTORY [i]; 43 delete in_BRANCH_COMPLETE_DIRECTION[i]; 44 } 45 delete in_BRANCH_COMPLETE_VAL ; 46 delete out_BRANCH_COMPLETE_ACK ; 47 delete in_BRANCH_COMPLETE_ADDRESS; 48 delete in_BRANCH_COMPLETE_HISTORY; 49 delete in_BRANCH_COMPLETE_DIRECTION; 29 delete [] in_BRANCH_COMPLETE_VAL ; 30 delete [] out_BRANCH_COMPLETE_ACK ; 31 delete [] in_BRANCH_COMPLETE_ADDRESS; 32 delete [] in_BRANCH_COMPLETE_HISTORY; 33 delete [] in_BRANCH_COMPLETE_DIRECTION; 50 34 51 35 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 52 36 delete component_Shifter; 53 37 delete component_RegisterFile; 38 39 delete _component; 54 40 }; 55 41 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_vhdl.cpp
r2 r42 21 21 void Branch_History_Table::vhdl (void) 22 22 { 23 Vhdl vhdl (_name);23 Vhdl * vhdl = new Vhdl (_name); 24 24 25 vhdl .set_library_work (_name + "_Pack");26 vhdl .set_library_work (_name + "_RegisterFile_Pack");27 vhdl .set_library_work (_name + "_Shifter_Pack");25 vhdl->set_library_work (_name + "_Pack"); 26 vhdl->set_library_work (_name + "_RegisterFile_Pack"); 27 vhdl->set_library_work (_name + "_Shifter_Pack"); 28 28 29 29 vhdl_port (vhdl); … … 32 32 vhdl_body (vhdl); 33 33 34 vhdl.generate_file(); 34 vhdl->generate_file(); 35 36 delete vhdl; 35 37 }; 36 38 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_vhdl_body.cpp
r15 r42 18 18 19 19 20 void Branch_History_Table::vhdl_body (Vhdl & vhdl)20 void Branch_History_Table::vhdl_body (Vhdl * & vhdl) 21 21 { 22 // vhdl .set_body ("-- Output : always at '1'");22 // vhdl->set_body ("-- Output : always at '1'"); 23 23 // for (uint32_t i=0; i<_param._nb_branch_complete; i++) 24 // vhdl .set_body ("out_BRANCH_COMPLETE_ACK_"+toString(i)+" <= '1';");24 // vhdl->set_body ("out_BRANCH_COMPLETE_ACK_"+toString(i)+" <= '1';"); 25 25 // for (uint32_t i=0; i<_param._nb_prediction ; i++) 26 // vhdl .set_body ("out_PREDICT_ACK_"+toString(i)+" <= '1';");27 // vhdl .set_body ("");26 // vhdl->set_body ("out_PREDICT_ACK_"+toString(i)+" <= '1';"); 27 // vhdl->set_body (""); 28 28 29 29 list<string> list_port_map; … … 31 31 for (uint32_t i=0; i<_param._nb_branch_complete; i++) 32 32 { 33 vhdl .set_body_component_port_map (list_port_map," in_SHIFTER_DATA_"+toString(i)+" "," in_BRANCH_COMPLETE_HISTORY_"+toString(i));34 vhdl .set_body_component_port_map (list_port_map," in_SHIFTER_CARRY_IN_"+toString(i)+" "," in_BRANCH_COMPLETE_DIRECTION_"+toString(i));35 vhdl .set_body_component_port_map (list_port_map,"out_SHIFTER_DATA_"+toString(i)+" ","signal_BRANCH_COMPLETE_HISTORY_"+toString(i));33 vhdl->set_body_component_port_map (list_port_map," in_SHIFTER_"+toString(i)+"_DATA "," in_BRANCH_COMPLETE_"+toString(i)+"_HISTORY" ); 34 vhdl->set_body_component_port_map (list_port_map," in_SHIFTER_"+toString(i)+"_CARRY_IN "," in_BRANCH_COMPLETE_"+toString(i)+"_DIRECTION"); 35 vhdl->set_body_component_port_map (list_port_map,"out_SHIFTER_"+toString(i)+"_DATA ","signal_BRANCH_COMPLETE_"+toString(i)+"_HISTORY" ); 36 36 } 37 37 38 vhdl .set_body_component ("component_Shifter",_name+"_Shifter",list_port_map);38 vhdl->set_body_component ("component_Shifter",_name+"_Shifter",list_port_map); 39 39 40 40 list_port_map.clear(); 41 vhdl .set_body_component_port_map (list_port_map,"in_CLOCK","in_CLOCK");42 vhdl .set_body_component_port_map (list_port_map,"in_NRESET","in_NRESET");41 vhdl->set_body_component_port_map (list_port_map,"in_CLOCK","in_CLOCK"); 42 vhdl->set_body_component_port_map (list_port_map,"in_NRESET","in_NRESET"); 43 43 44 44 for (uint32_t i=0; i<_param._nb_prediction; i++) 45 45 { 46 vhdl .set_body_component_port_map (list_port_map," in_READ_VAL_"+toString(i)+" "," in_PREDICT_VAL_"+toString(i));47 vhdl .set_body_component_port_map (list_port_map,"out_READ_ACK_"+toString(i)+" ","out_PREDICT_ACK_"+toString(i));48 vhdl .set_body_component_port_map (list_port_map," in_READ_ADDRESS_"+toString(i)+" "," in_PREDICT_ADDRESS_"+toString(i));49 vhdl .set_body_component_port_map (list_port_map,"out_READ_DATA_"+toString(i)+" ","out_PREDICT_HISTORY_"+toString(i));46 vhdl->set_body_component_port_map (list_port_map," in_READ_"+toString(i)+"_VAL "," In_PREDICT_"+toString(i)+"_VAL"); 47 vhdl->set_body_component_port_map (list_port_map,"out_READ_"+toString(i)+"_ACK ","out_PREDICT_"+toString(i)+"_ACK"); 48 vhdl->set_body_component_port_map (list_port_map," in_READ_"+toString(i)+"_ADDRESS "," in_PREDICT_"+toString(i)+"_ADDRESS"); 49 vhdl->set_body_component_port_map (list_port_map,"out_READ_"+toString(i)+"_DATA ","out_PREDICT_"+toString(i)+"_HISTORY"); 50 50 } 51 51 52 52 for (uint32_t i=0; i<_param._nb_branch_complete; i++) 53 53 { 54 vhdl .set_body_component_port_map (list_port_map," in_WRITE_VAL_"+toString(i)+" "," in_BRANCH_COMPLETE_VAL_"+toString(i)+"");55 vhdl .set_body_component_port_map (list_port_map,"out_WRITE_ACK_"+toString(i)+" "," out_BRANCH_COMPLETE_ACK_"+toString(i)+"");56 vhdl .set_body_component_port_map (list_port_map," in_WRITE_ADDRESS_"+toString(i)+""," in_BRANCH_COMPLETE_ADDRESS_"+toString(i));57 vhdl .set_body_component_port_map (list_port_map," in_WRITE_DATA_"+toString(i)+" ","signal_BRANCH_COMPLETE_HISTORY_"+toString(i));54 vhdl->set_body_component_port_map (list_port_map," in_WRITE_"+toString(i)+"_VAL "," in_BRANCH_COMPLETE_"+toString(i)+"_VAL"); 55 vhdl->set_body_component_port_map (list_port_map,"out_WRITE_"+toString(i)+"_ACK "," out_BRANCH_COMPLETE_"+toString(i)+"_ACK"); 56 vhdl->set_body_component_port_map (list_port_map," in_WRITE_"+toString(i)+"_ADDRESS"," in_BRANCH_COMPLETE_"+toString(i)+"_ADDRESS"); 57 vhdl->set_body_component_port_map (list_port_map," in_WRITE_"+toString(i)+"_DATA ","signal_BRANCH_COMPLETE_"+toString(i)+"_HISTORY"); 58 58 } 59 vhdl .set_body_component ("component_RegisterFile",_name+"_RegisterFile",list_port_map);59 vhdl->set_body_component ("component_RegisterFile",_name+"_RegisterFile",list_port_map); 60 60 }; 61 61 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_vhdl_port.cpp
r15 r42 18 18 19 19 20 void Branch_History_Table::vhdl_port (Vhdl & vhdl)20 void Branch_History_Table::vhdl_port (Vhdl * & vhdl) 21 21 { 22 vhdl.set_port (" in_CLOCK" , IN, 1); 23 vhdl.set_port (" in_NRESET", IN, 1); 24 25 for (uint32_t i=0; i<_param._nb_prediction; i++) 26 { 27 vhdl.set_port(" in_PREDICT_VAL_"+toString(i)+" ", IN, 1); 28 vhdl.set_port("out_PREDICT_ACK_"+toString(i)+" ",OUT, 1); 29 vhdl.set_port(" in_PREDICT_ADDRESS_"+toString(i)+" ", IN, static_cast<uint32_t>(ceil(log2(_param._nb_shifter)))); 30 vhdl.set_port("out_PREDICT_HISTORY_"+toString(i)+" ",OUT, _param._size_shifter); 31 } 32 for (uint32_t i=0; i<_param._nb_branch_complete; i++) 33 { 34 vhdl.set_port (" in_BRANCH_COMPLETE_VAL_"+toString(i)+" ", IN, 1); 35 vhdl.set_port ("out_BRANCH_COMPLETE_ACK_"+toString(i)+" ",OUT, 1); 36 vhdl.set_port (" in_BRANCH_COMPLETE_ADDRESS_"+toString(i)+" ", IN, static_cast<uint32_t>(ceil(log2(_param._nb_shifter)))); 37 vhdl.set_port (" in_BRANCH_COMPLETE_HISTORY_"+toString(i)+" ", IN, _param._size_shifter); 38 vhdl.set_port (" in_BRANCH_COMPLETE_DIRECTION_"+toString(i)+"", IN, 1); 39 } 22 _interfaces->set_port(vhdl); 40 23 }; 41 24 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_vhdl_signal.cpp
r3 r42 17 17 namespace branch_history_table { 18 18 19 void Branch_History_Table::vhdl_signal (Vhdl & vhdl)19 void Branch_History_Table::vhdl_signal (Vhdl * & vhdl) 20 20 { 21 21 for (uint32_t i=0; i<_param._nb_branch_complete; i++) 22 vhdl .set_signal ("signal_BRANCH_COMPLETE_HISTORY_"+toString(i), _param._size_shifter);22 vhdl->set_signal ("signal_BRANCH_COMPLETE_"+toString(i)+"_HISTORY", _param._size_shifter); 23 23 }; 24 24 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_vhdl_testbench_transition.cpp
r15 r42 20 20 void Branch_History_Table::vhdl_testbench_transition (void) 21 21 { 22 // In order with file Branch_History_Table_vhdl_testbench_port.cpp 23 #ifndef SYSTEMCASS_SPECIFIC 24 sc_cycle(0); 25 #endif 22 sc_start(0); 26 23 27 _vhdl_testbench->add_input (PORT_READ( in_NRESET)); 28 29 for (uint32_t i=0; i<_param._nb_prediction; i++) 30 { 31 _vhdl_testbench->add_input (PORT_READ( in_PREDICT_VAL [i])); 32 _vhdl_testbench->add_output (PORT_READ(component_RegisterFile->out_READ_ACK [i])); 33 _vhdl_testbench->add_input (PORT_READ( in_PREDICT_ADDRESS [i])); 34 _vhdl_testbench->add_output (PORT_READ(component_RegisterFile->out_READ_DATA [i])); 35 //_vhdl_testbench->add_output (PORT_READ(out_PREDICT_HISTORY [i])); 36 } 37 38 for (uint32_t i=0; i<_param._nb_branch_complete; i++) 39 { 40 _vhdl_testbench->add_input (PORT_READ( in_BRANCH_COMPLETE_VAL [i])); 41 _vhdl_testbench->add_output (PORT_READ(component_RegisterFile->out_WRITE_ACK [i])); 42 _vhdl_testbench->add_input (PORT_READ( in_BRANCH_COMPLETE_ADDRESS [i])); 43 _vhdl_testbench->add_input (PORT_READ( in_BRANCH_COMPLETE_HISTORY [i])); 44 _vhdl_testbench->add_input (PORT_READ( in_BRANCH_COMPLETE_DIRECTION[i])); 45 } 46 47 // add_test : 48 // - True : the cycle must be compare with the output of systemC 49 // - False : no test 50 _vhdl_testbench->add_test(true); 51 52 _vhdl_testbench->new_cycle (); // always at the end 24 _interfaces->testbench(); 53 25 }; 54 26 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/src/Branch_History_Table_vhdl_type.cpp
r2 r42 18 18 19 19 20 void Branch_History_Table::vhdl_type (Vhdl & vhdl)20 void Branch_History_Table::vhdl_type (Vhdl * & vhdl) 21 21 { 22 22 }; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/SelfTest/configuration.cfg
r2 r42 1 1 Pattern_History_Table 2 28 *2 # size_counter3 264 *4 # nb_counter4 12 +1 # nb_prediction5 12 +1 # nb_branch_complete2 8 8 *2 # size_counter 3 64 64 *4 # nb_counter 4 2 2 +1 # nb_prediction 5 2 2 +1 # nb_branch_complete -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/SelfTest/mkf.info
r15 r42 1 2 # Pattern_History_Table_0 3 target_dep all Pattern_History_Table_0.ngc 4 target_dep Pattern_History_Table_0.ngc Pattern_History_Table_0.prj 5 target_dep Pattern_History_Table_0.prj Pattern_History_Table_0_Counter_Pack.vhdl Pattern_History_Table_0_Counter.vhdl Pattern_History_Table_0_Pack.vhdl Pattern_History_Table_0_RegisterFile_Pack.vhdl Pattern_History_Table_0_RegisterFile.vhdl Pattern_History_Table_0.vhdl 6 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/SelfTest/src/test.cpp
r15 r42 7 7 */ 8 8 9 #define NB_ITERATION 10249 #define NB_ITERATION 512 10 10 11 11 #include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/SelfTest/include/test.h" … … 93 93 94 94 sc_start(0); 95 _Pattern_History_Table->vhdl_testbench_label("Initialisation");96 95 cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} Initialisation" << endl; 97 96 … … 127 126 sc_start(0); 128 127 129 _Pattern_History_Table->vhdl_testbench_label("Loop of Test");130 128 cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} Loop of Test" << endl; 131 129 132 130 for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++) 133 131 { 134 _Pattern_History_Table->vhdl_testbench_label("Iteration "+toString(iteration));135 132 num_port_branch_complete = rand() % param._nb_branch_complete; 136 133 num_port_predict = rand() % param._nb_prediction ; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/include/Pattern_History_Table.h
r15 r42 29 29 #include "Behavioural/include/Vhdl.h" 30 30 #endif 31 #ifdef VHDL_TESTBENCH 32 #include "Behavioural/include/Vhdl_Testbench.h" 33 #endif 31 #include "Behavioural/include/Component.h" 34 32 35 33 using namespace std; … … 62 60 #endif 63 61 64 #ifdef VHDL_TESTBENCH 65 private : Vhdl_Testbench * _vhdl_testbench; 66 #endif 62 public : Component * _component; 63 private : Interfaces * _interfaces; 67 64 68 65 #ifdef SYSTEMC … … 125 122 public : string statistics (uint32_t depth); 126 123 #endif 127 128 124 #if VHDL 129 125 public : void vhdl (void); 130 private : void vhdl_port (Vhdl & vhdl); 131 private : void vhdl_declaration (Vhdl & vhdl); 132 private : void vhdl_body (Vhdl & vhdl); 126 private : void vhdl_declaration (Vhdl * & vhdl); 127 private : void vhdl_body (Vhdl * & vhdl); 133 128 #endif 134 135 129 #ifdef VHDL_TESTBENCH 136 private : void vhdl_testbench_port (void);137 130 private : void vhdl_testbench_transition (void); 138 131 #endif 139 public : void vhdl_testbench_label (string label);140 132 }; 141 133 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table.cpp
r15 r42 33 33 { 34 34 log_printf(FUNC,Pattern_History_Table,"Pattern_History_Table","Begin"); 35 35 36 #ifdef SYSTEMC 37 allocation (); 38 #endif 39 36 40 #ifdef STATISTICS 37 41 // Allocation of statistics … … 39 43 param_statistics , 40 44 param); 41 #endif42 43 #ifdef VHDL_TESTBENCH44 // Creation of a testbench45 // -> port46 // -> clock's signals47 _vhdl_testbench = new Vhdl_Testbench (_name);48 vhdl_testbench_port ();49 _vhdl_testbench->set_clock ("in_CLOCK",true);50 45 #endif 51 46 … … 56 51 57 52 #ifdef SYSTEMC 58 allocation ();59 60 53 // // Constant 61 54 // for (uint32_t i=0; i<_param._nb_prediction ; i++) … … 82 75 log_printf(FUNC,Pattern_History_Table,"~Pattern_History_Table","Begin"); 83 76 84 #ifdef VHDL_TESTBENCH85 // generate the test bench86 _vhdl_testbench->generate_file();87 delete _vhdl_testbench;88 #endif89 90 77 #ifdef STATISTICS 91 78 _stat->generate_file(statistics(0)); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_allocation.cpp
r15 r42 20 20 void Pattern_History_Table::allocation (void) 21 21 { 22 string rename;23 24 22 log_printf(FUNC,Pattern_History_Table,"allocation","Begin"); 25 23 26 in_CLOCK = new SC_CLOCK ("in_CLOCK"); 27 in_NRESET = new SC_IN (Tcontrol_t) ("in_NRESET"); 28 24 _component = new Component (); 25 26 Entity * entity = _component->set_entity (_name 27 ,"Pattern_History_Table" 28 #ifdef POSITION 29 ,MIXTE 30 #endif 31 ); 32 33 _interfaces = entity->set_interfaces(); 34 35 // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 36 { 37 Interface * interface = _interfaces->set_interface("" 38 #ifdef POSITION 39 , IN 40 , SOUTH 41 , "Generalist interface" 42 #endif 43 ); 44 45 in_CLOCK = interface->set_signal_clk ("clock" ,1); 46 in_NRESET = interface->set_signal_in <Tcontrol_t> ("nreset",1,RESET_VHDL_YES); 47 } 48 49 // ~~~~~[ Interface : "predict" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 29 50 in_PREDICT_VAL = new SC_IN (Tcontrol_t) * [_param._nb_prediction]; 30 51 out_PREDICT_ACK = new SC_OUT(Tcontrol_t) * [_param._nb_prediction]; … … 34 55 for (uint32_t i=0; i<_param._nb_prediction; i++) 35 56 { 36 rename = "in_PREDICT_VAL[" +toString(i)+"]"; 37 in_PREDICT_VAL [i] = new SC_IN (Tcontrol_t) (rename.c_str()); 38 39 rename = "out_PREDICT_ACK[" +toString(i)+"]"; 40 out_PREDICT_ACK [i] = new SC_OUT(Tcontrol_t) (rename.c_str()); 41 42 rename = "in_PREDICT_ADDRESS["+toString(i)+"]"; 43 in_PREDICT_ADDRESS [i] = new SC_IN (Taddress_t) (rename.c_str()); 44 45 rename = "out_PREDICT_HISTORY["+toString(i)+"]"; 46 out_PREDICT_HISTORY [i] = new SC_OUT(Thistory_t) (rename.c_str()); 47 } 57 Interface_fifo * interface = _interfaces->set_interface("predict_"+toString(i) 58 #ifdef POSITION 59 , IN 60 , WEST 61 , "Interface Predict" 62 #endif 63 ); 64 65 in_PREDICT_VAL [i] = interface->set_signal_valack_in ("val" , VAL); 66 out_PREDICT_ACK [i] = interface->set_signal_valack_out ("ack" , ACK); 67 in_PREDICT_ADDRESS [i] = interface->set_signal_in <Taddress_t> ("address", static_cast<uint32_t>(ceil(log2(_param._nb_counter)))); 68 out_PREDICT_HISTORY [i] = interface->set_signal_out <Thistory_t> ("history", _param._size_counter); 69 } 70 71 // ~~~~~[ Interface : "branch_complete" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 48 72 49 73 in_BRANCH_COMPLETE_VAL = new SC_IN (Tcontrol_t) * [_param._nb_branch_complete]; … … 52 76 in_BRANCH_COMPLETE_HISTORY = new SC_IN (Thistory_t) * [_param._nb_branch_complete]; 53 77 in_BRANCH_COMPLETE_DIRECTION = new SC_IN (Tcontrol_t) * [_param._nb_branch_complete]; 54 signal_BRANCH_COMPLETE_HISTORY = new SC_SIGNAL (Thistory_t) * [_param._nb_branch_complete];55 78 56 79 for (uint32_t i=0; i<_param._nb_branch_complete; i++) 57 80 { 58 rename = "in_BRANCH_COMPLETE_VAL[" +toString(i)+"]"; 59 in_BRANCH_COMPLETE_VAL [i] = new SC_IN (Tcontrol_t) (rename.c_str()); 60 61 rename = "out_BRANCH_COMPLETE_ACK[" +toString(i)+"]"; 62 out_BRANCH_COMPLETE_ACK [i] = new SC_OUT(Tcontrol_t) (rename.c_str()); 63 64 rename = "in_BRANCH_COMPLETE_ADDRESS["+toString(i)+"]"; 65 in_BRANCH_COMPLETE_ADDRESS [i] = new SC_IN (Taddress_t) (rename.c_str()); 66 67 rename = "in_BRANCH_COMPLETE_HISTORY["+toString(i)+"]"; 68 in_BRANCH_COMPLETE_HISTORY [i] = new SC_IN (Thistory_t) (rename.c_str()); 69 70 rename = "in_BRANCH_COMPLETE_DIRECTION[" +toString(i)+"]"; 71 in_BRANCH_COMPLETE_DIRECTION [i] = new SC_IN (Tcontrol_t) (rename.c_str()); 72 73 rename = "signal_BRANCH_COMPLETE_HISTORY["+toString(i)+"]"; 74 signal_BRANCH_COMPLETE_HISTORY [i] = new SC_SIGNAL (Thistory_t) (rename.c_str()); 75 76 } 77 81 Interface_fifo * interface = _interfaces->set_interface("branch_complete_"+toString(i) 82 #ifdef POSITION 83 , IN 84 , EAST 85 , "Interface branch complete" 86 #endif 87 ); 88 89 in_BRANCH_COMPLETE_VAL [i] = interface->set_signal_valack_in ("val" , VAL); 90 out_BRANCH_COMPLETE_ACK [i] = interface->set_signal_valack_out ("ack" , ACK); 91 in_BRANCH_COMPLETE_ADDRESS [i] = interface->set_signal_in <Taddress_t> ("address" , static_cast<uint32_t>(ceil(log2(_param._nb_counter)))); 92 in_BRANCH_COMPLETE_HISTORY [i] = interface->set_signal_in <Thistory_t> ("history" , _param._size_counter); 93 in_BRANCH_COMPLETE_DIRECTION [i] = interface->set_signal_in <Tcontrol_t> ("direction", 1); 94 } 95 78 96 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 79 97 string name_component; 98 80 99 // =====[ component_Counter ]========================================= 81 100 82 101 name_component = _name+"_Counter"; 83 102 84 component_Counter = new morpheo::behavioural::generic::counter::Counter (name_component.c_str() ,103 component_Counter = new morpheo::behavioural::generic::counter::Counter (name_component.c_str() 85 104 #ifdef STATISTICS 86 _param_statistics , 87 #endif 88 *(_param._param_counter) ); 89 90 91 // Instantiation 105 ,_param_statistics 106 #endif 107 ,*(_param._param_counter)); 108 109 _component->set_component (component_Counter->_component 110 #ifdef POSITION 111 , 25 112 , 25 113 , 10 114 , 10 115 #endif 116 ); 117 118 // =====[ component_RegisterFile ]==================================== 119 120 name_component = _name+"_RegisterFile"; 121 122 component_RegisterFile = new morpheo::behavioural::generic::registerfile::registerfile_monolithic::RegisterFile_Monolithic(name_component.c_str(), 123 #ifdef STATISTICS 124 _param_statistics , 125 #endif 126 *(_param._param_registerfile)); 127 128 _component->set_component (component_RegisterFile->_component 129 #ifdef POSITION 130 , 75 131 , 75 132 , 10 133 , 10 134 #endif 135 ); 136 137 // ~~~~~[ Component - Instanciation ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 138 139 // =====[ component_RegisterFile - Instanciation ]==================== 140 141 #ifdef POSITION 142 _component->interface_map (_name+"_RegisterFile","", 143 _name ,""); 144 #endif 145 146 _component->port_map(_name+"_RegisterFile", "in_CLOCK" , _name,"in_CLOCK" ); 147 _component->port_map(_name+"_RegisterFile", "in_NRESET", _name,"in_NRESET"); 148 149 for (uint32_t i=0; i<_param._nb_prediction; i++) 150 { 151 #ifdef POSITION 152 _component->interface_map (_name+"_RegisterFile","read_" +toString(i), 153 _name ,"predict_"+toString(i)); 154 #endif 155 156 _component->port_map(_name+"_RegisterFile", "in_READ_"+toString(i)+"_VAL" , _name, "in_PREDICT_"+toString(i)+"_VAL" ); 157 _component->port_map(_name+"_RegisterFile","out_READ_"+toString(i)+"_ACK" , _name,"out_PREDICT_"+toString(i)+"_ACK" ); 158 _component->port_map(_name+"_RegisterFile", "in_READ_"+toString(i)+"_ADDRESS", _name, "in_PREDICT_"+toString(i)+"_ADDRESS"); 159 _component->port_map(_name+"_RegisterFile","out_READ_"+toString(i)+"_DATA" , _name,"out_PREDICT_"+toString(i)+"_HISTORY"); 160 } 161 162 for (uint32_t i=0; i<_param._nb_branch_complete; i++) 163 { 164 #ifdef POSITION 165 _component->interface_map (_name+"_RegisterFile","write_" +toString(i), 166 _name+"_Counter" ,"counter_"+toString(i)); 167 #endif 168 169 _component->port_map(_name+"_RegisterFile", "in_WRITE_"+toString(i)+"_VAL" , _name , "in_BRANCH_COMPLETE_"+toString(i)+"_VAL" ); 170 _component->port_map(_name+"_RegisterFile","out_WRITE_"+toString(i)+"_ACK" , _name ,"out_BRANCH_COMPLETE_"+toString(i)+"_ACK" ); 171 _component->port_map(_name+"_RegisterFile", "in_WRITE_"+toString(i)+"_ADDRESS", _name , "in_BRANCH_COMPLETE_"+toString(i)+"_ADDRESS"); 172 _component->port_map(_name+"_RegisterFile", "in_WRITE_"+toString(i)+"_DATA" , _name+"_Counter","out_COUNTER_" +toString(i)+"_DATA"); 173 } 174 175 // =====[ component_Counter - Instanciation ]========================= 176 92 177 #if (defined(STATISTICS) || defined (VHDL_TESTBENCH)) 93 (*(component_Counter->in_CLOCK)) (*(in_CLOCK)); 178 179 #ifdef POSITION 180 _component->interface_map (_name+"_Counter","", 181 _name ,""); 182 #endif 183 184 _component->port_map(_name+"_Counter", "in_CLOCK" , _name,"in_CLOCK" ); 185 _component->port_map(_name+"_Counter", "in_NRESET", _name,"in_NRESET"); 186 94 187 #endif 95 188 96 189 for (uint32_t i=0; i<_param._nb_branch_complete; i++) 97 190 { 98 (*(component_Counter-> in_COUNTER_DATA [i])) (*( in_BRANCH_COMPLETE_HISTORY [i])); 99 (*(component_Counter-> in_COUNTER_ADDSUB [i])) (*( in_BRANCH_COMPLETE_DIRECTION [i])); 100 (*(component_Counter->out_COUNTER_DATA [i])) (*(signal_BRANCH_COMPLETE_HISTORY [i])); 101 } 102 103 // =====[ component_RegisterFile ]==================================== 104 105 name_component = _name+"_RegisterFile"; 106 107 component_RegisterFile = new morpheo::behavioural::generic::registerfile::registerfile_monolithic::RegisterFile_Monolithic (name_component.c_str(), 108 #ifdef STATISTICS 109 _param_statistics , 110 #endif 111 *(_param._param_registerfile)); 112 113 // Instantiation 114 (*(component_RegisterFile->in_CLOCK)) (*(in_CLOCK)); 115 (*(component_RegisterFile->in_NRESET)) (*(in_NRESET)); 116 117 for (uint32_t i=0; i<_param._nb_prediction; i++) 118 { 119 (*(component_RegisterFile-> in_READ_VAL [i])) (*( in_PREDICT_VAL [i])); 120 (*(component_RegisterFile->out_READ_ACK [i])) (*(out_PREDICT_ACK [i])); 121 (*(component_RegisterFile-> in_READ_ADDRESS [i])) (*( in_PREDICT_ADDRESS [i])); 122 (*(component_RegisterFile->out_READ_DATA [i])) (*(out_PREDICT_HISTORY [i])); 123 } 124 125 for (uint32_t i=0; i<_param._nb_branch_complete; i++) 126 { 127 (*(component_RegisterFile-> in_WRITE_VAL [i])) (*( in_BRANCH_COMPLETE_VAL [i])); 128 (*(component_RegisterFile->out_WRITE_ACK [i])) (*( out_BRANCH_COMPLETE_ACK [i])); 129 (*(component_RegisterFile-> in_WRITE_ADDRESS [i])) (*( in_BRANCH_COMPLETE_ADDRESS [i])); 130 (*(component_RegisterFile-> in_WRITE_DATA [i])) (*(signal_BRANCH_COMPLETE_HISTORY [i])); 131 } 191 #ifdef POSITION 192 _component->interface_map (_name+"_Counter","counter_"+toString(i), 193 _name ,"branch_complete_"+toString(i)); 194 195 #endif 196 197 _component->port_map(_name+"_Counter", "in_COUNTER_" +toString(i)+"_DATA" , _name , "in_BRANCH_COMPLETE_"+toString(i)+"_HISTORY"); 198 _component->port_map(_name+"_Counter", "in_COUNTER_" +toString(i)+"_ADDSUB" , _name , "in_BRANCH_COMPLETE_"+toString(i)+"_DIRECTION"); 199 _component->port_map(_name+"_Counter", "out_COUNTER_"+toString(i)+"_DATA" , _name+"_RegisterFile", "in_WRITE_"+toString(i)+"_DATA"); 200 } 201 202 #ifdef POSITION 203 _component->generate_file(); 204 #endif 132 205 133 206 log_printf(FUNC,Pattern_History_Table,"allocation","End"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_deallocation.cpp
r15 r42 22 22 log_printf(FUNC,Pattern_History_Table,"deallocation","Begin"); 23 23 24 delete in_CLOCK;25 delete in_NRESET;24 delete in_CLOCK; 25 delete in_NRESET; 26 26 27 for (uint32_t i=0; i<_param._nb_prediction; i++) 28 { 29 delete in_PREDICT_VAL [i]; 30 delete out_PREDICT_ACK [i]; 31 delete in_PREDICT_ADDRESS [i]; 32 delete out_PREDICT_HISTORY [i]; 33 } 27 delete [] in_PREDICT_VAL ; 28 delete [] out_PREDICT_ACK ; 29 delete [] in_PREDICT_ADDRESS; 30 delete [] out_PREDICT_HISTORY; 34 31 35 delete in_PREDICT_VAL ; 36 delete out_PREDICT_ACK ; 37 delete in_PREDICT_ADDRESS; 38 delete out_PREDICT_HISTORY; 39 40 for (uint32_t i=0; i<_param._nb_branch_complete; i++) 41 { 42 delete in_BRANCH_COMPLETE_VAL [i]; 43 delete out_BRANCH_COMPLETE_ACK [i]; 44 delete in_BRANCH_COMPLETE_ADDRESS [i]; 45 delete in_BRANCH_COMPLETE_HISTORY [i]; 46 delete in_BRANCH_COMPLETE_DIRECTION [i]; 47 } 48 delete in_BRANCH_COMPLETE_VAL ; 49 delete out_BRANCH_COMPLETE_ACK ; 50 delete in_BRANCH_COMPLETE_ADDRESS; 51 delete in_BRANCH_COMPLETE_HISTORY; 52 delete in_BRANCH_COMPLETE_DIRECTION; 32 delete [] in_BRANCH_COMPLETE_VAL ; 33 delete [] out_BRANCH_COMPLETE_ACK ; 34 delete [] in_BRANCH_COMPLETE_ADDRESS; 35 delete [] in_BRANCH_COMPLETE_HISTORY; 36 delete [] in_BRANCH_COMPLETE_DIRECTION; 53 37 54 38 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 55 39 delete component_Counter; 56 40 delete component_RegisterFile; 41 42 delete _component; 57 43 58 44 log_printf(FUNC,Pattern_History_Table,"deallocation","End"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_vhdl.cpp
r2 r42 22 22 { 23 23 log_printf(FUNC,Pattern_History_Table,"vhdl","Begin"); 24 Vhdl vhdl (_name);24 Vhdl * vhdl = new Vhdl (_name); 25 25 26 vhdl.set_library_work (_name + "_Pack"); 27 vhdl.set_library_work (_name + "_RegisterFile_Pack"); 28 vhdl.set_library_work (_name + "_Counter_Pack"); 26 _interfaces->set_port(vhdl); 27 _component->vhdl_instance(vhdl); 29 28 30 vhdl_port (vhdl);31 29 vhdl_declaration (vhdl); 32 30 vhdl_body (vhdl); 33 31 34 vhdl.generate_file(); 32 vhdl->generate_file(); 33 34 delete vhdl; 35 35 36 log_printf(FUNC,Pattern_History_Table,"vhdl","End"); 36 37 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_vhdl_body.cpp
r15 r42 18 18 19 19 20 void Pattern_History_Table::vhdl_body (Vhdl & vhdl)20 void Pattern_History_Table::vhdl_body (Vhdl * & vhdl) 21 21 { 22 22 log_printf(FUNC,Pattern_History_Table,"vhdl_body","Begin"); 23 23 24 // vhdl .set_body ("-- Output : always at '1'");24 // vhdl->set_body ("-- Output : always at '1'"); 25 25 // for (uint32_t i=0; i<_param._nb_branch_complete; i++) 26 // vhdl .set_body ("out_BRANCH_COMPLETE_ACK_"+toString(i)+" <= '1';");26 // vhdl->set_body ("out_BRANCH_COMPLETE_ACK_"+toString(i)+" <= '1';"); 27 27 // for (uint32_t i=0; i<_param._nb_prediction ; i++) 28 // vhdl.set_body ("out_PREDICT_ACK_"+toString(i)+" <= '1';"); 29 // vhdl.set_body (""); 30 31 list<string> list_port_map; 32 33 for (uint32_t i=0; i<_param._nb_branch_complete; i++) 34 { 35 vhdl.set_body_component_port_map (list_port_map," in_COUNTER_DATA_"+toString(i)+" "," in_BRANCH_COMPLETE_HISTORY_"+toString(i)); 36 vhdl.set_body_component_port_map (list_port_map," in_COUNTER_ADDSUB_"+toString(i)+" "," in_BRANCH_COMPLETE_DIRECTION_"+toString(i) ); 37 vhdl.set_body_component_port_map (list_port_map,"out_COUNTER_DATA_"+toString(i)+" ","signal_BRANCH_COMPLETE_HISTORY_"+toString(i)); 38 } 39 vhdl.set_body_component ("component_Counter",_name+"_Counter",list_port_map); 40 41 42 list_port_map.clear(); 43 vhdl.set_body_component_port_map (list_port_map,"in_CLOCK ","in_CLOCK "); 44 vhdl.set_body_component_port_map (list_port_map,"in_NRESET","in_NRESET"); 45 46 for (uint32_t i=0; i<_param._nb_prediction; i++) 47 { 48 vhdl.set_body_component_port_map (list_port_map," in_READ_VAL_"+toString(i)+" "," in_PREDICT_VAL_"+toString(i)); 49 vhdl.set_body_component_port_map (list_port_map,"out_READ_ACK_"+toString(i)+" ","out_PREDICT_ACK_"+toString(i)); 50 vhdl.set_body_component_port_map (list_port_map," in_READ_ADDRESS_"+toString(i)+" "," in_PREDICT_ADDRESS_"+toString(i)); 51 vhdl.set_body_component_port_map (list_port_map,"out_READ_DATA_"+toString(i)+" ","out_PREDICT_HISTORY_"+toString(i)); 52 } 53 54 for (uint32_t i=0; i<_param._nb_branch_complete; i++) 55 { 56 vhdl.set_body_component_port_map (list_port_map," in_WRITE_VAL_"+toString(i)+" "," in_BRANCH_COMPLETE_VAL_"+toString(i)+""); 57 vhdl.set_body_component_port_map (list_port_map,"out_WRITE_ACK_"+toString(i)+" "," out_BRANCH_COMPLETE_ACK_"+toString(i)+""); 58 vhdl.set_body_component_port_map (list_port_map," in_WRITE_ADDRESS_"+toString(i)+""," in_BRANCH_COMPLETE_ADDRESS_"+toString(i)); 59 vhdl.set_body_component_port_map (list_port_map," in_WRITE_DATA_"+toString(i)+" ","signal_BRANCH_COMPLETE_HISTORY_"+toString(i)); 60 } 61 vhdl.set_body_component ("component_RegisterFile",_name+"_RegisterFile",list_port_map); 28 // vhdl->set_body ("out_PREDICT_ACK_"+toString(i)+" <= '1';"); 29 // vhdl->set_body (""); 62 30 63 31 log_printf(FUNC,Pattern_History_Table,"vhdl_body","End"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_vhdl_port.cpp
r15 r42 18 18 19 19 20 void Pattern_History_Table::vhdl_port (Vhdl& vhdl)21 {22 log_printf(FUNC,Pattern_History_Table,"vhdl_port","Begin");20 // void Pattern_History_Table::vhdl_port (Vhdl * & vhdl) 21 // { 22 // log_printf(FUNC,Pattern_History_Table,"vhdl_port","Begin"); 23 23 24 vhdl.set_port (" in_CLOCK" , IN, 1); 25 vhdl.set_port (" in_NRESET", IN, 1); 24 // _interfaces->set_port(vhdl); 26 25 27 for (uint32_t i=0; i<_param._nb_prediction; i++) 28 { 29 vhdl.set_port(" in_PREDICT_VAL_"+toString(i)+" ", IN, 1); 30 vhdl.set_port("out_PREDICT_ACK_"+toString(i)+" ",OUT, 1); 31 vhdl.set_port(" in_PREDICT_ADDRESS_"+toString(i)+" ", IN, static_cast<uint32_t>(ceil(log2(_param._nb_counter)))); 32 vhdl.set_port("out_PREDICT_HISTORY_"+toString(i)+" ",OUT, _param._size_counter); 33 } 34 for (uint32_t i=0; i<_param._nb_branch_complete; i++) 35 { 36 vhdl.set_port (" in_BRANCH_COMPLETE_VAL_"+toString(i)+" ", IN, 1); 37 vhdl.set_port ("out_BRANCH_COMPLETE_ACK_"+toString(i)+" ",OUT, 1); 38 vhdl.set_port (" in_BRANCH_COMPLETE_ADDRESS_"+toString(i)+" ", IN, static_cast<uint32_t>(ceil(log2(_param._nb_counter)))); 39 vhdl.set_port (" in_BRANCH_COMPLETE_HISTORY_"+toString(i)+" ", IN, _param._size_counter); 40 vhdl.set_port (" in_BRANCH_COMPLETE_DIRECTION_"+toString(i)+"", IN, 1); 41 } 42 43 log_printf(FUNC,Pattern_History_Table,"vhdl_port","End"); 44 }; 26 // log_printf(FUNC,Pattern_History_Table,"vhdl_port","End"); 27 // }; 45 28 46 29 }; // end namespace pattern_history_table -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_vhdl_signal.cpp
r2 r42 18 18 19 19 20 void Pattern_History_Table::vhdl_declaration (Vhdl & vhdl)20 void Pattern_History_Table::vhdl_declaration (Vhdl * & vhdl) 21 21 { 22 22 log_printf(FUNC,Pattern_History_Table,"vhdl_declaration","Begin"); 23 24 for (uint32_t i=0; i<_param._nb_branch_complete; i++)25 vhdl.set_signal ("signal_BRANCH_COMPLETE_HISTORY_"+toString(i), _param._size_counter);26 23 27 24 log_printf(FUNC,Pattern_History_Table,"vhdl_declaration","End"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_vhdl_testbench_transition.cpp
r15 r42 22 22 log_printf(FUNC,Pattern_History_Table,"vhdl_testbench_transition","Begin"); 23 23 24 #ifndef SYSTEMCASS_SPECIFIC 25 sc_cycle(0); 26 #endif 24 sc_start(0); 27 25 28 // In order with file Pattern_History_Table_vhdl_testbench_port.cpp 29 // Warning : if a output depend of a subcomponent, take directly the port of subcomponent 30 // (because we have no control on the ordonnancer's policy) 31 32 _vhdl_testbench->add_input (PORT_READ( in_NRESET)); 33 34 for (uint32_t i=0; i<_param._nb_prediction; i++) 35 { 36 _vhdl_testbench->add_input (PORT_READ( in_PREDICT_VAL [i])); 37 _vhdl_testbench->add_output (PORT_READ(component_RegisterFile->out_READ_ACK [i])); 38 _vhdl_testbench->add_input (PORT_READ( in_PREDICT_ADDRESS [i])); 39 _vhdl_testbench->add_output (PORT_READ(component_RegisterFile->out_READ_DATA [i])); 40 //_vhdl_testbench->add_output (PORT_READ(out_PREDICT_HISTORY [i])); 41 } 42 43 for (uint32_t i=0; i<_param._nb_branch_complete; i++) 44 { 45 _vhdl_testbench->add_input (PORT_READ( in_BRANCH_COMPLETE_VAL [i])); 46 _vhdl_testbench->add_output (PORT_READ(component_RegisterFile->out_WRITE_ACK [i])); 47 _vhdl_testbench->add_input (PORT_READ( in_BRANCH_COMPLETE_ADDRESS [i])); 48 _vhdl_testbench->add_input (PORT_READ( in_BRANCH_COMPLETE_HISTORY [i])); 49 _vhdl_testbench->add_input (PORT_READ( in_BRANCH_COMPLETE_DIRECTION[i])); 50 } 51 52 // add_test : 53 // - True : the cycle must be compare with the output of systemC 54 // - False : no test 55 _vhdl_testbench->add_test(true); 56 57 _vhdl_testbench->new_cycle (); // always at the end 26 _interfaces->testbench(); 58 27 59 28 log_printf(FUNC,Pattern_History_Table,"vhdl_testbench_transition","End"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/SelfTest/src/test.cpp
r2 r42 44 44 *********************************************************************/ 45 45 sc_clock CLOCK ("clock", 1.0, 0.5); 46 sc_signal<Tcontrol_t> NRESET; 46 47 47 48 sc_signal<Tcontrol_t> PREDICT_BHT_ACK [param._nb_prediction]; … … 68 69 cout << "<" << name << "> Instanciation of _Two_Level_Branch_Predictor_Glue" << endl; 69 70 70 #if defined(STATISTICS) or defined(VHDL_TESTBENCH)71 71 (*(_Two_Level_Branch_Predictor_Glue->in_CLOCK)) (CLOCK); 72 #endif 72 (*(_Two_Level_Branch_Predictor_Glue->in_NRESET)) (NRESET); 73 73 74 74 for (uint32_t i=0; i<param._nb_prediction; i++) … … 125 125 126 126 sc_start(0); 127 _Two_Level_Branch_Predictor_Glue->vhdl_testbench_label("Initialisation"); 127 128 128 cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} Initialisation" << endl; 129 129 130 131 _Two_Level_Branch_Predictor_Glue->vhdl_testbench_label("Test ack"); 130 NRESET.write(1); 131 132 132 cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} Test ack" << endl; 133 133 134 134 for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++) 135 135 { 136 _Two_Level_Branch_Predictor_Glue->vhdl_testbench_label("Iteration "+toString(iteration));137 138 136 // Branch History Table 139 137 if (param._have_bht) … … 191 189 192 190 193 _Two_Level_Branch_Predictor_Glue->vhdl_testbench_label("Test address");194 191 cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} Test address" << endl; 195 192 196 193 for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++) 197 194 { 198 _Two_Level_Branch_Predictor_Glue->vhdl_testbench_label("Iteration "+toString(iteration));199 200 195 predict_address = rand()%(1<<param._size_address ); 201 196 predict_bht_history = 0; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/include/Two_Level_Branch_Predictor_Glue.h
r5 r42 25 25 #include "Behavioural/include/Vhdl.h" 26 26 #endif 27 #ifdef VHDL_TESTBENCH 28 #include "Behavioural/include/Vhdl_Testbench.h" 29 #endif 27 #include "Behavioural/include/Component.h" 30 28 31 29 using namespace std; … … 58 56 #endif 59 57 60 #ifdef VHDL_TESTBENCH 61 private : Vhdl_Testbench * _vhdl_testbench; 62 #endif 58 public : Component * _component; 59 private : Interfaces * _interfaces; 63 60 64 61 #ifdef SYSTEMC … … 66 63 // Interface 67 64 public : SC_CLOCK * in_CLOCK ; 65 public : SC_IN (Tcontrol_t) * in_NRESET ; 68 66 69 67 public : SC_IN (Tcontrol_t) ** in_PREDICT_BHT_ACK ; … … 129 127 public : string statistics (uint32_t depth); 130 128 #endif 131 132 129 #if VHDL 133 130 public : void vhdl (void); 134 private : void vhdl_port (Vhdl & vhdl);135 private : void vhdl_declaration (Vhdl & vhdl);136 private : void vhdl_body (Vhdl & vhdl);131 private : void vhdl_port (Vhdl * & vhdl); 132 private : void vhdl_declaration (Vhdl * & vhdl); 133 private : void vhdl_body (Vhdl * & vhdl); 137 134 #endif 138 139 135 #ifdef VHDL_TESTBENCH 140 private : void vhdl_testbench_port (void);141 136 private : void vhdl_testbench_transition (void); 142 137 #endif 143 public : void vhdl_testbench_label (string label);144 138 }; 145 139 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue.cpp
r3 r42 34 34 log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"Two_Level_Branch_Predictor_Glue","Begin"); 35 35 36 #ifdef SYSTEMC 37 allocation (); 38 #endif 39 36 40 #ifdef STATISTICS 37 41 // Allocation of statistics … … 41 45 #endif 42 46 43 #ifdef VHDL_TESTBENCH44 // Creation of a testbench45 // -> port46 // -> clock's signals47 _vhdl_testbench = new Vhdl_Testbench (_name);48 vhdl_testbench_port ();49 _vhdl_testbench->set_clock ("in_CLOCK",false);50 #endif51 52 47 #ifdef VHDL 53 48 // generate the vhdl … … 56 51 57 52 #ifdef SYSTEMC 58 allocation ();59 60 53 #if defined(STATISTICS) or defined(VHDL_TESTBENCH) 61 54 SC_METHOD (transition); … … 192 185 log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"~Two_Level_Branch_Predictor_Glue","Begin"); 193 186 194 #ifdef VHDL_TESTBENCH195 // generate the test bench196 _vhdl_testbench->generate_file();197 delete _vhdl_testbench;198 #endif199 200 187 #ifdef STATISTICS 201 188 _stat->generate_file(statistics(0)); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_allocation.cpp
r2 r42 24 24 log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"allocation","Begin"); 25 25 26 #if defined(STATISTICS) or defined(VHDL_TESTBENCH) 27 in_CLOCK = new SC_CLOCK ("in_CLOCK"); 26 _component = new Component (); 27 28 Entity * entity = _component->set_entity (_name 29 ,"Two_Level_Branch_Predictor_Glue" 30 #ifdef POSITION 31 ,COMBINATORY 28 32 #endif 33 ); 29 34 35 _interfaces = entity->set_interfaces(); 36 37 // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 38 { 39 Interface * interface = _interfaces->set_interface("" 40 #ifdef POSITION 41 , IN 42 , SOUTH 43 , "Generalist interface" 44 #endif 45 ); 46 47 in_CLOCK = interface->set_signal_clk ("clock" ,1,CLOCK_VHDL_NO); 48 in_NRESET = interface->set_signal_in <Tcontrol_t> ("nreset",1,RESET_VHDL_NO); 49 } 50 51 // ~~~~~[ Interface : "Predict" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 30 52 if (_param._have_bht) 31 53 { … … 45 67 for (uint32_t i=0; i<_param._nb_prediction; i++) 46 68 { 69 Interface_fifo * interface = _interfaces->set_interface("predict_"+toString(i) 70 #ifdef POSITION 71 , IN 72 , WEST 73 , "Interface Predict" 74 #endif 75 ); 76 47 77 if (_param._have_bht) 48 78 { 49 rename = " in_PREDICT_BHT_ACK_" +toString(i); 50 in_PREDICT_BHT_ACK [i] = new SC_IN (Tcontrol_t) (rename.c_str()); 51 52 rename = "out_PREDICT_BHT_ADDRESS_"+toString(i); 53 out_PREDICT_BHT_ADDRESS [i] = new SC_OUT(Taddress_t) (rename.c_str()); 79 in_PREDICT_BHT_ACK [i] = interface->set_signal_in <Tcontrol_t> ("bht_ack" ,1); 80 out_PREDICT_BHT_ADDRESS [i] = interface->set_signal_out <Taddress_t> ("bht_address",_param._bht_size_address); 54 81 } 55 82 if (_param._have_pht) 56 83 { 57 rename = " in_PREDICT_PHT_ACK_" +toString(i); 58 in_PREDICT_PHT_ACK [i] = new SC_IN (Tcontrol_t) (rename.c_str()); 59 60 rename = "out_PREDICT_PHT_ADDRESS_"+toString(i); 61 out_PREDICT_PHT_ADDRESS [i] = new SC_OUT(Taddress_t) (rename.c_str()); 84 in_PREDICT_PHT_ACK [i] = interface->set_signal_in <Tcontrol_t> ("pht_ack" ,1); 85 out_PREDICT_PHT_ADDRESS [i] = interface->set_signal_out <Taddress_t> ("pht_address",_param._pht_size_address); 62 86 } 63 87 if (_param._have_bht and _param._have_pht) 64 { 65 rename = " in_PREDICT_BHT_HISTORY_"+toString(i); 66 in_PREDICT_BHT_HISTORY [i] = new SC_IN (Tbht_history_t) (rename.c_str()); 67 } 68 rename = "out_PREDICT_ACK_" +toString(i); 69 out_PREDICT_ACK [i] = new SC_OUT(Tcontrol_t) (rename.c_str()); 70 71 rename = " in_PREDICT_ADDRESS_" +toString(i); 72 in_PREDICT_ADDRESS [i] = new SC_IN (Taddress_t) (rename.c_str()); 88 in_PREDICT_BHT_HISTORY [i] = interface->set_signal_in <Tbht_history_t> ("bht_history",_param._bht_size_history); 89 out_PREDICT_ACK [i] = interface->set_signal_out <Tcontrol_t> ("ack" ,1); 90 in_PREDICT_ADDRESS [i] = interface->set_signal_in <Taddress_t> ("address" ,_param._size_address); 73 91 } 92 93 // ~~~~~[ Interface : "branch_complete" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 74 94 75 95 if (_param._have_bht) … … 91 111 for (uint32_t i=0; i<_param._nb_branch_complete; i++) 92 112 { 113 Interface_fifo * interface = _interfaces->set_interface("branch_complete_"+toString(i) 114 #ifdef POSITION 115 , IN 116 , EAST 117 , "Interface branch complete" 118 #endif 119 ); 93 120 if (_param._have_bht) 94 121 { 95 rename = " in_BRANCH_COMPLETE_BHT_ACK_" +toString(i); 96 in_BRANCH_COMPLETE_BHT_ACK [i] = new SC_IN (Tcontrol_t) (rename.c_str()); 97 98 rename = "out_BRANCH_COMPLETE_BHT_ADDRESS_"+toString(i); 99 out_BRANCH_COMPLETE_BHT_ADDRESS [i] = new SC_OUT(Taddress_t) (rename.c_str()); 122 in_BRANCH_COMPLETE_BHT_ACK [i] = interface->set_signal_in <Tcontrol_t> ("bht_ack" ,1); 123 out_BRANCH_COMPLETE_BHT_ADDRESS [i] = interface->set_signal_out <Taddress_t> ("bht_address",_param._bht_size_address); 100 124 } 101 125 if (_param._have_pht) 102 126 { 103 rename = " in_BRANCH_COMPLETE_PHT_ACK_" +toString(i); 104 in_BRANCH_COMPLETE_PHT_ACK [i] = new SC_IN (Tcontrol_t) (rename.c_str()); 105 106 rename = "out_BRANCH_COMPLETE_PHT_ADDRESS_"+toString(i); 107 out_BRANCH_COMPLETE_PHT_ADDRESS [i] = new SC_OUT(Taddress_t) (rename.c_str()); 127 in_BRANCH_COMPLETE_PHT_ACK [i] = interface->set_signal_in <Tcontrol_t> ("pht_ack" ,1); 128 out_BRANCH_COMPLETE_PHT_ADDRESS [i] = interface->set_signal_out <Taddress_t> ("pht_address",_param._pht_size_address); 108 129 } 109 130 if (_param._have_bht and _param._have_pht) 110 { 111 rename = " in_BRANCH_COMPLETE_BHT_HISTORY_"+toString(i); 112 in_BRANCH_COMPLETE_BHT_HISTORY [i] = new SC_IN (Tbht_history_t) (rename.c_str()); 113 } 114 rename = "out_BRANCH_COMPLETE_ACK_" +toString(i); 115 out_BRANCH_COMPLETE_ACK [i] = new SC_OUT(Tcontrol_t) (rename.c_str()); 116 117 rename = " in_BRANCH_COMPLETE_ADDRESS_" +toString(i); 118 in_BRANCH_COMPLETE_ADDRESS [i] = new SC_IN (Taddress_t) (rename.c_str()); 131 in_BRANCH_COMPLETE_BHT_HISTORY [i] = interface->set_signal_in <Tbht_history_t> ("bht_history",_param._bht_size_history); 132 133 out_BRANCH_COMPLETE_ACK [i] = interface->set_signal_out <Tcontrol_t> ("ack" ,1); 134 in_BRANCH_COMPLETE_ADDRESS [i] = interface->set_signal_in <Taddress_t> ("address" ,_param._size_address); 119 135 } 120 136 121 137 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 138 139 #ifdef POSITION 140 _component->generate_file(); 141 #endif 122 142 123 143 log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"allocation","End"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_deallocation.cpp
r2 r42 22 22 log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"deallocation","Begin"); 23 23 24 delete in_CLOCK; 24 delete in_CLOCK; 25 delete in_NRESET; 25 26 26 for (uint32_t i=0; i<_param._nb_prediction; i++)27 {28 if (_param._have_bht)29 {30 delete in_PREDICT_BHT_ACK [i];31 delete out_PREDICT_BHT_ADDRESS [i];32 }33 if (_param._have_pht)34 {35 delete in_PREDICT_PHT_ACK [i];36 delete out_PREDICT_PHT_ADDRESS [i];37 }38 if (_param._have_bht and _param._have_pht)39 delete in_PREDICT_BHT_HISTORY [i];40 delete out_PREDICT_ACK [i];41 delete in_PREDICT_ADDRESS [i];42 }43 27 if (_param._have_bht) 44 28 { 45 delete in_PREDICT_BHT_ACK ;46 delete out_PREDICT_BHT_ADDRESS;29 delete [] in_PREDICT_BHT_ACK ; 30 delete [] out_PREDICT_BHT_ADDRESS; 47 31 } 48 32 if (_param._have_pht) 49 33 { 50 delete in_PREDICT_PHT_ACK ;51 delete out_PREDICT_PHT_ADDRESS;34 delete [] in_PREDICT_PHT_ACK ; 35 delete [] out_PREDICT_PHT_ADDRESS; 52 36 } 53 37 if (_param._have_bht and _param._have_pht) 54 delete in_PREDICT_BHT_HISTORY;38 delete [] in_PREDICT_BHT_HISTORY; 55 39 56 delete out_PREDICT_ACK ;57 delete in_PREDICT_ADDRESS ;40 delete [] out_PREDICT_ACK ; 41 delete [] in_PREDICT_ADDRESS ; 58 42 59 for (uint32_t i=0; i<_param._nb_branch_complete; i++)60 {61 if (_param._have_bht)62 {63 delete in_BRANCH_COMPLETE_BHT_ACK [i];64 delete out_BRANCH_COMPLETE_BHT_ADDRESS [i];65 }66 if (_param._have_pht)67 {68 delete in_BRANCH_COMPLETE_PHT_ACK [i];69 delete out_BRANCH_COMPLETE_PHT_ADDRESS [i];70 }71 if (_param._have_bht and _param._have_pht)72 delete in_BRANCH_COMPLETE_BHT_HISTORY [i];73 delete out_BRANCH_COMPLETE_ACK [i];74 delete in_BRANCH_COMPLETE_ADDRESS [i];75 }76 43 if (_param._have_bht) 77 44 { 78 delete in_BRANCH_COMPLETE_BHT_ACK ;79 delete out_BRANCH_COMPLETE_BHT_ADDRESS;45 delete [] in_BRANCH_COMPLETE_BHT_ACK ; 46 delete [] out_BRANCH_COMPLETE_BHT_ADDRESS; 80 47 } 81 48 if (_param._have_pht) 82 49 { 83 delete in_BRANCH_COMPLETE_PHT_ACK ;84 delete out_BRANCH_COMPLETE_PHT_ADDRESS;50 delete [] in_BRANCH_COMPLETE_PHT_ACK ; 51 delete [] out_BRANCH_COMPLETE_PHT_ADDRESS; 85 52 } 86 53 if (_param._have_bht and _param._have_pht) 87 delete in_BRANCH_COMPLETE_BHT_HISTORY;88 delete out_BRANCH_COMPLETE_ACK ;89 delete in_BRANCH_COMPLETE_ADDRESS ;54 delete [] in_BRANCH_COMPLETE_BHT_HISTORY; 55 delete [] out_BRANCH_COMPLETE_ACK ; 56 delete [] in_BRANCH_COMPLETE_ADDRESS ; 90 57 91 58 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 59 delete _component; 92 60 93 61 log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"deallocation","End"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_vhdl.cpp
r2 r42 22 22 { 23 23 log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"vhdl","Begin"); 24 Vhdl vhdl (_name); 24 25 Vhdl * vhdl = new Vhdl (_name); 25 26 26 vhdl .set_library_work (_name + "_Pack");27 vhdl->set_library_work (_name + "_Pack"); 27 28 28 29 vhdl_port (vhdl); … … 30 31 vhdl_body (vhdl); 31 32 32 vhdl.generate_file(); 33 vhdl->generate_file(); 34 35 delete vhdl; 36 33 37 log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"vhdl","End"); 34 38 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_vhdl_body.cpp
r2 r42 18 18 19 19 20 void Two_Level_Branch_Predictor_Glue::vhdl_body (Vhdl & vhdl)20 void Two_Level_Branch_Predictor_Glue::vhdl_body (Vhdl * & vhdl) 21 21 { 22 22 log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"vhdl_body","Begin"); 23 23 24 vhdl .set_body ("-- ack output");24 vhdl->set_body ("-- ack output"); 25 25 for (uint32_t i=0; i<_param._nb_prediction; i++) 26 26 { … … 28 28 29 29 if (_param._have_bht) 30 bht_ack = "in_PREDICT_ BHT_ACK_"+toString(i);30 bht_ack = "in_PREDICT_"+toString(i)+"_BHT_ACK"; 31 31 else 32 32 bht_ack = "'1'"; 33 33 34 34 if (_param._have_pht) 35 pht_ack = "in_PREDICT_ PHT_ACK_"+toString(i);35 pht_ack = "in_PREDICT_"+toString(i)+"_PHT_ACK"; 36 36 else 37 37 pht_ack = "'1'"; 38 38 39 vhdl .set_body ("out_PREDICT_ACK_"+toString(i)+"<= "+bht_ack+" and "+pht_ack+";");39 vhdl->set_body ("out_PREDICT_"+toString(i)+"_ACK <= "+bht_ack+" and "+pht_ack+";"); 40 40 } 41 41 … … 45 45 46 46 if (_param._have_bht) 47 bht_ack = "in_BRANCH_COMPLETE_ BHT_ACK_"+toString(i);47 bht_ack = "in_BRANCH_COMPLETE_"+toString(i)+"_BHT_ACK"; 48 48 else 49 49 bht_ack = "'1'"; 50 50 51 51 if (_param._have_pht) 52 pht_ack = "in_BRANCH_COMPLETE_ PHT_ACK_"+toString(i);52 pht_ack = "in_BRANCH_COMPLETE_"+toString(i)+"_PHT_ACK"; 53 53 else 54 54 pht_ack = "'1'"; 55 55 56 vhdl .set_body ("out_BRANCH_COMPLETE_ACK_"+toString(i)+"<= "+bht_ack+" and "+pht_ack+";");56 vhdl->set_body ("out_BRANCH_COMPLETE_"+toString(i)+"_ACK <= "+bht_ack+" and "+pht_ack+";"); 57 57 } 58 58 59 vhdl .set_body ("");60 vhdl .set_body ("-- address output");59 vhdl->set_body (""); 60 vhdl->set_body ("-- address output"); 61 61 62 62 for (uint32_t i=0; i<_param._nb_prediction; i++) … … 64 64 // The address is higher than the address size of bht 65 65 if (_param._have_bht) 66 vhdl .set_body ("out_PREDICT_BHT_ADDRESS_"+toString(i)+" <= in_PREDICT_ADDRESS_"+toString(i)+std_logic_range(_param._bht_size_address)+";");66 vhdl->set_body ("out_PREDICT_"+toString(i)+"_BHT_ADDRESS <= in_PREDICT_"+toString(i)+"_ADDRESS"+std_logic_range(_param._bht_size_address)+";"); 67 67 68 68 if (_param._have_pht) … … 93 93 { 94 94 min = _param._pht_size_address_shift; 95 vhdl .set_body ("out_PREDICT_PHT_ADDRESS_"+toString(i)+std_logic_range(min) + " <= in_PREDICT_BHT_HISTORY_"+toString(i)+std_logic_range(min)+";");95 vhdl->set_body ("out_PREDICT_"+toString(i)+"_PHT_ADDRESS"+std_logic_range(min) + " <= in_PREDICT_"+toString(i)+"_BHT_HISTORY"+std_logic_range(min)+";"); 96 96 } 97 97 … … 99 99 { 100 100 max = _param._bht_size_history; 101 vhdl .set_body ("out_PREDICT_PHT_ADDRESS_"+toString(i)+std_logic_range(_param._pht_size_address-1,max) + " <= in_PREDICT_ADDRESS_"+toString(i)+std_logic_range(_param._pht_size_address-1-_param._pht_size_address_shift, _param._pht_size_address_share)+";");101 vhdl->set_body ("out_PREDICT_"+toString(i)+"_PHT_ADDRESS"+std_logic_range(_param._pht_size_address-1,max) + " <= in_PREDICT_"+toString(i)+"_ADDRESS"+std_logic_range(_param._pht_size_address-1-_param._pht_size_address_shift, _param._pht_size_address_share)+";"); 102 102 } 103 103 104 104 // intersection 105 105 if (_param._pht_size_address_share > 0) 106 vhdl .set_body ("out_PREDICT_PHT_ADDRESS_"+toString(i)+std_logic_range(max-1,min) + " <= in_PREDICT_ADDRESS_"+toString(i)+std_logic_range(_param._pht_size_address_share-1,0)+" xor in_PREDICT_BHT_HISTORY_"+toString(i)+std_logic_range(max-1,min)+";");106 vhdl->set_body ("out_PREDICT_"+toString(i)+"_PHT_ADDRESS"+std_logic_range(max-1,min) + " <= in_PREDICT_"+toString(i)+"_ADDRESS"+std_logic_range(_param._pht_size_address_share-1,0)+" xor in_PREDICT_"+toString(i)+"_BHT_HISTORY"+std_logic_range(max-1,min)+";"); 107 107 } 108 108 else 109 vhdl .set_body ("out_PREDICT_PHT_ADDRESS_"+toString(i)+" <= in_PREDICT_ADDRESS_"+toString(i)+std_logic_range(_param._pht_size_address)+";");109 vhdl->set_body ("out_PREDICT_"+toString(i)+"_PHT_ADDRESS <= in_PREDICT_"+toString(i)+"_ADDRESS"+std_logic_range(_param._pht_size_address)+";"); 110 110 } 111 111 } … … 115 115 // The address is higher than the address size of bht 116 116 if (_param._have_bht) 117 vhdl .set_body ("out_BRANCH_COMPLETE_BHT_ADDRESS_"+toString(i)+" <= in_BRANCH_COMPLETE_ADDRESS_"+toString(i)+std_logic_range(_param._bht_size_address)+";");117 vhdl->set_body ("out_BRANCH_COMPLETE_"+toString(i)+"_BHT_ADDRESS <= in_BRANCH_COMPLETE_"+toString(i)+"_ADDRESS"+std_logic_range(_param._bht_size_address)+";"); 118 118 119 119 if (_param._have_pht) … … 129 129 { 130 130 min = _param._pht_size_address_shift; 131 vhdl .set_body ("out_BRANCH_COMPLETE_PHT_ADDRESS_"+toString(i)+std_logic_range(min) + " <= in_BRANCH_COMPLETE_BHT_HISTORY_"+toString(i)+std_logic_range(min)+";");131 vhdl->set_body ("out_BRANCH_COMPLETE_"+toString(i)+"_PHT_ADDRESS"+std_logic_range(min) + " <= in_BRANCH_COMPLETE_"+toString(i)+"_BHT_HISTORY"+std_logic_range(min)+";"); 132 132 } 133 133 … … 135 135 { 136 136 max = _param._bht_size_history; 137 vhdl .set_body ("out_BRANCH_COMPLETE_PHT_ADDRESS_"+toString(i)+std_logic_range(_param._pht_size_address-1,max) + " <= in_BRANCH_COMPLETE_ADDRESS_"+toString(i)+std_logic_range(_param._pht_size_address-1-_param._pht_size_address_shift, _param._pht_size_address_share)+";");137 vhdl->set_body ("out_BRANCH_COMPLETE_"+toString(i)+"_PHT_ADDRESS"+std_logic_range(_param._pht_size_address-1,max) + " <= in_BRANCH_COMPLETE_"+toString(i)+"_ADDRESS"+std_logic_range(_param._pht_size_address-1-_param._pht_size_address_shift, _param._pht_size_address_share)+";"); 138 138 } 139 139 140 140 // intersection 141 141 if (_param._pht_size_address_share > 0) 142 vhdl .set_body ("out_BRANCH_COMPLETE_PHT_ADDRESS_"+toString(i)+std_logic_range(max-1,min) + " <= in_BRANCH_COMPLETE_ADDRESS_"+toString(i)+std_logic_range(_param._pht_size_address_share-1,0)+" xor in_BRANCH_COMPLETE_BHT_HISTORY_"+toString(i)+std_logic_range(max-1,min)+";");142 vhdl->set_body ("out_BRANCH_COMPLETE_"+toString(i)+"_PHT_ADDRESS"+std_logic_range(max-1,min) + " <= in_BRANCH_COMPLETE_"+toString(i)+"_ADDRESS"+std_logic_range(_param._pht_size_address_share-1,0)+" xor in_BRANCH_COMPLETE_"+toString(i)+"_BHT_HISTORY"+std_logic_range(max-1,min)+";"); 143 143 } 144 144 else 145 vhdl .set_body ("out_BRANCH_COMPLETE_PHT_ADDRESS_"+toString(i)+" <= in_BRANCH_COMPLETE_ADDRESS_"+toString(i)+std_logic_range(_param._pht_size_address)+";");145 vhdl->set_body ("out_BRANCH_COMPLETE_"+toString(i)+"_PHT_ADDRESS <= in_BRANCH_COMPLETE_"+toString(i)+"_ADDRESS"+std_logic_range(_param._pht_size_address)+";"); 146 146 } 147 147 } -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_vhdl_declaration.cpp
r2 r42 18 18 19 19 20 void Two_Level_Branch_Predictor_Glue::vhdl_declaration (Vhdl & vhdl)20 void Two_Level_Branch_Predictor_Glue::vhdl_declaration (Vhdl * & vhdl) 21 21 { 22 22 log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"vhdl_declaration","Begin"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_vhdl_port.cpp
r3 r42 18 18 19 19 20 void Two_Level_Branch_Predictor_Glue::vhdl_port (Vhdl & vhdl)20 void Two_Level_Branch_Predictor_Glue::vhdl_port (Vhdl * & vhdl) 21 21 { 22 22 log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"vhdl_port","Begin"); 23 23 24 for (uint32_t i=0; i<_param._nb_prediction; i++) 25 { 26 if (_param._have_bht) 27 { 28 vhdl.set_port (" in_PREDICT_BHT_ACK_" +toString(i), IN, 1); 29 vhdl.set_port ("out_PREDICT_BHT_ADDRESS_"+toString(i),OUT,_param._bht_size_address); 30 } 31 if (_param._have_bht and _param._have_pht) 32 vhdl.set_port (" in_PREDICT_BHT_HISTORY_"+toString(i), IN,_param._bht_size_history); 33 if (_param._have_pht) 34 { 35 vhdl.set_port (" in_PREDICT_PHT_ACK_" +toString(i), IN, 1); 36 vhdl.set_port ("out_PREDICT_PHT_ADDRESS_"+toString(i),OUT,_param._pht_size_address); 37 } 38 39 vhdl.set_port ("out_PREDICT_ACK_" +toString(i),OUT, 1); 40 vhdl.set_port (" in_PREDICT_ADDRESS_" +toString(i), IN,_param._size_address); 41 } 42 43 for (uint32_t i=0; i<_param._nb_branch_complete; i++) 44 { 45 if (_param._have_bht) 46 { 47 vhdl.set_port (" in_BRANCH_COMPLETE_BHT_ACK_" +toString(i), IN, 1); 48 vhdl.set_port ("out_BRANCH_COMPLETE_BHT_ADDRESS_"+toString(i),OUT,_param._bht_size_address); 49 } 50 if (_param._have_bht and _param._have_pht) 51 vhdl.set_port (" in_BRANCH_COMPLETE_BHT_HISTORY_"+toString(i), IN,_param._bht_size_history); 52 if (_param._have_pht) 53 { 54 vhdl.set_port (" in_BRANCH_COMPLETE_PHT_ACK_" +toString(i), IN, 1); 55 vhdl.set_port ("out_BRANCH_COMPLETE_PHT_ADDRESS_"+toString(i),OUT,_param._pht_size_address); 56 } 57 vhdl.set_port ("out_BRANCH_COMPLETE_ACK_" +toString(i),OUT, 1); 58 vhdl.set_port (" in_BRANCH_COMPLETE_ADDRESS_" +toString(i), IN,_param._size_address); 59 } 24 _interfaces->set_port(vhdl); 60 25 61 26 log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"vhdl_port","End"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/src/Two_Level_Branch_Predictor_Glue_vhdl_testbench_transition.cpp
r2 r42 22 22 log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"vhdl_testbench_transition","Begin"); 23 23 24 #ifndef SYSTEMCASS_SPECIFIC 25 sc_cycle(0); 26 #endif 24 sc_start(0); 27 25 28 // In order with file Two_Level_Branch_Predictor_Glue_vhdl_testbench_port.cpp 29 // Warning : if a output depend of a subcomponent, take directly the port of subcomponent 30 // (because we have no control on the ordonnancer's policy) 31 32 // _vhdl_testbench->add_input (PORT_READ( in_NRESET)); 33 for (uint32_t i=0; i<_param._nb_prediction; i++) 34 { 35 if (_param._have_bht) 36 { 37 _vhdl_testbench->add_input (PORT_READ( in_PREDICT_BHT_ACK [i])); 38 _vhdl_testbench->add_output (PORT_READ(out_PREDICT_BHT_ADDRESS [i])); 39 } 40 if (_param._have_bht and _param._have_pht) 41 _vhdl_testbench->add_input (PORT_READ( in_PREDICT_BHT_HISTORY [i])); 42 if (_param._have_pht) 43 { 44 _vhdl_testbench->add_input (PORT_READ( in_PREDICT_PHT_ACK [i])); 45 _vhdl_testbench->add_output (PORT_READ(out_PREDICT_PHT_ADDRESS [i])); 46 } 47 _vhdl_testbench->add_output (PORT_READ(out_PREDICT_ACK [i])); 48 _vhdl_testbench->add_input (PORT_READ( in_PREDICT_ADDRESS [i])); 49 } 50 51 for (uint32_t i=0; i<_param._nb_branch_complete; i++) 52 { 53 if (_param._have_bht) 54 { 55 _vhdl_testbench->add_input (PORT_READ( in_BRANCH_COMPLETE_BHT_ACK [i])); 56 _vhdl_testbench->add_output (PORT_READ(out_BRANCH_COMPLETE_BHT_ADDRESS [i])); 57 } 58 if (_param._have_bht and _param._have_pht) 59 _vhdl_testbench->add_input (PORT_READ( in_BRANCH_COMPLETE_BHT_HISTORY [i])); 60 if (_param._have_pht) 61 { 62 _vhdl_testbench->add_input (PORT_READ( in_BRANCH_COMPLETE_PHT_ACK [i])); 63 _vhdl_testbench->add_output (PORT_READ(out_BRANCH_COMPLETE_PHT_ADDRESS [i])); 64 } 65 _vhdl_testbench->add_output (PORT_READ(out_BRANCH_COMPLETE_ACK [i])); 66 _vhdl_testbench->add_input (PORT_READ( in_BRANCH_COMPLETE_ADDRESS [i])); 67 } 68 // add_test : 69 // - True : the cycle must be compare with the output of systemC 70 // - False : no test 71 _vhdl_testbench->add_test(true); 72 73 _vhdl_testbench->new_cycle (); // always at the end 26 _interfaces->testbench(); 74 27 75 28 log_printf(FUNC,Two_Level_Branch_Predictor_Glue,"vhdl_testbench_transition","End"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/include/Two_Level_Branch_Predictor.h
r15 r42 30 30 #include "Behavioural/include/Vhdl.h" 31 31 #endif 32 #ifdef VHDL_TESTBENCH 33 #include "Behavioural/include/Vhdl_Testbench.h" 34 #endif 32 #include "Behavioural/include/Component.h" 35 33 36 34 using namespace std; … … 62 60 #endif 63 61 64 #ifdef VHDL_TESTBENCH 65 private : Vhdl_Testbench * _vhdl_testbench; 66 #endif 62 public : Component * _component; 63 private : Interfaces * _interfaces; 67 64 68 65 #ifdef SYSTEMC … … 138 135 #if VHDL 139 136 public : void vhdl (void); 140 private : void vhdl_port (Vhdl & vhdl);141 private : void vhdl_declaration (Vhdl & vhdl);142 private : void vhdl_body (Vhdl & vhdl);137 private : void vhdl_port (Vhdl * & vhdl); 138 private : void vhdl_declaration (Vhdl * & vhdl); 139 private : void vhdl_body (Vhdl * & vhdl); 143 140 #endif 144 145 141 #ifdef VHDL_TESTBENCH 146 private : void vhdl_testbench_port (void);147 142 private : void vhdl_testbench_transition (void); 148 143 #endif 149 public : void vhdl_testbench_label (string label);150 144 }; 151 145 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor.cpp
r5 r42 33 33 log_printf(FUNC,Two_Level_Branch_Predictor,"Two_Level_Branch_Predictor","Begin"); 34 34 35 #ifdef SYSTEMC 36 allocation (); 37 #endif 38 35 39 #ifdef STATISTICS 36 40 // Allocation of statistics … … 38 42 param_statistics , 39 43 param); 40 #endif41 42 #ifdef VHDL_TESTBENCH43 // Creation of a testbench44 // -> port45 // -> clock's signals46 _vhdl_testbench = new Vhdl_Testbench (_name);47 vhdl_testbench_port ();48 _vhdl_testbench->set_clock ("in_CLOCK",true);49 44 #endif 50 45 … … 55 50 56 51 #ifdef SYSTEMC 57 allocation ();58 59 52 #if (defined(STATISTICS) || defined (VHDL_TESTBENCH)) 60 53 SC_METHOD (transition); … … 79 72 log_printf(FUNC,Two_Level_Branch_Predictor,"~Two_Level_Branch_Predictor","Begin"); 80 73 81 #ifdef VHDL_TESTBENCH82 // generate the test bench83 _vhdl_testbench->generate_file();84 delete _vhdl_testbench;85 #endif86 87 74 #ifdef STATISTICS 88 75 _stat->generate_file(statistics(0)); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_allocation.cpp
r15 r42 22 22 log_printf(FUNC,Two_Level_Branch_Predictor,"allocation","Begin"); 23 23 24 in_CLOCK = new SC_CLOCK ("in_CLOCK"); 25 in_NRESET = new SC_IN (Tcontrol_t) ("in_NRESET"); 24 _component = new Component (); 25 26 Entity * entity = _component->set_entity (_name 27 ,"Two_Level_Branch_Predictor" 28 #ifdef POSITION 29 ,MIXTE 30 #endif 31 ); 32 33 _interfaces = entity->set_interfaces(); 34 35 // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 36 { 37 Interface * interface = _interfaces->set_interface("" 38 #ifdef POSITION 39 , IN 40 , SOUTH 41 , "Generalist interface" 42 #endif 43 ); 44 45 in_CLOCK = interface->set_signal_clk ("clock" ,1); 46 in_NRESET = interface->set_signal_in <Tcontrol_t> ("nreset",1,RESET_VHDL_YES); 47 } 48 49 // ~~~~~[ Interface : "predict" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 26 50 27 51 in_PREDICT_VAL = new SC_IN (Tcontrol_t) * [_param._nb_prediction ]; … … 32 56 if (_param._have_pht) 33 57 out_PREDICT_PHT_HISTORY = new SC_OUT(Tpht_history_t) * [_param._nb_prediction ]; 34 if (_param._have_bht)35 {36 signal_PREDICT_BHT_ACK = new SC_SIGNAL(Tcontrol_t) * [_param._nb_prediction];37 signal_PREDICT_BHT_ADDRESS = new SC_SIGNAL(Taddress_t) * [_param._nb_prediction];38 }39 if (_param._have_pht)40 {41 signal_PREDICT_PHT_ACK = new SC_SIGNAL(Tcontrol_t) * [_param._nb_prediction];42 signal_PREDICT_PHT_ADDRESS = new SC_SIGNAL(Taddress_t) * [_param._nb_prediction];43 }44 58 45 59 for (uint32_t i=0; i<_param._nb_prediction; i++) 46 60 { 47 rename = "in_PREDICT_VAL_" +toString(i); 48 in_PREDICT_VAL [i] = new SC_IN (Tcontrol_t) (rename.c_str()); 49 50 rename = "out_PREDICT_ACK_" +toString(i); 51 out_PREDICT_ACK [i] = new SC_OUT(Tcontrol_t) (rename.c_str()); 52 53 rename = "in_PREDICT_ADDRESS_" +toString(i); 54 in_PREDICT_ADDRESS [i] = new SC_IN (Taddress_t) (rename.c_str()); 55 61 Interface_fifo * interface = _interfaces->set_interface("predict_"+toString(i) 62 #ifdef POSITION 63 , IN 64 , WEST 65 , "Interface Predict" 66 #endif 67 ); 68 69 in_PREDICT_VAL [i] = interface->set_signal_valack_in ("val" , VAL); 70 out_PREDICT_ACK [i] = interface->set_signal_valack_out ("ack" , ACK); 71 in_PREDICT_ADDRESS [i] = interface->set_signal_in <Taddress_t> ("address", _param._size_address); 56 72 if (_param._have_bht) 57 { 58 rename = "out_PREDICT_BHT_HISTORY_"+toString(i); 59 out_PREDICT_BHT_HISTORY [i] = new SC_OUT(Tbht_history_t) (rename.c_str()); 60 } 61 73 out_PREDICT_BHT_HISTORY [i] = interface->set_signal_out <Tbht_history_t> ("bht_history", _param._bht_size_shifter); 62 74 if (_param._have_pht) 63 { 64 rename = "out_PREDICT_PHT_HISTORY_"+toString(i); 65 out_PREDICT_PHT_HISTORY [i] = new SC_OUT(Tpht_history_t) (rename.c_str()); 66 } 67 68 if (_param._have_bht) 69 { 70 rename = "signal_PREDICT_BHT_ACK_" +toString(i); 71 signal_PREDICT_BHT_ACK [i] = new SC_SIGNAL(Tcontrol_t) (rename.c_str()); 72 73 rename = "signal_PREDICT_BHT_ADDRESS_"+toString(i); 74 signal_PREDICT_BHT_ADDRESS [i] = new SC_SIGNAL(Taddress_t) (rename.c_str()); 75 } 76 77 if (_param._have_pht) 78 { 79 rename = "signal_PREDICT_PHT_ACK_" +toString(i); 80 signal_PREDICT_PHT_ACK [i] = new SC_SIGNAL(Tcontrol_t) (rename.c_str()); 81 82 rename = "signal_PREDICT_PHT_ADDRESS_"+toString(i); 83 signal_PREDICT_PHT_ADDRESS [i] = new SC_SIGNAL(Taddress_t) (rename.c_str()); 84 } 85 } 75 out_PREDICT_PHT_HISTORY [i] = interface->set_signal_out <Tpht_history_t> ("pht_history", _param._pht_size_counter); 76 } 77 78 // ~~~~~[ Interface : "branch_complete" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 86 79 87 80 in_BRANCH_COMPLETE_VAL = new SC_IN (Tcontrol_t) * [_param._nb_branch_complete]; … … 93 86 in_BRANCH_COMPLETE_PHT_HISTORY = new SC_IN (Tpht_history_t) * [_param._nb_branch_complete]; 94 87 in_BRANCH_COMPLETE_DIRECTION = new SC_IN (Tcontrol_t) * [_param._nb_branch_complete]; 95 if (_param._have_bht)96 {97 signal_BRANCH_COMPLETE_BHT_ACK = new SC_SIGNAL(Tcontrol_t) * [_param._nb_branch_complete];98 signal_BRANCH_COMPLETE_BHT_ADDRESS = new SC_SIGNAL(Taddress_t) * [_param._nb_branch_complete];99 }100 if (_param._have_pht)101 {102 signal_BRANCH_COMPLETE_PHT_ACK = new SC_SIGNAL(Tcontrol_t) * [_param._nb_branch_complete];103 signal_BRANCH_COMPLETE_PHT_ADDRESS = new SC_SIGNAL(Taddress_t) * [_param._nb_branch_complete];104 }105 88 106 89 for (uint32_t i=0; i<_param._nb_branch_complete; i++) 107 90 { 108 rename = "in_BRANCH_COMPLETE_VAL_" +toString(i); 109 in_BRANCH_COMPLETE_VAL [i] = new SC_IN (Tcontrol_t) (rename.c_str()); 110 111 rename = "out_BRANCH_COMPLETE_ACK_" +toString(i); 112 out_BRANCH_COMPLETE_ACK [i] = new SC_OUT(Tcontrol_t) (rename.c_str()); 113 114 rename = "in_BRANCH_COMPLETE_ADDRESS_" +toString(i); 115 in_BRANCH_COMPLETE_ADDRESS [i] = new SC_IN (Taddress_t) (rename.c_str()); 116 91 in_BRANCH_COMPLETE_VAL [i] = new interface->set_signal_valack_in ("val" , VAL); 92 out_BRANCH_COMPLETE_ACK [i] = new interface->set_signal_valack_out ("ack" , ACK); 93 in_BRANCH_COMPLETE_ADDRESS [i] = new interface->set_signal_in <Taddress_t > ("address" , _param._size_address); 117 94 if (_param._have_bht) 118 { 119 rename = "in_BRANCH_COMPLETE_BHT_HISTORY_"+toString(i); 120 in_BRANCH_COMPLETE_BHT_HISTORY [i] = new SC_IN (Tbht_history_t) (rename.c_str()); 121 } 95 in_BRANCH_COMPLETE_BHT_HISTORY [i] = new interface->set_signal_in <Tbht_history_t> ("bht_history", _param._bht_size_shifter); 122 96 if (_param._have_pht) 123 { 124 rename = "in_BRANCH_COMPLETE_PHT_HISTORY_"+toString(i); 125 in_BRANCH_COMPLETE_PHT_HISTORY [i] = new SC_IN (Tpht_history_t) (rename.c_str()); 126 } 127 rename = "in_BRANCH_COMPLETE_DIRECTION_" +toString(i); 128 in_BRANCH_COMPLETE_DIRECTION [i] = new SC_IN (Tcontrol_t) (rename.c_str()); 129 if (_param._have_bht) 130 { 131 rename = "signal_BRANCH_COMPLETE_BHT_ACK_" +toString(i); 132 signal_BRANCH_COMPLETE_BHT_ACK [i] = new SC_SIGNAL(Tcontrol_t) (rename.c_str()); 133 134 rename = "signal_BRANCH_COMPLETE_BHT_ADDRESS_"+toString(i); 135 signal_BRANCH_COMPLETE_BHT_ADDRESS [i] = new SC_SIGNAL(Taddress_t) (rename.c_str()); 136 } 137 if (_param._have_pht) 138 { 139 rename = "signal_BRANCH_COMPLETE_PHT_ACK_" +toString(i); 140 signal_BRANCH_COMPLETE_PHT_ACK [i] = new SC_SIGNAL(Tcontrol_t) (rename.c_str()); 141 142 rename = "signal_BRANCH_COMPLETE_PHT_ADDRESS_"+toString(i); 143 signal_BRANCH_COMPLETE_PHT_ADDRESS [i] = new SC_SIGNAL(Taddress_t) (rename.c_str()); 144 } 97 in_BRANCH_COMPLETE_PHT_HISTORY [i] = new interface->set_signal_in <Tpht_history_t> ("pht_history", _param._pht_size_counter); 98 in_BRANCH_COMPLETE_DIRECTION [i] = new interface->set_signal_in <Tcontrol_t > ("direction" , 1); 145 99 } 146 100 … … 152 106 { 153 107 name_component = _name+"_Branch_History_Table"; 154 155 log_printf(INFO,Two_Level_Branch_Predictor,"allocation","Allocation : %s",name_component.c_str()); 156 157 component_Branch_History_Table = new morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::branch_history_table ::Branch_History_Table (name_component.c_str() , 108 109 component_Branch_History_Table = new morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::branch_history_table ::Branch_History_Table (name_component.c_str() 158 110 #ifdef STATISTICS 159 _param_statistics , 160 #endif 161 *(_param._param_branch_history_table)); 162 163 // Instantiation 164 (*(component_Branch_History_Table->in_CLOCK )) (*(in_CLOCK )); 165 (*(component_Branch_History_Table->in_NRESET)) (*(in_NRESET)); 166 167 for (uint32_t i=0; i<_param._nb_prediction; i++) 168 { 169 (*(component_Branch_History_Table-> in_PREDICT_VAL [i])) (*( in_PREDICT_VAL [i])); 170 (*(component_Branch_History_Table->out_PREDICT_ACK [i])) (*(signal_PREDICT_BHT_ACK [i])); 171 (*(component_Branch_History_Table-> in_PREDICT_ADDRESS [i])) (*(signal_PREDICT_BHT_ADDRESS [i])); 172 (*(component_Branch_History_Table->out_PREDICT_HISTORY [i])) (*( out_PREDICT_BHT_HISTORY [i])); 173 } 174 175 for (uint32_t i=0; i<_param._nb_branch_complete; i++) 176 { 177 (*(component_Branch_History_Table-> in_BRANCH_COMPLETE_VAL [i])) (*( in_BRANCH_COMPLETE_VAL [i])); 178 (*(component_Branch_History_Table->out_BRANCH_COMPLETE_ACK [i])) (*(signal_BRANCH_COMPLETE_BHT_ACK [i])); 179 (*(component_Branch_History_Table-> in_BRANCH_COMPLETE_ADDRESS [i])) (*(signal_BRANCH_COMPLETE_BHT_ADDRESS [i])); 180 (*(component_Branch_History_Table-> in_BRANCH_COMPLETE_HISTORY [i])) (*( in_BRANCH_COMPLETE_BHT_HISTORY [i])); 181 (*(component_Branch_History_Table-> in_BRANCH_COMPLETE_DIRECTION [i])) (*( in_BRANCH_COMPLETE_DIRECTION [i])); 182 } 183 } 184 111 ,_param_statistics 112 #endif 113 ,*(_param._param_counter)); 114 115 _component->set_component (component_Branch_History_Table->_component 116 #ifdef POSITION 117 , 75 118 , 25 119 , 10 120 , 10 121 #endif 122 ); 123 } 124 185 125 // =====[ component_Pattern_History_Table ]=========================== 186 126 if (_param._have_pht) … … 188 128 name_component = _name+"_Pattern_History_Table"; 189 129 190 log_printf(INFO,Two_Level_Branch_Predictor,"allocation","Allocation : %s",name_component.c_str()); 191 192 component_Pattern_History_Table = new morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::pattern_history_table::Pattern_History_Table (name_component.c_str() , 130 component_Pattern_History_Table = new morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::pattern_history_table ::Pattern_History_Table (name_component.c_str() 193 131 #ifdef STATISTICS 194 _param_statistics , 195 #endif 196 *(_param._param_pattern_history_table)); 197 198 // Instantiation 199 (*(component_Pattern_History_Table->in_CLOCK)) (*(in_CLOCK)); 200 (*(component_Pattern_History_Table->in_NRESET)) (*(in_NRESET)); 201 132 ,_param_statistics 133 #endif 134 ,*(_param._param_counter)); 135 136 _component->set_component (component_Pattern_History_Table->_component 137 #ifdef POSITION 138 , 75 139 , 75 140 , 10 141 , 10 142 #endif 143 ); 144 } 145 146 // =====[ component_Two_Level_Branch_Predictor_Glue ]================= 147 148 name_component = _name+"_Two_Level_Branch_Predictor_Glue"; 149 150 component_Two_Level_Branch_Predictor_Glue = new morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::two_level_branch_predictor_glue::Two_Level_Branch_Predictor_Glue (name_component.c_str() 151 #ifdef STATISTICS 152 ,_param_statistics 153 #endif 154 ,*(_param._param_counter)); 155 156 _component->set_component (component_Pattern_History_Table->_component 157 #ifdef POSITION 158 , 50 159 , 75 160 , 10 161 , 10 162 #endif 163 ); 164 165 // ~~~~~[ Component - Instanciation ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 166 167 // =====[ component_Branch_History_Table - Instanciation ]============ 168 if (_param._have_bht) 169 { 170 #ifdef POSITION 171 _component->interface_map (_name+"_Branch_History_Table","", 172 _name ,""); 173 #endif 174 175 _component->port_map(_name+"_Branch_History_Table", "in_CLOCK" , _name,"in_CLOCK" ); 176 _component->port_map(_name+"_Branch_History_Table", "in_NRESET", _name,"in_NRESET"); 177 202 178 for (uint32_t i=0; i<_param._nb_prediction; i++) 203 179 { 204 (*(component_Pattern_History_Table-> in_PREDICT_VAL [i])) (*( in_PREDICT_VAL [i])); 205 (*(component_Pattern_History_Table->out_PREDICT_ACK [i])) (*(signal_PREDICT_PHT_ACK [i])); 206 (*(component_Pattern_History_Table-> in_PREDICT_ADDRESS [i])) (*(signal_PREDICT_PHT_ADDRESS [i])); 207 (*(component_Pattern_History_Table->out_PREDICT_HISTORY [i])) (*( out_PREDICT_PHT_HISTORY [i])); 180 #ifdef POSITION 181 _component->interface_map (_name+"_Branch_History_Table","predict_"+toString(i), 182 _name ,"predict_"+toString(i)); 183 #endif 184 _component->port_map(_name+"_Branch_History_Table", "in_PREDICT_"+toString(i)+"_VAL" , _name , "in_PREDICT_"+toString(i)+"_VAL" ); 185 _component->port_map(_name+"_Branch_History_Table","out_PREDICT_"+toString(i)+"_ACK" , _name+"_Two_Level_Branch_Predictor_Glue", "in_PREDICT_"+toString(i)+"_BHT_ACK" ); 186 _component->port_map(_name+"_Branch_History_Table", "in_PREDICT_"+toString(i)+"_ADDRESS", _name+"_Two_Level_Branch_Predictor_Glue","out_PREDICT_"+toString(i)+"_BHT_ADDRESS"); 187 _component->port_map(_name+"_Branch_History_Table","out_PREDICT_"+toString(i)+"_HISTORY", _name ,"out_PREDICT_"+toString(i)+"_BHT_HISTORY"); 208 188 } 209 189 210 190 for (uint32_t i=0; i<_param._nb_branch_complete; i++) 211 191 { 212 (*(component_Pattern_History_Table-> in_BRANCH_COMPLETE_VAL [i])) (*( in_BRANCH_COMPLETE_VAL [i])); 213 (*(component_Pattern_History_Table->out_BRANCH_COMPLETE_ACK [i])) (*(signal_BRANCH_COMPLETE_PHT_ACK [i])); 214 (*(component_Pattern_History_Table-> in_BRANCH_COMPLETE_ADDRESS [i])) (*(signal_BRANCH_COMPLETE_PHT_ADDRESS [i])); 215 (*(component_Pattern_History_Table-> in_BRANCH_COMPLETE_HISTORY [i])) (*( in_BRANCH_COMPLETE_PHT_HISTORY [i])); 216 (*(component_Pattern_History_Table-> in_BRANCH_COMPLETE_DIRECTION [i])) (*( in_BRANCH_COMPLETE_DIRECTION [i])); 217 } 218 } 219 220 // =====[ component_Two_Level_Branch_Predictor_Glue ]=========================== 221 name_component = _name+"_Two_Level_Branch_Predictor_Glue"; 222 223 log_printf(INFO,Two_Level_Branch_Predictor,"allocation","Allocation : %s",name_component.c_str()); 224 225 component_Two_Level_Branch_Predictor_Glue = new morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::two_level_branch_predictor_glue::Two_Level_Branch_Predictor_Glue (name_component.c_str() , 226 #ifdef STATISTICS 227 _param_statistics , 228 #endif 229 *(_param._param_two_level_branch_predictor_glue)); 230 231 // Instantiation 232 #if defined(STATISTICS) or defined(VHDL_TESTBENCH) 233 (*(component_Two_Level_Branch_Predictor_Glue->in_CLOCK)) (*(in_CLOCK)); 234 #endif 235 for (uint32_t i=0; i<_param._nb_prediction; i++) 236 { 192 #ifdef POSITION 193 _component->interface_map (_name+"_Branch_History_Table","branch_complete_"+toString(i), 194 _name ,"branch_complete_"+toString(i)); 195 #endif 196 _component->port_map(_name+"_Branch_History_Table", "in_BRANCH_COMPLETE_"+toString(i)+"_VAL" , _name , "in_BRANCH_COMPLETE_"+toString(i)+"_VAL" ); 197 _component->port_map(_name+"_Branch_History_Table","out_BRANCH_COMPLETE_"+toString(i)+"_ACK" , _name+"_Two_Level_Branch_Predictor_Glue", "in_BRANCH_COMPLETE_"+toString(i)+"_BHT_ACK" ); 198 _component->port_map(_name+"_Branch_History_Table", "in_BRANCH_COMPLETE_"+toString(i)+"_ADDRESS" , _name+"_Two_Level_Branch_Predictor_Glue","out_BRANCH_COMPLETE_"+toString(i)+"_BHT_ADDRESS" ); 199 _component->port_map(_name+"_Branch_History_Table", "in_BRANCH_COMPLETE_"+toString(i)+"_HISTORY" , _name , "in_BRANCH_COMPLETE_"+toString(i)+"_BHT_HISTORY" ); 200 _component->port_map(_name+"_Branch_History_Table", "in_BRANCH_COMPLETE_"+toString(i)+"_DIRECTION", _name , "in_BRANCH_COMPLETE_"+toString(i)+"_DIRECTION" ); 201 } 202 } 203 204 // =====[ component_Pattern_History_Table - Instanciation ]=========== 205 if (_param._have_pht) 206 { 207 #ifdef POSITION 208 _component->interface_map (_name+"_Pattern_History_Table","", 209 _name ,""); 210 #endif 211 212 _component->port_map(_name+"_Pattern_History_Table", "in_CLOCK" , _name,"in_CLOCK" ); 213 _component->port_map(_name+"_Pattern_History_Table", "in_NRESET", _name,"in_NRESET"); 214 215 for (uint32_t i=0; i<_param._nb_prediction; i++) 216 { 217 #ifdef POSITION 218 _component->interface_map (_name+"_Pattern_History_Table","predict_"+toString(i), 219 _name ,"predict_"+toString(i)); 220 #endif 221 _component->port_map(_name+"_Pattern_History_Table", "in_PREDICT_"+toString(i)+"_VAL" , _name , "in_PREDICT_"+toString(i)+"_VAL" ); 222 _component->port_map(_name+"_Pattern_History_Table","out_PREDICT_"+toString(i)+"_ACK" , _name+"_Two_Level_Branch_Predictor_Glue", "in_PREDICT_"+toString(i)+"_PHT_ACK" ); 223 _component->port_map(_name+"_Pattern_History_Table", "in_PREDICT_"+toString(i)+"_ADDRESS", _name+"_Two_Level_Branch_Predictor_Glue","out_PREDICT_"+toString(i)+"_PHT_ADDRESS"); 224 _component->port_map(_name+"_Pattern_History_Table","out_PREDICT_"+toString(i)+"_HISTORY", _name ,"out_PREDICT_"+toString(i)+"_PHT_HISTORY"); 225 } 226 227 for (uint32_t i=0; i<_param._nb_branch_complete; i++) 228 { 229 #ifdef POSITION 230 _component->interface_map (_name+"_Pattern_History_Table","branch_complete_"+toString(i), 231 _name ,"branch_complete_"+toString(i)); 232 #endif 233 _component->port_map(_name+"_Pattern_History_Table", "in_BRANCH_COMPLETE_"+toString(i)+"_VAL" , _name , "in_BRANCH_COMPLETE_"+toString(i)+"_VAL" ); 234 _component->port_map(_name+"_Pattern_History_Table","out_BRANCH_COMPLETE_"+toString(i)+"_ACK" , _name+"_Two_Level_Branch_Predictor_Glue", "in_BRANCH_COMPLETE_"+toString(i)+"_PHT_ACK" ); 235 _component->port_map(_name+"_Pattern_History_Table", "in_BRANCH_COMPLETE_"+toString(i)+"_ADDRESS" , _name+"_Two_Level_Branch_Predictor_Glue","out_BRANCH_COMPLETE_"+toString(i)+"_PHT_ADDRESS" ); 236 _component->port_map(_name+"_Pattern_History_Table", "in_BRANCH_COMPLETE_"+toString(i)+"_HISTORY" , _name , "in_BRANCH_COMPLETE_"+toString(i)+"_PHT_HISTORY" ); 237 _component->port_map(_name+"_Pattern_History_Table", "in_BRANCH_COMPLETE_"+toString(i)+"_DIRECTION", _name , "in_BRANCH_COMPLETE_"+toString(i)+"_DIRECTION" ); 238 } 239 } 240 241 // =====[ component_Two_Level_Branch_Predictor_Glue - Instanciation ]= 242 #ifdef POSITION 243 _component->interface_map (_name+"_Two_Level_Branch_Predictor_Glue","", 244 _name ,""); 245 #endif 246 _component->port_map(_name+"_Two_Level_Branch_Predictor_Glue", "in_CLOCK" , _name,"in_CLOCK" ); 247 _component->port_map(_name+"_Two_Level_Branch_Predictor_Glue", "in_NRESET", _name,"in_NRESET"); 248 249 for (uint32_t i=0; i<_param._nb_prediction; i++) 250 { 237 251 if (_param._have_bht) 238 252 { 239 (*(component_Two_Level_Branch_Predictor_Glue-> in_PREDICT_BHT_ACK [i])) (*(signal_PREDICT_BHT_ACK [i])); 240 (*(component_Two_Level_Branch_Predictor_Glue->out_PREDICT_BHT_ADDRESS [i])) (*(signal_PREDICT_BHT_ADDRESS [i])); 241 } 242 if (_param._have_pht) 243 { 244 (*(component_Two_Level_Branch_Predictor_Glue-> in_PREDICT_PHT_ACK [i])) (*(signal_PREDICT_PHT_ACK [i])); 245 (*(component_Two_Level_Branch_Predictor_Glue->out_PREDICT_PHT_ADDRESS [i])) (*(signal_PREDICT_PHT_ADDRESS [i])); 246 } 247 if (_param._have_bht and _param._have_pht) 248 { 249 (*(component_Two_Level_Branch_Predictor_Glue-> in_PREDICT_BHT_HISTORY [i])) (*( out_PREDICT_BHT_HISTORY [i])); 250 } 251 (*(component_Two_Level_Branch_Predictor_Glue->out_PREDICT_ACK [i])) (*( out_PREDICT_ACK [i])); 252 (*(component_Two_Level_Branch_Predictor_Glue-> in_PREDICT_ADDRESS [i])) (*( in_PREDICT_ADDRESS [i])); 253 } 253 _component->port_map(_name+"_Two_Level_Branch_Predictor_Glue", "in_PREDICT_"+toString(i)+"_BHT_ACK" , _name+"_Branch_History_Table" , "out_PREDICT_"+toString(i)+"_BHT_ACK" ); 254 _component->port_map(_name+"_Two_Level_Branch_Predictor_Glue", "out_PREDICT_"+toString(i)+"_BHT_ADDRESS", _name+"_Branch_History_Table" , "in_PREDICT_"+toString(i)+"_BHT_ADDRESS"); 255 } 256 if (_param._have_pht) 257 { 258 _component->port_map(_name+"_Two_Level_Branch_Predictor_Glue", "in_PREDICT_"+toString(i)+"_PHT_ACK" , _name+"_Pattern_History_Table", "out_PREDICT_"+toString(i)+"_PHT_ACK" ); 259 _component->port_map(_name+"_Two_Level_Branch_Predictor_Glue", "out_PREDICT_"+toString(i)+"_PHT_ADDRESS", _name+"_Pattern_History_Table", "in_PREDICT_"+toString(i)+"_PHT_ADDRESS"); 260 } 261 if (_param._have_bht and _param._have_pht) 262 _component->port_map(_name+"_Two_Level_Branch_Predictor_Glue", "in_PREDICT_"+toString(i)+"_BHT_HISTORY" , _name , "in_PREDICT_"+toString(i)+"_BHT_HISTORY"); 263 _component->port_map(_name+"_Two_Level_Branch_Predictor_Glue","out_PREDICT_"+toString(i)+"_ACK" , _name ,"out_PREDICT_"+toString(i)+"_ACK"); 264 _component->port_map(_name+"_Two_Level_Branch_Predictor_Glue", "in_PREDICT_"+toString(i)+"_ADDRESS" , _name , "in_PREDICT_"+toString(i)+"_ADDRESS"); 265 } 254 266 255 267 for (uint32_t i=0; i<_param._nb_branch_complete; i++) … … 257 269 if (_param._have_bht) 258 270 { 259 (*(component_Two_Level_Branch_Predictor_Glue-> in_BRANCH_COMPLETE_BHT_ACK [i])) (*(signal_BRANCH_COMPLETE_BHT_ACK [i])); 260 (*(component_Two_Level_Branch_Predictor_Glue->out_BRANCH_COMPLETE_BHT_ADDRESS [i])) (*(signal_BRANCH_COMPLETE_BHT_ADDRESS [i])); 261 } 262 if (_param._have_pht) 263 { 264 (*(component_Two_Level_Branch_Predictor_Glue-> in_BRANCH_COMPLETE_PHT_ACK [i])) (*(signal_BRANCH_COMPLETE_PHT_ACK [i])); 265 (*(component_Two_Level_Branch_Predictor_Glue->out_BRANCH_COMPLETE_PHT_ADDRESS [i])) (*(signal_BRANCH_COMPLETE_PHT_ADDRESS [i])); 266 } 267 if (_param._have_bht and _param._have_pht) 268 { 269 (*(component_Two_Level_Branch_Predictor_Glue-> in_BRANCH_COMPLETE_BHT_HISTORY [i])) (*( in_BRANCH_COMPLETE_BHT_HISTORY [i])); 270 } 271 (*(component_Two_Level_Branch_Predictor_Glue->out_BRANCH_COMPLETE_ACK [i])) (*( out_BRANCH_COMPLETE_ACK [i])); 272 (*(component_Two_Level_Branch_Predictor_Glue-> in_BRANCH_COMPLETE_ADDRESS [i])) (*( in_BRANCH_COMPLETE_ADDRESS [i])); 271 _component->port_map(_name+"_Two_Level_Branch_Predictor_Glue", "in_BRANCH_COMPLETE_"+toString(i)+"_BHT_ACK" , _name+"_Branch_History_Table" , "out_BRANCH_COMPLETE_"+toString(i)+"_BHT_ACK" ); 272 _component->port_map(_name+"_Two_Level_Branch_Predictor_Glue", "out_BRANCH_COMPLETE_"+toString(i)+"_BHT_ADDRESS", _name+"_Branch_History_Table" , "in_BRANCH_COMPLETE_"+toString(i)+"_BHT_ADDRESS"); 273 } 274 if (_param._have_pht) 275 { 276 _component->port_map(_name+"_Two_Level_Branch_Predictor_Glue", "in_BRANCH_COMPLETE_"+toString(i)+"_PHT_ACK" , _name+"_Pattern_History_Table", "out_BRANCH_COMPLETE_"+toString(i)+"_PHT_ACK" ); 277 _component->port_map(_name+"_Two_Level_Branch_Predictor_Glue", "out_BRANCH_COMPLETE_"+toString(i)+"_PHT_ADDRESS", _name+"_Pattern_History_Table", "in_BRANCH_COMPLETE_"+toString(i)+"_PHT_ADDRESS"); 278 } 279 if (_param._have_bht and _param._have_pht) 280 _component->port_map(_name+"_Two_Level_Branch_Predictor_Glue", "in_BRANCH_COMPLETE_"+toString(i)+"_BHT_HISTORY" , _name , "in_BRANCH_COMPLETE_"+toString(i)+"_BHT_HISTORY"); 281 _component->port_map(_name+"_Two_Level_Branch_Predictor_Glue","out_BRANCH_COMPLETE_"+toString(i)+"_ACK" , _name ,"out_BRANCH_COMPLETE_"+toString(i)+"_ACK"); 282 _component->port_map(_name+"_Two_Level_Branch_Predictor_Glue", "in_BRANCH_COMPLETE_"+toString(i)+"_ADDRESS" , _name , "in_BRANCH_COMPLETE_"+toString(i)+"_ADDRESS"); 273 283 } 274 284 285 #ifdef POSITION 286 _component->generate_file(); 287 #endif 288 275 289 log_printf(FUNC,Two_Level_Branch_Predictor,"allocation","End"); 276 290 }; 291 292 293 294 295 296 297 298 // void Two_Level_Branch_Predictor::allocation (void) 299 // { 300 // string rename; 301 302 // log_printf(FUNC,Two_Level_Branch_Predictor,"allocation","Begin"); 303 304 // _component = new Component (); 305 306 // Entity * entity = _component->set_entity (_name 307 // #ifdef POSITION 308 // ,"Two_Level_Branch_Predictor" 309 // ,MIXTE 310 // #endif 311 // ); 312 313 // _interfaces = entity->set_interfaces(); 314 315 // // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 316 // { 317 // Interface * interface = _interfaces->set_interface("" 318 // #ifdef POSITION 319 // , IN 320 // , SOUTH 321 // , "Generalist interface" 322 // #endif 323 // ); 324 325 // in_CLOCK = interface->set_signal_clk ("clock" ,1); 326 // in_NRESET = interface->set_signal_in <Tcontrol_t> ("nreset",1,RESET_VHDL_YES); 327 // } 328 329 // // ~~~~~[ Interface : "predict" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 330 331 // in_PREDICT_VAL = new SC_IN (Tcontrol_t) * [_param._nb_prediction ]; 332 // out_PREDICT_ACK = new SC_OUT(Tcontrol_t) * [_param._nb_prediction ]; 333 // in_PREDICT_ADDRESS = new SC_IN (Taddress_t) * [_param._nb_prediction ]; 334 // if (_param._have_bht) 335 // out_PREDICT_BHT_HISTORY = new SC_OUT(Tbht_history_t) * [_param._nb_prediction ]; 336 // if (_param._have_pht) 337 // out_PREDICT_PHT_HISTORY = new SC_OUT(Tpht_history_t) * [_param._nb_prediction ]; 338 // // if (_param._have_bht) 339 // // { 340 // // signal_PREDICT_BHT_ACK = new SC_SIGNAL(Tcontrol_t) * [_param._nb_prediction]; 341 // // signal_PREDICT_BHT_ADDRESS = new SC_SIGNAL(Taddress_t) * [_param._nb_prediction]; 342 // // } 343 // // if (_param._have_pht) 344 // // { 345 // // signal_PREDICT_PHT_ACK = new SC_SIGNAL(Tcontrol_t) * [_param._nb_prediction]; 346 // // signal_PREDICT_PHT_ADDRESS = new SC_SIGNAL(Taddress_t) * [_param._nb_prediction]; 347 // // } 348 349 // for (uint32_t i=0; i<_param._nb_prediction; i++) 350 // { 351 // rename = "in_PREDICT_VAL_" +toString(i); 352 // in_PREDICT_VAL [i] = new SC_IN (Tcontrol_t) (rename.c_str()); 353 354 // rename = "out_PREDICT_ACK_" +toString(i); 355 // out_PREDICT_ACK [i] = new SC_OUT(Tcontrol_t) (rename.c_str()); 356 357 // rename = "in_PREDICT_ADDRESS_" +toString(i); 358 // in_PREDICT_ADDRESS [i] = new SC_IN (Taddress_t) (rename.c_str()); 359 360 // if (_param._have_bht) 361 // { 362 // rename = "out_PREDICT_BHT_HISTORY_"+toString(i); 363 // out_PREDICT_BHT_HISTORY [i] = new SC_OUT(Tbht_history_t) (rename.c_str()); 364 // } 365 366 // if (_param._have_pht) 367 // { 368 // rename = "out_PREDICT_PHT_HISTORY_"+toString(i); 369 // out_PREDICT_PHT_HISTORY [i] = new SC_OUT(Tpht_history_t) (rename.c_str()); 370 // } 371 372 // // if (_param._have_bht) 373 // // { 374 // // rename = "signal_PREDICT_BHT_ACK_" +toString(i); 375 // // signal_PREDICT_BHT_ACK [i] = new SC_SIGNAL(Tcontrol_t) (rename.c_str()); 376 377 // // rename = "signal_PREDICT_BHT_ADDRESS_"+toString(i); 378 // // signal_PREDICT_BHT_ADDRESS [i] = new SC_SIGNAL(Taddress_t) (rename.c_str()); 379 // // } 380 381 // // if (_param._have_pht) 382 // // { 383 // // rename = "signal_PREDICT_PHT_ACK_" +toString(i); 384 // // signal_PREDICT_PHT_ACK [i] = new SC_SIGNAL(Tcontrol_t) (rename.c_str()); 385 386 // // rename = "signal_PREDICT_PHT_ADDRESS_"+toString(i); 387 // // signal_PREDICT_PHT_ADDRESS [i] = new SC_SIGNAL(Taddress_t) (rename.c_str()); 388 // // } 389 // } 390 391 // in_BRANCH_COMPLETE_VAL = new SC_IN (Tcontrol_t) * [_param._nb_branch_complete]; 392 // out_BRANCH_COMPLETE_ACK = new SC_OUT(Tcontrol_t) * [_param._nb_branch_complete]; 393 // in_BRANCH_COMPLETE_ADDRESS = new SC_IN (Taddress_t) * [_param._nb_branch_complete]; 394 // if (_param._have_bht) 395 // in_BRANCH_COMPLETE_BHT_HISTORY = new SC_IN (Tbht_history_t) * [_param._nb_branch_complete]; 396 // if (_param._have_pht) 397 // in_BRANCH_COMPLETE_PHT_HISTORY = new SC_IN (Tpht_history_t) * [_param._nb_branch_complete]; 398 // in_BRANCH_COMPLETE_DIRECTION = new SC_IN (Tcontrol_t) * [_param._nb_branch_complete]; 399 // // if (_param._have_bht) 400 // // { 401 // // signal_BRANCH_COMPLETE_BHT_ACK = new SC_SIGNAL(Tcontrol_t) * [_param._nb_branch_complete]; 402 // // signal_BRANCH_COMPLETE_BHT_ADDRESS = new SC_SIGNAL(Taddress_t) * [_param._nb_branch_complete]; 403 // // } 404 // // if (_param._have_pht) 405 // // { 406 // // signal_BRANCH_COMPLETE_PHT_ACK = new SC_SIGNAL(Tcontrol_t) * [_param._nb_branch_complete]; 407 // // signal_BRANCH_COMPLETE_PHT_ADDRESS = new SC_SIGNAL(Taddress_t) * [_param._nb_branch_complete]; 408 // // } 409 410 // for (uint32_t i=0; i<_param._nb_branch_complete; i++) 411 // { 412 // rename = "in_BRANCH_COMPLETE_VAL_" +toString(i); 413 // in_BRANCH_COMPLETE_VAL [i] = new SC_IN (Tcontrol_t) (rename.c_str()); 414 415 // rename = "out_BRANCH_COMPLETE_ACK_" +toString(i); 416 // out_BRANCH_COMPLETE_ACK [i] = new SC_OUT(Tcontrol_t) (rename.c_str()); 417 418 // rename = "in_BRANCH_COMPLETE_ADDRESS_" +toString(i); 419 // in_BRANCH_COMPLETE_ADDRESS [i] = new SC_IN (Taddress_t) (rename.c_str()); 420 421 // if (_param._have_bht) 422 // { 423 // rename = "in_BRANCH_COMPLETE_BHT_HISTORY_"+toString(i); 424 // in_BRANCH_COMPLETE_BHT_HISTORY [i] = new SC_IN (Tbht_history_t) (rename.c_str()); 425 // } 426 // if (_param._have_pht) 427 // { 428 // rename = "in_BRANCH_COMPLETE_PHT_HISTORY_"+toString(i); 429 // in_BRANCH_COMPLETE_PHT_HISTORY [i] = new SC_IN (Tpht_history_t) (rename.c_str()); 430 // } 431 // rename = "in_BRANCH_COMPLETE_DIRECTION_" +toString(i); 432 // in_BRANCH_COMPLETE_DIRECTION [i] = new SC_IN (Tcontrol_t) (rename.c_str()); 433 // // if (_param._have_bht) 434 // // { 435 // // rename = "signal_BRANCH_COMPLETE_BHT_ACK_" +toString(i); 436 // // signal_BRANCH_COMPLETE_BHT_ACK [i] = new SC_SIGNAL(Tcontrol_t) (rename.c_str()); 437 438 // // rename = "signal_BRANCH_COMPLETE_BHT_ADDRESS_"+toString(i); 439 // // signal_BRANCH_COMPLETE_BHT_ADDRESS [i] = new SC_SIGNAL(Taddress_t) (rename.c_str()); 440 // // } 441 // // if (_param._have_pht) 442 // // { 443 // // rename = "signal_BRANCH_COMPLETE_PHT_ACK_" +toString(i); 444 // // signal_BRANCH_COMPLETE_PHT_ACK [i] = new SC_SIGNAL(Tcontrol_t) (rename.c_str()); 445 446 // // rename = "signal_BRANCH_COMPLETE_PHT_ADDRESS_"+toString(i); 447 // // signal_BRANCH_COMPLETE_PHT_ADDRESS [i] = new SC_SIGNAL(Taddress_t) (rename.c_str()); 448 // // } 449 // } 450 451 // // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 452 // string name_component; 453 454 // // =====[ component_Branch_History_Table ]============================ 455 // if (_param._have_bht) 456 // { 457 // name_component = _name+"_Branch_History_Table"; 458 459 // log_printf(INFO,Two_Level_Branch_Predictor,"allocation","Allocation : %s",name_component.c_str()); 460 461 // component_Branch_History_Table = new morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::branch_history_table ::Branch_History_Table (name_component.c_str() , 462 // #ifdef STATISTICS 463 // _param_statistics , 464 // #endif 465 // *(_param._param_branch_history_table)); 466 467 // // Instantiation 468 // (*(component_Branch_History_Table->in_CLOCK )) (*(in_CLOCK )); 469 // (*(component_Branch_History_Table->in_NRESET)) (*(in_NRESET)); 470 471 // for (uint32_t i=0; i<_param._nb_prediction; i++) 472 // { 473 // (*(component_Branch_History_Table-> in_PREDICT_VAL [i])) (*( in_PREDICT_VAL [i])); 474 // (*(component_Branch_History_Table->out_PREDICT_ACK [i])) (*(signal_PREDICT_BHT_ACK [i])); 475 // (*(component_Branch_History_Table-> in_PREDICT_ADDRESS [i])) (*(signal_PREDICT_BHT_ADDRESS [i])); 476 // (*(component_Branch_History_Table->out_PREDICT_HISTORY [i])) (*( out_PREDICT_BHT_HISTORY [i])); 477 // } 478 479 // for (uint32_t i=0; i<_param._nb_branch_complete; i++) 480 // { 481 // (*(component_Branch_History_Table-> in_BRANCH_COMPLETE_VAL [i])) (*( in_BRANCH_COMPLETE_VAL [i])); 482 // (*(component_Branch_History_Table->out_BRANCH_COMPLETE_ACK [i])) (*(signal_BRANCH_COMPLETE_BHT_ACK [i])); 483 // (*(component_Branch_History_Table-> in_BRANCH_COMPLETE_ADDRESS [i])) (*(signal_BRANCH_COMPLETE_BHT_ADDRESS [i])); 484 // (*(component_Branch_History_Table-> in_BRANCH_COMPLETE_HISTORY [i])) (*( in_BRANCH_COMPLETE_BHT_HISTORY [i])); 485 // (*(component_Branch_History_Table-> in_BRANCH_COMPLETE_DIRECTION [i])) (*( in_BRANCH_COMPLETE_DIRECTION [i])); 486 // } 487 // } 488 489 // // =====[ component_Pattern_History_Table ]=========================== 490 // if (_param._have_pht) 491 // { 492 // name_component = _name+"_Pattern_History_Table"; 493 494 // log_printf(INFO,Two_Level_Branch_Predictor,"allocation","Allocation : %s",name_component.c_str()); 495 496 // component_Pattern_History_Table = new morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::pattern_history_table::Pattern_History_Table (name_component.c_str() , 497 // #ifdef STATISTICS 498 // _param_statistics , 499 // #endif 500 // *(_param._param_pattern_history_table)); 501 502 // // Instantiation 503 // (*(component_Pattern_History_Table->in_CLOCK)) (*(in_CLOCK)); 504 // (*(component_Pattern_History_Table->in_NRESET)) (*(in_NRESET)); 505 506 // for (uint32_t i=0; i<_param._nb_prediction; i++) 507 // { 508 // (*(component_Pattern_History_Table-> in_PREDICT_VAL [i])) (*( in_PREDICT_VAL [i])); 509 // (*(component_Pattern_History_Table->out_PREDICT_ACK [i])) (*(signal_PREDICT_PHT_ACK [i])); 510 // (*(component_Pattern_History_Table-> in_PREDICT_ADDRESS [i])) (*(signal_PREDICT_PHT_ADDRESS [i])); 511 // (*(component_Pattern_History_Table->out_PREDICT_HISTORY [i])) (*( out_PREDICT_PHT_HISTORY [i])); 512 // } 513 514 // for (uint32_t i=0; i<_param._nb_branch_complete; i++) 515 // { 516 // (*(component_Pattern_History_Table-> in_BRANCH_COMPLETE_VAL [i])) (*( in_BRANCH_COMPLETE_VAL [i])); 517 // (*(component_Pattern_History_Table->out_BRANCH_COMPLETE_ACK [i])) (*(signal_BRANCH_COMPLETE_PHT_ACK [i])); 518 // (*(component_Pattern_History_Table-> in_BRANCH_COMPLETE_ADDRESS [i])) (*(signal_BRANCH_COMPLETE_PHT_ADDRESS [i])); 519 // (*(component_Pattern_History_Table-> in_BRANCH_COMPLETE_HISTORY [i])) (*( in_BRANCH_COMPLETE_PHT_HISTORY [i])); 520 // (*(component_Pattern_History_Table-> in_BRANCH_COMPLETE_DIRECTION [i])) (*( in_BRANCH_COMPLETE_DIRECTION [i])); 521 // } 522 // } 523 524 // // =====[ component_Two_Level_Branch_Predictor_Glue ]=========================== 525 // name_component = _name+"_Two_Level_Branch_Predictor_Glue"; 526 527 // log_printf(INFO,Two_Level_Branch_Predictor,"allocation","Allocation : %s",name_component.c_str()); 528 529 // component_Two_Level_Branch_Predictor_Glue = new morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::two_level_branch_predictor_glue::Two_Level_Branch_Predictor_Glue (name_component.c_str() , 530 // #ifdef STATISTICS 531 // _param_statistics , 532 // #endif 533 // *(_param._param_two_level_branch_predictor_glue)); 534 535 // // Instantiation 536 // #if defined(STATISTICS) or defined(VHDL_TESTBENCH) 537 // (*(component_Two_Level_Branch_Predictor_Glue->in_CLOCK)) (*(in_CLOCK)); 538 // #endif 539 // for (uint32_t i=0; i<_param._nb_prediction; i++) 540 // { 541 // if (_param._have_bht) 542 // { 543 // (*(component_Two_Level_Branch_Predictor_Glue-> in_PREDICT_BHT_ACK [i])) (*(signal_PREDICT_BHT_ACK [i])); 544 // (*(component_Two_Level_Branch_Predictor_Glue->out_PREDICT_BHT_ADDRESS [i])) (*(signal_PREDICT_BHT_ADDRESS [i])); 545 // } 546 // if (_param._have_pht) 547 // { 548 // (*(component_Two_Level_Branch_Predictor_Glue-> in_PREDICT_PHT_ACK [i])) (*(signal_PREDICT_PHT_ACK [i])); 549 // (*(component_Two_Level_Branch_Predictor_Glue->out_PREDICT_PHT_ADDRESS [i])) (*(signal_PREDICT_PHT_ADDRESS [i])); 550 // } 551 // if (_param._have_bht and _param._have_pht) 552 // { 553 // (*(component_Two_Level_Branch_Predictor_Glue-> in_PREDICT_BHT_HISTORY [i])) (*( out_PREDICT_BHT_HISTORY [i])); 554 // } 555 // (*(component_Two_Level_Branch_Predictor_Glue->out_PREDICT_ACK [i])) (*( out_PREDICT_ACK [i])); 556 // (*(component_Two_Level_Branch_Predictor_Glue-> in_PREDICT_ADDRESS [i])) (*( in_PREDICT_ADDRESS [i])); 557 // } 558 559 // for (uint32_t i=0; i<_param._nb_branch_complete; i++) 560 // { 561 // if (_param._have_bht) 562 // { 563 // (*(component_Two_Level_Branch_Predictor_Glue-> in_BRANCH_COMPLETE_BHT_ACK [i])) (*(signal_BRANCH_COMPLETE_BHT_ACK [i])); 564 // (*(component_Two_Level_Branch_Predictor_Glue->out_BRANCH_COMPLETE_BHT_ADDRESS [i])) (*(signal_BRANCH_COMPLETE_BHT_ADDRESS [i])); 565 // } 566 // if (_param._have_pht) 567 // { 568 // (*(component_Two_Level_Branch_Predictor_Glue-> in_BRANCH_COMPLETE_PHT_ACK [i])) (*(signal_BRANCH_COMPLETE_PHT_ACK [i])); 569 // (*(component_Two_Level_Branch_Predictor_Glue->out_BRANCH_COMPLETE_PHT_ADDRESS [i])) (*(signal_BRANCH_COMPLETE_PHT_ADDRESS [i])); 570 // } 571 // if (_param._have_bht and _param._have_pht) 572 // { 573 // (*(component_Two_Level_Branch_Predictor_Glue-> in_BRANCH_COMPLETE_BHT_HISTORY [i])) (*( in_BRANCH_COMPLETE_BHT_HISTORY [i])); 574 // } 575 // (*(component_Two_Level_Branch_Predictor_Glue->out_BRANCH_COMPLETE_ACK [i])) (*( out_BRANCH_COMPLETE_ACK [i])); 576 // (*(component_Two_Level_Branch_Predictor_Glue-> in_BRANCH_COMPLETE_ADDRESS [i])) (*( in_BRANCH_COMPLETE_ADDRESS [i])); 577 // } 578 579 // log_printf(FUNC,Two_Level_Branch_Predictor,"allocation","End"); 580 // }; 277 581 278 582 }; // end namespace two_level_branch_predictor -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_deallocation.cpp
r15 r42 23 23 delete in_NRESET; 24 24 25 for (uint32_t i=0; i<_param._nb_prediction; i++) 26 { 27 delete in_PREDICT_VAL [i]; 28 delete out_PREDICT_ACK [i]; 29 delete in_PREDICT_ADDRESS [i]; 30 if (_param._have_bht) 31 delete out_PREDICT_BHT_HISTORY [i]; 32 if (_param._have_pht) 33 delete out_PREDICT_PHT_HISTORY [i]; 34 if (_param._have_bht) 35 { 36 delete signal_PREDICT_BHT_ACK [i]; 37 delete signal_PREDICT_BHT_ADDRESS [i]; 38 } 39 if (_param._have_pht) 40 { 41 delete signal_PREDICT_PHT_ACK [i]; 42 delete signal_PREDICT_PHT_ADDRESS [i]; 43 } 25 delete [] in_PREDICT_VAL ; 26 delete [] out_PREDICT_ACK ; 27 delete [] in_PREDICT_ADDRESS ; 28 if (_param._have_bht) 29 delete [] out_PREDICT_BHT_HISTORY; 30 if (_param._have_pht) 31 delete [] out_PREDICT_PHT_HISTORY; 44 32 45 } 46 47 delete in_PREDICT_VAL ; 48 delete out_PREDICT_ACK ; 49 delete in_PREDICT_ADDRESS ; 33 delete [] in_BRANCH_COMPLETE_VAL ; 34 delete [] out_BRANCH_COMPLETE_ACK ; 35 delete [] in_BRANCH_COMPLETE_ADDRESS ; 50 36 if (_param._have_bht) 51 delete out_PREDICT_BHT_HISTORY;37 delete [] in_BRANCH_COMPLETE_BHT_HISTORY; 52 38 if (_param._have_pht) 53 delete out_PREDICT_PHT_HISTORY; 54 if (_param._have_bht) 55 { 56 delete signal_PREDICT_BHT_ACK ; 57 delete signal_PREDICT_BHT_ADDRESS; 58 } 59 if (_param._have_pht) 60 { 61 delete signal_PREDICT_PHT_ACK ; 62 delete signal_PREDICT_PHT_ADDRESS; 63 } 64 65 for (uint32_t i=0; i<_param._nb_branch_complete; i++) 66 { 67 delete in_BRANCH_COMPLETE_VAL [i]; 68 delete out_BRANCH_COMPLETE_ACK [i]; 69 delete in_BRANCH_COMPLETE_ADDRESS [i]; 70 if (_param._have_bht) 71 delete in_BRANCH_COMPLETE_BHT_HISTORY [i]; 72 if (_param._have_pht) 73 delete in_BRANCH_COMPLETE_PHT_HISTORY [i]; 74 delete in_BRANCH_COMPLETE_DIRECTION [i]; 75 if (_param._have_bht) 76 { 77 delete signal_BRANCH_COMPLETE_BHT_ACK [i]; 78 delete signal_BRANCH_COMPLETE_BHT_ADDRESS [i]; 79 } 80 if (_param._have_pht) 81 { 82 delete signal_BRANCH_COMPLETE_PHT_ACK [i]; 83 delete signal_BRANCH_COMPLETE_PHT_ADDRESS [i]; 84 } 85 } 86 87 delete in_BRANCH_COMPLETE_VAL ; 88 delete out_BRANCH_COMPLETE_ACK ; 89 delete in_BRANCH_COMPLETE_ADDRESS ; 90 if (_param._have_bht) 91 delete in_BRANCH_COMPLETE_BHT_HISTORY; 92 if (_param._have_pht) 93 delete in_BRANCH_COMPLETE_PHT_HISTORY; 94 delete in_BRANCH_COMPLETE_DIRECTION ; 95 if (_param._have_bht) 96 { 97 delete signal_BRANCH_COMPLETE_BHT_ACK ; 98 delete signal_BRANCH_COMPLETE_BHT_ADDRESS; 99 } 100 if (_param._have_pht) 101 { 102 delete signal_BRANCH_COMPLETE_PHT_ACK ; 103 delete signal_BRANCH_COMPLETE_PHT_ADDRESS; 104 } 39 delete [] in_BRANCH_COMPLETE_PHT_HISTORY; 40 delete [] in_BRANCH_COMPLETE_DIRECTION ; 105 41 106 42 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ … … 111 47 delete component_Pattern_History_Table; 112 48 delete component_Two_Level_Branch_Predictor_Glue; 49 delete _component; 113 50 114 51 log_printf(FUNC,Two_Level_Branch_Predictor,"deallocation","End"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_vhdl.cpp
r3 r42 21 21 { 22 22 log_printf(FUNC,Two_Level_Branch_Predictor,"vhdl","Begin"); 23 Vhdl vhdl (_name);23 Vhdl * vhdl = new Vhdl (_name); 24 24 25 vhdl .set_library_work (_name + "_Pack");25 vhdl->set_library_work (_name + "_Pack"); 26 26 if (_param._have_bht) 27 vhdl .set_library_work (_name + "_Branch_History_Table_Pack");27 vhdl->set_library_work (_name + "_Branch_History_Table_Pack"); 28 28 if (_param._have_pht) 29 vhdl .set_library_work (_name + "_Pattern_History_Table_Pack");30 vhdl .set_library_work (_name + "_Two_Level_Branch_Predictor_Glue_Pack");29 vhdl->set_library_work (_name + "_Pattern_History_Table_Pack"); 30 vhdl->set_library_work (_name + "_Two_Level_Branch_Predictor_Glue_Pack"); 31 31 32 32 vhdl_port (vhdl); … … 34 34 vhdl_body (vhdl); 35 35 36 vhdl.generate_file(); 36 vhdl->generate_file(); 37 38 delete vhdl; 39 37 40 log_printf(FUNC,Two_Level_Branch_Predictor,"vhdl","End"); 38 41 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_vhdl_body.cpp
r15 r42 17 17 18 18 19 void Two_Level_Branch_Predictor::vhdl_body (Vhdl & vhdl)19 void Two_Level_Branch_Predictor::vhdl_body (Vhdl * & vhdl) 20 20 { 21 21 log_printf(FUNC,Two_Level_Branch_Predictor,"vhdl_body","Begin"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_vhdl_declaration.cpp
r3 r42 17 17 18 18 19 void Two_Level_Branch_Predictor::vhdl_declaration (Vhdl & vhdl)19 void Two_Level_Branch_Predictor::vhdl_declaration (Vhdl * & vhdl) 20 20 { 21 21 log_printf(FUNC,Two_Level_Branch_Predictor,"vhdl_declaration","Begin"); … … 25 25 if (_param._have_bht) 26 26 { 27 vhdl .set_signal ("signal_PREDICT_BHT_ACK_"+toString(i), 1);28 vhdl .set_signal ("signal_PREDICT_BHT_ADDRESS_"+toString(i), _param._bht_size_address);29 vhdl .set_signal ("signal_PREDICT_BHT_HISTORY_"+toString(i), _param._bht_size_shifter);27 vhdl->set_signal ("signal_PREDICT_BHT_ACK_"+toString(i), 1); 28 vhdl->set_signal ("signal_PREDICT_BHT_ADDRESS_"+toString(i), _param._bht_size_address); 29 vhdl->set_signal ("signal_PREDICT_BHT_HISTORY_"+toString(i), _param._bht_size_shifter); 30 30 } 31 31 if (_param._have_pht) 32 32 { 33 vhdl .set_signal ("signal_PREDICT_PHT_ACK_"+toString(i), 1);34 vhdl .set_signal ("signal_PREDICT_PHT_ADDRESS_"+toString(i), _param._pht_size_address);33 vhdl->set_signal ("signal_PREDICT_PHT_ACK_"+toString(i), 1); 34 vhdl->set_signal ("signal_PREDICT_PHT_ADDRESS_"+toString(i), _param._pht_size_address); 35 35 } 36 36 } … … 40 40 if (_param._have_bht) 41 41 { 42 vhdl .set_signal ("signal_BRANCH_COMPLETE_BHT_ACK_"+toString(i), 1);43 vhdl .set_signal ("signal_BRANCH_COMPLETE_BHT_ADDRESS_"+toString(i), _param._bht_size_address);42 vhdl->set_signal ("signal_BRANCH_COMPLETE_BHT_ACK_"+toString(i), 1); 43 vhdl->set_signal ("signal_BRANCH_COMPLETE_BHT_ADDRESS_"+toString(i), _param._bht_size_address); 44 44 } 45 45 if (_param._have_pht) 46 46 { 47 vhdl .set_signal ("signal_BRANCH_COMPLETE_PHT_ACK_"+toString(i), 1);48 vhdl .set_signal ("signal_BRANCH_COMPLETE_PHT_ADDRESS_"+toString(i), _param._pht_size_address);47 vhdl->set_signal ("signal_BRANCH_COMPLETE_PHT_ACK_"+toString(i), 1); 48 vhdl->set_signal ("signal_BRANCH_COMPLETE_PHT_ADDRESS_"+toString(i), _param._pht_size_address); 49 49 } 50 50 } -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_vhdl_port.cpp
r15 r42 16 16 namespace two_level_branch_predictor { 17 17 18 void Two_Level_Branch_Predictor::vhdl_port (Vhdl & vhdl)18 void Two_Level_Branch_Predictor::vhdl_port (Vhdl * & vhdl) 19 19 { 20 20 log_printf(FUNC,Two_Level_Branch_Predictor,"vhdl_port","Begin"); 21 21 22 vhdl.set_port (" in_CLOCK ", IN, 1); 23 vhdl.set_port (" in_NRESET", IN, 1); 24 25 for (uint32_t i=0; i<_param._nb_prediction; i++) 26 { 27 vhdl.set_port (" in_PREDICT_VAL_"+toString(i)+" ", IN, 1); 28 vhdl.set_port ("out_PREDICT_ACK_"+toString(i)+" ",OUT, 1); 29 vhdl.set_port (" in_PREDICT_ADDRESS_"+toString(i)+" ", IN,_param._size_address); 30 if (_param._have_bht) 31 vhdl.set_port ("out_PREDICT_BHT_HISTORY_"+toString(i)+" ",OUT,_param._bht_size_shifter); 32 if (_param._have_pht) 33 vhdl.set_port ("out_PREDICT_PHT_HISTORY_"+toString(i)+" ",OUT,_param._pht_size_counter); 34 } 35 36 for (uint32_t i=0; i<_param._nb_branch_complete; i++) 37 { 38 vhdl.set_port (" in_BRANCH_COMPLETE_VAL_"+toString(i)+" ", IN, 1); 39 vhdl.set_port ("out_BRANCH_COMPLETE_ACK_"+toString(i)+" ",OUT, 1); 40 vhdl.set_port (" in_BRANCH_COMPLETE_ADDRESS_"+toString(i)+" ", IN,_param._size_address); 41 if (_param._have_bht) 42 vhdl.set_port (" in_BRANCH_COMPLETE_BHT_HISTORY_"+toString(i)+"", IN,_param._bht_size_shifter); 43 if (_param._have_pht) 44 vhdl.set_port (" in_BRANCH_COMPLETE_PHT_HISTORY_"+toString(i)+"", IN,_param._pht_size_counter); 45 vhdl.set_port (" in_BRANCH_COMPLETE_DIRECTION_"+toString(i)+" ", IN, 1); 46 } 22 _interfaces->set_port(vhdl); 47 23 48 24 log_printf(FUNC,Two_Level_Branch_Predictor,"vhdl_port","End"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_vhdl_testbench_transition.cpp
r15 r42 21 21 log_printf(FUNC,Two_Level_Branch_Predictor,"vhdl_testbench_transition","Begin"); 22 22 23 #ifndef SYSTEMCASS_SPECIFIC 24 sc_cycle(0); 25 #endif 23 sc_start(0); 26 24 27 _vhdl_testbench->add_input (PORT_READ( in_NRESET)); 28 29 // In order with file Two_Level_Branch_Predictor_vhdl_testbench_port.cpp 30 // Warning : if a output depend of a subcomponent, take directly the port of subcomponent 31 // (because we have no control on the ordonnancer's policy) 32 33 for (uint32_t i=0; i<_param._nb_prediction; i++) 34 { 35 _vhdl_testbench->add_input (PORT_READ( in_PREDICT_VAL [i])); 36 _vhdl_testbench->add_output(PORT_READ(component_Two_Level_Branch_Predictor_Glue-> 37 out_PREDICT_ACK [i])); 38 _vhdl_testbench->add_input (PORT_READ( in_PREDICT_ADDRESS [i])); 39 if (_param._have_bht) 40 _vhdl_testbench->add_output(PORT_READ(component_Branch_History_Table -> 41 component_RegisterFile -> 42 out_READ_DATA [i])); 43 if (_param._have_pht) 44 _vhdl_testbench->add_output(PORT_READ(component_Pattern_History_Table -> 45 component_RegisterFile -> 46 out_READ_DATA [i])); 47 } 48 49 for (uint32_t i=0; i<_param._nb_branch_complete; i++) 50 { 51 _vhdl_testbench->add_input (PORT_READ( in_BRANCH_COMPLETE_VAL [i])); 52 _vhdl_testbench->add_output(PORT_READ(component_Two_Level_Branch_Predictor_Glue-> 53 out_BRANCH_COMPLETE_ACK [i])); 54 _vhdl_testbench->add_input (PORT_READ( in_BRANCH_COMPLETE_ADDRESS [i])); 55 if (_param._have_bht) 56 _vhdl_testbench->add_input (PORT_READ( in_BRANCH_COMPLETE_BHT_HISTORY [i])); 57 if (_param._have_pht) 58 _vhdl_testbench->add_input (PORT_READ( in_BRANCH_COMPLETE_PHT_HISTORY [i])); 59 _vhdl_testbench->add_input (PORT_READ( in_BRANCH_COMPLETE_DIRECTION [i])); 60 } 61 62 // add_test : 63 // - True : the cycle must be compare with the output of systemC 64 // - False : no test 65 _vhdl_testbench->add_test(true); 66 67 _vhdl_testbench->new_cycle (); // always at the end 25 _interfaces->testbench(); 68 26 69 27 log_printf(FUNC,Two_Level_Branch_Predictor,"vhdl_testbench_transition","End"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Component.h
r38 r42 1 #ifdef POSITION 2 #ifndef morpheo_behavioural_Position_h 3 #define morpheo_behavioural_Position_h 1 #ifndef morpheo_behavioural_Component_h 2 #define morpheo_behavioural_Component_h 4 3 5 4 /* … … 13 12 #include <iostream> 14 13 #include <list> 14 #include <map> 15 #ifdef VHDL 16 #include "Behavioural/include/Vhdl.h" 17 #endif 18 //#include "Behavioural/include/Description.h" 15 19 #include "Behavioural/include/Entity.h" 16 20 #include "Include/ToString.h" … … 22 26 namespace behavioural { 23 27 24 class Position28 class Component 25 29 { 26 30 // -----[ fields ]---------------------------------------------------- … … 29 33 30 34 // -----[ methods ]--------------------------------------------------- 31 public : Position(void);32 public : Position (const Position & position);33 public : ~ Position();35 public : Component (void); 36 public : Component (const Component & component); 37 public : ~Component (); 34 38 35 public : Entity * set_entity (string name , 36 string type , 37 schema_t schema ); 39 public : Entity * set_entity (string name 40 ,string type 41 #ifdef POSITION 42 ,schema_t schema 43 #endif 44 ); 38 45 private : string get_entity (void); 39 46 40 public : void set_component (Position * position, 41 uint32_t pos_x , 42 uint32_t pos_y , 43 uint32_t size_x , 44 uint32_t size_y ); 47 public : void set_component (Component * component 48 #ifdef POSITION 49 ,uint32_t pos_x 50 ,uint32_t pos_y 51 ,uint32_t size_x 52 ,uint32_t size_y 53 #endif 54 ); 45 55 46 56 private : string get_component (void); 47 48 public : void port_map (string component1,49 string signal1 ,50 string component2,51 string signal2 );52 53 public : XML toXML (void);54 57 55 58 private : Entity * find_entity (string name); … … 57 60 Entity * entity); 58 61 62 #ifdef VHDL 63 public : void vhdl_instance (Vhdl * & vhdl); 64 #endif 65 66 public : void port_map (string component_src , 67 string port_src , 68 string component_dest, 69 string port_dest ); 70 71 #ifdef POSITION 72 public : void interface_map (string component_src , 73 string port_dest, 74 string component_dest, 75 string port_dest ); 76 77 public : XML toXML (void); 78 59 79 public : void generate_file (void); 60 80 #endif 61 81 public : friend ostream& operator<< (ostream& output_stream, 62 morpheo::behavioural:: Position& x);82 morpheo::behavioural::Component & x); 63 83 }; 64 84 … … 67 87 68 88 #endif 69 #endif -
trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Direction.h
r41 r42 7 7 namespace behavioural { 8 8 9 typedef enum { IN, OUT } direction_t;10 9 typedef enum {INTERNAL, IN, OUT } direction_t; 10 //typedef enum { IN, OUT, INOUT } direction_t; 11 11 12 12 }; // end namespace behavioural … … 16 16 switch (x) 17 17 { 18 case morpheo::behavioural::IN : return "in" ; break; 19 case morpheo::behavioural::OUT : return "out" ; break; 20 // case morpheo::behavioural::INOUT : return "inout" ; break; 18 case morpheo::behavioural::INTERNAL : return "internal" ; break; 19 case morpheo::behavioural::IN : return "in" ; break; 20 case morpheo::behavioural::OUT : return "out" ; break; 21 // case morpheo::behavioural::INOUT : return "inout" ; break; 21 22 default : return "" ; break; 22 23 } -
trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Entity.h
r38 r42 1 #ifdef POSITION2 1 #ifndef morpheo_behavioural_Entity_h 3 2 #define morpheo_behavioural_Entity_h … … 13 12 #include <iostream> 14 13 #include <list> 14 //#include "Behavioural/include/Description.h" 15 15 #include "Behavioural/include/Interfaces.h" 16 16 #include "Behavioural/include/Schema.h" … … 26 26 class Entity 27 27 { 28 friend class Position;29 friend class Interface;30 31 28 // -----[ fields ]---------------------------------------------------- 32 29 private : const string _name ; 33 30 private : const string _type ; 31 #ifdef POSITION 34 32 private : const schema_t _schema ; 33 #endif 35 34 private : Interfaces * _interfaces ; 35 36 #ifdef POSITION 36 37 private : string _comment ; 37 38 … … 41 42 private : uint32_t _map_pos_x ; 42 43 private : uint32_t _map_pos_y ; 44 #endif 43 45 44 46 // -----[ methods ]--------------------------------------------------- 45 public : Entity (string name , 46 string type , 47 schema_t schema ); 47 public : Entity ( string name 48 ,string type 49 #ifdef POSITION 50 ,schema_t schema 51 #endif 52 ); 48 53 public : Entity (const Entity & entity); 49 54 public : ~Entity (); 50 55 56 public : string get_name (void); 57 public : string get_type (void); 58 59 #ifdef POSITION 51 60 public : void set_comment (string comment); 52 61 private : string get_comment (void ); 53 62 #endif 54 63 public : Interfaces * set_interfaces (void); 55 64 private : string get_interfaces (void); 65 public : Interfaces * get_interfaces_list(void); 56 66 57 67 public : Interface * find_interface (string name); 68 public : Signal * find_signal (string name); 69 public : bool find_signal (Signal * signal); 58 70 71 #ifdef POSITION 59 72 public : void mapping (uint32_t pos_x, 60 73 uint32_t pos_y, 61 74 uint32_t size_x , 62 75 uint32_t size_y ); 76 #endif 63 77 78 #ifdef POSITION 64 79 public : XML toXML (void); 65 80 public : XML toXML_mapping (void); 66 81 #endif 67 82 public : friend ostream& operator<< (ostream& output_stream, 68 83 morpheo::behavioural::Entity & x); … … 73 88 74 89 #endif 75 #endif -
trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Environnement.h
r40 r42 10 10 # error "To have the vhdl's test bench, you must set flags VHDL" 11 11 #endif 12 13 #if (defined(VHDL_TESTBENCH_ASSERT) and not defined(VHDL_TESTBENCH)) 14 # error "To have an assert in vhdl's test bench, you must set flags VHDL_TESTBENCH" 15 #endif 16 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Interface.h
r41 r42 33 33 class Interface 34 34 { 35 friend class Interfaces;36 37 35 // -----[ fields ]---------------------------------------------------- 38 36 protected : const string _name ; 37 #ifdef POSITION 39 38 protected : const direction_t _direction ; 40 39 protected : const localisation_t _localisation ; 41 40 protected : string _comment ; 41 #endif 42 42 43 43 protected : list<Signal *> * _list_signal ; … … 54 54 55 55 // -----[ methods ]--------------------------------------------------- 56 public : Interface (string name , 57 direction_t direction , 58 localisation_t localisation); 56 public : Interface (string name 57 #ifdef POSITION 58 ,direction_t direction 59 ,localisation_t localisation 60 #endif 61 ); 59 62 60 63 public : Interface (const Interface & interface); 61 64 public : ~Interface (); 62 65 66 public : string get_name (); 67 68 #ifdef POSITION 63 69 public : void set_comment (string comment); 64 70 protected : string get_comment (void ); 71 #endif 65 72 66 73 protected : string signal_name (string name_interface, 67 74 string name_signal , 68 75 direction_t direction ); 76 77 public : Signal * find_signal (string name); 78 public : bool find_signal (Signal * signal); 69 79 70 80 protected : string get_signal (void); … … 73 83 uint32_t size , 74 84 presence_port_t presence_port = PORT_VHDL_YES_TESTBENCH_YES); 85 public : list<Signal *> * get_signal_list (void); 75 86 76 87 #ifdef SYSTEMC … … 85 96 throw ErrorMorpheo ("Signal \""+name+"\" is a clock, bad presence_port."); 86 97 87 Signal * sig = set_signal (name, IN , size, presence_port); 88 sc_in_clk * signal = new sc_in_clk (sig->_name.c_str()); 98 Signal * sig = set_signal (name, IN , size, presence_port); 99 sc_in_clk * port = new sc_in_clk (sig->_name.c_str()); 100 101 sig->alloc<bool> (static_cast<void *>(port)); 89 102 90 103 log_printf(FUNC,Behavioural,"set_signal_clk","End"); 91 104 92 return signal;105 return port; 93 106 }; 94 107 … … 104 117 throw ErrorMorpheo ("Signal \""+name+"\" is not a clock, bad presence_port."); 105 118 106 Signal * sig= set_signal (name, IN , size, presence_port);119 Signal * sig = set_signal (name, IN , size, presence_port); 107 120 sc_in <T> * port = new sc_in <T> (sig->_name.c_str()); 108 #ifdef VHDL_TESTBENCH 121 109 122 sig->alloc<T> (static_cast<void *>(port)); 110 #endif111 123 112 124 log_printf(FUNC,Behavioural,"set_signal_in","End"); … … 128 140 Signal * sig = set_signal (name, OUT , size, presence_port); 129 141 sc_out <T> * port = new sc_out <T> (sig->_name.c_str()); 130 #ifdef VHDL_TESTBENCH 142 131 143 sig->alloc<T> (static_cast<void *>(port)); 132 #endif133 144 134 145 log_printf(FUNC,Behavioural,"set_signal_out","End"); … … 136 147 return port; 137 148 }; 149 150 public : template <typename T> 151 sc_signal <T> * set_signal_internal (string name, 152 uint32_t size) 153 { 154 log_printf(FUNC,Behavioural,"set_signal_internal","Begin"); 155 156 Signal * sig = set_signal (name, INTERNAL , size, PORT_VHDL_NO_TESTBENCH_NO); 157 sc_signal <T> * port = new sc_signal <T> (sig->_name.c_str()); 158 159 sig->alloc<T> (static_cast<void *>(port)); 160 161 log_printf(FUNC,Behavioural,"set_signal_internal","End"); 162 163 return port; 164 }; 165 138 166 #endif 139 167 140 168 #ifdef VHDL 141 169 public : void set_port (Vhdl * & vhdl); 142 # ifdef VHDL_TESTBENCH170 # ifdef VHDL_TESTBENCH 143 171 public : void set_signal (Vhdl * & vhdl); 144 172 public : void get_signal (list<string> * & list_signal); 145 # endif173 # endif 146 174 #endif 147 175 #ifdef VHDL_TESTBENCH 148 176 public : uint32_t get_cycle (void); 149 public : string get_clock (void); 177 public : Signal * get_clock (void); 178 public : Signal * get_reset (void); 150 179 151 180 public : void testbench (void); 152 181 public : void testbench_cycle (void); 153 182 public : void testbench_body (Vhdl * & vhdl , 154 string counter_name ); 183 string counter_name , 184 string reset_name ); 155 185 public : string testbench_test (Vhdl * & vhdl , 156 string counter_name); 186 string counter_name, 187 string reset_name); 157 188 public : string testbench_test_ok (Vhdl * & vhdl ); 158 189 protected : string testbench_test_name (Vhdl * & vhdl); 159 190 protected : string testbench_test_ok_name(Vhdl * & vhdl); 160 161 #endif 162 163 #ifdef POSITION 164 public : void port_map(void * entity,191 protected : string testbench_test_transaction_name(Vhdl * & vhdl); 192 #endif 193 194 #ifdef POSITION 195 public : void interface_map (void * entity, 165 196 void * interface); 166 #endif167 168 197 public : XML toXML (void); 169 #ifdef POSITION170 198 public : XML toXML_mapping (void); 171 199 #endif -
trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Interface_fifo.h
r41 r42 24 24 private : bool _test_exhaustive; 25 25 private : list<uint32_t> * _list_cycle ; 26 27 26 #endif 28 27 29 28 // -----[ methods ]--------------------------------------------------- 30 public : Interface_fifo (string name , 31 direction_t direction , 32 localisation_t localisation); 29 public : Interface_fifo (string name 30 #ifdef POSITION 31 ,direction_t direction 32 ,localisation_t localisation 33 #endif 34 ); 33 35 34 36 public : Interface_fifo (const Interface_fifo & interface_fifo); … … 79 81 public : bool testbench_transaction(void); 80 82 public : void testbench_cycle (void); 81 public : string testbench_test (Vhdl * & vhdl , 82 string counter_name); 83 public : string testbench_test (Vhdl * & vhdl , 84 string counter_name, 85 string reset_name ); 86 87 public : string testbench_test_transaction (Vhdl * & vhdl); 83 88 #endif 84 89 }; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Interfaces.h
r41 r42 35 35 public : ~Interfaces (); 36 36 37 public : Interface_fifo * set_interface (string name , 38 direction_t direction , 39 localisation_t localisation); 37 public : Interface_fifo * set_interface (string name 38 #ifdef POSITION 39 ,direction_t direction 40 ,localisation_t localisation 41 #endif 42 ); 43 #ifdef POSITION 40 44 public : Interface_fifo * set_interface (string name , 41 45 direction_t direction , 42 46 localisation_t localisation, 43 47 string comment ); 48 #endif 44 49 private : string get_interface (void); 50 public :list<Interface_fifo*>* get_interface_list (void); 45 51 46 52 #ifdef VHDL … … 53 59 #ifdef VHDL_TESTBENCH 54 60 private : uint32_t get_cycle (void); 55 private : string get_clock (void); 61 private : Signal * get_clock (void); 62 private : Signal * get_reset (void); 56 63 57 64 private : void testbench_generate_file (void); 58 65 public : void testbench (void); 59 66 private : string testbench_body (Vhdl * & vhdl , 60 string counter_name ); 67 string counter_name , 68 string reset_name ); 61 69 #endif 62 70 63 71 public : Interface_fifo * find_interface (string name); 72 public : Signal * find_signal (string name); 73 public : bool find_signal (Signal * signal); 64 74 75 #ifdef POSITION 65 76 public : XML toXML (void); 66 #ifdef POSITION67 77 public : XML toXML_mapping (void); 68 78 #endif -
trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Localisation.h
r31 r42 1 #ifdef POSITION 1 2 #ifndef morpheo_behavioural_Localisation_h 2 3 #define morpheo_behavioural_Localisation_h … … 26 27 27 28 #endif 29 #endif -
trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Signal.h
r41 r42 44 44 PORT_VHDL_NO_TESTBENCH_NO , 45 45 CLOCK_VHDL_YES , 46 CLOCK_VHDL_NO } presence_port_t; 46 CLOCK_VHDL_NO , 47 RESET_VHDL_YES , 48 RESET_VHDL_NO } presence_port_t; 47 49 48 50 class Signal … … 56 58 private : const presence_port_t _presence_port; 57 59 60 private : Signal * _signal ; 61 private : bool _is_allocate ; 62 private : void * _sc_signal ; 63 private : bool _is_map ; 64 private : void * _sc_signal_map; 65 private : type_info_t _type_info ; 66 58 67 #ifdef VHDL_TESTBENCH 59 private : void * _signal ;60 private : type_info_t _type_info ;61 62 68 private : list<string> * _list_value ; 63 69 #endif … … 71 77 public : ~Signal (); 72 78 73 #ifdef VHDL_TESTBENCH 79 public : string get_name (void); 80 public : uint32_t get_size (void); 81 public : Signal * get_signal_link (void); 82 83 public : bool presence_vhdl (void); 84 public : bool presence_testbench (void); 85 86 public : void mapping (Signal * signal); 87 public : void link (Signal * signal); 88 89 #ifdef SYSTEMC 74 90 public :template <typename T> 75 91 T read (void) … … 88 104 switch (_type_info) 89 105 { 90 case BOOL : return (static_cast<sc_in <bool > *>(_s ignal)->read());91 case UINT8_T : return (static_cast<sc_in <uint8_t > *>(_s ignal)->read());92 case UINT16_T : return (static_cast<sc_in <uint16_t> *>(_s ignal)->read());93 case UINT32_T : return (static_cast<sc_in <uint32_t> *>(_s ignal)->read());94 case UINT64_T : return (static_cast<sc_in <uint64_t> *>(_s ignal)->read());106 case BOOL : return (static_cast<sc_in <bool > *>(_sc_signal_map)->read()); 107 case UINT8_T : return (static_cast<sc_in <uint8_t > *>(_sc_signal_map)->read()); 108 case UINT16_T : return (static_cast<sc_in <uint16_t> *>(_sc_signal_map)->read()); 109 case UINT32_T : return (static_cast<sc_in <uint32_t> *>(_sc_signal_map)->read()); 110 case UINT64_T : return (static_cast<sc_in <uint64_t> *>(_sc_signal_map)->read()); 95 111 default : throw (ErrorMorpheo ("Signal \""+_name+"\" : type unknow.")); 96 112 } … … 102 118 switch (_type_info) 103 119 { 104 case BOOL : return (static_cast<sc_out <bool > *>(_s ignal)->read());105 case UINT8_T : return (static_cast<sc_out <uint8_t > *>(_s ignal)->read());106 case UINT16_T : return (static_cast<sc_out <uint16_t> *>(_s ignal)->read());107 case UINT32_T : return (static_cast<sc_out <uint32_t> *>(_s ignal)->read());108 case UINT64_T : return (static_cast<sc_out <uint64_t> *>(_s ignal)->read());120 case BOOL : return (static_cast<sc_out <bool > *>(_sc_signal_map)->read()); 121 case UINT8_T : return (static_cast<sc_out <uint8_t > *>(_sc_signal_map)->read()); 122 case UINT16_T : return (static_cast<sc_out <uint16_t> *>(_sc_signal_map)->read()); 123 case UINT32_T : return (static_cast<sc_out <uint32_t> *>(_sc_signal_map)->read()); 124 case UINT64_T : return (static_cast<sc_out <uint64_t> *>(_sc_signal_map)->read()); 109 125 default : throw (ErrorMorpheo ("Signal \""+_name+"\" : type unknow.")); 110 126 } … … 117 133 throw (ErrorMorpheo ("Signal \""+_name+"\" : already allocate.")); 118 134 119 _signal = port; 135 _is_allocate = true; 136 _sc_signal = port; 137 _sc_signal_map = port; 120 138 121 139 if (typeid(T) == typeid(bool )) … … 136 154 _type_info = UNKNOW; 137 155 } 138 139 public : void testbench (void); 140 public : void testbench_body (Vhdl * & vhdl , 141 string counter_name ); 142 public : void testbench_test_ok(Vhdl * & vhdl ); 143 #endif 156 #endif 157 144 158 #ifdef VHDL 145 159 public : void set_port (Vhdl * & vhdl); 146 160 # ifdef VHDL_TESTBENCH 147 public : string get_clock (void); 161 public : Signal * get_clock (void); 162 public : Signal * get_reset (void); 163 public : uint32_t get_reset_cycle (bool active_low); 164 148 165 public : void set_signal (Vhdl * & vhdl); 149 166 public : void get_name_vhdl (list<string> * & list_signal); 167 168 public : void testbench (void); 169 public : void testbench_body (Vhdl * & vhdl , 170 string counter_name , 171 string reset_name ); 172 public : void testbench_test_ok(Vhdl * & vhdl ); 150 173 # endif 151 174 #endif … … 162 185 switch (x) 163 186 { 164 case morpheo::behavioural::PORT_VHDL_YES_TESTBENCH_YES : return "Port is in VHDL's model and TestBench's model" ; break; 165 case morpheo::behavioural::PORT_VHDL_YES_TESTBENCH_NO : return "Port is in VHDL's model " ; break; 166 case morpheo::behavioural::PORT_VHDL_NO_TESTBENCH_YES : return "Port is in TestBench's model" ; break; 167 case morpheo::behavioural::PORT_VHDL_NO_TESTBENCH_NO : return "Port is in none model " ; break; 187 case morpheo::behavioural::PORT_VHDL_YES_TESTBENCH_YES : return "Port is in VHDL's model and TestBench's model" ; break; 188 case morpheo::behavioural::PORT_VHDL_YES_TESTBENCH_NO : return "Port is in VHDL's model " ; break; 189 case morpheo::behavioural::PORT_VHDL_NO_TESTBENCH_YES : return "Port is in TestBench's model" ; break; 190 case morpheo::behavioural::PORT_VHDL_NO_TESTBENCH_NO : return "Port is in none model " ; break; 191 case morpheo::behavioural::CLOCK_VHDL_YES : return "Clock is in VHDL's model " ; break; 192 case morpheo::behavioural::CLOCK_VHDL_NO : return "Clock is not in VHDL's model " ; break; 193 case morpheo::behavioural::RESET_VHDL_YES : return "Reset is in VHDL's model " ; break; 194 case morpheo::behavioural::RESET_VHDL_NO : return "Reset is not in VHDL's model " ; break; 168 195 default : return ""; break; 169 196 } -
trunk/IPs/systemC/processor/Morpheo/Behavioural/mkf.info
r23 r42 25 25 #target_dep all Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue/SelfTest 26 26 #target_dep all Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/SelfTest 27 #target_dep all Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/SelfTest27 target_dep all Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/SelfTest 28 28 #target_dep all Stage_5_Execute/Execution_cluster/Execution_group/Execution_unit/SelfTest 29 29 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Component.cpp
r38 r42 1 #ifdef POSITION2 1 /* 3 2 * $Id$ … … 7 6 */ 8 7 9 #include "Behavioural/include/ Position.h"8 #include "Behavioural/include/Component.h" 10 9 11 10 namespace morpheo { 12 11 namespace behavioural { 13 12 14 Position::Position(void)13 Component::Component (void) 15 14 { 16 log_printf(FUNC,Behavioural," Position","Begin");15 log_printf(FUNC,Behavioural,"Component","Begin"); 17 16 _list_component = new list<Entity *>; 18 log_printf(FUNC,Behavioural," Position","End");17 log_printf(FUNC,Behavioural,"Component","End"); 19 18 }; 20 19 21 Position::Position (const Position & position)20 Component::Component (const Component & component) 22 21 { 23 log_printf(FUNC,Behavioural," Position(copy)","Begin");24 _entity = position._entity ;25 _list_component = position._list_component;26 log_printf(FUNC,Behavioural," Position(copy)","End");22 log_printf(FUNC,Behavioural,"Component (copy)","Begin"); 23 _entity = component._entity ; 24 _list_component = component._list_component; 25 log_printf(FUNC,Behavioural,"Component (copy)","End"); 27 26 }; 28 27 29 Position::~Position()28 Component::~Component () 30 29 { 31 log_printf(FUNC,Behavioural,"~ Position","Begin");30 log_printf(FUNC,Behavioural,"~Component","Begin"); 32 31 delete _entity; 33 34 // if (_list_component->empty()== false)35 // {36 // list<Entity *>::iterator i = _list_component->begin();37 38 // while (i != _list_component->end())39 // {40 // delete (*i);41 // ++i;42 // }43 // }44 45 32 delete _list_component; 46 log_printf(FUNC,Behavioural,"~ Position","End");33 log_printf(FUNC,Behavioural,"~Component","End"); 47 34 }; 48 35 … … 50 37 }; // end namespace behavioural 51 38 }; // end namespace morpheo 52 #endif -
trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Component_find_entity.cpp
r31 r42 1 #ifdef POSITION2 1 /* 3 2 * $Id$ … … 7 6 */ 8 7 9 #include "Behavioural/include/ Position.h"8 #include "Behavioural/include/Component.h" 10 9 11 10 namespace morpheo { 12 11 namespace behavioural { 13 12 14 Entity * Position::find_entity (string name)13 Entity * Component::find_entity (string name) 15 14 { 16 15 17 if (_entity-> _name== name)16 if (_entity->get_name() == name) 18 17 return _entity; 19 18 else … … 24 23 while (i != _list_component->end()) 25 24 { 26 if ((*i)-> _name== name)25 if ((*i)->get_name() == name) 27 26 { 28 27 return *i; … … 38 37 }; // end namespace behavioural 39 38 }; // end namespace morpheo 40 #endif -
trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Component_generate_file.cpp
r31 r42 7 7 */ 8 8 9 #include "Behavioural/include/ Position.h"9 #include "Behavioural/include/Component.h" 10 10 11 11 namespace morpheo { 12 12 namespace behavioural { 13 13 14 void Position::generate_file (void)14 void Component::generate_file (void) 15 15 { 16 16 try … … 25 25 catch (ErrorMorpheo e) 26 26 { 27 throw (ErrorMorpheo (" Position \""+_entity->_name+"\" have a bad mapping : "+e.what()));27 throw (ErrorMorpheo ("Component \""+_entity->get_name()+"\" have a bad mapping : "+e.what())); 28 28 } 29 29 }; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Component_get_component.cpp
r31 r42 1 #ifdef POSITION2 1 /* 3 2 * $Id$ … … 7 6 */ 8 7 9 #include "Behavioural/include/ Position.h"8 #include "Behavioural/include/Component.h" 10 9 11 10 namespace morpheo { 12 11 namespace behavioural { 13 12 14 string Position::get_component (void)13 string Component::get_component (void) 15 14 { 16 15 uint32_t depth = 0; … … 49 48 }; // end namespace behavioural 50 49 }; // end namespace morpheo 51 #endif -
trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Component_get_entity.cpp
r31 r42 1 #ifdef POSITION2 1 /* 3 2 * $Id$ … … 7 6 */ 8 7 9 #include "Behavioural/include/ Position.h"8 #include "Behavioural/include/Component.h" 10 9 11 10 namespace morpheo { 12 11 namespace behavioural { 13 12 14 string Position::get_entity (void)13 string Component::get_entity (void) 15 14 { 16 15 ostringstream text; … … 21 20 }; // end namespace behavioural 22 21 }; // end namespace morpheo 23 #endif -
trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Component_port_map.cpp
r31 r42 1 #ifdef POSITION2 1 /* 3 2 * $Id$ … … 7 6 */ 8 7 9 #include "Behavioural/include/ Position.h"8 #include "Behavioural/include/Component.h" 10 9 11 10 namespace morpheo { 12 11 namespace behavioural { 13 12 14 void Position::port_map (string component1,15 string signal1,16 string component2,17 string signal2)13 void Component::port_map (string component_src , 14 string port_src , 15 string component_dest, 16 string port_dest ) 18 17 { 19 Entity * entity1 = find_entity(component1);18 string name_entity = _entity->get_name(); 20 19 21 if (entity1 == NULL)22 throw (ErrorMorpheo ("Position \""+_entity->_name+"\", port map with unknow component \""+component1+"\"."));20 // First entity 21 Entity * entity_dest = find_entity(component_dest); 23 22 24 bool is_top_level1 = _entity->_name == component1; 23 if (entity_dest == NULL) 24 throw (ErrorMorpheo ("Component \""+name_entity+"\", port map with unknow component \""+component_dest+"\".")); 25 25 26 Interface * interface1 = find_interface (signal1, entity1);26 Signal * signal_dest = entity_dest->find_signal (port_dest); 27 27 28 if ( interface1== NULL)29 throw (ErrorMorpheo (" Position \""+_entity->_name+"\", port map with component \""+component1+"\" and a unknow port \""+signal1+"\"."));28 if (signal_dest == NULL) 29 throw (ErrorMorpheo ("Component \""+name_entity+"\", port map with component \""+component_dest+"\" and a unknow signal \""+port_dest+"\".")); 30 30 31 Entity * entity2 = find_entity(component2); 31 // Second entity 32 Entity * entity_src = find_entity(component_src); 32 33 33 if (entity 2== NULL)34 throw (ErrorMorpheo (" Position \""+_entity->_name+"\", port map with unknow component \""+component2+"\"."));34 if (entity_src == NULL) 35 throw (ErrorMorpheo ("Component \""+name_entity+"\", port map with unknow component \""+component_src+"\".")); 35 36 36 bool is_top_level2 = _entity->_name == component2;37 Signal * signal_src = entity_src->find_signal (port_src); 37 38 38 Interface * interface2 = find_interface (signal2, entity2); 39 if (signal_src == NULL) 40 throw (ErrorMorpheo ("Component \""+name_entity+"\", port map with component \""+component_src+"\" and a unknow signal \""+port_src+"\".")); 39 41 40 if (interface2 == NULL) 41 throw (ErrorMorpheo ("Position \""+_entity->_name+"\", port map with component \""+component2+"\" and a unknow port \""+signal2+"\".")); 42 43 // all is ok 44 if (is_top_level1 == false) 45 interface1->port_map(static_cast<void *>(entity2 ), 46 static_cast<void *>(interface2)); 47 48 if (is_top_level2 == false) 49 interface2->port_map(static_cast<void *>(entity1 ), 50 static_cast<void *>(interface1)); 51 42 // If all is ok, mapping 43 signal_src ->link (signal_dest); 44 signal_dest->mapping(signal_src ); 52 45 }; 53 46 54 47 }; // end namespace behavioural 55 48 }; // end namespace morpheo 56 #endif -
trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Component_print.cpp
r31 r42 1 #ifdef POSITION2 1 /* 3 2 * $Id$ … … 7 6 */ 8 7 9 #include "Behavioural/include/ Position.h"8 #include "Behavioural/include/Component.h" 10 9 11 10 … … 14 13 15 14 ostream& operator<< (ostream& output_stream, 16 morpheo::behavioural:: Position& x)15 morpheo::behavioural::Component & x) 17 16 { 18 17 output_stream << x.get_entity () << endl; … … 23 22 }; // end namespace behavioural 24 23 }; // end namespace morpheo 25 #endif -
trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Component_set_component.cpp
r38 r42 1 #ifdef POSITION2 1 /* 3 2 * $Id$ … … 7 6 */ 8 7 9 #include "Behavioural/include/ Position.h"8 #include "Behavioural/include/Component.h" 10 9 11 10 namespace morpheo { 12 11 namespace behavioural { 13 12 14 void Position::set_component (Position * position, 15 uint32_t pos_x , 16 uint32_t pos_y , 17 uint32_t size_x , 18 uint32_t size_y ) 13 void Component::set_component (Component * component 14 #ifdef POSITION 15 ,uint32_t pos_x 16 ,uint32_t pos_y 17 ,uint32_t size_x 18 ,uint32_t size_y 19 #endif 20 ) 19 21 { 20 Entity * entity = position->_entity;22 Entity * entity = component->_entity; 21 23 22 24 _list_component->push_back(entity); 23 25 26 #ifdef POSITION 24 27 entity->mapping( pos_x, pos_y, size_x, size_y); 28 #endif 25 29 }; 26 30 27 31 }; // end namespace behavioural 28 32 }; // end namespace morpheo 29 #endif -
trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Component_set_entity.cpp
r31 r42 1 #ifdef POSITION2 1 /* 3 2 * $Id$ … … 7 6 */ 8 7 9 #include "Behavioural/include/ Position.h"8 #include "Behavioural/include/Component.h" 10 9 11 10 namespace morpheo { 12 11 namespace behavioural { 13 12 14 Entity * Position::set_entity (string name , 15 string type , 16 schema_t schema ) 13 Entity * Component::set_entity (string name 14 ,string type 15 #ifdef POSITION 16 ,schema_t schema 17 #endif 18 ) 17 19 { 18 Entity * entity = new Entity (name , 19 type , 20 schema ); 20 Entity * entity = new Entity (name 21 ,type 22 #ifdef POSITION 23 ,schema 24 #endif 25 ); 21 26 _entity = entity; 22 27 … … 26 31 }; // end namespace behavioural 27 32 }; // end namespace morpheo 28 #endif -
trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Component_toXML.cpp
r31 r42 7 7 */ 8 8 9 #include "Behavioural/include/ Position.h"9 #include "Behavioural/include/Component.h" 10 10 11 11 namespace morpheo { 12 12 namespace behavioural { 13 13 14 XML Position::toXML (void)14 XML Component::toXML (void) 15 15 { 16 XML xml (_entity-> _name);16 XML xml (_entity->get_name()); 17 17 18 18 xml.balise_open ("description"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Entity.cpp
r41 r42 1 #ifdef POSITION2 1 /* 3 2 * $Id$ … … 12 11 namespace behavioural { 13 12 14 Entity::Entity (string name , 15 string type , 16 schema_t schema): 17 _name (name ), 18 _type (type ), 19 _schema (schema ) 13 Entity::Entity ( string name 14 ,string type 15 #ifdef POSITION 16 ,schema_t schema 17 #endif 18 ): 19 _name (name ) 20 ,_type (type ) 21 #ifdef POSITION 22 ,_schema (schema ) 23 #endif 20 24 { 21 25 log_printf(FUNC,Behavioural,"Entity","Begin"); 22 26 _interfaces = new Interfaces (name); 27 #ifdef POSITION 23 28 _is_map = false; 29 #endif 24 30 log_printf(FUNC,Behavioural,"Entity","End"); 25 31 }; 26 32 27 33 Entity::Entity (const Entity & entity): 28 _name (entity._name ), 29 _type (entity._type ), 30 _schema (entity._schema ) 34 _name (entity._name ) 35 ,_type (entity._type ) 36 #ifdef POSITION 37 ,_schema (entity._schema ) 38 #endif 31 39 { 32 40 log_printf(FUNC,Behavioural,"Entity (copy)","Begin"); 41 _interfaces = entity._interfaces; 42 #ifdef POSITION 33 43 _is_map = entity._is_map ; 34 _interfaces = entity._interfaces;35 44 _comment = entity._comment ; 45 #endif 36 46 log_printf(FUNC,Behavioural,"Entity (copy)","End"); 37 47 }; … … 43 53 log_printf(FUNC,Behavioural,"~Entity","End"); 44 54 }; 45 46 55 47 56 }; // end namespace behavioural 48 57 }; // end namespace morpheo 49 #endif -
trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Entity_find_interface.cpp
r31 r42 1 #ifdef POSITION2 1 /* 3 2 * $Id$ … … 19 18 }; // end namespace behavioural 20 19 }; // end namespace morpheo 21 #endif -
trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Entity_get_interfaces.cpp
r31 r42 1 #ifdef POSITION2 1 /* 3 2 * $Id$ … … 20 19 }; 21 20 21 Interfaces * Entity::get_interfaces_list (void) 22 { 23 return _interfaces; 24 }; 25 26 22 27 }; // end namespace behavioural 23 28 }; // end namespace morpheo 24 #endif -
trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Entity_print.cpp
r31 r42 1 #ifdef POSITION2 1 /* 3 2 * $Id$ … … 16 15 morpheo::behavioural::Entity & x) 17 16 { 17 #ifdef POSITION 18 18 output_stream << x._name + "\t"+x._type+"\t"+toString(x._schema) << endl; 19 19 output_stream << x.get_comment() << endl; 20 #else 21 output_stream << x._name + "\t"+x._type<< endl; 22 #endif 20 23 output_stream << x.get_interfaces() << endl; 21 24 return output_stream; … … 24 27 }; // end namespace behavioural 25 28 }; // end namespace morpheo 26 #endif -
trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Entity_set_interfaces.cpp
r41 r42 1 #ifdef POSITION2 1 /* 3 2 * $Id$ … … 19 18 }; // end namespace behavioural 20 19 }; // end namespace morpheo 21 #endif -
trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Interface.cpp
r41 r42 11 11 namespace behavioural { 12 12 13 Interface::Interface (string name , 14 direction_t direction , 15 localisation_t localisation ): 16 _name (name ), 17 _direction (direction ), 18 _localisation (localisation) 13 Interface::Interface (string name 14 #ifdef POSITION 15 ,direction_t direction 16 ,localisation_t localisation 17 #endif 18 ): 19 _name (name ) 20 #ifdef POSITION 21 ,_direction (direction ) 22 ,_localisation (localisation) 23 #endif 19 24 { 20 25 log_printf(FUNC,Behavioural,"Interface","Begin"); 21 26 22 _comment = "";23 27 _list_signal = new (list<Signal*>); 24 28 25 29 #ifdef POSITION 30 _comment = ""; 26 31 _is_map = false; 27 32 _entity_map = NULL; … … 37 42 38 43 Interface::Interface (const Interface & interface): 39 _name (interface._name ), 40 _direction (interface._direction ), 41 _localisation (interface._localisation) 44 _name (interface._name ) 45 #ifdef POSITION 46 ,_direction (interface._direction ) 47 ,_localisation (interface._localisation) 48 #endif 42 49 { 43 50 log_printf(FUNC,Behavioural,"Interface (copy)","Begin"); 44 _comment = interface._comment ;45 51 _list_signal = interface._list_signal; 46 52 #ifdef POSITION 53 _comment = interface._comment ; 47 54 _is_map = interface._is_map ; 48 55 _entity_map = interface._entity_map ; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Interface_fifo.cpp
r41 r42 11 11 namespace behavioural { 12 12 13 Interface_fifo::Interface_fifo (string name , 14 direction_t direction , 15 localisation_t localisation): 16 Interface (name , 17 direction , 18 localisation) 13 Interface_fifo::Interface_fifo (string name 14 #ifdef POSITION 15 ,direction_t direction 16 ,localisation_t localisation 17 #endif 18 ): 19 Interface (name 20 #ifdef POSITION 21 ,direction 22 ,localisation 23 #endif 24 ) 19 25 { 20 26 log_printf(FUNC,Behavioural,"Interface_fifo","Begin"); … … 32 38 33 39 Interface_fifo::Interface_fifo (const Interface_fifo & interface_fifo) : 34 Interface (interface_fifo._name , 35 interface_fifo._direction , 36 interface_fifo._localisation) 40 Interface (interface_fifo._name 41 #ifdef POSITION 42 ,interface_fifo._direction 43 ,interface_fifo._localisation 44 #endif 45 ) 37 46 { 38 47 log_printf(FUNC,Behavioural,"Interface_fifo (copy)","Begin"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Interface_fifo_get_cycle.cpp
r41 r42 17 17 if (_test_exhaustive == true) 18 18 return Interface::get_cycle(); 19 20 return _list_cycle->back(); 19 20 if (_list_cycle->empty() == true) 21 return 0; 22 else 23 return _list_cycle->back(); 21 24 }; 22 25 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Interface_fifo_testbench_test.cpp
r41 r42 13 13 14 14 string Interface_fifo::testbench_test (Vhdl * & vhdl, 15 string counter_name) 15 string counter_name, 16 string reset_name ) 16 17 { 17 18 log_printf(FUNC,Behavioural,"testbench_test","Begin"); … … 19 20 20 21 if (_test_exhaustive == true) 21 test_name = Interface::testbench_test(vhdl,counter_name );22 test_name = Interface::testbench_test(vhdl,counter_name,reset_name); 22 23 else 23 24 { … … 26 27 vhdl->set_body(""); 27 28 28 test_name = testbench_test_name (vhdl); 29 string test_name_ok = testbench_test_ok (vhdl); 29 test_name = testbench_test_name (vhdl); 30 string test_name_tmp = test_name+"_tmp"; 31 string test_name_ok = testbench_test_ok (vhdl); 32 string test_transaction = testbench_test_transaction (vhdl); 33 34 vhdl->set_signal(test_name_tmp,1); 30 35 31 36 if (_list_cycle->empty()== false) 32 37 { 33 38 vhdl->set_body ("with "+counter_name+" select"); 34 vhdl->set_body ("\t"+test_name +" <=");39 vhdl->set_body ("\t"+test_name_tmp+" <="); 35 40 36 41 list<uint32_t>::iterator i = _list_cycle->begin(); … … 38 43 while (i != _list_cycle->end()) 39 44 { 40 vhdl->set_body ("\t"+test_ name_ok+" when "+toString(*i)+",");45 vhdl->set_body ("\t"+test_transaction+" and "+test_name_ok+" when "+toString(*i)+","); 41 46 ++i; 42 47 } 43 vhdl->set_body ("\t '1'when others;");48 vhdl->set_body ("\tnot "+test_transaction+" when others;"); 44 49 } 50 else 51 vhdl->set_body (test_name_tmp+" <= not "+test_transaction+";"); 52 53 vhdl->set_body(""); 54 vhdl->set_body(test_name + " <= '1' when ("+reset_name+" = '0') else "+test_name_tmp+";"); 55 56 #ifdef VHDL_TESTBENCH_ASSERT 57 if (_list_cycle->empty()== false) 58 { 59 vhdl->set_body(""); 60 vhdl->set_body("-- Assert ..."); 61 vhdl->set_body(""); 62 63 uint32_t j = 0; 64 list<uint32_t>::iterator i = _list_cycle->begin(); 65 66 while (i != _list_cycle->end()) 67 { 68 vhdl->set_body("assert not ( ("+counter_name+" = "+toString(*i)+")) report \"***** <"+_name+"> interface's test number "+toString(j)+" *****\" severity NOTE;"); 69 j++; 70 ++i; 71 } 72 73 vhdl->set_body(""); 74 } 75 #endif 45 76 } 46 77 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Interface_fifo_testbench_transaction.cpp
r40 r42 1 #ifdef VHDL_TESTBENCH 1 2 /* 2 3 * $Id$ … … 48 49 }; // end namespace behavioural 49 50 }; // end namespace morpheo 51 #endif -
trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Interface_get_clock.cpp
r41 r42 13 13 namespace behavioural { 14 14 15 stringInterface::get_clock (void)15 Signal * Interface::get_clock (void) 16 16 { 17 string clock = "";17 Signal * clock = NULL; 18 18 19 19 if (not _list_signal->empty()) … … 23 23 while (i != _list_signal->end()) 24 24 { 25 string str= (*i)->get_clock ();25 Signal * sig = (*i)->get_clock (); 26 26 27 if (s tr != "")27 if (sig != NULL) 28 28 { 29 if (clock != "")29 if (clock != NULL) 30 30 throw ErrorMorpheo ("<Interface.get_clock> : find too many clock."); 31 clock = s tr;31 clock = sig; 32 32 } 33 33 ++i; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Interface_get_comment.cpp
r38 r42 1 #ifdef POSITION 1 2 /* 2 3 * $Id$ … … 22 23 }; // end namespace behavioural 23 24 }; // end namespace morpheo 25 #endif -
trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Interface_get_signal.cpp
r41 r42 69 69 #endif 70 70 71 list<Signal *> * Interface::get_signal_list (void) 72 { 73 return _list_signal; 74 } 75 71 76 }; // end namespace behavioural 72 77 }; // end namespace morpheo -
trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Interface_port_map.cpp
r38 r42 1 #ifdef POSITION2 1 /* 3 2 * $Id$ … … 13 12 namespace behavioural { 14 13 15 void Interface::port_map (void * entity, 16 void * interface) 17 { 18 log_printf(FUNC,Behavioural,"port_map","Begin"); 19 _is_map = true ; 20 _entity_map = entity ; 21 _interface_map = interface; 22 log_printf(FUNC,Behavioural,"port_map","End"); 23 }; 14 // void Interface::port_map (void * entity, 15 // void * interface) 16 // { 17 // log_printf(FUNC,Behavioural,"port_map","Begin"); 18 // #ifdef POSITION 19 // _is_map = true ; 20 // _entity_map = entity ; 21 // _interface_map = interface; 22 // #endif 23 // log_printf(FUNC,Behavioural,"port_map","End"); 24 // }; 24 25 25 26 }; // end namespace behavioural 26 27 }; // end namespace morpheo 27 #endif -
trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Interface_print.cpp
r41 r42 16 16 { 17 17 log_printf(FUNC,Behavioural,"operator<<","Begin"); 18 #ifdef POSITION 18 19 output_stream << x._name + "\t"+toString(x._localisation)+"\t"+toString(x._direction) << endl; 19 20 output_stream << x.get_comment() << endl; 21 #else 22 output_stream << x._name << endl; 23 #endif 20 24 output_stream << x.get_signal () << endl; 21 25 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Interface_set_comment.cpp
r38 r42 1 #ifdef POSITION 1 2 /* 2 3 * $Id$ … … 21 22 }; // end namespace behavioural 22 23 }; // end namespace morpheo 24 #endif -
trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Interface_set_signal.cpp
r41 r42 20 20 string signame = signal_name(_name, name, direction); 21 21 22 Signal * sig = new Signal (signame , 23 direction , 24 size , 25 presence_port); 22 Signal * sig = new Signal (signame, direction, size, presence_port); 26 23 27 24 _list_signal->push_back (sig); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Interface_testbench_body.cpp
r41 r42 14 14 15 15 void Interface::testbench_body (Vhdl * & vhdl, 16 string counter_name) 16 string counter_name, 17 string reset_name ) 17 18 { 18 19 log_printf(FUNC,Behavioural,"testbench_body","Begin"); … … 28 29 while (i != _list_signal->end()) 29 30 { 30 (*i)->testbench_body(vhdl, counter_name );31 (*i)->testbench_body(vhdl, counter_name, reset_name); 31 32 ++i; 32 33 } -
trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Interface_testbench_test.cpp
r41 r42 14 14 15 15 string Interface::testbench_test (Vhdl * & vhdl, 16 string counter_name) 16 string counter_name, 17 string reset_name ) 17 18 { 18 19 log_printf(FUNC,Behavioural,"testbench_test","Begin"); … … 25 26 string test_name_ok = testbench_test_ok (vhdl); 26 27 27 vhdl->set_body(test_name + " <= "+test_name_ok+";");28 vhdl->set_body(test_name + " <= '1' when ("+reset_name+" = '0') else "+test_name_ok+";"); 28 29 29 30 log_printf(FUNC,Behavioural,"testbench_test","End"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Interface_testbench_test_name.cpp
r41 r42 49 49 }; 50 50 51 string Interface::testbench_test_transaction_name (Vhdl * & vhdl) 52 { 53 log_printf(FUNC,Behavioural,"testbench_test_transaction_name","Begin"); 54 55 string name; 56 57 name = "interface_"; 58 if (_name != "") 59 name += _name + "_"; 60 name += "test_transaction"; 61 62 vhdl->set_signal(name,1); 63 64 log_printf(FUNC,Behavioural,"testbench_test_transaction_name","End"); 65 66 return name; 67 }; 68 51 69 }; // end namespace behavioural 52 70 }; // end namespace morpheo -
trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Interface_testbench_test_ok.cpp
r41 r42 20 20 21 21 vhdl->set_body(test_name + " <= '1' when true"); 22 22 23 // set all condition 23 24 if (_list_signal->empty()== false) … … 31 32 } 32 33 } 33 vhdl->set_body(" else '0';");34 vhdl->set_body("\telse '0';"); 34 35 vhdl->set_body(""); 35 36 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Interface_toXML.cpp
r38 r42 1 #ifdef POSITION 1 2 /* 2 3 * $Id$ … … 43 44 }; 44 45 45 #ifdef POSITION46 46 XML Interface::toXML_mapping (void) 47 47 { … … 55 55 xml.singleton_begin ("port_map"); 56 56 xml. attribut ("name" ,_name ); 57 xml. attribut ("component",(static_cast<Entity *>(_entity_map ))-> _name);58 xml. attribut ("port" ,(static_cast<Interface *>(_interface_map))-> _name);57 xml. attribut ("component",(static_cast<Entity *>(_entity_map ))->get_name()); 58 xml. attribut ("port" ,(static_cast<Interface *>(_interface_map))->get_name()); 59 59 xml.singleton_end (); 60 60 … … 63 63 return xml; 64 64 }; 65 #endif66 65 }; // end namespace behavioural 67 66 }; // end namespace morpheo 67 #endif -
trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Interfaces_find_interface.cpp
r40 r42 15 15 if (_list_interface->empty()== false) 16 16 { 17 list<Interface_fifo*>::iterator i 17 list<Interface_fifo*>::iterator i = _list_interface->begin(); 18 18 19 19 while (i != _list_interface->end()) 20 20 { 21 if ((*i)-> _name== name)21 if ((*i)->get_name() == name) 22 22 return (*i); 23 23 ++i; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Interfaces_get_clock.cpp
r41 r42 13 13 namespace behavioural { 14 14 15 stringInterfaces::get_clock (void)15 Signal * Interfaces::get_clock (void) 16 16 { 17 string clock = "";17 Signal * clock = NULL; 18 18 19 19 if (not _list_interface->empty()) 20 20 { 21 list<Interface_fifo*>::iterator i 21 list<Interface_fifo*>::iterator i = _list_interface->begin(); 22 22 23 23 while (i != _list_interface->end()) 24 24 { 25 string str= (*i)->get_clock ();25 Signal * sig = (*i)->get_clock (); 26 26 27 if (s tr != "")27 if (sig != NULL) 28 28 { 29 if (clock != "")29 if (clock != NULL) 30 30 throw ErrorMorpheo ("<Interfaces.get_clock> : find too many clock."); 31 clock = s tr;31 clock = sig; 32 32 } 33 33 ++i; … … 35 35 } 36 36 37 if (clock == "")37 if (clock == NULL) 38 38 throw ErrorMorpheo ("<Interfaces.get_clock> : no clock find."); 39 39 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Interfaces_get_interface.cpp
r40 r42 47 47 }; 48 48 49 list<Interface_fifo*>* Interfaces::get_interface_list (void) 50 { 51 return _list_interface; 52 }; 53 49 54 }; // end namespace behavioural 50 55 }; // end namespace morpheo -
trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Interfaces_set_interface.cpp
r40 r42 11 11 namespace behavioural { 12 12 13 Interface_fifo * Interfaces::set_interface (string name , 14 direction_t direction , 15 localisation_t localisation) 13 Interface_fifo * Interfaces::set_interface (string name 14 #ifdef POSITION 15 ,direction_t direction 16 ,localisation_t localisation 17 #endif 18 ) 16 19 { 17 Interface_fifo * interface = new Interface_fifo (name, direction, localisation); 20 Interface_fifo * interface = new Interface_fifo (name 21 #ifdef POSITION 22 ,direction 23 ,localisation 24 #endif 25 ); 18 26 19 27 _list_interface->push_back (interface); … … 22 30 }; 23 31 32 #ifdef POSITION 24 33 Interface_fifo * Interfaces::set_interface (string name , 25 34 direction_t direction , … … 33 42 return interface; 34 43 }; 35 44 #endif 36 45 37 46 }; // end namespace behavioural -
trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Interfaces_testbench_body.cpp
r41 r42 14 14 15 15 string Interfaces::testbench_body (Vhdl * & vhdl, 16 string counter_name) 16 string counter_name, 17 string reset_name ) 17 18 { 18 19 log_printf(FUNC,Behavioural,"testbench_body","Begin"); … … 28 29 while (i != _list_interface->end()) 29 30 { 30 (*i)->testbench_body(vhdl, counter_name );31 string str = (*i)->testbench_test(vhdl, counter_name );31 (*i)->testbench_body(vhdl, counter_name, reset_name); 32 string str = (*i)->testbench_test(vhdl, counter_name, reset_name); 32 33 33 34 test += " and "+str; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Interfaces_testbench_generate_file.cpp
r41 r42 19 19 Vhdl * vhdl = new Vhdl(_name+"_Testbench"); 20 20 string counter = "counter"; 21 string clock = this->get_clock(); 21 Signal * clock = this->get_clock(); 22 Signal * reset = this->get_reset(); 23 string clock_name = clock->get_name(); 24 string reset_name = reset->get_name(); 22 25 uint32_t cycle = this->get_cycle(); 23 26 24 vhdl ->set_signal (counter, "natural", "0"); 25 vhdl ->set_signal (clock , 1 , 0); // modif Signal_set_signal 27 vhdl->set_signal (clock_name, 1, 0); 28 vhdl->set_signal (reset_name, 1, 0); 29 vhdl->set_signal (counter, "natural"); 26 30 this->set_signal (vhdl); 27 31 28 32 vhdl->set_body(""); 29 33 vhdl->set_body("------------------------------------------------------"); 30 vhdl->set_body("-- Component ");34 vhdl->set_body("-- Component - Intanciation"); 31 35 vhdl->set_body("------------------------------------------------------"); 32 36 vhdl->set_body(""); … … 54 58 delete list_signal; 55 59 56 vhdl->set_body(""); 57 vhdl->set_body("------------------------------------------------------"); 58 vhdl->set_body("-- Port's affectation"); 59 vhdl->set_body("------------------------------------------------------"); 60 vhdl->set_body(""); 61 string test_name = this->testbench_body(vhdl,counter); 60 string test_name = this->testbench_body(vhdl,counter, reset_name); 62 61 63 62 vhdl->set_body(""); 64 63 vhdl->set_body("------------------------------------------------------"); 65 vhdl->set_body("-- process clock");64 vhdl->set_body("-- reset"); 66 65 vhdl->set_body("------------------------------------------------------"); 67 66 vhdl->set_body(""); 68 vhdl->set_body(clock+" <= not "+clock+" after 50 ns;"); 67 vhdl->set_body("-- if the systemC simulate have multiple reset, we make the last"); 68 vhdl->set_body(reset_name+" <= '1' after 150 ns;"); 69 69 70 vhdl->set_body(""); 70 vhdl->set_body("process ("+clock+")"); 71 vhdl->set_body("------------------------------------------------------"); 72 vhdl->set_body("-- process clock_name"); 73 vhdl->set_body("------------------------------------------------------"); 74 vhdl->set_body(""); 75 vhdl->set_body(clock_name+" <= not "+clock_name+" after 50 ns;"); 76 vhdl->set_body(""); 77 vhdl->set_body("process ("+clock_name+")"); 71 78 vhdl->set_body("begin"); 72 vhdl->set_body("\tif "+clock+"'event and "+clock+" = '1' then"); 73 vhdl->set_body("\t\t"+counter+" <= "+counter+"+1;"); 79 vhdl->set_body("\tif ("+clock_name+"'event and "+clock_name+" = '1') then"); 74 80 vhdl->set_body(""); 75 vhdl->set_body("\t\tassert ("+test_name+" = '1') report \"Test KO\" severity FAILURE;"); 76 vhdl->set_body("\t\tassert not ("+counter+" = "+toString(cycle)+") report \"Test OK\" severity FAILURE;"); 81 vhdl->set_body("\t\tif ("+reset_name+" = '0') then"); 77 82 vhdl->set_body(""); 83 vhdl->set_body("\t\t\t"+counter+" <= "+toString(reset->get_reset_cycle(true))+";"); 84 vhdl->set_body(""); 85 vhdl->set_body("\t\telse"); 86 vhdl->set_body(""); 87 vhdl->set_body("\t\t\t"+counter+" <= "+counter+"+1;"); 88 vhdl->set_body(""); 89 vhdl->set_body("\t\t\tassert not ("+counter+" = "+toString(cycle)+") report \"Test OK\" severity FAILURE;"); 90 vhdl->set_body("\t\t\tassert not ("+test_name+" = '0') report \"Test KO\" severity FAILURE;"); 91 92 #ifdef VHDL_TESTBENCH_ASSERT 93 vhdl->set_body("\t\t\t-- Assert ..."); 94 for (uint32_t cpt=0; cpt<=cycle; cpt++) 95 vhdl->set_body("\t\t\tassert not ("+counter+" = "+toString(cpt)+") report \"===== Test number "+toString(cpt)+" =====\" severity NOTE;"); 96 #endif 97 98 vhdl->set_body(""); 99 vhdl->set_body("\t\tend if;"); 78 100 vhdl->set_body("\tend if;"); 79 101 vhdl->set_body("end process;"); 80 102 81 vhdl->generate_file(); 103 104 vhdl->generate_file(false,true); 82 105 83 106 delete vhdl; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Interfaces_toXML.cpp
r40 r42 1 #ifdef POSITION 1 2 /* 2 3 * $Id$ … … 29 30 }; 30 31 31 #ifdef POSITION32 32 XML Interfaces::toXML_mapping (void) 33 33 { … … 47 47 return xml; 48 48 }; 49 #endif50 49 }; // end namespace behavioural 51 50 }; // end namespace morpheo 51 #endif -
trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Signal.cpp
r40 r42 18 18 _direction (direction ), 19 19 _size (size ), 20 _presence_port ( presence_port)20 _presence_port ((direction==INTERNAL)?PORT_VHDL_NO_TESTBENCH_NO:presence_port) 21 21 { 22 22 log_printf(FUNC,Behavioural,"Signal","Begin"); 23 _is_allocate = false; 24 _is_map = false; 25 _signal = NULL; 26 _sc_signal = NULL; 27 _sc_signal_map = NULL; 28 _type_info = UNKNOW; 23 29 #ifdef VHDL_TESTBENCH 24 _signal = NULL; 25 _type_info = UNKNOW; 26 _list_value = new list<string>; 30 _list_value = new list<string>; 27 31 #endif 28 32 log_printf(FUNC,Behavioural,"Signal","End"); … … 36 40 { 37 41 log_printf(FUNC,Behavioural,"Signal (copy)","Begin"); 42 _is_allocate= signal._is_allocate; 43 _is_map = signal._is_map ; 44 _sc_signal = signal._sc_signal ; 45 _sc_signal_map = signal._sc_signal_map; 46 _type_info = signal._type_info ; 38 47 #ifdef VHDL_TESTBENCH 39 _signal = signal._signal ;40 _type_info = signal._type_info ;41 48 _list_value = signal._list_value; 42 49 #endif … … 47 54 { 48 55 log_printf(FUNC,Behavioural,"~Signal","Begin"); 56 57 // if (_is_allocate == true) 58 // switch (_direction) 59 // { 60 // case IN : 61 // { 62 // switch (_type_info) 63 // { 64 // case BOOL : {delete (static_cast<sc_in <bool > *>(_sc_signal)); break;} 65 // case UINT8_T : {delete (static_cast<sc_in <uint8_t > *>(_sc_signal)); break;} 66 // case UINT16_T : {delete (static_cast<sc_in <uint16_t> *>(_sc_signal)); break;} 67 // case UINT32_T : {delete (static_cast<sc_in <uint32_t> *>(_sc_signal)); break;} 68 // case UINT64_T : {delete (static_cast<sc_in <uint64_t> *>(_sc_signal)); break;} 69 // default : {throw (ErrorMorpheo ("Signal \""+_name+"\" : type unknow.")); break;} 70 // } 71 // break; 72 // } 73 // case OUT : 74 // { 75 // switch (_type_info) 76 // { 77 // case BOOL : {delete (static_cast<sc_out <bool > *>(_sc_signal)); break;} 78 // case UINT8_T : {delete (static_cast<sc_out <uint8_t > *>(_sc_signal)); break;} 79 // case UINT16_T : {delete (static_cast<sc_out <uint16_t> *>(_sc_signal)); break;} 80 // case UINT32_T : {delete (static_cast<sc_out <uint32_t> *>(_sc_signal)); break;} 81 // case UINT64_T : {delete (static_cast<sc_out <uint64_t> *>(_sc_signal)); break;} 82 // default : {throw (ErrorMorpheo ("Signal \""+_name+"\" : type unknow.")); break;} 83 // } 84 // break; 85 // } 86 // case INTERNAL : 87 // { 88 // switch (_type_info) 89 // { 90 // case BOOL : {delete (static_cast<sc_sc_signal <bool > *>(_sc_signal)); break;} 91 // case UINT8_T : {delete (static_cast<sc_sc_signal <uint8_t > *>(_sc_signal)); break;} 92 // case UINT16_T : {delete (static_cast<sc_sc_signal <uint16_t> *>(_sc_signal)); break;} 93 // case UINT32_T : {delete (static_cast<sc_sc_signal <uint32_t> *>(_sc_signal)); break;} 94 // case UINT64_T : {delete (static_cast<sc_sc_signal <uint64_t> *>(_sc_signal)); break;} 95 // default : {throw (ErrorMorpheo ("Signal \""+_name+"\" : type unknow.")); break;} 96 // } 97 // break; 98 // } 99 // default : {throw (ErrorMorpheo ("Signal \""+_name+"\" : direction unknow.")); break;} 100 // } 101 49 102 #ifdef VHDL_TESTBENCH 50 103 delete _list_value; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Signal_get_clock.cpp
r41 r42 13 13 namespace behavioural { 14 14 15 stringSignal::get_clock (void)15 Signal * Signal::get_clock (void) 16 16 { 17 17 if ((_presence_port == CLOCK_VHDL_YES) or 18 18 (_presence_port == CLOCK_VHDL_NO )) 19 return _name;19 return this; 20 20 else 21 return "";21 return NULL; 22 22 }; 23 23 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Signal_get_name_vhdl.cpp
r41 r42 1 # ifdef VHDL_TESTBENCH1 # ifdef VHDL_TESTBENCH 2 2 /* 3 3 * $Id$ … … 17 17 if ((_presence_port == PORT_VHDL_YES_TESTBENCH_YES) or 18 18 (_presence_port == PORT_VHDL_YES_TESTBENCH_NO ) or 19 (_presence_port == CLOCK_VHDL_YES)) 19 (_presence_port == CLOCK_VHDL_YES) or 20 (_presence_port == RESET_VHDL_YES)) 20 21 list_signal->push_back(_name); 21 22 }; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Signal_print.cpp
r40 r42 21 21 << toString(x._presence_port); 22 22 23 // #ifdef VHDL_TESTBENCH24 // if (x._list_value->empty()== false)25 // {26 // list<string>::iterator i = x._list_value->begin();27 28 // while (i != x._list_value->end())29 // {30 // output_stream << "\n\t" << *i ;31 // ++i;32 // }33 // }34 // #endif35 36 23 log_printf(FUNC,Behavioural,"operator<<","End"); 37 24 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Signal_set_port.cpp
r41 r42 19 19 if ((_presence_port == PORT_VHDL_YES_TESTBENCH_YES) or 20 20 (_presence_port == PORT_VHDL_YES_TESTBENCH_NO ) or 21 (_presence_port == CLOCK_VHDL_YES)) 21 (_presence_port == CLOCK_VHDL_YES) or 22 (_presence_port == RESET_VHDL_YES)) 22 23 vhdl->set_port (_name,_direction,_size); 23 24 … … 30 31 log_printf(FUNC,Behavioural,"set_signal (Vhdl)","Begin"); 31 32 32 if ((_presence_port == PORT_VHDL_YES_TESTBENCH_YES) or 33 (_presence_port == PORT_VHDL_NO_TESTBENCH_YES )// or 34 // (_presence_port == CLOCK_VHDL_YES) or 35 // (_presence_port == CLOCK_VHDL_NO ) 33 if ( (_presence_port == PORT_VHDL_YES_TESTBENCH_YES) 34 or (_presence_port == PORT_VHDL_NO_TESTBENCH_YES ) 35 // or (_presence_port == CLOCK_VHDL_YES) 36 // or (_presence_port == CLOCK_VHDL_NO ) 37 // or (_presence_port == RESET_VHDL_YES) 38 // or (_presence_port == RESET_VHDL_NO ) 36 39 ) 37 40 vhdl->set_signal (_name ,_size); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Signal_testbench.cpp
r41 r42 18 18 19 19 if ((_presence_port == PORT_VHDL_YES_TESTBENCH_YES) or 20 (_presence_port == PORT_VHDL_NO_TESTBENCH_YES )) 20 (_presence_port == PORT_VHDL_NO_TESTBENCH_YES ) or 21 (_presence_port == RESET_VHDL_YES ) or 22 (_presence_port == RESET_VHDL_NO ) ) 21 23 { 22 24 string str; … … 32 34 case IN : {str = toBase2 (value); break;} 33 35 case OUT : {str = toBase2 (value); break;} 34 // case INOUT: {break;}36 default : {break;} 35 37 } 36 38 break; … … 44 46 case IN : {str = toBase2 (value,_size); break;} 45 47 case OUT : {str = toBase2 (value,_size); break;} 46 // case INOUT: {break;}48 default : {break;} 47 49 } 48 50 break; … … 56 58 case IN : {str = toBase2 (value,_size); break;} 57 59 case OUT : {str = toBase2 (value,_size); break;} 58 // case INOUT: {break;}60 default : {break;} 59 61 } 60 62 break; … … 68 70 case IN : {str = toBase2 (value,_size); break;} 69 71 case OUT : {str = toBase2 (value,_size); break;} 70 // case INOUT: {break;}72 default : {break;} 71 73 } 72 74 break; … … 80 82 case IN : {str = toBase2 (value,_size); break;} 81 83 case OUT : {str = toBase2 (value,_size); break;} 82 // case INOUT: {break;}84 default : {break;} 83 85 } 84 86 break; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Signal_testbench_body.cpp
r41 r42 13 13 14 14 void Signal::testbench_body (Vhdl * & vhdl, 15 string counter_name) 15 string counter_name, 16 string reset_name ) 16 17 { 17 18 log_printf(FUNC,Behavioural,"testbench_body","Begin"); 18 19 19 20 // _list_value is empty if we don't trace 20 if (_list_value->empty()== false)21 {22 string separator;23 if (_size == 1)24 separator = "\'";25 else26 separator = "\"";27 21 28 string signame = (_direction==OUT)?(_name+"_test"):_name; 29 30 vhdl->set_body (""); 31 vhdl->set_body ("with "+counter_name+" select"); 32 vhdl->set_body ("\t"+signame+" <="); 33 34 uint32_t cpt = 0; 35 list<string>::iterator i = _list_value->begin(); 36 37 while (i != _list_value->end()) 38 { 39 list<string>::iterator j = i; 40 41 ++i; 42 43 if (i != _list_value->end()) 22 if ((_presence_port == PORT_VHDL_YES_TESTBENCH_YES) or 23 (_presence_port == PORT_VHDL_NO_TESTBENCH_YES )) 24 if (_list_value->empty()== false) 25 { 26 string separator; 27 if (_size == 1) 28 separator = "\'"; 29 else 30 separator = "\""; 31 32 string signame = (_direction==OUT)?(_name+"_test"):_name; 33 34 vhdl->set_body (""); 35 vhdl->set_body ("with "+counter_name+" select"); 36 vhdl->set_body ("\t"+signame+" <="); 37 38 uint32_t cpt = 0; 39 list<string>::iterator i = _list_value->begin(); 40 41 while (i != _list_value->end()) 42 { 43 list<string>::iterator j = i; 44 45 ++i; 46 44 47 vhdl->set_body ("\t"+separator+*j+separator+" when "+toString(cpt++)+","); 45 else 46 vhdl->set_body ("\t"+separator+*j+separator+" when others;"); 47 } 48 } 49 48 } 49 50 if (_size == 1) 51 vhdl->set_body ("\t'0' when others;"); 52 else 53 vhdl->set_body ("\t(others => '0') when others;"); 54 } 55 50 56 log_printf(FUNC,Behavioural,"testbench_body","End"); 51 57 }; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Signal_testbench_test_ok.cpp
r41 r42 18 18 19 19 if (_direction == OUT) 20 vhdl->set_body (" and "+_name+" = "+_name+"_test");20 vhdl->set_body ("\tand "+_name+" = "+_name+"_test"); 21 21 22 22 log_printf(FUNC,Behavioural,"testbench_test_ok","End"); -
trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Include/ppt-style.sty
r41 r42 8 8 \usepackage[french]{babel} 9 9 \usepackage{pgf,pgfarrows,pgfheaps,pgfnodes,pgfpages,pgfshade} 10 11 10 \usepackage{openbib} 12 11 \bibliographystyle{plain} 13 12 14 \useoutertheme{infolines} 13 %\useoutertheme{infolines} 14 %\usetheme{Darmstadt} 15 %\usetheme{Malmoe} 16 %\usetheme{Copenhagen} 17 18 %\usebackgroundtemplate{\includegraphics[height=\paperheight] {Include/background}} 15 19 16 20 %% % file, Dimension -
trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Makefile
r23 r42 30 30 DIR_SCHEMA = Schema 31 31 DIR_SCHEMA_EPS = Schema_eps 32 DIR_SCHEMA_ JPG = Schema_jpg32 DIR_SCHEMA_PNG = Schema_png 33 33 DIR_TEX = Source 34 34 … … 58 58 #-------------------------------------------------------------------------------- 59 59 .PHONY : all clean view help doc doc_all new delete 60 .SECONDARY : $(DVI_FILES) $(PS_FILES) $(PDF_FILES) $(EPS_FILES) $(DIR_SCHEMA_EPS) $(DIR_SCHEMA_ JPG)60 .SECONDARY : $(DVI_FILES) $(PS_FILES) $(PDF_FILES) $(EPS_FILES) $(DIR_SCHEMA_EPS) $(DIR_SCHEMA_PNG) 61 61 62 62 all : help … … 365 365 @$(MKDIR) $@ 366 366 367 $(DIR_SCHEMA_ JPG) :367 $(DIR_SCHEMA_PNG) : 368 368 @$(ECHO) "Make directory : $@" 369 369 @$(MKDIR) $@ … … 373 373 @$(MKDIR) $@ 374 374 375 $(DIR_SCHEMA_EPS)/%.eps : $(DIR_SCHEMA)/%.eps $(DIR_SCHEMA_EPS) $(DIR_SCHEMA_ JPG)375 $(DIR_SCHEMA_EPS)/%.eps : $(DIR_SCHEMA)/%.eps $(DIR_SCHEMA_EPS) $(DIR_SCHEMA_PNG) 376 376 @$(ECHO) "Generate files : $*.eps" 377 377 @$(CP) $(DIR_SCHEMA)/$*.eps $(DIR_SCHEMA_EPS) 378 @$(EPS2 JPG) $@ $(DIR_SCHEMA_JPG)/$*.jpg379 380 $(DIR_SCHEMA_EPS)/%.eps : $(DIR_SCHEMA)/%.fig $(DIR_SCHEMA_EPS) $(DIR_SCHEMA_ JPG)378 @$(EPS2PNG) $@ $(DIR_SCHEMA_PNG)/$*.png 379 380 $(DIR_SCHEMA_EPS)/%.eps : $(DIR_SCHEMA)/%.fig $(DIR_SCHEMA_EPS) $(DIR_SCHEMA_PNG) 381 381 @$(ECHO) "Generate files : $*.eps" 382 382 @$(FIG2EPS) $< $@ 383 @$(EPS2 JPG) $@ $(DIR_SCHEMA_JPG)/$*.jpg384 385 $(DIR_SCHEMA_EPS)/%.eps : $(DIR_GRAPH)/%.p $(DIR_SCHEMA_EPS) $(DIR_SCHEMA_ JPG)383 @$(EPS2PNG) $@ $(DIR_SCHEMA_PNG)/$*.png 384 385 $(DIR_SCHEMA_EPS)/%.eps : $(DIR_GRAPH)/%.p $(DIR_SCHEMA_EPS) $(DIR_SCHEMA_PNG) 386 386 @$(ECHO) "Generate files : $*.eps" 387 387 @$(CD) $(DIR_GRAPH); $(GNUPLOT) $*.p 388 @$(EPS2 JPG) $@ $(DIR_SCHEMA_JPG)/$*.jpg388 @$(EPS2PNG) $@ $(DIR_SCHEMA_PNG)/$*.png 389 389 390 390 #-------------------------------------------------------------------------------- … … 394 394 clean : 395 395 @$(ECHO) "Delete temporary files "$(PWD) 396 @$(RM) $(DIR_SCHEMA_EPS) $(DIR_SCHEMA_ JPG) $(DIR_TEX) $(DIR_PACKAGE)/*.aux396 @$(RM) $(DIR_SCHEMA_EPS) $(DIR_SCHEMA_PNG) $(DIR_TEX) $(DIR_PACKAGE)/*.aux 397 397 @$(RM) $(DVI_FILES) $(PS_FILES) $(PDF_FILES) 398 398 @$(MAKE) clean_rec DIR_CLEAN=.
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